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drm/i915: fix port checks for MST support on gen >= 11
[linux/fpc-iii.git] / sound / soc / davinci / davinci-i2s.c
bloba3206e65e5e54d3abc84eea1f66fd02cd512e0bb
1 /*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * DT support (c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
8 * based on davinci-mcasp.c DT support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * TODO:
15 * on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/platform_data/davinci_asp.h>
26
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
32 #include <sound/dmaengine_pcm.h>
33
34 #include "edma-pcm.h"
35 #include "davinci-i2s.h"
36
37 #define DRV_NAME "davinci-i2s"
38
39 /*
40 * NOTE: terminology here is confusing.
41 *
42 * - This driver supports the "Audio Serial Port" (ASP),
43 * found on dm6446, dm355, and other DaVinci chips.
44 *
45 * - But it labels it a "Multi-channel Buffered Serial Port"
46 * (McBSP) as on older chips like the dm642 ... which was
47 * backward-compatible, possibly explaining that confusion.
48 *
49 * - OMAP chips have a controller called McBSP, which is
50 * incompatible with the DaVinci flavor of McBSP.
51 *
52 * - Newer DaVinci chips have a controller called McASP,
53 * incompatible with ASP and with either McBSP.
54 *
55 * In short: this uses ASP to implement I2S, not McBSP.
56 * And it won't be the only DaVinci implemention of I2S.
57 */
58 #define DAVINCI_MCBSP_DRR_REG 0x00
59 #define DAVINCI_MCBSP_DXR_REG 0x04
60 #define DAVINCI_MCBSP_SPCR_REG 0x08
61 #define DAVINCI_MCBSP_RCR_REG 0x0c
62 #define DAVINCI_MCBSP_XCR_REG 0x10
63 #define DAVINCI_MCBSP_SRGR_REG 0x14
64 #define DAVINCI_MCBSP_PCR_REG 0x24
65
66 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
67 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
68 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
69 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
70 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
71 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
72 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
73
74 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
75 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
76 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
77 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
78 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
79 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
80 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
81
82 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
83 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
84 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
85 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
86 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
87 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
88 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
89
90 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
91 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
92 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
93 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
94
95 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
96 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
97 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
98 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
99 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
100 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
101 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
102 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
103 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
104
105 enum {
106 DAVINCI_MCBSP_WORD_8 = 0,
107 DAVINCI_MCBSP_WORD_12,
108 DAVINCI_MCBSP_WORD_16,
109 DAVINCI_MCBSP_WORD_20,
110 DAVINCI_MCBSP_WORD_24,
111 DAVINCI_MCBSP_WORD_32,
112 };
113
114 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
115 [SNDRV_PCM_FORMAT_S8] = 1,
116 [SNDRV_PCM_FORMAT_S16_LE] = 2,
117 [SNDRV_PCM_FORMAT_S32_LE] = 4,
118 };
119
120 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
121 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
122 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
123 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
124 };
125
126 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
127 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
128 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
129 };
130
131 struct davinci_mcbsp_dev {
132 struct device *dev;
133 struct snd_dmaengine_dai_dma_data dma_data[2];
134 int dma_request[2];
135 void __iomem *base;
136 #define MOD_DSP_A 0
137 #define MOD_DSP_B 1
138 int mode;
139 u32 pcr;
140 struct clk *clk;
141 /*
142 * Combining both channels into 1 element will at least double the
143 * amount of time between servicing the dma channel, increase
144 * effiency, and reduce the chance of overrun/underrun. But,
145 * it will result in the left & right channels being swapped.
146 *
147 * If relabeling the left and right channels is not possible,
148 * you may want to let the codec know to swap them back.
149 *
150 * It may allow x10 the amount of time to service dma requests,
151 * if the codec is master and is using an unnecessarily fast bit clock
152 * (ie. tlvaic23b), independent of the sample rate. So, having an
153 * entire frame at once means it can be serviced at the sample rate
154 * instead of the bit clock rate.
155 *
156 * In the now unlikely case that an underrun still
157 * occurs, both the left and right samples will be repeated
158 * so that no pops are heard, and the left and right channels
159 * won't end up being swapped because of the underrun.
160 */
161 unsigned enable_channel_combine:1;
162
163 unsigned int fmt;
164 int clk_div;
165 int clk_input_pin;
166 bool i2s_accurate_sck;
167 };
168
169 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
170 int reg, u32 val)
171 {
172 __raw_writel(val, dev->base + reg);
173 }
174
175 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
176 {
177 return __raw_readl(dev->base + reg);
178 }
179
180 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
181 {
182 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
183 /* The clock needs to toggle to complete reset.
184 * So, fake it by toggling the clk polarity.
185 */
186 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
187 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
188 }
189
190 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
191 struct snd_pcm_substream *substream)
192 {
193 struct snd_soc_pcm_runtime *rtd = substream->private_data;
194 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
195 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
196 u32 spcr;
197 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
198 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
199 if (spcr & mask) {
200 /* start off disabled */
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
202 spcr & ~mask);
203 toggle_clock(dev, playback);
204 }
205 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
206 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
207 /* Start the sample generator */
208 spcr |= DAVINCI_MCBSP_SPCR_GRST;
209 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
210 }
211
212 if (playback) {
213 /* Stop the DMA to avoid data loss */
214 /* while the transmitter is out of reset to handle XSYNCERR */
215 if (component->driver->ops->trigger) {
216 int ret = component->driver->ops->trigger(substream,
217 SNDRV_PCM_TRIGGER_STOP);
218 if (ret < 0)
219 printk(KERN_DEBUG "Playback DMA stop failed\n");
220 }
221
222 /* Enable the transmitter */
223 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
224 spcr |= DAVINCI_MCBSP_SPCR_XRST;
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
226
227 /* wait for any unexpected frame sync error to occur */
228 udelay(100);
229
230 /* Disable the transmitter to clear any outstanding XSYNCERR */
231 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
232 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
233 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
234 toggle_clock(dev, playback);
235
236 /* Restart the DMA */
237 if (component->driver->ops->trigger) {
238 int ret = component->driver->ops->trigger(substream,
239 SNDRV_PCM_TRIGGER_START);
240 if (ret < 0)
241 printk(KERN_DEBUG "Playback DMA start failed\n");
242 }
243 }
244
245 /* Enable transmitter or receiver */
246 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
247 spcr |= mask;
248
249 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
250 /* Start frame sync */
251 spcr |= DAVINCI_MCBSP_SPCR_FRST;
252 }
253 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
254 }
255
256 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
257 {
258 u32 spcr;
259
260 /* Reset transmitter/receiver and sample rate/frame sync generators */
261 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
262 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
263 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
264 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
265 toggle_clock(dev, playback);
266 }
267
268 #define DEFAULT_BITPERSAMPLE 16
269
270 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
271 unsigned int fmt)
272 {
273 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
274 unsigned int pcr;
275 unsigned int srgr;
276 bool inv_fs = false;
277 /* Attention srgr is updated by hw_params! */
278 srgr = DAVINCI_MCBSP_SRGR_FSGM |
279 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
280 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
281
282 dev->fmt = fmt;
283 /* set master/slave audio interface */
284 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
285 case SND_SOC_DAIFMT_CBS_CFS:
286 /* cpu is master */
287 pcr = DAVINCI_MCBSP_PCR_FSXM |
288 DAVINCI_MCBSP_PCR_FSRM |
289 DAVINCI_MCBSP_PCR_CLKXM |
290 DAVINCI_MCBSP_PCR_CLKRM;
291 break;
292 case SND_SOC_DAIFMT_CBM_CFS:
293 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
294 /*
295 * Selection of the clock input pin that is the
296 * input for the Sample Rate Generator.
297 * McBSP FSR and FSX are driven by the Sample Rate
298 * Generator.
299 */
300 switch (dev->clk_input_pin) {
301 case MCBSP_CLKS:
302 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
303 DAVINCI_MCBSP_PCR_CLKRM;
304 break;
305 case MCBSP_CLKR:
306 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
307 break;
308 default:
309 dev_err(dev->dev, "bad clk_input_pin\n");
310 return -EINVAL;
311 }
312
313 break;
314 case SND_SOC_DAIFMT_CBM_CFM:
315 /* codec is master */
316 pcr = 0;
317 break;
318 default:
319 printk(KERN_ERR "%s:bad master\n", __func__);
320 return -EINVAL;
321 }
322
323 /* interface format */
324 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
325 case SND_SOC_DAIFMT_I2S:
326 /* Davinci doesn't support TRUE I2S, but some codecs will have
327 * the left and right channels contiguous. This allows
328 * dsp_a mode to be used with an inverted normal frame clk.
329 * If your codec is master and does not have contiguous
330 * channels, then you will have sound on only one channel.
331 * Try using a different mode, or codec as slave.
332 *
333 * The TLV320AIC33 is an example of a codec where this works.
334 * It has a variable bit clock frequency allowing it to have
335 * valid data on every bit clock.
336 *
337 * The TLV320AIC23 is an example of a codec where this does not
338 * work. It has a fixed bit clock frequency with progressively
339 * more empty bit clock slots between channels as the sample
340 * rate is lowered.
341 */
342 inv_fs = true;
343 /* fall through */
344 case SND_SOC_DAIFMT_DSP_A:
345 dev->mode = MOD_DSP_A;
346 break;
347 case SND_SOC_DAIFMT_DSP_B:
348 dev->mode = MOD_DSP_B;
349 break;
350 default:
351 printk(KERN_ERR "%s:bad format\n", __func__);
352 return -EINVAL;
353 }
354
355 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
356 case SND_SOC_DAIFMT_NB_NF:
357 /* CLKRP Receive clock polarity,
358 * 1 - sampled on rising edge of CLKR
359 * valid on rising edge
360 * CLKXP Transmit clock polarity,
361 * 1 - clocked on falling edge of CLKX
362 * valid on rising edge
363 * FSRP Receive frame sync pol, 0 - active high
364 * FSXP Transmit frame sync pol, 0 - active high
365 */
366 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
367 break;
368 case SND_SOC_DAIFMT_IB_IF:
369 /* CLKRP Receive clock polarity,
370 * 0 - sampled on falling edge of CLKR
371 * valid on falling edge
372 * CLKXP Transmit clock polarity,
373 * 0 - clocked on rising edge of CLKX
374 * valid on falling edge
375 * FSRP Receive frame sync pol, 1 - active low
376 * FSXP Transmit frame sync pol, 1 - active low
377 */
378 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
379 break;
380 case SND_SOC_DAIFMT_NB_IF:
381 /* CLKRP Receive clock polarity,
382 * 1 - sampled on rising edge of CLKR
383 * valid on rising edge
384 * CLKXP Transmit clock polarity,
385 * 1 - clocked on falling edge of CLKX
386 * valid on rising edge
387 * FSRP Receive frame sync pol, 1 - active low
388 * FSXP Transmit frame sync pol, 1 - active low
389 */
390 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
391 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
392 break;
393 case SND_SOC_DAIFMT_IB_NF:
394 /* CLKRP Receive clock polarity,
395 * 0 - sampled on falling edge of CLKR
396 * valid on falling edge
397 * CLKXP Transmit clock polarity,
398 * 0 - clocked on rising edge of CLKX
399 * valid on falling edge
400 * FSRP Receive frame sync pol, 0 - active high
401 * FSXP Transmit frame sync pol, 0 - active high
402 */
403 break;
404 default:
405 return -EINVAL;
406 }
407 if (inv_fs == true)
408 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
409 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
410 dev->pcr = pcr;
411 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
412 return 0;
413 }
414
415 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
416 int div_id, int div)
417 {
418 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
419
420 if (div_id != DAVINCI_MCBSP_CLKGDV)
421 return -ENODEV;
422
423 dev->clk_div = div;
424 return 0;
425 }
426
427 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
428 struct snd_pcm_hw_params *params,
429 struct snd_soc_dai *dai)
430 {
431 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
432 struct snd_interval *i = NULL;
433 int mcbsp_word_length, master;
434 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
435 u32 spcr;
436 snd_pcm_format_t fmt;
437 unsigned element_cnt = 1;
438
439 /* general line settings */
440 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
441 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
442 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
443 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
444 } else {
445 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
446 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
447 }
448
449 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
450 fmt = params_format(params);
451 mcbsp_word_length = asp_word_length[fmt];
452
453 switch (master) {
454 case SND_SOC_DAIFMT_CBS_CFS:
455 freq = clk_get_rate(dev->clk);
456 srgr = DAVINCI_MCBSP_SRGR_FSGM |
457 DAVINCI_MCBSP_SRGR_CLKSM;
458 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
459 8 - 1);
460 if (dev->i2s_accurate_sck) {
461 clk_div = 256;
462 do {
463 framesize = (freq / (--clk_div)) /
464 params->rate_num *
465 params->rate_den;
466 } while (((framesize < 33) || (framesize > 4095)) &&
467 (clk_div));
468 clk_div--;
469 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
470 } else {
471 /* symmetric waveforms */
472 clk_div = freq / (mcbsp_word_length * 16) /
473 params->rate_num * params->rate_den;
474 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
475 16 - 1);
476 }
477 clk_div &= 0xFF;
478 srgr |= clk_div;
479 break;
480 case SND_SOC_DAIFMT_CBM_CFS:
481 srgr = DAVINCI_MCBSP_SRGR_FSGM;
482 clk_div = dev->clk_div - 1;
483 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
484 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
485 clk_div &= 0xFF;
486 srgr |= clk_div;
487 break;
488 case SND_SOC_DAIFMT_CBM_CFM:
489 /* Clock and frame sync given from external sources */
490 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
491 srgr = DAVINCI_MCBSP_SRGR_FSGM;
492 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
493 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
494 __func__, __LINE__, snd_interval_value(i) - 1);
495
496 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
497 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
498 break;
499 default:
500 return -EINVAL;
501 }
502 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
503
504 rcr = DAVINCI_MCBSP_RCR_RFIG;
505 xcr = DAVINCI_MCBSP_XCR_XFIG;
506 if (dev->mode == MOD_DSP_B) {
507 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
508 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
509 } else {
510 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
511 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
512 }
513 /* Determine xfer data type */
514 fmt = params_format(params);
515 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
516 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
517 return -EINVAL;
518 }
519
520 if (params_channels(params) == 2) {
521 element_cnt = 2;
522 if (double_fmt[fmt] && dev->enable_channel_combine) {
523 element_cnt = 1;
524 fmt = double_fmt[fmt];
525 }
526 switch (master) {
527 case SND_SOC_DAIFMT_CBS_CFS:
528 case SND_SOC_DAIFMT_CBS_CFM:
529 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
530 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
531 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
532 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
533 break;
534 case SND_SOC_DAIFMT_CBM_CFM:
535 case SND_SOC_DAIFMT_CBM_CFS:
536 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
537 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
538 break;
539 default:
540 return -EINVAL;
541 }
542 }
543 mcbsp_word_length = asp_word_length[fmt];
544
545 switch (master) {
546 case SND_SOC_DAIFMT_CBS_CFS:
547 case SND_SOC_DAIFMT_CBS_CFM:
548 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
549 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
550 break;
551 case SND_SOC_DAIFMT_CBM_CFM:
552 case SND_SOC_DAIFMT_CBM_CFS:
553 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
554 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
555 break;
556 default:
557 return -EINVAL;
558 }
559
560 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
561 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
562 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
563 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
564
565 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
566 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
567 else
568 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
569
570 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
571 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
572 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
573 return 0;
574 }
575
576 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
577 struct snd_soc_dai *dai)
578 {
579 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
580 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
581 davinci_mcbsp_stop(dev, playback);
582 return 0;
583 }
584
585 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
586 struct snd_soc_dai *dai)
587 {
588 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
589 int ret = 0;
590 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
591
592 switch (cmd) {
593 case SNDRV_PCM_TRIGGER_START:
594 case SNDRV_PCM_TRIGGER_RESUME:
595 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
596 davinci_mcbsp_start(dev, substream);
597 break;
598 case SNDRV_PCM_TRIGGER_STOP:
599 case SNDRV_PCM_TRIGGER_SUSPEND:
600 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
601 davinci_mcbsp_stop(dev, playback);
602 break;
603 default:
604 ret = -EINVAL;
605 }
606 return ret;
607 }
608
609 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
610 struct snd_soc_dai *dai)
611 {
612 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
613 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
614 davinci_mcbsp_stop(dev, playback);
615 }
616
617 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
618
619 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
620 .shutdown = davinci_i2s_shutdown,
621 .prepare = davinci_i2s_prepare,
622 .trigger = davinci_i2s_trigger,
623 .hw_params = davinci_i2s_hw_params,
624 .set_fmt = davinci_i2s_set_dai_fmt,
625 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
626
627 };
628
629 static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
630 {
631 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
632
633 dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
634 dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
635
636 return 0;
637 }
638
639 static struct snd_soc_dai_driver davinci_i2s_dai = {
640 .probe = davinci_i2s_dai_probe,
641 .playback = {
642 .channels_min = 2,
643 .channels_max = 2,
644 .rates = DAVINCI_I2S_RATES,
645 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
646 .capture = {
647 .channels_min = 2,
648 .channels_max = 2,
649 .rates = DAVINCI_I2S_RATES,
650 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
651 .ops = &davinci_i2s_dai_ops,
652
653 };
654
655 static const struct snd_soc_component_driver davinci_i2s_component = {
656 .name = DRV_NAME,
657 };
658
659 static int davinci_i2s_probe(struct platform_device *pdev)
660 {
661 struct snd_dmaengine_dai_dma_data *dma_data;
662 struct davinci_mcbsp_dev *dev;
663 struct resource *mem, *res;
664 void __iomem *io_base;
665 int *dma;
666 int ret;
667
668 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
669 if (!mem) {
670 dev_warn(&pdev->dev,
671 "\"mpu\" mem resource not found, using index 0\n");
672 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
673 if (!mem) {
674 dev_err(&pdev->dev, "no mem resource?\n");
675 return -ENODEV;
676 }
677 }
678
679 io_base = devm_ioremap_resource(&pdev->dev, mem);
680 if (IS_ERR(io_base))
681 return PTR_ERR(io_base);
682
683 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
684 GFP_KERNEL);
685 if (!dev)
686 return -ENOMEM;
687
688 dev->base = io_base;
689
690 /* setup DMA, first TX, then RX */
691 dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
692 dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
693
694 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
695 if (res) {
696 dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
697 *dma = res->start;
698 dma_data->filter_data = dma;
699 } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
700 dma_data->filter_data = "tx";
701 } else {
702 dev_err(&pdev->dev, "Missing DMA tx resource\n");
703 return -ENODEV;
704 }
705
706 dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
707 dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
708
709 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
710 if (res) {
711 dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
712 *dma = res->start;
713 dma_data->filter_data = dma;
714 } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
715 dma_data->filter_data = "rx";
716 } else {
717 dev_err(&pdev->dev, "Missing DMA rx resource\n");
718 return -ENODEV;
719 }
720
721 dev->clk = clk_get(&pdev->dev, NULL);
722 if (IS_ERR(dev->clk))
723 return -ENODEV;
724 clk_enable(dev->clk);
725
726 dev->dev = &pdev->dev;
727 dev_set_drvdata(&pdev->dev, dev);
728
729 ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
730 &davinci_i2s_dai, 1);
731 if (ret != 0)
732 goto err_release_clk;
733
734 ret = edma_pcm_platform_register(&pdev->dev);
735 if (ret) {
736 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
737 goto err_unregister_component;
738 }
739
740 return 0;
741
742 err_unregister_component:
743 snd_soc_unregister_component(&pdev->dev);
744 err_release_clk:
745 clk_disable(dev->clk);
746 clk_put(dev->clk);
747 return ret;
748 }
749
750 static int davinci_i2s_remove(struct platform_device *pdev)
751 {
752 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
753
754 snd_soc_unregister_component(&pdev->dev);
755
756 clk_disable(dev->clk);
757 clk_put(dev->clk);
758 dev->clk = NULL;
759
760 return 0;
761 }
762
763 static const struct of_device_id davinci_i2s_match[] = {
764 { .compatible = "ti,da850-mcbsp" },
765 {},
766 };
767 MODULE_DEVICE_TABLE(of, davinci_i2s_match);
768
769 static struct platform_driver davinci_mcbsp_driver = {
770 .probe = davinci_i2s_probe,
771 .remove = davinci_i2s_remove,
772 .driver = {
773 .name = "davinci-mcbsp",
774 .of_match_table = of_match_ptr(davinci_i2s_match),
775 },
776 };
777
778 module_platform_driver(davinci_mcbsp_driver);
779
780 MODULE_AUTHOR("Vladimir Barinov");
781 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
782 MODULE_LICENSE("GPL");
Linux with added FPC-III support