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drm/i915: fix port checks for MST support on gen >= 11
[linux/fpc-iii.git] / sound / soc / davinci / davinci-mcasp.c
blob14ab16e1369f8cf59501956c5cdb6828f69146e3
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39
40 #include "edma-pcm.h"
41 #include "../omap/sdma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 #ifdef CONFIG_PM
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
61 };
62
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
67 bool pm_state;
68 };
69 #endif
70
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74 };
75
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
78 void __iomem *base;
79 u32 fifo_base;
80 struct device *dev;
81 struct snd_pcm_substream *substreams[2];
82 unsigned int dai_fmt;
83
84 /* McASP specific data */
85 int tdm_slots;
86 u32 tdm_mask[2];
87 int slot_width;
88 u8 op_mode;
89 u8 num_serializer;
90 u8 *serial_dir;
91 u8 version;
92 u8 bclk_div;
93 int streams;
94 u32 irq_request[2];
95 int dma_request[2];
96
97 int sysclk_freq;
98 bool bclk_master;
99
100 /* McASP FIFO related */
101 u8 txnumevt;
102 u8 rxnumevt;
103
104 bool dat_port;
105
106 /* Used for comstraint setting on the second stream */
107 u32 channels;
108
109 #ifdef CONFIG_PM_SLEEP
110 struct davinci_mcasp_context context;
111 #endif
112
113 struct davinci_mcasp_ruledata ruledata[2];
114 struct snd_pcm_hw_constraint_list chconstr[2];
115 };
116
117 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
118 u32 val)
119 {
120 void __iomem *reg = mcasp->base + offset;
121 __raw_writel(__raw_readl(reg) | val, reg);
122 }
123
124 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
125 u32 val)
126 {
127 void __iomem *reg = mcasp->base + offset;
128 __raw_writel((__raw_readl(reg) & ~(val)), reg);
129 }
130
131 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
132 u32 val, u32 mask)
133 {
134 void __iomem *reg = mcasp->base + offset;
135 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
136 }
137
138 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
139 u32 val)
140 {
141 __raw_writel(val, mcasp->base + offset);
142 }
143
144 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
145 {
146 return (u32)__raw_readl(mcasp->base + offset);
147 }
148
149 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
150 {
151 int i = 0;
152
153 mcasp_set_bits(mcasp, ctl_reg, val);
154
155 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
156 /* loop count is to avoid the lock-up */
157 for (i = 0; i < 1000; i++) {
158 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
159 break;
160 }
161
162 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
163 printk(KERN_ERR "GBLCTL write error\n");
164 }
165
166 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
167 {
168 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
169 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
170
171 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
172 }
173
174 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
175 {
176 if (mcasp->rxnumevt) { /* enable FIFO */
177 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
178
179 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
180 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
181 }
182
183 /* Start clocks */
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
185 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
186 /*
187 * When ASYNC == 0 the transmit and receive sections operate
188 * synchronously from the transmit clock and frame sync. We need to make
189 * sure that the TX signlas are enabled when starting reception.
190 */
191 if (mcasp_is_synchronous(mcasp)) {
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
194 }
195
196 /* Activate serializer(s) */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
198 /* Release RX state machine */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
200 /* Release Frame Sync generator */
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
202 if (mcasp_is_synchronous(mcasp))
203 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
204
205 /* enable receive IRQs */
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
207 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
208 }
209
210 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
211 {
212 u32 cnt;
213
214 if (mcasp->txnumevt) { /* enable FIFO */
215 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
216
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
219 }
220
221 /* Start clocks */
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
224 /* Activate serializer(s) */
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
226
227 /* wait for XDATA to be cleared */
228 cnt = 0;
229 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
230 (cnt < 100000))
231 cnt++;
232
233 /* Release TX state machine */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
235 /* Release Frame Sync generator */
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
237
238 /* enable transmit IRQs */
239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
240 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
241 }
242
243 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
244 {
245 mcasp->streams++;
246
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
248 mcasp_start_tx(mcasp);
249 else
250 mcasp_start_rx(mcasp);
251 }
252
253 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
254 {
255 /* disable IRQ sources */
256 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
257 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
258
259 /*
260 * In synchronous mode stop the TX clocks if no other stream is
261 * running
262 */
263 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
265
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
268
269 if (mcasp->rxnumevt) { /* disable FIFO */
270 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
271
272 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
273 }
274 }
275
276 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
277 {
278 u32 val = 0;
279
280 /* disable IRQ sources */
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
283
284 /*
285 * In synchronous mode keep TX clocks running if the capture stream is
286 * still running.
287 */
288 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
289 val = TXHCLKRST | TXCLKRST | TXFSRST;
290
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
292 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
293
294 if (mcasp->txnumevt) { /* disable FIFO */
295 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
296
297 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
298 }
299 }
300
301 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
302 {
303 mcasp->streams--;
304
305 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
306 mcasp_stop_tx(mcasp);
307 else
308 mcasp_stop_rx(mcasp);
309 }
310
311 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
312 {
313 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
314 struct snd_pcm_substream *substream;
315 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
316 u32 handled_mask = 0;
317 u32 stat;
318
319 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
320 if (stat & XUNDRN & irq_mask) {
321 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
322 handled_mask |= XUNDRN;
323
324 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
325 if (substream)
326 snd_pcm_stop_xrun(substream);
327 }
328
329 if (!handled_mask)
330 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
331 stat);
332
333 if (stat & XRERR)
334 handled_mask |= XRERR;
335
336 /* Ack the handled event only */
337 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
338
339 return IRQ_RETVAL(handled_mask);
340 }
341
342 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
343 {
344 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
345 struct snd_pcm_substream *substream;
346 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
347 u32 handled_mask = 0;
348 u32 stat;
349
350 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
351 if (stat & ROVRN & irq_mask) {
352 dev_warn(mcasp->dev, "Receive buffer overflow\n");
353 handled_mask |= ROVRN;
354
355 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
356 if (substream)
357 snd_pcm_stop_xrun(substream);
358 }
359
360 if (!handled_mask)
361 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
362 stat);
363
364 if (stat & XRERR)
365 handled_mask |= XRERR;
366
367 /* Ack the handled event only */
368 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
369
370 return IRQ_RETVAL(handled_mask);
371 }
372
373 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
374 {
375 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
376 irqreturn_t ret = IRQ_NONE;
377
378 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
379 ret = davinci_mcasp_tx_irq_handler(irq, data);
380
381 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
382 ret |= davinci_mcasp_rx_irq_handler(irq, data);
383
384 return ret;
385 }
386
387 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
388 unsigned int fmt)
389 {
390 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
391 int ret = 0;
392 u32 data_delay;
393 bool fs_pol_rising;
394 bool inv_fs = false;
395
396 if (!fmt)
397 return 0;
398
399 pm_runtime_get_sync(mcasp->dev);
400 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
401 case SND_SOC_DAIFMT_DSP_A:
402 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
404 /* 1st data bit occur one ACLK cycle after the frame sync */
405 data_delay = 1;
406 break;
407 case SND_SOC_DAIFMT_DSP_B:
408 case SND_SOC_DAIFMT_AC97:
409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
411 /* No delay after FS */
412 data_delay = 0;
413 break;
414 case SND_SOC_DAIFMT_I2S:
415 /* configure a full-word SYNC pulse (LRCLK) */
416 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
417 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
418 /* 1st data bit occur one ACLK cycle after the frame sync */
419 data_delay = 1;
420 /* FS need to be inverted */
421 inv_fs = true;
422 break;
423 case SND_SOC_DAIFMT_LEFT_J:
424 /* configure a full-word SYNC pulse (LRCLK) */
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
427 /* No delay after FS */
428 data_delay = 0;
429 break;
430 default:
431 ret = -EINVAL;
432 goto out;
433 }
434
435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
436 FSXDLY(3));
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
438 FSRDLY(3));
439
440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
441 case SND_SOC_DAIFMT_CBS_CFS:
442 /* codec is clock and frame slave */
443 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
445
446 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
448
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
451 mcasp->bclk_master = 1;
452 break;
453 case SND_SOC_DAIFMT_CBS_CFM:
454 /* codec is clock slave and frame master */
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
457
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
460
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
463 mcasp->bclk_master = 1;
464 break;
465 case SND_SOC_DAIFMT_CBM_CFS:
466 /* codec is clock master and frame slave */
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
469
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
472
473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
475 mcasp->bclk_master = 0;
476 break;
477 case SND_SOC_DAIFMT_CBM_CFM:
478 /* codec is clock and frame master */
479 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
481
482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
484
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
486 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
487 mcasp->bclk_master = 0;
488 break;
489 default:
490 ret = -EINVAL;
491 goto out;
492 }
493
494 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
495 case SND_SOC_DAIFMT_IB_NF:
496 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
498 fs_pol_rising = true;
499 break;
500 case SND_SOC_DAIFMT_NB_IF:
501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
503 fs_pol_rising = false;
504 break;
505 case SND_SOC_DAIFMT_IB_IF:
506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
508 fs_pol_rising = false;
509 break;
510 case SND_SOC_DAIFMT_NB_NF:
511 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
513 fs_pol_rising = true;
514 break;
515 default:
516 ret = -EINVAL;
517 goto out;
518 }
519
520 if (inv_fs)
521 fs_pol_rising = !fs_pol_rising;
522
523 if (fs_pol_rising) {
524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
526 } else {
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
529 }
530
531 mcasp->dai_fmt = fmt;
532 out:
533 pm_runtime_put(mcasp->dev);
534 return ret;
535 }
536
537 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
538 int div, bool explicit)
539 {
540 pm_runtime_get_sync(mcasp->dev);
541 switch (div_id) {
542 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
544 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
546 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
547 break;
548
549 case MCASP_CLKDIV_BCLK: /* BCLK divider */
550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
551 ACLKXDIV(div - 1), ACLKXDIV_MASK);
552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
553 ACLKRDIV(div - 1), ACLKRDIV_MASK);
554 if (explicit)
555 mcasp->bclk_div = div;
556 break;
557
558 case MCASP_CLKDIV_BCLK_FS_RATIO:
559 /*
560 * BCLK/LRCLK ratio descries how many bit-clock cycles
561 * fit into one frame. The clock ratio is given for a
562 * full period of data (for I2S format both left and
563 * right channels), so it has to be divided by number
564 * of tdm-slots (for I2S - divided by 2).
565 * Instead of storing this ratio, we calculate a new
566 * tdm_slot width by dividing the the ratio by the
567 * number of configured tdm slots.
568 */
569 mcasp->slot_width = div / mcasp->tdm_slots;
570 if (div % mcasp->tdm_slots)
571 dev_warn(mcasp->dev,
572 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
573 __func__, div, mcasp->tdm_slots);
574 break;
575
576 default:
577 return -EINVAL;
578 }
579
580 pm_runtime_put(mcasp->dev);
581 return 0;
582 }
583
584 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
585 int div)
586 {
587 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
588
589 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
590 }
591
592 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
593 unsigned int freq, int dir)
594 {
595 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
596
597 pm_runtime_get_sync(mcasp->dev);
598 if (dir == SND_SOC_CLOCK_OUT) {
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
601 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
602 } else {
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
605 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
606 }
607
608 mcasp->sysclk_freq = freq;
609
610 pm_runtime_put(mcasp->dev);
611 return 0;
612 }
613
614 /* All serializers must have equal number of channels */
615 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
616 int serializers)
617 {
618 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
619 unsigned int *list = (unsigned int *) cl->list;
620 int slots = mcasp->tdm_slots;
621 int i, count = 0;
622
623 if (mcasp->tdm_mask[stream])
624 slots = hweight32(mcasp->tdm_mask[stream]);
625
626 for (i = 1; i <= slots; i++)
627 list[count++] = i;
628
629 for (i = 2; i <= serializers; i++)
630 list[count++] = i*slots;
631
632 cl->count = count;
633
634 return 0;
635 }
636
637 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
638 {
639 int rx_serializers = 0, tx_serializers = 0, ret, i;
640
641 for (i = 0; i < mcasp->num_serializer; i++)
642 if (mcasp->serial_dir[i] == TX_MODE)
643 tx_serializers++;
644 else if (mcasp->serial_dir[i] == RX_MODE)
645 rx_serializers++;
646
647 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
648 tx_serializers);
649 if (ret)
650 return ret;
651
652 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
653 rx_serializers);
654
655 return ret;
656 }
657
658
659 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
660 unsigned int tx_mask,
661 unsigned int rx_mask,
662 int slots, int slot_width)
663 {
664 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
665
666 dev_dbg(mcasp->dev,
667 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
668 __func__, tx_mask, rx_mask, slots, slot_width);
669
670 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
671 dev_err(mcasp->dev,
672 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
673 tx_mask, rx_mask, slots);
674 return -EINVAL;
675 }
676
677 if (slot_width &&
678 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
679 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
680 __func__, slot_width);
681 return -EINVAL;
682 }
683
684 mcasp->tdm_slots = slots;
685 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
686 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
687 mcasp->slot_width = slot_width;
688
689 return davinci_mcasp_set_ch_constraints(mcasp);
690 }
691
692 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
693 int sample_width)
694 {
695 u32 fmt;
696 u32 tx_rotate = (sample_width / 4) & 0x7;
697 u32 mask = (1ULL << sample_width) - 1;
698 u32 slot_width = sample_width;
699
700 /*
701 * For captured data we should not rotate, inversion and masking is
702 * enoguh to get the data to the right position:
703 * Format data from bus after reverse (XRBUF)
704 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
705 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
706 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
707 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
708 */
709 u32 rx_rotate = 0;
710
711 /*
712 * Setting the tdm slot width either with set_clkdiv() or
713 * set_tdm_slot() allows us to for example send 32 bits per
714 * channel to the codec, while only 16 of them carry audio
715 * payload.
716 */
717 if (mcasp->slot_width) {
718 /*
719 * When we have more bclk then it is needed for the
720 * data, we need to use the rotation to move the
721 * received samples to have correct alignment.
722 */
723 slot_width = mcasp->slot_width;
724 rx_rotate = (slot_width - sample_width) / 4;
725 }
726
727 /* mapping of the XSSZ bit-field as described in the datasheet */
728 fmt = (slot_width >> 1) - 1;
729
730 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
731 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
732 RXSSZ(0x0F));
733 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
734 TXSSZ(0x0F));
735 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
736 TXROT(7));
737 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
738 RXROT(7));
739 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
740 }
741
742 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
743
744 return 0;
745 }
746
747 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
748 int period_words, int channels)
749 {
750 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
751 int i;
752 u8 tx_ser = 0;
753 u8 rx_ser = 0;
754 u8 slots = mcasp->tdm_slots;
755 u8 max_active_serializers = (channels + slots - 1) / slots;
756 int active_serializers, numevt;
757 u32 reg;
758 /* Default configuration */
759 if (mcasp->version < MCASP_VERSION_3)
760 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
761
762 /* All PINS as McASP */
763 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
764
765 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
766 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
767 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
768 } else {
769 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
770 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
771 }
772
773 for (i = 0; i < mcasp->num_serializer; i++) {
774 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
775 mcasp->serial_dir[i]);
776 if (mcasp->serial_dir[i] == TX_MODE &&
777 tx_ser < max_active_serializers) {
778 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
779 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
780 DISMOD_LOW, DISMOD_MASK);
781 tx_ser++;
782 } else if (mcasp->serial_dir[i] == RX_MODE &&
783 rx_ser < max_active_serializers) {
784 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
785 rx_ser++;
786 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
787 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
788 SRMOD_INACTIVE, SRMOD_MASK);
789 }
790 }
791
792 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
793 active_serializers = tx_ser;
794 numevt = mcasp->txnumevt;
795 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
796 } else {
797 active_serializers = rx_ser;
798 numevt = mcasp->rxnumevt;
799 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
800 }
801
802 if (active_serializers < max_active_serializers) {
803 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
804 "enabled in mcasp (%d)\n", channels,
805 active_serializers * slots);
806 return -EINVAL;
807 }
808
809 /* AFIFO is not in use */
810 if (!numevt) {
811 /* Configure the burst size for platform drivers */
812 if (active_serializers > 1) {
813 /*
814 * If more than one serializers are in use we have one
815 * DMA request to provide data for all serializers.
816 * For example if three serializers are enabled the DMA
817 * need to transfer three words per DMA request.
818 */
819 dma_data->maxburst = active_serializers;
820 } else {
821 dma_data->maxburst = 0;
822 }
823 return 0;
824 }
825
826 if (period_words % active_serializers) {
827 dev_err(mcasp->dev, "Invalid combination of period words and "
828 "active serializers: %d, %d\n", period_words,
829 active_serializers);
830 return -EINVAL;
831 }
832
833 /*
834 * Calculate the optimal AFIFO depth for platform side:
835 * The number of words for numevt need to be in steps of active
836 * serializers.
837 */
838 numevt = (numevt / active_serializers) * active_serializers;
839
840 while (period_words % numevt && numevt > 0)
841 numevt -= active_serializers;
842 if (numevt <= 0)
843 numevt = active_serializers;
844
845 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
846 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
847
848 /* Configure the burst size for platform drivers */
849 if (numevt == 1)
850 numevt = 0;
851 dma_data->maxburst = numevt;
852
853 return 0;
854 }
855
856 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
857 int channels)
858 {
859 int i, active_slots;
860 int total_slots;
861 int active_serializers;
862 u32 mask = 0;
863 u32 busel = 0;
864
865 total_slots = mcasp->tdm_slots;
866
867 /*
868 * If more than one serializer is needed, then use them with
869 * all the specified tdm_slots. Otherwise, one serializer can
870 * cope with the transaction using just as many slots as there
871 * are channels in the stream.
872 */
873 if (mcasp->tdm_mask[stream]) {
874 active_slots = hweight32(mcasp->tdm_mask[stream]);
875 active_serializers = (channels + active_slots - 1) /
876 active_slots;
877 if (active_serializers == 1)
878 active_slots = channels;
879 for (i = 0; i < total_slots; i++) {
880 if ((1 << i) & mcasp->tdm_mask[stream]) {
881 mask |= (1 << i);
882 if (--active_slots <= 0)
883 break;
884 }
885 }
886 } else {
887 active_serializers = (channels + total_slots - 1) / total_slots;
888 if (active_serializers == 1)
889 active_slots = channels;
890 else
891 active_slots = total_slots;
892
893 for (i = 0; i < active_slots; i++)
894 mask |= (1 << i);
895 }
896 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
897
898 if (!mcasp->dat_port)
899 busel = TXSEL;
900
901 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
902 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
903 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
904 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
905 FSXMOD(total_slots), FSXMOD(0x1FF));
906 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
907 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
908 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
909 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
910 FSRMOD(total_slots), FSRMOD(0x1FF));
911 /*
912 * If McASP is set to be TX/RX synchronous and the playback is
913 * not running already we need to configure the TX slots in
914 * order to have correct FSX on the bus
915 */
916 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
917 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
918 FSXMOD(total_slots), FSXMOD(0x1FF));
919 }
920
921 return 0;
922 }
923
924 /* S/PDIF */
925 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
926 unsigned int rate)
927 {
928 u32 cs_value = 0;
929 u8 *cs_bytes = (u8*) &cs_value;
930
931 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
932 and LSB first */
933 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
934
935 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
936 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
937
938 /* Set the TX tdm : for all the slots */
939 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
940
941 /* Set the TX clock controls : div = 1 and internal */
942 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
943
944 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
945
946 /* Only 44100 and 48000 are valid, both have the same setting */
947 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
948
949 /* Enable the DIT */
950 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
951
952 /* Set S/PDIF channel status bits */
953 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
954 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
955
956 switch (rate) {
957 case 22050:
958 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
959 break;
960 case 24000:
961 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
962 break;
963 case 32000:
964 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
965 break;
966 case 44100:
967 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
968 break;
969 case 48000:
970 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
971 break;
972 case 88200:
973 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
974 break;
975 case 96000:
976 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
977 break;
978 case 176400:
979 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
980 break;
981 case 192000:
982 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
983 break;
984 default:
985 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
986 return -EINVAL;
987 }
988
989 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
990 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
991
992 return 0;
993 }
994
995 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
996 unsigned int bclk_freq, bool set)
997 {
998 int error_ppm;
999 unsigned int sysclk_freq = mcasp->sysclk_freq;
1000 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1001 int div = sysclk_freq / bclk_freq;
1002 int rem = sysclk_freq % bclk_freq;
1003 int aux_div = 1;
1004
1005 if (div > (ACLKXDIV_MASK + 1)) {
1006 if (reg & AHCLKXE) {
1007 aux_div = div / (ACLKXDIV_MASK + 1);
1008 if (div % (ACLKXDIV_MASK + 1))
1009 aux_div++;
1010
1011 sysclk_freq /= aux_div;
1012 div = sysclk_freq / bclk_freq;
1013 rem = sysclk_freq % bclk_freq;
1014 } else if (set) {
1015 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1016 sysclk_freq);
1017 }
1018 }
1019
1020 if (rem != 0) {
1021 if (div == 0 ||
1022 ((sysclk_freq / div) - bclk_freq) >
1023 (bclk_freq - (sysclk_freq / (div+1)))) {
1024 div++;
1025 rem = rem - bclk_freq;
1026 }
1027 }
1028 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1029 (int)bclk_freq)) / div - 1000000;
1030
1031 if (set) {
1032 if (error_ppm)
1033 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1034 error_ppm);
1035
1036 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1037 if (reg & AHCLKXE)
1038 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1039 aux_div, 0);
1040 }
1041
1042 return error_ppm;
1043 }
1044
1045 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1046 struct snd_pcm_hw_params *params,
1047 struct snd_soc_dai *cpu_dai)
1048 {
1049 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1050 int word_length;
1051 int channels = params_channels(params);
1052 int period_size = params_period_size(params);
1053 int ret;
1054
1055 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1056 if (ret)
1057 return ret;
1058
1059 /*
1060 * If mcasp is BCLK master, and a BCLK divider was not provided by
1061 * the machine driver, we need to calculate the ratio.
1062 */
1063 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1064 int slots = mcasp->tdm_slots;
1065 int rate = params_rate(params);
1066 int sbits = params_width(params);
1067
1068 if (mcasp->slot_width)
1069 sbits = mcasp->slot_width;
1070
1071 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1072 }
1073
1074 ret = mcasp_common_hw_param(mcasp, substream->stream,
1075 period_size * channels, channels);
1076 if (ret)
1077 return ret;
1078
1079 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1080 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1081 else
1082 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1083 channels);
1084
1085 if (ret)
1086 return ret;
1087
1088 switch (params_format(params)) {
1089 case SNDRV_PCM_FORMAT_U8:
1090 case SNDRV_PCM_FORMAT_S8:
1091 word_length = 8;
1092 break;
1093
1094 case SNDRV_PCM_FORMAT_U16_LE:
1095 case SNDRV_PCM_FORMAT_S16_LE:
1096 word_length = 16;
1097 break;
1098
1099 case SNDRV_PCM_FORMAT_U24_3LE:
1100 case SNDRV_PCM_FORMAT_S24_3LE:
1101 word_length = 24;
1102 break;
1103
1104 case SNDRV_PCM_FORMAT_U24_LE:
1105 case SNDRV_PCM_FORMAT_S24_LE:
1106 word_length = 24;
1107 break;
1108
1109 case SNDRV_PCM_FORMAT_U32_LE:
1110 case SNDRV_PCM_FORMAT_S32_LE:
1111 word_length = 32;
1112 break;
1113
1114 default:
1115 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1116 return -EINVAL;
1117 }
1118
1119 davinci_config_channel_size(mcasp, word_length);
1120
1121 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1122 mcasp->channels = channels;
1123
1124 return 0;
1125 }
1126
1127 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1128 int cmd, struct snd_soc_dai *cpu_dai)
1129 {
1130 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1131 int ret = 0;
1132
1133 switch (cmd) {
1134 case SNDRV_PCM_TRIGGER_RESUME:
1135 case SNDRV_PCM_TRIGGER_START:
1136 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1137 davinci_mcasp_start(mcasp, substream->stream);
1138 break;
1139 case SNDRV_PCM_TRIGGER_SUSPEND:
1140 case SNDRV_PCM_TRIGGER_STOP:
1141 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1142 davinci_mcasp_stop(mcasp, substream->stream);
1143 break;
1144
1145 default:
1146 ret = -EINVAL;
1147 }
1148
1149 return ret;
1150 }
1151
1152 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1153 struct snd_pcm_hw_rule *rule)
1154 {
1155 struct davinci_mcasp_ruledata *rd = rule->private;
1156 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1157 struct snd_mask nfmt;
1158 int i, slot_width;
1159
1160 snd_mask_none(&nfmt);
1161 slot_width = rd->mcasp->slot_width;
1162
1163 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1164 if (snd_mask_test(fmt, i)) {
1165 if (snd_pcm_format_width(i) <= slot_width) {
1166 snd_mask_set(&nfmt, i);
1167 }
1168 }
1169 }
1170
1171 return snd_mask_refine(fmt, &nfmt);
1172 }
1173
1174 static const unsigned int davinci_mcasp_dai_rates[] = {
1175 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1176 88200, 96000, 176400, 192000,
1177 };
1178
1179 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1180
1181 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1182 struct snd_pcm_hw_rule *rule)
1183 {
1184 struct davinci_mcasp_ruledata *rd = rule->private;
1185 struct snd_interval *ri =
1186 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1187 int sbits = params_width(params);
1188 int slots = rd->mcasp->tdm_slots;
1189 struct snd_interval range;
1190 int i;
1191
1192 if (rd->mcasp->slot_width)
1193 sbits = rd->mcasp->slot_width;
1194
1195 snd_interval_any(&range);
1196 range.empty = 1;
1197
1198 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1199 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1200 uint bclk_freq = sbits*slots*
1201 davinci_mcasp_dai_rates[i];
1202 int ppm;
1203
1204 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1205 false);
1206 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1207 if (range.empty) {
1208 range.min = davinci_mcasp_dai_rates[i];
1209 range.empty = 0;
1210 }
1211 range.max = davinci_mcasp_dai_rates[i];
1212 }
1213 }
1214 }
1215
1216 dev_dbg(rd->mcasp->dev,
1217 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1218 ri->min, ri->max, range.min, range.max, sbits, slots);
1219
1220 return snd_interval_refine(hw_param_interval(params, rule->var),
1221 &range);
1222 }
1223
1224 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1225 struct snd_pcm_hw_rule *rule)
1226 {
1227 struct davinci_mcasp_ruledata *rd = rule->private;
1228 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1229 struct snd_mask nfmt;
1230 int rate = params_rate(params);
1231 int slots = rd->mcasp->tdm_slots;
1232 int i, count = 0;
1233
1234 snd_mask_none(&nfmt);
1235
1236 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1237 if (snd_mask_test(fmt, i)) {
1238 uint sbits = snd_pcm_format_width(i);
1239 int ppm;
1240
1241 if (rd->mcasp->slot_width)
1242 sbits = rd->mcasp->slot_width;
1243
1244 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1245 sbits * slots * rate,
1246 false);
1247 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1248 snd_mask_set(&nfmt, i);
1249 count++;
1250 }
1251 }
1252 }
1253 dev_dbg(rd->mcasp->dev,
1254 "%d possible sample format for %d Hz and %d tdm slots\n",
1255 count, rate, slots);
1256
1257 return snd_mask_refine(fmt, &nfmt);
1258 }
1259
1260 static int davinci_mcasp_hw_rule_min_periodsize(
1261 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1262 {
1263 struct snd_interval *period_size = hw_param_interval(params,
1264 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1265 struct snd_interval frames;
1266
1267 snd_interval_any(&frames);
1268 frames.min = 64;
1269 frames.integer = 1;
1270
1271 return snd_interval_refine(period_size, &frames);
1272 }
1273
1274 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1275 struct snd_soc_dai *cpu_dai)
1276 {
1277 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1278 struct davinci_mcasp_ruledata *ruledata =
1279 &mcasp->ruledata[substream->stream];
1280 u32 max_channels = 0;
1281 int i, dir, ret;
1282 int tdm_slots = mcasp->tdm_slots;
1283
1284 /* Do not allow more then one stream per direction */
1285 if (mcasp->substreams[substream->stream])
1286 return -EBUSY;
1287
1288 mcasp->substreams[substream->stream] = substream;
1289
1290 if (mcasp->tdm_mask[substream->stream])
1291 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1292
1293 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1294 return 0;
1295
1296 /*
1297 * Limit the maximum allowed channels for the first stream:
1298 * number of serializers for the direction * tdm slots per serializer
1299 */
1300 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1301 dir = TX_MODE;
1302 else
1303 dir = RX_MODE;
1304
1305 for (i = 0; i < mcasp->num_serializer; i++) {
1306 if (mcasp->serial_dir[i] == dir)
1307 max_channels++;
1308 }
1309 ruledata->serializers = max_channels;
1310 ruledata->mcasp = mcasp;
1311 max_channels *= tdm_slots;
1312 /*
1313 * If the already active stream has less channels than the calculated
1314 * limnit based on the seirializers * tdm_slots, we need to use that as
1315 * a constraint for the second stream.
1316 * Otherwise (first stream or less allowed channels) we use the
1317 * calculated constraint.
1318 */
1319 if (mcasp->channels && mcasp->channels < max_channels)
1320 max_channels = mcasp->channels;
1321 /*
1322 * But we can always allow channels upto the amount of
1323 * the available tdm_slots.
1324 */
1325 if (max_channels < tdm_slots)
1326 max_channels = tdm_slots;
1327
1328 snd_pcm_hw_constraint_minmax(substream->runtime,
1329 SNDRV_PCM_HW_PARAM_CHANNELS,
1330 0, max_channels);
1331
1332 snd_pcm_hw_constraint_list(substream->runtime,
1333 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1334 &mcasp->chconstr[substream->stream]);
1335
1336 if (mcasp->slot_width) {
1337 /* Only allow formats require <= slot_width bits on the bus */
1338 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1339 SNDRV_PCM_HW_PARAM_FORMAT,
1340 davinci_mcasp_hw_rule_slot_width,
1341 ruledata,
1342 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1343 if (ret)
1344 return ret;
1345 }
1346
1347 /*
1348 * If we rely on implicit BCLK divider setting we should
1349 * set constraints based on what we can provide.
1350 */
1351 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1352 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1353 SNDRV_PCM_HW_PARAM_RATE,
1354 davinci_mcasp_hw_rule_rate,
1355 ruledata,
1356 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1357 if (ret)
1358 return ret;
1359 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1360 SNDRV_PCM_HW_PARAM_FORMAT,
1361 davinci_mcasp_hw_rule_format,
1362 ruledata,
1363 SNDRV_PCM_HW_PARAM_RATE, -1);
1364 if (ret)
1365 return ret;
1366 }
1367
1368 snd_pcm_hw_rule_add(substream->runtime, 0,
1369 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1370 davinci_mcasp_hw_rule_min_periodsize, NULL,
1371 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1372
1373 return 0;
1374 }
1375
1376 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1377 struct snd_soc_dai *cpu_dai)
1378 {
1379 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1380
1381 mcasp->substreams[substream->stream] = NULL;
1382
1383 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1384 return;
1385
1386 if (!cpu_dai->active)
1387 mcasp->channels = 0;
1388 }
1389
1390 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1391 .startup = davinci_mcasp_startup,
1392 .shutdown = davinci_mcasp_shutdown,
1393 .trigger = davinci_mcasp_trigger,
1394 .hw_params = davinci_mcasp_hw_params,
1395 .set_fmt = davinci_mcasp_set_dai_fmt,
1396 .set_clkdiv = davinci_mcasp_set_clkdiv,
1397 .set_sysclk = davinci_mcasp_set_sysclk,
1398 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1399 };
1400
1401 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1402 {
1403 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1404
1405 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1406 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1407
1408 return 0;
1409 }
1410
1411 #ifdef CONFIG_PM_SLEEP
1412 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1413 {
1414 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1415 struct davinci_mcasp_context *context = &mcasp->context;
1416 u32 reg;
1417 int i;
1418
1419 context->pm_state = pm_runtime_active(mcasp->dev);
1420 if (!context->pm_state)
1421 pm_runtime_get_sync(mcasp->dev);
1422
1423 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1424 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1425
1426 if (mcasp->txnumevt) {
1427 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1428 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1429 }
1430 if (mcasp->rxnumevt) {
1431 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1432 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1433 }
1434
1435 for (i = 0; i < mcasp->num_serializer; i++)
1436 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1437 DAVINCI_MCASP_XRSRCTL_REG(i));
1438
1439 pm_runtime_put_sync(mcasp->dev);
1440
1441 return 0;
1442 }
1443
1444 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1445 {
1446 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1447 struct davinci_mcasp_context *context = &mcasp->context;
1448 u32 reg;
1449 int i;
1450
1451 pm_runtime_get_sync(mcasp->dev);
1452
1453 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1454 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1455
1456 if (mcasp->txnumevt) {
1457 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1458 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1459 }
1460 if (mcasp->rxnumevt) {
1461 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1462 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1463 }
1464
1465 for (i = 0; i < mcasp->num_serializer; i++)
1466 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1467 context->xrsr_regs[i]);
1468
1469 if (!context->pm_state)
1470 pm_runtime_put_sync(mcasp->dev);
1471
1472 return 0;
1473 }
1474 #else
1475 #define davinci_mcasp_suspend NULL
1476 #define davinci_mcasp_resume NULL
1477 #endif
1478
1479 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1480
1481 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1482 SNDRV_PCM_FMTBIT_U8 | \
1483 SNDRV_PCM_FMTBIT_S16_LE | \
1484 SNDRV_PCM_FMTBIT_U16_LE | \
1485 SNDRV_PCM_FMTBIT_S24_LE | \
1486 SNDRV_PCM_FMTBIT_U24_LE | \
1487 SNDRV_PCM_FMTBIT_S24_3LE | \
1488 SNDRV_PCM_FMTBIT_U24_3LE | \
1489 SNDRV_PCM_FMTBIT_S32_LE | \
1490 SNDRV_PCM_FMTBIT_U32_LE)
1491
1492 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1493 {
1494 .name = "davinci-mcasp.0",
1495 .probe = davinci_mcasp_dai_probe,
1496 .suspend = davinci_mcasp_suspend,
1497 .resume = davinci_mcasp_resume,
1498 .playback = {
1499 .channels_min = 1,
1500 .channels_max = 32 * 16,
1501 .rates = DAVINCI_MCASP_RATES,
1502 .formats = DAVINCI_MCASP_PCM_FMTS,
1503 },
1504 .capture = {
1505 .channels_min = 1,
1506 .channels_max = 32 * 16,
1507 .rates = DAVINCI_MCASP_RATES,
1508 .formats = DAVINCI_MCASP_PCM_FMTS,
1509 },
1510 .ops = &davinci_mcasp_dai_ops,
1511
1512 .symmetric_samplebits = 1,
1513 .symmetric_rates = 1,
1514 },
1515 {
1516 .name = "davinci-mcasp.1",
1517 .probe = davinci_mcasp_dai_probe,
1518 .playback = {
1519 .channels_min = 1,
1520 .channels_max = 384,
1521 .rates = DAVINCI_MCASP_RATES,
1522 .formats = DAVINCI_MCASP_PCM_FMTS,
1523 },
1524 .ops = &davinci_mcasp_dai_ops,
1525 },
1526
1527 };
1528
1529 static const struct snd_soc_component_driver davinci_mcasp_component = {
1530 .name = "davinci-mcasp",
1531 };
1532
1533 /* Some HW specific values and defaults. The rest is filled in from DT. */
1534 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1535 .tx_dma_offset = 0x400,
1536 .rx_dma_offset = 0x400,
1537 .version = MCASP_VERSION_1,
1538 };
1539
1540 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1541 .tx_dma_offset = 0x2000,
1542 .rx_dma_offset = 0x2000,
1543 .version = MCASP_VERSION_2,
1544 };
1545
1546 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1547 .tx_dma_offset = 0,
1548 .rx_dma_offset = 0,
1549 .version = MCASP_VERSION_3,
1550 };
1551
1552 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1553 /* The CFG port offset will be calculated if it is needed */
1554 .tx_dma_offset = 0,
1555 .rx_dma_offset = 0,
1556 .version = MCASP_VERSION_4,
1557 };
1558
1559 static const struct of_device_id mcasp_dt_ids[] = {
1560 {
1561 .compatible = "ti,dm646x-mcasp-audio",
1562 .data = &dm646x_mcasp_pdata,
1563 },
1564 {
1565 .compatible = "ti,da830-mcasp-audio",
1566 .data = &da830_mcasp_pdata,
1567 },
1568 {
1569 .compatible = "ti,am33xx-mcasp-audio",
1570 .data = &am33xx_mcasp_pdata,
1571 },
1572 {
1573 .compatible = "ti,dra7-mcasp-audio",
1574 .data = &dra7_mcasp_pdata,
1575 },
1576 { /* sentinel */ }
1577 };
1578 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1579
1580 static int mcasp_reparent_fck(struct platform_device *pdev)
1581 {
1582 struct device_node *node = pdev->dev.of_node;
1583 struct clk *gfclk, *parent_clk;
1584 const char *parent_name;
1585 int ret;
1586
1587 if (!node)
1588 return 0;
1589
1590 parent_name = of_get_property(node, "fck_parent", NULL);
1591 if (!parent_name)
1592 return 0;
1593
1594 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1595
1596 gfclk = clk_get(&pdev->dev, "fck");
1597 if (IS_ERR(gfclk)) {
1598 dev_err(&pdev->dev, "failed to get fck\n");
1599 return PTR_ERR(gfclk);
1600 }
1601
1602 parent_clk = clk_get(NULL, parent_name);
1603 if (IS_ERR(parent_clk)) {
1604 dev_err(&pdev->dev, "failed to get parent clock\n");
1605 ret = PTR_ERR(parent_clk);
1606 goto err1;
1607 }
1608
1609 ret = clk_set_parent(gfclk, parent_clk);
1610 if (ret) {
1611 dev_err(&pdev->dev, "failed to reparent fck\n");
1612 goto err2;
1613 }
1614
1615 err2:
1616 clk_put(parent_clk);
1617 err1:
1618 clk_put(gfclk);
1619 return ret;
1620 }
1621
1622 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1623 struct platform_device *pdev)
1624 {
1625 struct device_node *np = pdev->dev.of_node;
1626 struct davinci_mcasp_pdata *pdata = NULL;
1627 const struct of_device_id *match =
1628 of_match_device(mcasp_dt_ids, &pdev->dev);
1629 struct of_phandle_args dma_spec;
1630
1631 const u32 *of_serial_dir32;
1632 u32 val;
1633 int i, ret = 0;
1634
1635 if (pdev->dev.platform_data) {
1636 pdata = pdev->dev.platform_data;
1637 return pdata;
1638 } else if (match) {
1639 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1640 GFP_KERNEL);
1641 if (!pdata) {
1642 ret = -ENOMEM;
1643 return pdata;
1644 }
1645 } else {
1646 /* control shouldn't reach here. something is wrong */
1647 ret = -EINVAL;
1648 goto nodata;
1649 }
1650
1651 ret = of_property_read_u32(np, "op-mode", &val);
1652 if (ret >= 0)
1653 pdata->op_mode = val;
1654
1655 ret = of_property_read_u32(np, "tdm-slots", &val);
1656 if (ret >= 0) {
1657 if (val < 2 || val > 32) {
1658 dev_err(&pdev->dev,
1659 "tdm-slots must be in rage [2-32]\n");
1660 ret = -EINVAL;
1661 goto nodata;
1662 }
1663
1664 pdata->tdm_slots = val;
1665 }
1666
1667 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1668 val /= sizeof(u32);
1669 if (of_serial_dir32) {
1670 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1671 (sizeof(*of_serial_dir) * val),
1672 GFP_KERNEL);
1673 if (!of_serial_dir) {
1674 ret = -ENOMEM;
1675 goto nodata;
1676 }
1677
1678 for (i = 0; i < val; i++)
1679 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1680
1681 pdata->num_serializer = val;
1682 pdata->serial_dir = of_serial_dir;
1683 }
1684
1685 ret = of_property_match_string(np, "dma-names", "tx");
1686 if (ret < 0)
1687 goto nodata;
1688
1689 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1690 &dma_spec);
1691 if (ret < 0)
1692 goto nodata;
1693
1694 pdata->tx_dma_channel = dma_spec.args[0];
1695
1696 /* RX is not valid in DIT mode */
1697 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1698 ret = of_property_match_string(np, "dma-names", "rx");
1699 if (ret < 0)
1700 goto nodata;
1701
1702 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1703 &dma_spec);
1704 if (ret < 0)
1705 goto nodata;
1706
1707 pdata->rx_dma_channel = dma_spec.args[0];
1708 }
1709
1710 ret = of_property_read_u32(np, "tx-num-evt", &val);
1711 if (ret >= 0)
1712 pdata->txnumevt = val;
1713
1714 ret = of_property_read_u32(np, "rx-num-evt", &val);
1715 if (ret >= 0)
1716 pdata->rxnumevt = val;
1717
1718 ret = of_property_read_u32(np, "sram-size-playback", &val);
1719 if (ret >= 0)
1720 pdata->sram_size_playback = val;
1721
1722 ret = of_property_read_u32(np, "sram-size-capture", &val);
1723 if (ret >= 0)
1724 pdata->sram_size_capture = val;
1725
1726 return pdata;
1727
1728 nodata:
1729 if (ret < 0) {
1730 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1731 ret);
1732 pdata = NULL;
1733 }
1734 return pdata;
1735 }
1736
1737 enum {
1738 PCM_EDMA,
1739 PCM_SDMA,
1740 };
1741 static const char *sdma_prefix = "ti,omap";
1742
1743 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1744 {
1745 struct dma_chan *chan;
1746 const char *tmp;
1747 int ret = PCM_EDMA;
1748
1749 if (!mcasp->dev->of_node)
1750 return PCM_EDMA;
1751
1752 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1753 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1754 if (IS_ERR(chan)) {
1755 if (PTR_ERR(chan) != -EPROBE_DEFER)
1756 dev_err(mcasp->dev,
1757 "Can't verify DMA configuration (%ld)\n",
1758 PTR_ERR(chan));
1759 return PTR_ERR(chan);
1760 }
1761 if (WARN_ON(!chan->device || !chan->device->dev))
1762 return -EINVAL;
1763
1764 if (chan->device->dev->of_node)
1765 ret = of_property_read_string(chan->device->dev->of_node,
1766 "compatible", &tmp);
1767 else
1768 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1769
1770 dma_release_channel(chan);
1771 if (ret)
1772 return ret;
1773
1774 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1775 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1776 return PCM_SDMA;
1777
1778 return PCM_EDMA;
1779 }
1780
1781 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1782 {
1783 int i;
1784 u32 offset = 0;
1785
1786 if (pdata->version != MCASP_VERSION_4)
1787 return pdata->tx_dma_offset;
1788
1789 for (i = 0; i < pdata->num_serializer; i++) {
1790 if (pdata->serial_dir[i] == TX_MODE) {
1791 if (!offset) {
1792 offset = DAVINCI_MCASP_TXBUF_REG(i);
1793 } else {
1794 pr_err("%s: Only one serializer allowed!\n",
1795 __func__);
1796 break;
1797 }
1798 }
1799 }
1800
1801 return offset;
1802 }
1803
1804 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1805 {
1806 int i;
1807 u32 offset = 0;
1808
1809 if (pdata->version != MCASP_VERSION_4)
1810 return pdata->rx_dma_offset;
1811
1812 for (i = 0; i < pdata->num_serializer; i++) {
1813 if (pdata->serial_dir[i] == RX_MODE) {
1814 if (!offset) {
1815 offset = DAVINCI_MCASP_RXBUF_REG(i);
1816 } else {
1817 pr_err("%s: Only one serializer allowed!\n",
1818 __func__);
1819 break;
1820 }
1821 }
1822 }
1823
1824 return offset;
1825 }
1826
1827 static int davinci_mcasp_probe(struct platform_device *pdev)
1828 {
1829 struct snd_dmaengine_dai_dma_data *dma_data;
1830 struct resource *mem, *res, *dat;
1831 struct davinci_mcasp_pdata *pdata;
1832 struct davinci_mcasp *mcasp;
1833 char *irq_name;
1834 int *dma;
1835 int irq;
1836 int ret;
1837
1838 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1839 dev_err(&pdev->dev, "No platform data supplied\n");
1840 return -EINVAL;
1841 }
1842
1843 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1844 GFP_KERNEL);
1845 if (!mcasp)
1846 return -ENOMEM;
1847
1848 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1849 if (!pdata) {
1850 dev_err(&pdev->dev, "no platform data\n");
1851 return -EINVAL;
1852 }
1853
1854 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1855 if (!mem) {
1856 dev_warn(mcasp->dev,
1857 "\"mpu\" mem resource not found, using index 0\n");
1858 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1859 if (!mem) {
1860 dev_err(&pdev->dev, "no mem resource?\n");
1861 return -ENODEV;
1862 }
1863 }
1864
1865 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1866 if (IS_ERR(mcasp->base))
1867 return PTR_ERR(mcasp->base);
1868
1869 pm_runtime_enable(&pdev->dev);
1870
1871 mcasp->op_mode = pdata->op_mode;
1872 /* sanity check for tdm slots parameter */
1873 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1874 if (pdata->tdm_slots < 2) {
1875 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1876 pdata->tdm_slots);
1877 mcasp->tdm_slots = 2;
1878 } else if (pdata->tdm_slots > 32) {
1879 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1880 pdata->tdm_slots);
1881 mcasp->tdm_slots = 32;
1882 } else {
1883 mcasp->tdm_slots = pdata->tdm_slots;
1884 }
1885 }
1886
1887 mcasp->num_serializer = pdata->num_serializer;
1888 #ifdef CONFIG_PM_SLEEP
1889 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1890 mcasp->num_serializer, sizeof(u32),
1891 GFP_KERNEL);
1892 if (!mcasp->context.xrsr_regs) {
1893 ret = -ENOMEM;
1894 goto err;
1895 }
1896 #endif
1897 mcasp->serial_dir = pdata->serial_dir;
1898 mcasp->version = pdata->version;
1899 mcasp->txnumevt = pdata->txnumevt;
1900 mcasp->rxnumevt = pdata->rxnumevt;
1901
1902 mcasp->dev = &pdev->dev;
1903
1904 irq = platform_get_irq_byname(pdev, "common");
1905 if (irq >= 0) {
1906 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1907 dev_name(&pdev->dev));
1908 if (!irq_name) {
1909 ret = -ENOMEM;
1910 goto err;
1911 }
1912 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1913 davinci_mcasp_common_irq_handler,
1914 IRQF_ONESHOT | IRQF_SHARED,
1915 irq_name, mcasp);
1916 if (ret) {
1917 dev_err(&pdev->dev, "common IRQ request failed\n");
1918 goto err;
1919 }
1920
1921 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1922 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1923 }
1924
1925 irq = platform_get_irq_byname(pdev, "rx");
1926 if (irq >= 0) {
1927 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1928 dev_name(&pdev->dev));
1929 if (!irq_name) {
1930 ret = -ENOMEM;
1931 goto err;
1932 }
1933 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1934 davinci_mcasp_rx_irq_handler,
1935 IRQF_ONESHOT, irq_name, mcasp);
1936 if (ret) {
1937 dev_err(&pdev->dev, "RX IRQ request failed\n");
1938 goto err;
1939 }
1940
1941 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1942 }
1943
1944 irq = platform_get_irq_byname(pdev, "tx");
1945 if (irq >= 0) {
1946 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1947 dev_name(&pdev->dev));
1948 if (!irq_name) {
1949 ret = -ENOMEM;
1950 goto err;
1951 }
1952 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1953 davinci_mcasp_tx_irq_handler,
1954 IRQF_ONESHOT, irq_name, mcasp);
1955 if (ret) {
1956 dev_err(&pdev->dev, "TX IRQ request failed\n");
1957 goto err;
1958 }
1959
1960 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1961 }
1962
1963 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1964 if (dat)
1965 mcasp->dat_port = true;
1966
1967 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1968 if (dat)
1969 dma_data->addr = dat->start;
1970 else
1971 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1972
1973 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1974 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1975 if (res)
1976 *dma = res->start;
1977 else
1978 *dma = pdata->tx_dma_channel;
1979
1980 /* dmaengine filter data for DT and non-DT boot */
1981 if (pdev->dev.of_node)
1982 dma_data->filter_data = "tx";
1983 else
1984 dma_data->filter_data = dma;
1985
1986 /* RX is not valid in DIT mode */
1987 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1988 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1989 if (dat)
1990 dma_data->addr = dat->start;
1991 else
1992 dma_data->addr =
1993 mem->start + davinci_mcasp_rxdma_offset(pdata);
1994
1995 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1996 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1997 if (res)
1998 *dma = res->start;
1999 else
2000 *dma = pdata->rx_dma_channel;
2001
2002 /* dmaengine filter data for DT and non-DT boot */
2003 if (pdev->dev.of_node)
2004 dma_data->filter_data = "rx";
2005 else
2006 dma_data->filter_data = dma;
2007 }
2008
2009 if (mcasp->version < MCASP_VERSION_3) {
2010 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2011 /* dma_params->dma_addr is pointing to the data port address */
2012 mcasp->dat_port = true;
2013 } else {
2014 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2015 }
2016
2017 /* Allocate memory for long enough list for all possible
2018 * scenarios. Maximum number tdm slots is 32 and there cannot
2019 * be more serializers than given in the configuration. The
2020 * serializer directions could be taken into account, but it
2021 * would make code much more complex and save only couple of
2022 * bytes.
2023 */
2024 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2025 devm_kcalloc(mcasp->dev,
2026 32 + mcasp->num_serializer - 1,
2027 sizeof(unsigned int),
2028 GFP_KERNEL);
2029
2030 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2031 devm_kcalloc(mcasp->dev,
2032 32 + mcasp->num_serializer - 1,
2033 sizeof(unsigned int),
2034 GFP_KERNEL);
2035
2036 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2037 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2038 ret = -ENOMEM;
2039 goto err;
2040 }
2041
2042 ret = davinci_mcasp_set_ch_constraints(mcasp);
2043 if (ret)
2044 goto err;
2045
2046 dev_set_drvdata(&pdev->dev, mcasp);
2047
2048 mcasp_reparent_fck(pdev);
2049
2050 ret = devm_snd_soc_register_component(&pdev->dev,
2051 &davinci_mcasp_component,
2052 &davinci_mcasp_dai[pdata->op_mode], 1);
2053
2054 if (ret != 0)
2055 goto err;
2056
2057 ret = davinci_mcasp_get_dma_type(mcasp);
2058 switch (ret) {
2059 case PCM_EDMA:
2060 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2061 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2062 IS_MODULE(CONFIG_SND_EDMA_SOC))
2063 ret = edma_pcm_platform_register(&pdev->dev);
2064 #else
2065 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2066 ret = -EINVAL;
2067 goto err;
2068 #endif
2069 break;
2070 case PCM_SDMA:
2071 #if IS_BUILTIN(CONFIG_SND_SDMA_SOC) || \
2072 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2073 IS_MODULE(CONFIG_SND_SDMA_SOC))
2074 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
2075 #else
2076 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2077 ret = -EINVAL;
2078 goto err;
2079 #endif
2080 break;
2081 default:
2082 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2083 case -EPROBE_DEFER:
2084 goto err;
2085 break;
2086 }
2087
2088 if (ret) {
2089 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2090 goto err;
2091 }
2092
2093 return 0;
2094
2095 err:
2096 pm_runtime_disable(&pdev->dev);
2097 return ret;
2098 }
2099
2100 static int davinci_mcasp_remove(struct platform_device *pdev)
2101 {
2102 pm_runtime_disable(&pdev->dev);
2103
2104 return 0;
2105 }
2106
2107 static struct platform_driver davinci_mcasp_driver = {
2108 .probe = davinci_mcasp_probe,
2109 .remove = davinci_mcasp_remove,
2110 .driver = {
2111 .name = "davinci-mcasp",
2112 .of_match_table = mcasp_dt_ids,
2113 },
2114 };
2115
2116 module_platform_driver(davinci_mcasp_driver);
2117
2118 MODULE_AUTHOR("Steve Chen");
2119 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2120 MODULE_LICENSE("GPL");
Linux with added FPC-III support