drivers/pcmcia/vg468.h

   1 /*
   2  * vg468.h 1.11 1999/10/25 20:03:34
   3  *
   4  * The contents of this file are subject to the Mozilla Public License
   5  * Version 1.1 (the "License"); you may not use this file except in
   6  * compliance with the License. You may obtain a copy of the License
   7  * at http://www.mozilla.org/MPL/
   8  *
   9  * Software distributed under the License is distributed on an "AS IS"
  10  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11  * the License for the specific language governing rights and
  12  * limitations under the License.
  13  *
  14  * The initial developer of the original code is David A. Hinds
  15  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
  16  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
  17  *
  18  * Alternatively, the contents of this file may be used under the
  19  * terms of the GNU General Public License version 2 (the "GPL"), in which
  20  * case the provisions of the GPL are applicable instead of the
  21  * above.  If you wish to allow the use of your version of this file
  22  * only under the terms of the GPL and not to allow others to use
  23  * your version of this file under the MPL, indicate your decision by
  24  * deleting the provisions above and replace them with the notice and
  25  * other provisions required by the GPL.  If you do not delete the
  26  * provisions above, a recipient may use your version of this file
  27  * under either the MPL or the GPL.
  28  */
  29
  30 #ifndef _LINUX_VG468_H
  31 #define _LINUX_VG468_H
  32
  33 /* Special bit in I365_IDENT used for Vadem chip detection */
  34 #define I365_IDENT_VADEM        0x08
  35
  36 /* Special definitions in I365_POWER */
  37 #define VG468_VPP2_MASK         0x0c
  38 #define VG468_VPP2_5V           0x04
  39 #define VG468_VPP2_12V          0x08
  40
  41 /* Unique Vadem registers */
  42 #define VG469_VSENSE            0x1f    /* Card voltage sense */
  43 #define VG469_VSELECT           0x2f    /* Card voltage select */
  44 #define VG468_CTL               0x38    /* Control register */
  45 #define VG468_TIMER             0x39    /* Timer control */
  46 #define VG468_MISC              0x3a    /* Miscellaneous */
  47 #define VG468_GPIO_CFG          0x3b    /* GPIO configuration */
  48 #define VG469_EXT_MODE          0x3c    /* Extended mode register */
  49 #define VG468_SELECT            0x3d    /* Programmable chip select */
  50 #define VG468_SELECT_CFG        0x3e    /* Chip select configuration */
  51 #define VG468_ATA               0x3f    /* ATA control */
  52
  53 /* Flags for VG469_VSENSE */
  54 #define VG469_VSENSE_A_VS1      0x01
  55 #define VG469_VSENSE_A_VS2      0x02
  56 #define VG469_VSENSE_B_VS1      0x04
  57 #define VG469_VSENSE_B_VS2      0x08
  58
  59 /* Flags for VG469_VSELECT */
  60 #define VG469_VSEL_VCC          0x03
  61 #define VG469_VSEL_5V           0x00
  62 #define VG469_VSEL_3V           0x03
  63 #define VG469_VSEL_MAX          0x0c
  64 #define VG469_VSEL_EXT_STAT     0x10
  65 #define VG469_VSEL_EXT_BUS      0x20
  66 #define VG469_VSEL_MIXED        0x40
  67 #define VG469_VSEL_ISA          0x80
  68
  69 /* Flags for VG468_CTL */
  70 #define VG468_CTL_SLOW          0x01    /* 600ns memory timing */
  71 #define VG468_CTL_ASYNC         0x02    /* Asynchronous bus clocking */
  72 #define VG468_CTL_TSSI          0x08    /* Tri-state some outputs */
  73 #define VG468_CTL_DELAY         0x10    /* Card detect debounce */
  74 #define VG468_CTL_INPACK        0x20    /* Obey INPACK signal? */
  75 #define VG468_CTL_POLARITY      0x40    /* VCCEN polarity */
  76 #define VG468_CTL_COMPAT        0x80    /* Compatibility stuff */
  77
  78 #define VG469_CTL_WS_COMPAT     0x04    /* Wait state compatibility */
  79 #define VG469_CTL_STRETCH       0x10    /* LED stretch */
  80
  81 /* Flags for VG468_TIMER */
  82 #define VG468_TIMER_ZEROPWR     0x10    /* Zero power control */
  83 #define VG468_TIMER_SIGEN       0x20    /* Power up */
  84 #define VG468_TIMER_STATUS      0x40    /* Activity timer status */
  85 #define VG468_TIMER_RES         0x80    /* Timer resolution */
  86 #define VG468_TIMER_MASK        0x0f    /* Activity timer timeout */
  87
  88 /* Flags for VG468_MISC */
  89 #define VG468_MISC_GPIO         0x04    /* General-purpose IO */
  90 #define VG468_MISC_DMAWSB       0x08    /* DMA wait state control */
  91 #define VG469_MISC_LEDENA       0x10    /* LED enable */
  92 #define VG468_MISC_VADEMREV     0x40    /* Vadem revision control */
  93 #define VG468_MISC_UNLOCK       0x80    /* Unique register lock */
  94
  95 /* Flags for VG469_EXT_MODE_A */
  96 #define VG469_MODE_VPPST        0x03    /* Vpp steering control */
  97 #define VG469_MODE_INT_SENSE    0x04    /* Internal voltage sense */
  98 #define VG469_MODE_CABLE        0x08
  99 #define VG469_MODE_COMPAT       0x10    /* i82365sl B or DF step */
 100 #define VG469_MODE_TEST         0x20
 101 #define VG469_MODE_RIO          0x40    /* Steer RIO to INTR? */
 102
 103 /* Flags for VG469_EXT_MODE_B */
 104 #define VG469_MODE_B_3V         0x01    /* 3.3v for socket B */
 105
 106 #endif /* _LINUX_VG468_H */