drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <linux/slab.h>
  33 #include <video/mipi_display.h>
  34 #include <asm/intel-mid.h>
  35 #include <video/mipi_display.h>
  36 #include "i915_drv.h"
  37 #include "intel_drv.h"
  38 #include "intel_dsi.h"
  39
  40 struct vbt_panel {
  41         struct drm_panel panel;
  42         struct intel_dsi *intel_dsi;
  43 };
  44
  45 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
  46 {
  47         return container_of(panel, struct vbt_panel, panel);
  48 }
  49
  50 #define MIPI_TRANSFER_MODE_SHIFT        0
  51 #define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  52 #define MIPI_PORT_SHIFT                 3
  53
  54 #define PREPARE_CNT_MAX         0x3F
  55 #define EXIT_ZERO_CNT_MAX       0x3F
  56 #define CLK_ZERO_CNT_MAX        0xFF
  57 #define TRAIL_CNT_MAX           0x1F
  58
  59 #define NS_KHZ_RATIO 1000000
  60
  61 #define GPI0_NC_0_HV_DDI0_HPD           0x4130
  62 #define GPIO_NC_0_HV_DDI0_PAD           0x4138
  63 #define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
  64 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
  65 #define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
  66 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
  67 #define GPIO_NC_3_PANEL0_VDDEN          0x4140
  68 #define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
  69 #define GPIO_NC_4_PANEL0_BLKEN          0x4150
  70 #define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
  71 #define GPIO_NC_5_PANEL0_BLKCTL         0x4160
  72 #define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
  73 #define GPIO_NC_6_PCONF0                0x4180
  74 #define GPIO_NC_6_PAD                   0x4188
  75 #define GPIO_NC_7_PCONF0                0x4190
  76 #define GPIO_NC_7_PAD                   0x4198
  77 #define GPIO_NC_8_PCONF0                0x4170
  78 #define GPIO_NC_8_PAD                   0x4178
  79 #define GPIO_NC_9_PCONF0                0x4100
  80 #define GPIO_NC_9_PAD                   0x4108
  81 #define GPIO_NC_10_PCONF0               0x40E0
  82 #define GPIO_NC_10_PAD                  0x40E8
  83 #define GPIO_NC_11_PCONF0               0x40F0
  84 #define GPIO_NC_11_PAD                  0x40F8
  85
  86 struct gpio_table {
  87         u16 function_reg;
  88         u16 pad_reg;
  89         u8 init;
  90 };
  91
  92 static struct gpio_table gtable[] = {
  93         { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
  94         { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
  95         { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
  96         { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
  97         { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
  98         { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
  99         { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
 100         { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
 101         { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
 102         { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
 103         { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
 104         { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 105 };
 106
 107 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 108 {
 109         return port ? PORT_C : PORT_A;
 110 }
 111
 112 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 113                                        const u8 *data)
 114 {
 115         struct mipi_dsi_device *dsi_device;
 116         u8 type, flags, seq_port;
 117         u16 len;
 118         enum port port;
 119
 120         flags = *data++;
 121         type = *data++;
 122
 123         len = *((u16 *) data);
 124         data += 2;
 125
 126         seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 127
 128         /* For DSI single link on Port A & C, the seq_port value which is
 129          * parsed from Sequence Block#53 of VBT has been set to 0
 130          * Now, read/write of packets for the DSI single link on Port A and
 131          * Port C will based on the DVO port from VBT block 2.
 132          */
 133         if (intel_dsi->ports == (1 << PORT_C))
 134                 port = PORT_C;
 135         else
 136                 port = intel_dsi_seq_port_to_port(seq_port);
 137
 138         dsi_device = intel_dsi->dsi_hosts[port]->device;
 139         if (!dsi_device) {
 140                 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
 141                 goto out;
 142         }
 143
 144         if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
 145                 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 146         else
 147                 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
 148
 149         dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
 150
 151         switch (type) {
 152         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 153                 mipi_dsi_generic_write(dsi_device, NULL, 0);
 154                 break;
 155         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 156                 mipi_dsi_generic_write(dsi_device, data, 1);
 157                 break;
 158         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 159                 mipi_dsi_generic_write(dsi_device, data, 2);
 160                 break;
 161         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 162         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 163         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 164                 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 165                 break;
 166         case MIPI_DSI_GENERIC_LONG_WRITE:
 167                 mipi_dsi_generic_write(dsi_device, data, len);
 168                 break;
 169         case MIPI_DSI_DCS_SHORT_WRITE:
 170                 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
 171                 break;
 172         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 173                 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
 174                 break;
 175         case MIPI_DSI_DCS_READ:
 176                 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 177                 break;
 178         case MIPI_DSI_DCS_LONG_WRITE:
 179                 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
 180                 break;
 181         }
 182
 183 out:
 184         data += len;
 185
 186         return data;
 187 }
 188
 189 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 190 {
 191         u32 delay = *((const u32 *) data);
 192
 193         usleep_range(delay, delay + 10);
 194         data += 4;
 195
 196         return data;
 197 }
 198
 199 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 200 {
 201         u8 gpio, action;
 202         u16 function, pad;
 203         u32 val;
 204         struct drm_device *dev = intel_dsi->base.base.dev;
 205         struct drm_i915_private *dev_priv = dev->dev_private;
 206
 207         gpio = *data++;
 208
 209         /* pull up/down */
 210         action = *data++;
 211
 212         function = gtable[gpio].function_reg;
 213         pad = gtable[gpio].pad_reg;
 214
 215         mutex_lock(&dev_priv->dpio_lock);
 216         if (!gtable[gpio].init) {
 217                 /* program the function */
 218                 /* FIXME: remove constant below */
 219                 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
 220                 gtable[gpio].init = 1;
 221         }
 222
 223         val = 0x4 | action;
 224
 225         /* pull up/down */
 226         vlv_gpio_nc_write(dev_priv, pad, val);
 227         mutex_unlock(&dev_priv->dpio_lock);
 228
 229         return data;
 230 }
 231
 232 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 233                                         const u8 *data);
 234 static const fn_mipi_elem_exec exec_elem[] = {
 235         NULL, /* reserved */
 236         mipi_exec_send_packet,
 237         mipi_exec_delay,
 238         mipi_exec_gpio,
 239         NULL, /* status read; later */
 240 };
 241
 242 /*
 243  * MIPI Sequence from VBT #53 parsing logic
 244  * We have already separated each seqence during bios parsing
 245  * Following is generic execution function for any sequence
 246  */
 247
 248 static const char * const seq_name[] = {
 249         "UNDEFINED",
 250         "MIPI_SEQ_ASSERT_RESET",
 251         "MIPI_SEQ_INIT_OTP",
 252         "MIPI_SEQ_DISPLAY_ON",
 253         "MIPI_SEQ_DISPLAY_OFF",
 254         "MIPI_SEQ_DEASSERT_RESET"
 255 };
 256
 257 static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 258 {
 259         fn_mipi_elem_exec mipi_elem_exec;
 260         int index;
 261
 262         if (!data)
 263                 return;
 264
 265         DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
 266
 267         /* go to the first element of the sequence */
 268         data++;
 269
 270         /* parse each byte till we reach end of sequence byte - 0x00 */
 271         while (1) {
 272                 index = *data;
 273                 mipi_elem_exec = exec_elem[index];
 274                 if (!mipi_elem_exec) {
 275                         DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
 276                         return;
 277                 }
 278
 279                 /* goto element payload */
 280                 data++;
 281
 282                 /* execute the element specific rotines */
 283                 data = mipi_elem_exec(intel_dsi, data);
 284
 285                 /*
 286                  * After processing the element, data should point to
 287                  * next element or end of sequence
 288                  * check if have we reached end of sequence
 289                  */
 290                 if (*data == 0x00)
 291                         break;
 292         }
 293 }
 294
 295 static int vbt_panel_prepare(struct drm_panel *panel)
 296 {
 297         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 298         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 299         struct drm_device *dev = intel_dsi->base.base.dev;
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301         const u8 *sequence;
 302
 303         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
 304         generic_exec_sequence(intel_dsi, sequence);
 305
 306         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
 307         generic_exec_sequence(intel_dsi, sequence);
 308
 309         return 0;
 310 }
 311
 312 static int vbt_panel_unprepare(struct drm_panel *panel)
 313 {
 314         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 315         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 316         struct drm_device *dev = intel_dsi->base.base.dev;
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318         const u8 *sequence;
 319
 320         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
 321         generic_exec_sequence(intel_dsi, sequence);
 322
 323         return 0;
 324 }
 325
 326 static int vbt_panel_enable(struct drm_panel *panel)
 327 {
 328         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 329         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 330         struct drm_device *dev = intel_dsi->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332         const u8 *sequence;
 333
 334         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
 335         generic_exec_sequence(intel_dsi, sequence);
 336
 337         return 0;
 338 }
 339
 340 static int vbt_panel_disable(struct drm_panel *panel)
 341 {
 342         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 343         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 344         struct drm_device *dev = intel_dsi->base.base.dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346         const u8 *sequence;
 347
 348         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
 349         generic_exec_sequence(intel_dsi, sequence);
 350
 351         return 0;
 352 }
 353
 354 static int vbt_panel_get_modes(struct drm_panel *panel)
 355 {
 356         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 357         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 358         struct drm_device *dev = intel_dsi->base.base.dev;
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360         struct drm_display_mode *mode;
 361
 362         if (!panel->connector)
 363                 return 0;
 364
 365         mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 366         if (!mode)
 367                 return 0;
 368
 369         mode->type |= DRM_MODE_TYPE_PREFERRED;
 370
 371         drm_mode_probed_add(panel->connector, mode);
 372
 373         return 1;
 374 }
 375
 376 static const struct drm_panel_funcs vbt_panel_funcs = {
 377         .disable = vbt_panel_disable,
 378         .unprepare = vbt_panel_unprepare,
 379         .prepare = vbt_panel_prepare,
 380         .enable = vbt_panel_enable,
 381         .get_modes = vbt_panel_get_modes,
 382 };
 383
 384 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 385 {
 386         struct drm_device *dev = intel_dsi->base.base.dev;
 387         struct drm_i915_private *dev_priv = dev->dev_private;
 388         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 389         struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 390         struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 391         struct vbt_panel *vbt_panel;
 392         u32 bits_per_pixel = 24;
 393         u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 394         u32 ui_num, ui_den;
 395         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 396         u32 ths_prepare_ns, tclk_trail_ns;
 397         u32 tclk_prepare_clkzero, ths_prepare_hszero;
 398         u32 lp_to_hs_switch, hs_to_lp_switch;
 399         u32 pclk, computed_ddr;
 400         u16 burst_mode_ratio;
 401         enum port port;
 402
 403         DRM_DEBUG_KMS("\n");
 404
 405         intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 406         intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 407         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 408         intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 409         intel_dsi->dual_link = mipi_config->dual_link;
 410         intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 411
 412         if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 413                 bits_per_pixel = 18;
 414         else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
 415                 bits_per_pixel = 16;
 416
 417         intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 418         intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 419         intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 420         intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 421         intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 422         intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 423         intel_dsi->init_count = mipi_config->master_init_timer;
 424         intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 425         intel_dsi->video_frmt_cfg_bits =
 426                 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 427
 428         pclk = mode->clock;
 429
 430         /* In dual link mode each port needs half of pixel clock */
 431         if (intel_dsi->dual_link) {
 432                 pclk = pclk / 2;
 433
 434                 /* we can enable pixel_overlap if needed by panel. In this
 435                  * case we need to increase the pixelclock for extra pixels
 436                  */
 437                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 438                         pclk += DIV_ROUND_UP(mode->vtotal *
 439                                                 intel_dsi->pixel_overlap *
 440                                                 60, 1000);
 441                 }
 442         }
 443
 444         /* Burst Mode Ratio
 445          * Target ddr frequency from VBT / non burst ddr freq
 446          * multiply by 100 to preserve remainder
 447          */
 448         if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 449                 if (mipi_config->target_burst_mode_freq) {
 450                         computed_ddr =
 451                                 (pclk * bits_per_pixel) / intel_dsi->lane_count;
 452
 453                         if (mipi_config->target_burst_mode_freq <
 454                                                                 computed_ddr) {
 455                                 DRM_ERROR("Burst mode freq is less than computed\n");
 456                                 return NULL;
 457                         }
 458
 459                         burst_mode_ratio = DIV_ROUND_UP(
 460                                 mipi_config->target_burst_mode_freq * 100,
 461                                 computed_ddr);
 462
 463                         pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
 464                 } else {
 465                         DRM_ERROR("Burst mode target is not set\n");
 466                         return NULL;
 467                 }
 468         } else
 469                 burst_mode_ratio = 100;
 470
 471         intel_dsi->burst_mode_ratio = burst_mode_ratio;
 472         intel_dsi->pclk = pclk;
 473
 474         bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
 475
 476         switch (intel_dsi->escape_clk_div) {
 477         case 0:
 478                 tlpx_ns = 50;
 479                 break;
 480         case 1:
 481                 tlpx_ns = 100;
 482                 break;
 483
 484         case 2:
 485                 tlpx_ns = 200;
 486                 break;
 487         default:
 488                 tlpx_ns = 50;
 489                 break;
 490         }
 491
 492         switch (intel_dsi->lane_count) {
 493         case 1:
 494         case 2:
 495                 extra_byte_count = 2;
 496                 break;
 497         case 3:
 498                 extra_byte_count = 4;
 499                 break;
 500         case 4:
 501         default:
 502                 extra_byte_count = 3;
 503                 break;
 504         }
 505
 506         /*
 507          * ui(s) = 1/f [f in hz]
 508          * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
 509          */
 510
 511         /* in Kbps */
 512         ui_num = NS_KHZ_RATIO;
 513         ui_den = bitrate;
 514
 515         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 516         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
 517
 518         /*
 519          * B060
 520          * LP byte clock = TLPX/ (8UI)
 521          */
 522         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 523
 524         /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
 525          *
 526          * Since txddrclkhs_i is 2xUI, all the count values programmed in
 527          * DPHY param register are divided by 2
 528          *
 529          * prepare count
 530          */
 531         ths_prepare_ns = max(mipi_config->ths_prepare,
 532                              mipi_config->tclk_prepare);
 533         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
 534
 535         /* exit zero count */
 536         exit_zero_cnt = DIV_ROUND_UP(
 537                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
 538                                 ui_num * 2
 539                                 );
 540
 541         /*
 542          * Exit zero  is unified val ths_zero and ths_exit
 543          * minimum value for ths_exit = 110ns
 544          * min (exit_zero_cnt * 2) = 110/UI
 545          * exit_zero_cnt = 55/UI
 546          */
 547          if (exit_zero_cnt < (55 * ui_den / ui_num))
 548                 if ((55 * ui_den) % ui_num)
 549                         exit_zero_cnt += 1;
 550
 551         /* clk zero count */
 552         clk_zero_cnt = DIV_ROUND_UP(
 553                         (tclk_prepare_clkzero - ths_prepare_ns)
 554                         * ui_den, 2 * ui_num);
 555
 556         /* trail count */
 557         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
 558         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
 559
 560         if (prepare_cnt > PREPARE_CNT_MAX ||
 561                 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
 562                 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
 563                 trail_cnt > TRAIL_CNT_MAX)
 564                 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
 565
 566         if (prepare_cnt > PREPARE_CNT_MAX)
 567                 prepare_cnt = PREPARE_CNT_MAX;
 568
 569         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
 570                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
 571
 572         if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
 573                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
 574
 575         if (trail_cnt > TRAIL_CNT_MAX)
 576                 trail_cnt = TRAIL_CNT_MAX;
 577
 578         /* B080 */
 579         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 580                                                 clk_zero_cnt << 8 | prepare_cnt;
 581
 582         /*
 583          * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
 584          *                                      + 10UI + Extra Byte Count
 585          *
 586          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
 587          * Extra Byte Count is calculated according to number of lanes.
 588          * High Low Switch Count is the Max of LP to HS and
 589          * HS to LP switch count
 590          *
 591          */
 592         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 593
 594         /* B044 */
 595         /* FIXME:
 596          * The comment above does not match with the code */
 597         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
 598                                                 exit_zero_cnt * 2 + 10, 8);
 599
 600         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
 601
 602         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 603         intel_dsi->hs_to_lp_count += extra_byte_count;
 604
 605         /* B088 */
 606         /* LP -> HS for clock lanes
 607          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 608          *                                              extra byte count
 609          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
 610          *                                      2(in UI) + extra byte count
 611          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
 612          *                                      8 + extra byte count
 613          */
 614         intel_dsi->clk_lp_to_hs_count =
 615                 DIV_ROUND_UP(
 616                         4 * tlpx_ui + prepare_cnt * 2 +
 617                         clk_zero_cnt * 2,
 618                         8);
 619
 620         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 621
 622         /* HS->LP for Clock Lanes
 623          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 624          *                                              Extra byte count
 625          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
 626          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
 627          *                                              Extra byte count
 628          */
 629         intel_dsi->clk_hs_to_lp_count =
 630                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 631                         8);
 632         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
 633
 634         DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
 635         DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 636                                                 "disabled" : "enabled");
 637         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
 638         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 639                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
 640         else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
 641                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
 642         else
 643                 DRM_DEBUG_KMS("Dual link: NONE\n");
 644         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 645         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 646         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
 647         DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
 648         DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
 649         DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
 650         DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 651         DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 652         DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
 653         DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
 654         DRM_DEBUG_KMS("BTA %s\n",
 655                         intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
 656                         "disabled" : "enabled");
 657
 658         /* delays in VBT are in unit of 100us, so need to convert
 659          * here in ms
 660          * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 661         intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 662         intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 663         intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 664         intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 665         intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 666
 667         /* This is cheating a bit with the cleanup. */
 668         vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
 669
 670         vbt_panel->intel_dsi = intel_dsi;
 671         drm_panel_init(&vbt_panel->panel);
 672         vbt_panel->panel.funcs = &vbt_panel_funcs;
 673         drm_panel_add(&vbt_panel->panel);
 674
 675         /* a regular driver would get the device in probe */
 676         for_each_dsi_port(port, intel_dsi->ports) {
 677                 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
 678         }
 679
 680         return &vbt_panel->panel;
 681 }