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bna: remove oper_state_cbfn from struct bna_rxf
[linux/fpc-iii.git] / drivers / mfd / ab8500-gpadc.c
blobdabbc93abdd717e5c40632b2d6b49209fb7149eb
1 /*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Arun R Murthy <arun.murthy@stericsson.com>
6 * Author: Daniel Willerud <daniel.willerud@stericsson.com>
7 * Author: Johan Palsson <johan.palsson@stericsson.com>
8 */
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/device.h>
12 #include <linux/interrupt.h>
13 #include <linux/spinlock.h>
14 #include <linux/delay.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/platform_device.h>
17 #include <linux/completion.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/err.h>
20 #include <linux/slab.h>
21 #include <linux/list.h>
22 #include <linux/mfd/abx500.h>
23 #include <linux/mfd/abx500/ab8500.h>
24 #include <linux/mfd/abx500/ab8500-gpadc.h>
25
26 /*
27 * GPADC register offsets
28 * Bank : 0x0A
29 */
30 #define AB8500_GPADC_CTRL1_REG 0x00
31 #define AB8500_GPADC_CTRL2_REG 0x01
32 #define AB8500_GPADC_CTRL3_REG 0x02
33 #define AB8500_GPADC_AUTO_TIMER_REG 0x03
34 #define AB8500_GPADC_STAT_REG 0x04
35 #define AB8500_GPADC_MANDATAL_REG 0x05
36 #define AB8500_GPADC_MANDATAH_REG 0x06
37 #define AB8500_GPADC_AUTODATAL_REG 0x07
38 #define AB8500_GPADC_AUTODATAH_REG 0x08
39 #define AB8500_GPADC_MUX_CTRL_REG 0x09
40 #define AB8540_GPADC_MANDATA2L_REG 0x09
41 #define AB8540_GPADC_MANDATA2H_REG 0x0A
42 #define AB8540_GPADC_APEAAX_REG 0x10
43 #define AB8540_GPADC_APEAAT_REG 0x11
44 #define AB8540_GPADC_APEAAM_REG 0x12
45 #define AB8540_GPADC_APEAAH_REG 0x13
46 #define AB8540_GPADC_APEAAL_REG 0x14
47
48 /*
49 * OTP register offsets
50 * Bank : 0x15
51 */
52 #define AB8500_GPADC_CAL_1 0x0F
53 #define AB8500_GPADC_CAL_2 0x10
54 #define AB8500_GPADC_CAL_3 0x11
55 #define AB8500_GPADC_CAL_4 0x12
56 #define AB8500_GPADC_CAL_5 0x13
57 #define AB8500_GPADC_CAL_6 0x14
58 #define AB8500_GPADC_CAL_7 0x15
59 /* New calibration for 8540 */
60 #define AB8540_GPADC_OTP4_REG_7 0x38
61 #define AB8540_GPADC_OTP4_REG_6 0x39
62 #define AB8540_GPADC_OTP4_REG_5 0x3A
63
64 /* gpadc constants */
65 #define EN_VINTCORE12 0x04
66 #define EN_VTVOUT 0x02
67 #define EN_GPADC 0x01
68 #define DIS_GPADC 0x00
69 #define AVG_1 0x00
70 #define AVG_4 0x20
71 #define AVG_8 0x40
72 #define AVG_16 0x60
73 #define ADC_SW_CONV 0x04
74 #define EN_ICHAR 0x80
75 #define BTEMP_PULL_UP 0x08
76 #define EN_BUF 0x40
77 #define DIS_ZERO 0x00
78 #define GPADC_BUSY 0x01
79 #define EN_FALLING 0x10
80 #define EN_TRIG_EDGE 0x02
81 #define EN_VBIAS_XTAL_TEMP 0x02
82
83 /* GPADC constants from AB8500 spec, UM0836 */
84 #define ADC_RESOLUTION 1024
85 #define ADC_CH_BTEMP_MIN 0
86 #define ADC_CH_BTEMP_MAX 1350
87 #define ADC_CH_DIETEMP_MIN 0
88 #define ADC_CH_DIETEMP_MAX 1350
89 #define ADC_CH_CHG_V_MIN 0
90 #define ADC_CH_CHG_V_MAX 20030
91 #define ADC_CH_ACCDET2_MIN 0
92 #define ADC_CH_ACCDET2_MAX 2500
93 #define ADC_CH_VBAT_MIN 2300
94 #define ADC_CH_VBAT_MAX 4800
95 #define ADC_CH_CHG_I_MIN 0
96 #define ADC_CH_CHG_I_MAX 1500
97 #define ADC_CH_BKBAT_MIN 0
98 #define ADC_CH_BKBAT_MAX 3200
99
100 /* GPADC constants from AB8540 spec */
101 #define ADC_CH_IBAT_MIN (-6000) /* mA range measured by ADC for ibat*/
102 #define ADC_CH_IBAT_MAX 6000
103 #define ADC_CH_IBAT_MIN_V (-60) /* mV range measured by ADC for ibat*/
104 #define ADC_CH_IBAT_MAX_V 60
105 #define IBAT_VDROP_L (-56) /* mV */
106 #define IBAT_VDROP_H 56
107
108 /* This is used to not lose precision when dividing to get gain and offset */
109 #define CALIB_SCALE 1000
110 /*
111 * Number of bits shift used to not lose precision
112 * when dividing to get ibat gain.
113 */
114 #define CALIB_SHIFT_IBAT 20
115
116 /* Time in ms before disabling regulator */
117 #define GPADC_AUDOSUSPEND_DELAY 1
118
119 #define CONVERSION_TIME 500 /* ms */
120
121 enum cal_channels {
122 ADC_INPUT_VMAIN = 0,
123 ADC_INPUT_BTEMP,
124 ADC_INPUT_VBAT,
125 ADC_INPUT_IBAT,
126 NBR_CAL_INPUTS,
127 };
128
129 /**
130 * struct adc_cal_data - Table for storing gain and offset for the calibrated
131 * ADC channels
132 * @gain: Gain of the ADC channel
133 * @offset: Offset of the ADC channel
134 */
135 struct adc_cal_data {
136 s64 gain;
137 s64 offset;
138 u16 otp_calib_hi;
139 u16 otp_calib_lo;
140 };
141
142 /**
143 * struct ab8500_gpadc - AB8500 GPADC device information
144 * @dev: pointer to the struct device
145 * @node: a list of AB8500 GPADCs, hence prepared for
146 reentrance
147 * @parent: pointer to the struct ab8500
148 * @ab8500_gpadc_complete: pointer to the struct completion, to indicate
149 * the completion of gpadc conversion
150 * @ab8500_gpadc_lock: structure of type mutex
151 * @regu: pointer to the struct regulator
152 * @irq_sw: interrupt number that is used by gpadc for Sw
153 * conversion
154 * @irq_hw: interrupt number that is used by gpadc for Hw
155 * conversion
156 * @cal_data array of ADC calibration data structs
157 */
158 struct ab8500_gpadc {
159 struct device *dev;
160 struct list_head node;
161 struct ab8500 *parent;
162 struct completion ab8500_gpadc_complete;
163 struct mutex ab8500_gpadc_lock;
164 struct regulator *regu;
165 int irq_sw;
166 int irq_hw;
167 struct adc_cal_data cal_data[NBR_CAL_INPUTS];
168 };
169
170 static LIST_HEAD(ab8500_gpadc_list);
171
172 /**
173 * ab8500_gpadc_get() - returns a reference to the primary AB8500 GPADC
174 * (i.e. the first GPADC in the instance list)
175 */
176 struct ab8500_gpadc *ab8500_gpadc_get(char *name)
177 {
178 struct ab8500_gpadc *gpadc;
179
180 list_for_each_entry(gpadc, &ab8500_gpadc_list, node) {
181 if (!strcmp(name, dev_name(gpadc->dev)))
182 return gpadc;
183 }
184
185 return ERR_PTR(-ENOENT);
186 }
187 EXPORT_SYMBOL(ab8500_gpadc_get);
188
189 /**
190 * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
191 */
192 int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, u8 channel,
193 int ad_value)
194 {
195 int res;
196
197 switch (channel) {
198 case MAIN_CHARGER_V:
199 /* For some reason we don't have calibrated data */
200 if (!gpadc->cal_data[ADC_INPUT_VMAIN].gain) {
201 res = ADC_CH_CHG_V_MIN + (ADC_CH_CHG_V_MAX -
202 ADC_CH_CHG_V_MIN) * ad_value /
203 ADC_RESOLUTION;
204 break;
205 }
206 /* Here we can use the calibrated data */
207 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VMAIN].gain +
208 gpadc->cal_data[ADC_INPUT_VMAIN].offset) / CALIB_SCALE;
209 break;
210
211 case XTAL_TEMP:
212 case BAT_CTRL:
213 case BTEMP_BALL:
214 case ACC_DETECT1:
215 case ADC_AUX1:
216 case ADC_AUX2:
217 /* For some reason we don't have calibrated data */
218 if (!gpadc->cal_data[ADC_INPUT_BTEMP].gain) {
219 res = ADC_CH_BTEMP_MIN + (ADC_CH_BTEMP_MAX -
220 ADC_CH_BTEMP_MIN) * ad_value /
221 ADC_RESOLUTION;
222 break;
223 }
224 /* Here we can use the calibrated data */
225 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_BTEMP].gain +
226 gpadc->cal_data[ADC_INPUT_BTEMP].offset) / CALIB_SCALE;
227 break;
228
229 case MAIN_BAT_V:
230 case VBAT_TRUE_MEAS:
231 /* For some reason we don't have calibrated data */
232 if (!gpadc->cal_data[ADC_INPUT_VBAT].gain) {
233 res = ADC_CH_VBAT_MIN + (ADC_CH_VBAT_MAX -
234 ADC_CH_VBAT_MIN) * ad_value /
235 ADC_RESOLUTION;
236 break;
237 }
238 /* Here we can use the calibrated data */
239 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VBAT].gain +
240 gpadc->cal_data[ADC_INPUT_VBAT].offset) / CALIB_SCALE;
241 break;
242
243 case DIE_TEMP:
244 res = ADC_CH_DIETEMP_MIN +
245 (ADC_CH_DIETEMP_MAX - ADC_CH_DIETEMP_MIN) * ad_value /
246 ADC_RESOLUTION;
247 break;
248
249 case ACC_DETECT2:
250 res = ADC_CH_ACCDET2_MIN +
251 (ADC_CH_ACCDET2_MAX - ADC_CH_ACCDET2_MIN) * ad_value /
252 ADC_RESOLUTION;
253 break;
254
255 case VBUS_V:
256 res = ADC_CH_CHG_V_MIN +
257 (ADC_CH_CHG_V_MAX - ADC_CH_CHG_V_MIN) * ad_value /
258 ADC_RESOLUTION;
259 break;
260
261 case MAIN_CHARGER_C:
262 case USB_CHARGER_C:
263 res = ADC_CH_CHG_I_MIN +
264 (ADC_CH_CHG_I_MAX - ADC_CH_CHG_I_MIN) * ad_value /
265 ADC_RESOLUTION;
266 break;
267
268 case BK_BAT_V:
269 res = ADC_CH_BKBAT_MIN +
270 (ADC_CH_BKBAT_MAX - ADC_CH_BKBAT_MIN) * ad_value /
271 ADC_RESOLUTION;
272 break;
273
274 case IBAT_VIRTUAL_CHANNEL:
275 /* For some reason we don't have calibrated data */
276 if (!gpadc->cal_data[ADC_INPUT_IBAT].gain) {
277 res = ADC_CH_IBAT_MIN + (ADC_CH_IBAT_MAX -
278 ADC_CH_IBAT_MIN) * ad_value /
279 ADC_RESOLUTION;
280 break;
281 }
282 /* Here we can use the calibrated data */
283 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_IBAT].gain +
284 gpadc->cal_data[ADC_INPUT_IBAT].offset)
285 >> CALIB_SHIFT_IBAT;
286 break;
287
288 default:
289 dev_err(gpadc->dev,
290 "unknown channel, not possible to convert\n");
291 res = -EINVAL;
292 break;
293
294 }
295 return res;
296 }
297 EXPORT_SYMBOL(ab8500_gpadc_ad_to_voltage);
298
299 /**
300 * ab8500_gpadc_sw_hw_convert() - gpadc conversion
301 * @channel: analog channel to be converted to digital data
302 * @avg_sample: number of ADC sample to average
303 * @trig_egde: selected ADC trig edge
304 * @trig_timer: selected ADC trigger delay timer
305 * @conv_type: selected conversion type (HW or SW conversion)
306 *
307 * This function converts the selected analog i/p to digital
308 * data.
309 */
310 int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
311 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
312 {
313 int ad_value;
314 int voltage;
315
316 ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
317 trig_edge, trig_timer, conv_type);
318 /* On failure retry a second time */
319 if (ad_value < 0)
320 ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
321 trig_edge, trig_timer, conv_type);
322 if (ad_value < 0) {
323 dev_err(gpadc->dev, "GPADC raw value failed ch: %d\n",
324 channel);
325 return ad_value;
326 }
327
328 voltage = ab8500_gpadc_ad_to_voltage(gpadc, channel, ad_value);
329 if (voltage < 0)
330 dev_err(gpadc->dev, "GPADC to voltage conversion failed ch:"
331 " %d AD: 0x%x\n", channel, ad_value);
332
333 return voltage;
334 }
335 EXPORT_SYMBOL(ab8500_gpadc_sw_hw_convert);
336
337 /**
338 * ab8500_gpadc_read_raw() - gpadc read
339 * @channel: analog channel to be read
340 * @avg_sample: number of ADC sample to average
341 * @trig_edge: selected trig edge
342 * @trig_timer: selected ADC trigger delay timer
343 * @conv_type: selected conversion type (HW or SW conversion)
344 *
345 * This function obtains the raw ADC value for an hardware conversion,
346 * this then needs to be converted by calling ab8500_gpadc_ad_to_voltage()
347 */
348 int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
349 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
350 {
351 int raw_data;
352 raw_data = ab8500_gpadc_double_read_raw(gpadc, channel,
353 avg_sample, trig_edge, trig_timer, conv_type, NULL);
354 return raw_data;
355 }
356
357 int ab8500_gpadc_double_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
358 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type,
359 int *ibat)
360 {
361 int ret;
362 int looplimit = 0;
363 unsigned long completion_timeout;
364 u8 val, low_data, high_data, low_data2, high_data2;
365 u8 val_reg1 = 0;
366 unsigned int delay_min = 0;
367 unsigned int delay_max = 0;
368 u8 data_low_addr, data_high_addr;
369
370 if (!gpadc)
371 return -ENODEV;
372
373 /* check if convertion is supported */
374 if ((gpadc->irq_sw < 0) && (conv_type == ADC_SW))
375 return -ENOTSUPP;
376 if ((gpadc->irq_hw < 0) && (conv_type == ADC_HW))
377 return -ENOTSUPP;
378
379 mutex_lock(&gpadc->ab8500_gpadc_lock);
380 /* Enable VTVout LDO this is required for GPADC */
381 pm_runtime_get_sync(gpadc->dev);
382
383 /* Check if ADC is not busy, lock and proceed */
384 do {
385 ret = abx500_get_register_interruptible(gpadc->dev,
386 AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
387 if (ret < 0)
388 goto out;
389 if (!(val & GPADC_BUSY))
390 break;
391 msleep(10);
392 } while (++looplimit < 10);
393 if (looplimit >= 10 && (val & GPADC_BUSY)) {
394 dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
395 ret = -EINVAL;
396 goto out;
397 }
398
399 /* Enable GPADC */
400 val_reg1 |= EN_GPADC;
401
402 /* Select the channel source and set average samples */
403 switch (avg_sample) {
404 case SAMPLE_1:
405 val = channel | AVG_1;
406 break;
407 case SAMPLE_4:
408 val = channel | AVG_4;
409 break;
410 case SAMPLE_8:
411 val = channel | AVG_8;
412 break;
413 default:
414 val = channel | AVG_16;
415 break;
416 }
417
418 if (conv_type == ADC_HW) {
419 ret = abx500_set_register_interruptible(gpadc->dev,
420 AB8500_GPADC, AB8500_GPADC_CTRL3_REG, val);
421 val_reg1 |= EN_TRIG_EDGE;
422 if (trig_edge)
423 val_reg1 |= EN_FALLING;
424 }
425 else
426 ret = abx500_set_register_interruptible(gpadc->dev,
427 AB8500_GPADC, AB8500_GPADC_CTRL2_REG, val);
428 if (ret < 0) {
429 dev_err(gpadc->dev,
430 "gpadc_conversion: set avg samples failed\n");
431 goto out;
432 }
433
434 /*
435 * Enable ADC, buffering, select rising edge and enable ADC path
436 * charging current sense if it needed, ABB 3.0 needs some special
437 * treatment too.
438 */
439 switch (channel) {
440 case MAIN_CHARGER_C:
441 case USB_CHARGER_C:
442 val_reg1 |= EN_BUF | EN_ICHAR;
443 break;
444 case BTEMP_BALL:
445 if (!is_ab8500_2p0_or_earlier(gpadc->parent)) {
446 val_reg1 |= EN_BUF | BTEMP_PULL_UP;
447 /*
448 * Delay might be needed for ABB8500 cut 3.0, if not,
449 * remove when hardware will be availible
450 */
451 delay_min = 1000; /* Delay in micro seconds */
452 delay_max = 10000; /* large range to optimise sleep mode */
453 break;
454 }
455 /* Intentional fallthrough */
456 default:
457 val_reg1 |= EN_BUF;
458 break;
459 }
460
461 /* Write configuration to register */
462 ret = abx500_set_register_interruptible(gpadc->dev,
463 AB8500_GPADC, AB8500_GPADC_CTRL1_REG, val_reg1);
464 if (ret < 0) {
465 dev_err(gpadc->dev,
466 "gpadc_conversion: set Control register failed\n");
467 goto out;
468 }
469
470 if (delay_min != 0)
471 usleep_range(delay_min, delay_max);
472
473 if (conv_type == ADC_HW) {
474 /* Set trigger delay timer */
475 ret = abx500_set_register_interruptible(gpadc->dev,
476 AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG, trig_timer);
477 if (ret < 0) {
478 dev_err(gpadc->dev,
479 "gpadc_conversion: trig timer failed\n");
480 goto out;
481 }
482 completion_timeout = 2 * HZ;
483 data_low_addr = AB8500_GPADC_AUTODATAL_REG;
484 data_high_addr = AB8500_GPADC_AUTODATAH_REG;
485 } else {
486 /* Start SW conversion */
487 ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
488 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
489 ADC_SW_CONV, ADC_SW_CONV);
490 if (ret < 0) {
491 dev_err(gpadc->dev,
492 "gpadc_conversion: start s/w conv failed\n");
493 goto out;
494 }
495 completion_timeout = msecs_to_jiffies(CONVERSION_TIME);
496 data_low_addr = AB8500_GPADC_MANDATAL_REG;
497 data_high_addr = AB8500_GPADC_MANDATAH_REG;
498 }
499
500 /* wait for completion of conversion */
501 if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete,
502 completion_timeout)) {
503 dev_err(gpadc->dev,
504 "timeout didn't receive GPADC conv interrupt\n");
505 ret = -EINVAL;
506 goto out;
507 }
508
509 /* Read the converted RAW data */
510 ret = abx500_get_register_interruptible(gpadc->dev,
511 AB8500_GPADC, data_low_addr, &low_data);
512 if (ret < 0) {
513 dev_err(gpadc->dev, "gpadc_conversion: read low data failed\n");
514 goto out;
515 }
516
517 ret = abx500_get_register_interruptible(gpadc->dev,
518 AB8500_GPADC, data_high_addr, &high_data);
519 if (ret < 0) {
520 dev_err(gpadc->dev, "gpadc_conversion: read high data failed\n");
521 goto out;
522 }
523
524 /* Check if double convertion is required */
525 if ((channel == BAT_CTRL_AND_IBAT) ||
526 (channel == VBAT_MEAS_AND_IBAT) ||
527 (channel == VBAT_TRUE_MEAS_AND_IBAT) ||
528 (channel == BAT_TEMP_AND_IBAT)) {
529
530 if (conv_type == ADC_HW) {
531 /* not supported */
532 ret = -ENOTSUPP;
533 dev_err(gpadc->dev,
534 "gpadc_conversion: only SW double conversion supported\n");
535 goto out;
536 } else {
537 /* Read the converted RAW data 2 */
538 ret = abx500_get_register_interruptible(gpadc->dev,
539 AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG,
540 &low_data2);
541 if (ret < 0) {
542 dev_err(gpadc->dev,
543 "gpadc_conversion: read sw low data 2 failed\n");
544 goto out;
545 }
546
547 ret = abx500_get_register_interruptible(gpadc->dev,
548 AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG,
549 &high_data2);
550 if (ret < 0) {
551 dev_err(gpadc->dev,
552 "gpadc_conversion: read sw high data 2 failed\n");
553 goto out;
554 }
555 if (ibat != NULL) {
556 *ibat = (high_data2 << 8) | low_data2;
557 } else {
558 dev_warn(gpadc->dev,
559 "gpadc_conversion: ibat not stored\n");
560 }
561
562 }
563 }
564
565 /* Disable GPADC */
566 ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
567 AB8500_GPADC_CTRL1_REG, DIS_GPADC);
568 if (ret < 0) {
569 dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
570 goto out;
571 }
572
573 /* Disable VTVout LDO this is required for GPADC */
574 pm_runtime_mark_last_busy(gpadc->dev);
575 pm_runtime_put_autosuspend(gpadc->dev);
576
577 mutex_unlock(&gpadc->ab8500_gpadc_lock);
578
579 return (high_data << 8) | low_data;
580
581 out:
582 /*
583 * It has shown to be needed to turn off the GPADC if an error occurs,
584 * otherwise we might have problem when waiting for the busy bit in the
585 * GPADC status register to go low. In V1.1 there wait_for_completion
586 * seems to timeout when waiting for an interrupt.. Not seen in V2.0
587 */
588 (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
589 AB8500_GPADC_CTRL1_REG, DIS_GPADC);
590 pm_runtime_put(gpadc->dev);
591 mutex_unlock(&gpadc->ab8500_gpadc_lock);
592 dev_err(gpadc->dev,
593 "gpadc_conversion: Failed to AD convert channel %d\n", channel);
594 return ret;
595 }
596 EXPORT_SYMBOL(ab8500_gpadc_read_raw);
597
598 /**
599 * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
600 * @irq: irq number
601 * @data: pointer to the data passed during request irq
602 *
603 * This is a interrupt service routine for gpadc conversion completion.
604 * Notifies the gpadc completion is completed and the converted raw value
605 * can be read from the registers.
606 * Returns IRQ status(IRQ_HANDLED)
607 */
608 static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *_gpadc)
609 {
610 struct ab8500_gpadc *gpadc = _gpadc;
611
612 complete(&gpadc->ab8500_gpadc_complete);
613
614 return IRQ_HANDLED;
615 }
616
617 static int otp_cal_regs[] = {
618 AB8500_GPADC_CAL_1,
619 AB8500_GPADC_CAL_2,
620 AB8500_GPADC_CAL_3,
621 AB8500_GPADC_CAL_4,
622 AB8500_GPADC_CAL_5,
623 AB8500_GPADC_CAL_6,
624 AB8500_GPADC_CAL_7,
625 };
626
627 static int otp4_cal_regs[] = {
628 AB8540_GPADC_OTP4_REG_7,
629 AB8540_GPADC_OTP4_REG_6,
630 AB8540_GPADC_OTP4_REG_5,
631 };
632
633 static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
634 {
635 int i;
636 int ret[ARRAY_SIZE(otp_cal_regs)];
637 u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
638 int ret_otp4[ARRAY_SIZE(otp4_cal_regs)];
639 u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)];
640 int vmain_high, vmain_low;
641 int btemp_high, btemp_low;
642 int vbat_high, vbat_low;
643 int ibat_high, ibat_low;
644 s64 V_gain, V_offset, V2A_gain, V2A_offset;
645 struct ab8500 *ab8500;
646
647 ab8500 = gpadc->parent;
648
649 /* First we read all OTP registers and store the error code */
650 for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
651 ret[i] = abx500_get_register_interruptible(gpadc->dev,
652 AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]);
653 if (ret[i] < 0)
654 dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
655 __func__, otp_cal_regs[i]);
656 }
657
658 /*
659 * The ADC calibration data is stored in OTP registers.
660 * The layout of the calibration data is outlined below and a more
661 * detailed description can be found in UM0836
662 *
663 * vm_h/l = vmain_high/low
664 * bt_h/l = btemp_high/low
665 * vb_h/l = vbat_high/low
666 *
667 * Data bits 8500/9540:
668 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
669 * |.......|.......|.......|.......|.......|.......|.......|.......
670 * | | vm_h9 | vm_h8
671 * |.......|.......|.......|.......|.......|.......|.......|.......
672 * | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
673 * |.......|.......|.......|.......|.......|.......|.......|.......
674 * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
675 * |.......|.......|.......|.......|.......|.......|.......|.......
676 * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
677 * |.......|.......|.......|.......|.......|.......|.......|.......
678 * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
679 * |.......|.......|.......|.......|.......|.......|.......|.......
680 * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
681 * |.......|.......|.......|.......|.......|.......|.......|.......
682 * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
683 * |.......|.......|.......|.......|.......|.......|.......|.......
684 *
685 * Data bits 8540:
686 * OTP2
687 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
688 * |.......|.......|.......|.......|.......|.......|.......|.......
689 * |
690 * |.......|.......|.......|.......|.......|.......|.......|.......
691 * | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
692 * |.......|.......|.......|.......|.......|.......|.......|.......
693 * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
694 * |.......|.......|.......|.......|.......|.......|.......|.......
695 * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
696 * |.......|.......|.......|.......|.......|.......|.......|.......
697 * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
698 * |.......|.......|.......|.......|.......|.......|.......|.......
699 * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
700 * |.......|.......|.......|.......|.......|.......|.......|.......
701 * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
702 * |.......|.......|.......|.......|.......|.......|.......|.......
703 *
704 * Data bits 8540:
705 * OTP4
706 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
707 * |.......|.......|.......|.......|.......|.......|.......|.......
708 * | | ib_h9 | ib_h8 | ib_h7
709 * |.......|.......|.......|.......|.......|.......|.......|.......
710 * | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5
711 * |.......|.......|.......|.......|.......|.......|.......|.......
712 * | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 |
713 *
714 *
715 * Ideal output ADC codes corresponding to injected input voltages
716 * during manufacturing is:
717 *
718 * vmain_high: Vin = 19500mV / ADC ideal code = 997
719 * vmain_low: Vin = 315mV / ADC ideal code = 16
720 * btemp_high: Vin = 1300mV / ADC ideal code = 985
721 * btemp_low: Vin = 21mV / ADC ideal code = 16
722 * vbat_high: Vin = 4700mV / ADC ideal code = 982
723 * vbat_low: Vin = 2380mV / ADC ideal code = 33
724 */
725
726 if (is_ab8540(ab8500)) {
727 /* Calculate gain and offset for VMAIN if all reads succeeded*/
728 if (!(ret[1] < 0 || ret[2] < 0)) {
729 vmain_high = (((gpadc_cal[1] & 0xFF) << 2) |
730 ((gpadc_cal[2] & 0xC0) >> 6));
731 vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
732
733 gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi =
734 (u16)vmain_high;
735 gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo =
736 (u16)vmain_low;
737
738 gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE *
739 (19500 - 315) / (vmain_high - vmain_low);
740 gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE *
741 19500 - (CALIB_SCALE * (19500 - 315) /
742 (vmain_high - vmain_low)) * vmain_high;
743 } else {
744 gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0;
745 }
746
747 /* Read IBAT calibration Data */
748 for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) {
749 ret_otp4[i] = abx500_get_register_interruptible(
750 gpadc->dev, AB8500_OTP_EMUL,
751 otp4_cal_regs[i], &gpadc_otp4[i]);
752 if (ret_otp4[i] < 0)
753 dev_err(gpadc->dev,
754 "%s: read otp4 reg 0x%02x failed\n",
755 __func__, otp4_cal_regs[i]);
756 }
757
758 /* Calculate gain and offset for IBAT if all reads succeeded */
759 if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) {
760 ibat_high = (((gpadc_otp4[0] & 0x07) << 7) |
761 ((gpadc_otp4[1] & 0xFE) >> 1));
762 ibat_low = (((gpadc_otp4[1] & 0x01) << 5) |
763 ((gpadc_otp4[2] & 0xF8) >> 3));
764
765 gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi =
766 (u16)ibat_high;
767 gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo =
768 (u16)ibat_low;
769
770 V_gain = ((IBAT_VDROP_H - IBAT_VDROP_L)
771 << CALIB_SHIFT_IBAT) / (ibat_high - ibat_low);
772
773 V_offset = (IBAT_VDROP_H << CALIB_SHIFT_IBAT) -
774 (((IBAT_VDROP_H - IBAT_VDROP_L) <<
775 CALIB_SHIFT_IBAT) / (ibat_high - ibat_low))
776 * ibat_high;
777 /*
778 * Result obtained is in mV (at a scale factor),
779 * we need to calculate gain and offset to get mA
780 */
781 V2A_gain = (ADC_CH_IBAT_MAX - ADC_CH_IBAT_MIN)/
782 (ADC_CH_IBAT_MAX_V - ADC_CH_IBAT_MIN_V);
783 V2A_offset = ((ADC_CH_IBAT_MAX_V * ADC_CH_IBAT_MIN -
784 ADC_CH_IBAT_MAX * ADC_CH_IBAT_MIN_V)
785 << CALIB_SHIFT_IBAT)
786 / (ADC_CH_IBAT_MAX_V - ADC_CH_IBAT_MIN_V);
787
788 gpadc->cal_data[ADC_INPUT_IBAT].gain = V_gain * V2A_gain;
789 gpadc->cal_data[ADC_INPUT_IBAT].offset = V_offset *
790 V2A_gain + V2A_offset;
791 } else {
792 gpadc->cal_data[ADC_INPUT_IBAT].gain = 0;
793 }
794
795 dev_dbg(gpadc->dev, "IBAT gain %llu offset %llu\n",
796 gpadc->cal_data[ADC_INPUT_IBAT].gain,
797 gpadc->cal_data[ADC_INPUT_IBAT].offset);
798 } else {
799 /* Calculate gain and offset for VMAIN if all reads succeeded */
800 if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
801 vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
802 ((gpadc_cal[1] & 0x3F) << 2) |
803 ((gpadc_cal[2] & 0xC0) >> 6));
804 vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
805
806 gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi =
807 (u16)vmain_high;
808 gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo =
809 (u16)vmain_low;
810
811 gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE *
812 (19500 - 315) / (vmain_high - vmain_low);
813
814 gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE *
815 19500 - (CALIB_SCALE * (19500 - 315) /
816 (vmain_high - vmain_low)) * vmain_high;
817 } else {
818 gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0;
819 }
820 }
821
822 /* Calculate gain and offset for BTEMP if all reads succeeded */
823 if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
824 btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
825 (gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7));
826 btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
827
828 gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_hi = (u16)btemp_high;
829 gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_lo = (u16)btemp_low;
830
831 gpadc->cal_data[ADC_INPUT_BTEMP].gain =
832 CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
833 gpadc->cal_data[ADC_INPUT_BTEMP].offset = CALIB_SCALE * 1300 -
834 (CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low))
835 * btemp_high;
836 } else {
837 gpadc->cal_data[ADC_INPUT_BTEMP].gain = 0;
838 }
839
840 /* Calculate gain and offset for VBAT if all reads succeeded */
841 if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
842 vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
843 vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
844
845 gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_hi = (u16)vbat_high;
846 gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_lo = (u16)vbat_low;
847
848 gpadc->cal_data[ADC_INPUT_VBAT].gain = CALIB_SCALE *
849 (4700 - 2380) / (vbat_high - vbat_low);
850 gpadc->cal_data[ADC_INPUT_VBAT].offset = CALIB_SCALE * 4700 -
851 (CALIB_SCALE * (4700 - 2380) /
852 (vbat_high - vbat_low)) * vbat_high;
853 } else {
854 gpadc->cal_data[ADC_INPUT_VBAT].gain = 0;
855 }
856
857 dev_dbg(gpadc->dev, "VMAIN gain %llu offset %llu\n",
858 gpadc->cal_data[ADC_INPUT_VMAIN].gain,
859 gpadc->cal_data[ADC_INPUT_VMAIN].offset);
860
861 dev_dbg(gpadc->dev, "BTEMP gain %llu offset %llu\n",
862 gpadc->cal_data[ADC_INPUT_BTEMP].gain,
863 gpadc->cal_data[ADC_INPUT_BTEMP].offset);
864
865 dev_dbg(gpadc->dev, "VBAT gain %llu offset %llu\n",
866 gpadc->cal_data[ADC_INPUT_VBAT].gain,
867 gpadc->cal_data[ADC_INPUT_VBAT].offset);
868 }
869
870 #ifdef CONFIG_PM
871 static int ab8500_gpadc_runtime_suspend(struct device *dev)
872 {
873 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
874
875 regulator_disable(gpadc->regu);
876 return 0;
877 }
878
879 static int ab8500_gpadc_runtime_resume(struct device *dev)
880 {
881 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
882 int ret;
883
884 ret = regulator_enable(gpadc->regu);
885 if (ret)
886 dev_err(dev, "Failed to enable vtvout LDO: %d\n", ret);
887 return ret;
888 }
889 #endif
890
891 #ifdef CONFIG_PM_SLEEP
892 static int ab8500_gpadc_suspend(struct device *dev)
893 {
894 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
895
896 mutex_lock(&gpadc->ab8500_gpadc_lock);
897
898 pm_runtime_get_sync(dev);
899
900 regulator_disable(gpadc->regu);
901 return 0;
902 }
903
904 static int ab8500_gpadc_resume(struct device *dev)
905 {
906 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
907 int ret;
908
909 ret = regulator_enable(gpadc->regu);
910 if (ret)
911 dev_err(dev, "Failed to enable vtvout LDO: %d\n", ret);
912
913 pm_runtime_mark_last_busy(gpadc->dev);
914 pm_runtime_put_autosuspend(gpadc->dev);
915
916 mutex_unlock(&gpadc->ab8500_gpadc_lock);
917 return ret;
918 }
919 #endif
920
921 static int ab8500_gpadc_probe(struct platform_device *pdev)
922 {
923 int ret = 0;
924 struct ab8500_gpadc *gpadc;
925
926 gpadc = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_gpadc), GFP_KERNEL);
927 if (!gpadc) {
928 dev_err(&pdev->dev, "Error: No memory\n");
929 return -ENOMEM;
930 }
931
932 gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
933 if (gpadc->irq_sw < 0)
934 dev_err(gpadc->dev, "failed to get platform sw_conv_end irq\n");
935
936 gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
937 if (gpadc->irq_hw < 0)
938 dev_err(gpadc->dev, "failed to get platform hw_conv_end irq\n");
939
940 gpadc->dev = &pdev->dev;
941 gpadc->parent = dev_get_drvdata(pdev->dev.parent);
942 mutex_init(&gpadc->ab8500_gpadc_lock);
943
944 /* Initialize completion used to notify completion of conversion */
945 init_completion(&gpadc->ab8500_gpadc_complete);
946
947 /* Register interrupts */
948 if (gpadc->irq_sw >= 0) {
949 ret = request_threaded_irq(gpadc->irq_sw, NULL,
950 ab8500_bm_gpadcconvend_handler,
951 IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-sw",
952 gpadc);
953 if (ret < 0) {
954 dev_err(gpadc->dev,
955 "Failed to register interrupt irq: %d\n",
956 gpadc->irq_sw);
957 goto fail;
958 }
959 }
960
961 if (gpadc->irq_hw >= 0) {
962 ret = request_threaded_irq(gpadc->irq_hw, NULL,
963 ab8500_bm_gpadcconvend_handler,
964 IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-hw",
965 gpadc);
966 if (ret < 0) {
967 dev_err(gpadc->dev,
968 "Failed to register interrupt irq: %d\n",
969 gpadc->irq_hw);
970 goto fail_irq;
971 }
972 }
973
974 /* VTVout LDO used to power up ab8500-GPADC */
975 gpadc->regu = devm_regulator_get(&pdev->dev, "vddadc");
976 if (IS_ERR(gpadc->regu)) {
977 ret = PTR_ERR(gpadc->regu);
978 dev_err(gpadc->dev, "failed to get vtvout LDO\n");
979 goto fail_irq;
980 }
981
982 platform_set_drvdata(pdev, gpadc);
983
984 ret = regulator_enable(gpadc->regu);
985 if (ret) {
986 dev_err(gpadc->dev, "Failed to enable vtvout LDO: %d\n", ret);
987 goto fail_enable;
988 }
989
990 pm_runtime_set_autosuspend_delay(gpadc->dev, GPADC_AUDOSUSPEND_DELAY);
991 pm_runtime_use_autosuspend(gpadc->dev);
992 pm_runtime_set_active(gpadc->dev);
993 pm_runtime_enable(gpadc->dev);
994
995 ab8500_gpadc_read_calibration_data(gpadc);
996 list_add_tail(&gpadc->node, &ab8500_gpadc_list);
997 dev_dbg(gpadc->dev, "probe success\n");
998
999 return 0;
1000
1001 fail_enable:
1002 fail_irq:
1003 free_irq(gpadc->irq_sw, gpadc);
1004 free_irq(gpadc->irq_hw, gpadc);
1005 fail:
1006 return ret;
1007 }
1008
1009 static int ab8500_gpadc_remove(struct platform_device *pdev)
1010 {
1011 struct ab8500_gpadc *gpadc = platform_get_drvdata(pdev);
1012
1013 /* remove this gpadc entry from the list */
1014 list_del(&gpadc->node);
1015 /* remove interrupt - completion of Sw ADC conversion */
1016 if (gpadc->irq_sw >= 0)
1017 free_irq(gpadc->irq_sw, gpadc);
1018 if (gpadc->irq_hw >= 0)
1019 free_irq(gpadc->irq_hw, gpadc);
1020
1021 pm_runtime_get_sync(gpadc->dev);
1022 pm_runtime_disable(gpadc->dev);
1023
1024 regulator_disable(gpadc->regu);
1025
1026 pm_runtime_set_suspended(gpadc->dev);
1027
1028 pm_runtime_put_noidle(gpadc->dev);
1029
1030 return 0;
1031 }
1032
1033 static const struct dev_pm_ops ab8500_gpadc_pm_ops = {
1034 SET_RUNTIME_PM_OPS(ab8500_gpadc_runtime_suspend,
1035 ab8500_gpadc_runtime_resume,
1036 NULL)
1037 SET_SYSTEM_SLEEP_PM_OPS(ab8500_gpadc_suspend,
1038 ab8500_gpadc_resume)
1039
1040 };
1041
1042 static struct platform_driver ab8500_gpadc_driver = {
1043 .probe = ab8500_gpadc_probe,
1044 .remove = ab8500_gpadc_remove,
1045 .driver = {
1046 .name = "ab8500-gpadc",
1047 .pm = &ab8500_gpadc_pm_ops,
1048 },
1049 };
1050
1051 static int __init ab8500_gpadc_init(void)
1052 {
1053 return platform_driver_register(&ab8500_gpadc_driver);
1054 }
1055
1056 static void __exit ab8500_gpadc_exit(void)
1057 {
1058 platform_driver_unregister(&ab8500_gpadc_driver);
1059 }
1060
1061 /**
1062 * ab8540_gpadc_get_otp() - returns OTP values
1063 *
1064 */
1065 void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc,
1066 u16 *vmain_l, u16 *vmain_h, u16 *btemp_l, u16 *btemp_h,
1067 u16 *vbat_l, u16 *vbat_h, u16 *ibat_l, u16 *ibat_h)
1068 {
1069 *vmain_l = gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo;
1070 *vmain_h = gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi;
1071 *btemp_l = gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_lo;
1072 *btemp_h = gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_hi;
1073 *vbat_l = gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_lo;
1074 *vbat_h = gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_hi;
1075 *ibat_l = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo;
1076 *ibat_h = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi;
1077 return ;
1078 }
1079
1080 subsys_initcall_sync(ab8500_gpadc_init);
1081 module_exit(ab8500_gpadc_exit);
1082
1083 MODULE_LICENSE("GPL v2");
1084 MODULE_AUTHOR("Arun R Murthy, Daniel Willerud, Johan Palsson,"
1085 "M'boumba Cedric Madianga");
1086 MODULE_ALIAS("platform:ab8500_gpadc");
1087 MODULE_DESCRIPTION("AB8500 GPADC driver");
Linux with added FPC-III support