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bna: remove oper_state_cbfn from struct bna_rxf
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-xway.c
blob779950c62e53d238e7a4c35d7290ca66475fed86
1 /*
2 * linux/drivers/pinctrl/pinmux-xway.c
3 * based on linux/drivers/pinctrl/pinmux-pxa910.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 *
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
10 */
11
12 #include <linux/err.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/of_address.h>
17 #include <linux/of_gpio.h>
18 #include <linux/ioport.h>
19 #include <linux/io.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22
23 #include "pinctrl-lantiq.h"
24
25 #include <lantiq_soc.h>
26
27 /* we have 3 1/2 banks of 16 bit each */
28 #define PINS 16
29 #define PORT3 3
30 #define PORT(x) (x / PINS)
31 #define PORT_PIN(x) (x % PINS)
32
33 /* we have 2 mux bits that can be set for each pin */
34 #define MUX_ALT0 0x1
35 #define MUX_ALT1 0x2
36
37 /*
38 * each bank has this offset apart from the 1/2 bank that is mixed into the
39 * other 3 ranges
40 */
41 #define REG_OFF 0x30
42
43 /* these are the offsets to our registers */
44 #define GPIO_BASE(p) (REG_OFF * PORT(p))
45 #define GPIO_OUT(p) GPIO_BASE(p)
46 #define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
47 #define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
48 #define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
49 #define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
50 #define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
51 #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
52 #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
53
54 /* the 1/2 port needs special offsets for some registers */
55 #define GPIO3_OD (GPIO_BASE(0) + 0x24)
56 #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
57 #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
58 #define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
59
60 /* macros to help us access the registers */
61 #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
62 #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
63 #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
64
65 #define MFP_XWAY(a, f0, f1, f2, f3) \
66 { \
67 .name = #a, \
68 .pin = a, \
69 .func = { \
70 XWAY_MUX_##f0, \
71 XWAY_MUX_##f1, \
72 XWAY_MUX_##f2, \
73 XWAY_MUX_##f3, \
74 }, \
75 }
76
77 #define GRP_MUX(a, m, p) \
78 { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
79
80 #define FUNC_MUX(f, m) \
81 { .func = f, .mux = XWAY_MUX_##m, }
82
83 #define XWAY_MAX_PIN 32
84 #define XR9_MAX_PIN 56
85
86 enum xway_mux {
87 XWAY_MUX_GPIO = 0,
88 XWAY_MUX_SPI,
89 XWAY_MUX_ASC,
90 XWAY_MUX_PCI,
91 XWAY_MUX_CGU,
92 XWAY_MUX_EBU,
93 XWAY_MUX_JTAG,
94 XWAY_MUX_EXIN,
95 XWAY_MUX_TDM,
96 XWAY_MUX_STP,
97 XWAY_MUX_SIN,
98 XWAY_MUX_GPT,
99 XWAY_MUX_NMI,
100 XWAY_MUX_MDIO,
101 XWAY_MUX_MII,
102 XWAY_MUX_EPHY,
103 XWAY_MUX_DFE,
104 XWAY_MUX_SDIO,
105 XWAY_MUX_GPHY,
106 XWAY_MUX_NONE = 0xffff,
107 };
108
109 static const struct ltq_mfp_pin xway_mfp[] = {
110 /* pin f0 f1 f2 f3 */
111 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
112 MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
113 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
114 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
115 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
116 MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY),
117 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
118 MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY),
119 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
120 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
121 MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
122 MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
123 MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE),
124 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
125 MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE),
126 MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
127 MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
128 MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
129 MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
130 MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE),
131 MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE),
132 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
133 MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
134 MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
135 MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
136 MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC),
137 MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM),
138 MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC),
139 MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE),
140 MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE),
141 MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE),
142 MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
143 MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU),
144 MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU),
145 MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU),
146 MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU),
147 MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU),
148 MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
149 MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
150 MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE),
151 MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE),
152 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
153 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
154 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
155 MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN),
156 MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
157 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
158 MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
159 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
160 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
161 MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
162 MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
163 MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
164 MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
165 MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
166 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
167 };
168
169 static const struct ltq_mfp_pin ase_mfp[] = {
170 /* pin f0 f1 f2 f3 */
171 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
172 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
173 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
174 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
175 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
176 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
177 MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
178 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
179 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
180 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
181 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
182 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
183 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
184 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
185 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
186 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
187 MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
188 MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
189 MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
190 MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
191 MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
192 MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO),
193 MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
194 MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
195 MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII),
196 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
197 MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
198 MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII),
199 MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
200 MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
201 MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
202 MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
203 };
204
205 static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
206 static const unsigned pins_asc0[] = {GPIO11, GPIO12};
207 static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
208 static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
209 static const unsigned pins_nmi[] = {GPIO8};
210 static const unsigned pins_mdio[] = {GPIO42, GPIO43};
211
212 static const unsigned pins_gphy0_led0[] = {GPIO5};
213 static const unsigned pins_gphy0_led1[] = {GPIO7};
214 static const unsigned pins_gphy0_led2[] = {GPIO2};
215 static const unsigned pins_gphy1_led0[] = {GPIO44};
216 static const unsigned pins_gphy1_led1[] = {GPIO45};
217 static const unsigned pins_gphy1_led2[] = {GPIO47};
218
219 static const unsigned pins_ebu_a24[] = {GPIO13};
220 static const unsigned pins_ebu_clk[] = {GPIO21};
221 static const unsigned pins_ebu_cs1[] = {GPIO23};
222 static const unsigned pins_ebu_a23[] = {GPIO24};
223 static const unsigned pins_ebu_wait[] = {GPIO26};
224 static const unsigned pins_ebu_a25[] = {GPIO31};
225 static const unsigned pins_ebu_rdy[] = {GPIO48};
226 static const unsigned pins_ebu_rd[] = {GPIO49};
227
228 static const unsigned pins_nand_ale[] = {GPIO13};
229 static const unsigned pins_nand_cs1[] = {GPIO23};
230 static const unsigned pins_nand_cle[] = {GPIO24};
231 static const unsigned pins_nand_rdy[] = {GPIO48};
232 static const unsigned pins_nand_rd[] = {GPIO49};
233
234 static const unsigned pins_exin0[] = {GPIO0};
235 static const unsigned pins_exin1[] = {GPIO1};
236 static const unsigned pins_exin2[] = {GPIO2};
237 static const unsigned pins_exin3[] = {GPIO39};
238 static const unsigned pins_exin4[] = {GPIO46};
239 static const unsigned pins_exin5[] = {GPIO9};
240
241 static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
242 static const unsigned pins_spi_cs1[] = {GPIO15};
243 static const unsigned pins_spi_cs2[] = {GPIO21};
244 static const unsigned pins_spi_cs3[] = {GPIO13};
245 static const unsigned pins_spi_cs4[] = {GPIO10};
246 static const unsigned pins_spi_cs5[] = {GPIO9};
247 static const unsigned pins_spi_cs6[] = {GPIO11};
248
249 static const unsigned pins_gpt1[] = {GPIO28};
250 static const unsigned pins_gpt2[] = {GPIO21};
251 static const unsigned pins_gpt3[] = {GPIO6};
252
253 static const unsigned pins_clkout0[] = {GPIO8};
254 static const unsigned pins_clkout1[] = {GPIO7};
255 static const unsigned pins_clkout2[] = {GPIO3};
256 static const unsigned pins_clkout3[] = {GPIO2};
257
258 static const unsigned pins_pci_gnt1[] = {GPIO30};
259 static const unsigned pins_pci_gnt2[] = {GPIO23};
260 static const unsigned pins_pci_gnt3[] = {GPIO19};
261 static const unsigned pins_pci_gnt4[] = {GPIO38};
262 static const unsigned pins_pci_req1[] = {GPIO29};
263 static const unsigned pins_pci_req2[] = {GPIO31};
264 static const unsigned pins_pci_req3[] = {GPIO3};
265 static const unsigned pins_pci_req4[] = {GPIO37};
266
267 static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
268 static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
269 static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
270 static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4};
271 static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2};
272
273 static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10};
274 static const unsigned ase_pins_spi_cs1[] = {GPIO7};
275 static const unsigned ase_pins_spi_cs2[] = {GPIO15};
276 static const unsigned ase_pins_spi_cs3[] = {GPIO14};
277
278 static const unsigned ase_pins_exin0[] = {GPIO6};
279 static const unsigned ase_pins_exin1[] = {GPIO29};
280 static const unsigned ase_pins_exin2[] = {GPIO0};
281
282 static const unsigned ase_pins_gpt1[] = {GPIO5};
283 static const unsigned ase_pins_gpt2[] = {GPIO4};
284 static const unsigned ase_pins_gpt3[] = {GPIO25};
285
286 static const struct ltq_pin_group xway_grps[] = {
287 GRP_MUX("exin0", EXIN, pins_exin0),
288 GRP_MUX("exin1", EXIN, pins_exin1),
289 GRP_MUX("exin2", EXIN, pins_exin2),
290 GRP_MUX("jtag", JTAG, pins_jtag),
291 GRP_MUX("ebu a23", EBU, pins_ebu_a23),
292 GRP_MUX("ebu a24", EBU, pins_ebu_a24),
293 GRP_MUX("ebu a25", EBU, pins_ebu_a25),
294 GRP_MUX("ebu clk", EBU, pins_ebu_clk),
295 GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
296 GRP_MUX("ebu wait", EBU, pins_ebu_wait),
297 GRP_MUX("nand ale", EBU, pins_nand_ale),
298 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
299 GRP_MUX("nand cle", EBU, pins_nand_cle),
300 GRP_MUX("spi", SPI, pins_spi),
301 GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
302 GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
303 GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
304 GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
305 GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
306 GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
307 GRP_MUX("asc0", ASC, pins_asc0),
308 GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
309 GRP_MUX("stp", STP, pins_stp),
310 GRP_MUX("nmi", NMI, pins_nmi),
311 GRP_MUX("gpt1", GPT, pins_gpt1),
312 GRP_MUX("gpt2", GPT, pins_gpt2),
313 GRP_MUX("gpt3", GPT, pins_gpt3),
314 GRP_MUX("clkout0", CGU, pins_clkout0),
315 GRP_MUX("clkout1", CGU, pins_clkout1),
316 GRP_MUX("clkout2", CGU, pins_clkout2),
317 GRP_MUX("clkout3", CGU, pins_clkout3),
318 GRP_MUX("gnt1", PCI, pins_pci_gnt1),
319 GRP_MUX("gnt2", PCI, pins_pci_gnt2),
320 GRP_MUX("gnt3", PCI, pins_pci_gnt3),
321 GRP_MUX("req1", PCI, pins_pci_req1),
322 GRP_MUX("req2", PCI, pins_pci_req2),
323 GRP_MUX("req3", PCI, pins_pci_req3),
324 /* xrx only */
325 GRP_MUX("nand rdy", EBU, pins_nand_rdy),
326 GRP_MUX("nand rd", EBU, pins_nand_rd),
327 GRP_MUX("exin3", EXIN, pins_exin3),
328 GRP_MUX("exin4", EXIN, pins_exin4),
329 GRP_MUX("exin5", EXIN, pins_exin5),
330 GRP_MUX("gnt4", PCI, pins_pci_gnt4),
331 GRP_MUX("req4", PCI, pins_pci_gnt4),
332 GRP_MUX("mdio", MDIO, pins_mdio),
333 GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
334 GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
335 GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2),
336 GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
337 GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
338 GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
339 };
340
341 static const struct ltq_pin_group ase_grps[] = {
342 GRP_MUX("exin0", EXIN, ase_pins_exin0),
343 GRP_MUX("exin1", EXIN, ase_pins_exin1),
344 GRP_MUX("exin2", EXIN, ase_pins_exin2),
345 GRP_MUX("jtag", JTAG, ase_pins_jtag),
346 GRP_MUX("stp", STP, ase_pins_stp),
347 GRP_MUX("asc", ASC, ase_pins_asc),
348 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
349 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
350 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
351 GRP_MUX("ephy", EPHY, ase_pins_ephy),
352 GRP_MUX("dfe", DFE, ase_pins_dfe),
353 GRP_MUX("spi", SPI, ase_pins_spi),
354 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
355 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
356 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
357 };
358
359 static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
360 "gnt3", "req1",
361 "req2", "req3"};
362 static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
363 "spi_cs2", "spi_cs3",
364 "spi_cs4", "spi_cs5",
365 "spi_cs6"};
366 static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
367 "clkout2", "clkout3"};
368 static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
369 "ebu a25", "ebu cs1",
370 "ebu wait", "ebu clk",
371 "nand ale", "nand cs1",
372 "nand cle"};
373 static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
374 static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
375 static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
376 static const char * const xway_jtag_grps[] = {"jtag"};
377 static const char * const xway_stp_grps[] = {"stp"};
378 static const char * const xway_nmi_grps[] = {"nmi"};
379
380 /* ar9/vr9/gr9 */
381 static const char * const xrx_mdio_grps[] = {"mdio"};
382 static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
383 "gphy0 led2", "gphy1 led0",
384 "gphy1 led1", "gphy1 led2"};
385 static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
386 "ebu a25", "ebu cs1",
387 "ebu wait", "ebu clk",
388 "nand ale", "nand cs1",
389 "nand cle", "nand rdy",
390 "nand rd"};
391 static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
392 "exin3", "exin4", "exin5"};
393 static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
394 "gnt3", "gnt4",
395 "req1", "req2",
396 "req3", "req4"};
397
398 /* ase */
399 static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
400 static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
401 static const char * const ase_dfe_grps[] = {"dfe"};
402 static const char * const ase_ephy_grps[] = {"ephy"};
403 static const char * const ase_asc_grps[] = {"asc"};
404 static const char * const ase_jtag_grps[] = {"jtag"};
405 static const char * const ase_stp_grps[] = {"stp"};
406 static const char * const ase_spi_grps[] = {"spi", "spi_cs1",
407 "spi_cs2", "spi_cs3"};
408
409 static const struct ltq_pmx_func danube_funcs[] = {
410 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
411 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
412 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
413 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
414 {"exin", ARRAY_AND_SIZE(xway_exin_grps)},
415 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
416 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
417 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
418 {"pci", ARRAY_AND_SIZE(xway_pci_grps)},
419 {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)},
420 };
421
422 static const struct ltq_pmx_func xrx_funcs[] = {
423 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
424 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
425 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
426 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
427 {"exin", ARRAY_AND_SIZE(xrx_exin_grps)},
428 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
429 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
430 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
431 {"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
432 {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
433 {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
434 {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)},
435 };
436
437 static const struct ltq_pmx_func ase_funcs[] = {
438 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
439 {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
440 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
441 {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
442 {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
443 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
444 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
445 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
446 };
447
448 /* --------- pinconf related code --------- */
449 static int xway_pinconf_get(struct pinctrl_dev *pctldev,
450 unsigned pin,
451 unsigned long *config)
452 {
453 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
454 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
455 int port = PORT(pin);
456 u32 reg;
457
458 switch (param) {
459 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
460 if (port == PORT3)
461 reg = GPIO3_OD;
462 else
463 reg = GPIO_OD(pin);
464 *config = LTQ_PINCONF_PACK(param,
465 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
466 break;
467
468 case LTQ_PINCONF_PARAM_PULL:
469 if (port == PORT3)
470 reg = GPIO3_PUDEN;
471 else
472 reg = GPIO_PUDEN(pin);
473 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
474 *config = LTQ_PINCONF_PACK(param, 0);
475 break;
476 }
477
478 if (port == PORT3)
479 reg = GPIO3_PUDSEL;
480 else
481 reg = GPIO_PUDSEL(pin);
482 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
483 *config = LTQ_PINCONF_PACK(param, 2);
484 else
485 *config = LTQ_PINCONF_PACK(param, 1);
486 break;
487
488 case LTQ_PINCONF_PARAM_OUTPUT:
489 reg = GPIO_DIR(pin);
490 *config = LTQ_PINCONF_PACK(param,
491 gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
492 break;
493 default:
494 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
495 return -ENOTSUPP;
496 }
497 return 0;
498 }
499
500 static int xway_pinconf_set(struct pinctrl_dev *pctldev,
501 unsigned pin,
502 unsigned long *configs,
503 unsigned num_configs)
504 {
505 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
506 enum ltq_pinconf_param param;
507 int arg;
508 int port = PORT(pin);
509 u32 reg;
510 int i;
511
512 for (i = 0; i < num_configs; i++) {
513 param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
514 arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
515
516 switch (param) {
517 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
518 if (port == PORT3)
519 reg = GPIO3_OD;
520 else
521 reg = GPIO_OD(pin);
522 if (arg == 0)
523 gpio_setbit(info->membase[0],
524 reg,
525 PORT_PIN(pin));
526 else
527 gpio_clearbit(info->membase[0],
528 reg,
529 PORT_PIN(pin));
530 break;
531
532 case LTQ_PINCONF_PARAM_PULL:
533 if (port == PORT3)
534 reg = GPIO3_PUDEN;
535 else
536 reg = GPIO_PUDEN(pin);
537 if (arg == 0) {
538 gpio_clearbit(info->membase[0],
539 reg,
540 PORT_PIN(pin));
541 break;
542 }
543 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
544
545 if (port == PORT3)
546 reg = GPIO3_PUDSEL;
547 else
548 reg = GPIO_PUDSEL(pin);
549 if (arg == 1)
550 gpio_clearbit(info->membase[0],
551 reg,
552 PORT_PIN(pin));
553 else if (arg == 2)
554 gpio_setbit(info->membase[0],
555 reg,
556 PORT_PIN(pin));
557 else
558 dev_err(pctldev->dev,
559 "Invalid pull value %d\n", arg);
560 break;
561
562 case LTQ_PINCONF_PARAM_OUTPUT:
563 reg = GPIO_DIR(pin);
564 if (arg == 0)
565 gpio_clearbit(info->membase[0],
566 reg,
567 PORT_PIN(pin));
568 else
569 gpio_setbit(info->membase[0],
570 reg,
571 PORT_PIN(pin));
572 break;
573
574 default:
575 dev_err(pctldev->dev,
576 "Invalid config param %04x\n", param);
577 return -ENOTSUPP;
578 }
579 } /* for each config */
580
581 return 0;
582 }
583
584 int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
585 unsigned selector,
586 unsigned long *configs,
587 unsigned num_configs)
588 {
589 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
590 int i, ret = 0;
591
592 for (i = 0; i < info->grps[selector].npins && !ret; i++)
593 ret = xway_pinconf_set(pctldev,
594 info->grps[selector].pins[i],
595 configs,
596 num_configs);
597
598 return ret;
599 }
600
601 static const struct pinconf_ops xway_pinconf_ops = {
602 .pin_config_get = xway_pinconf_get,
603 .pin_config_set = xway_pinconf_set,
604 .pin_config_group_set = xway_pinconf_group_set,
605 };
606
607 static struct pinctrl_desc xway_pctrl_desc = {
608 .owner = THIS_MODULE,
609 .confops = &xway_pinconf_ops,
610 };
611
612 static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
613 int pin, int mux)
614 {
615 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
616 int port = PORT(pin);
617 u32 alt1_reg = GPIO_ALT1(pin);
618
619 if (port == PORT3)
620 alt1_reg = GPIO3_ALT1;
621
622 if (mux & MUX_ALT0)
623 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
624 else
625 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
626
627 if (mux & MUX_ALT1)
628 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
629 else
630 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
631
632 return 0;
633 }
634
635 static const struct ltq_cfg_param xway_cfg_params[] = {
636 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
637 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
638 {"lantiq,output", LTQ_PINCONF_PARAM_OUTPUT},
639 };
640
641 static struct ltq_pinmux_info xway_info = {
642 .desc = &xway_pctrl_desc,
643 .apply_mux = xway_mux_apply,
644 .params = xway_cfg_params,
645 .num_params = ARRAY_SIZE(xway_cfg_params),
646 };
647
648 /* --------- gpio_chip related code --------- */
649 static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
650 {
651 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
652
653 if (val)
654 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
655 else
656 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
657 }
658
659 static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
660 {
661 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
662
663 return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
664 }
665
666 static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
667 {
668 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
669
670 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
671
672 return 0;
673 }
674
675 static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
676 {
677 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
678
679 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
680 xway_gpio_set(chip, pin, val);
681
682 return 0;
683 }
684
685 static int xway_gpio_req(struct gpio_chip *chip, unsigned offset)
686 {
687 int gpio = chip->base + offset;
688
689 return pinctrl_request_gpio(gpio);
690 }
691
692 static void xway_gpio_free(struct gpio_chip *chip, unsigned offset)
693 {
694 int gpio = chip->base + offset;
695
696 pinctrl_free_gpio(gpio);
697 }
698
699 static struct gpio_chip xway_chip = {
700 .label = "gpio-xway",
701 .direction_input = xway_gpio_dir_in,
702 .direction_output = xway_gpio_dir_out,
703 .get = xway_gpio_get,
704 .set = xway_gpio_set,
705 .request = xway_gpio_req,
706 .free = xway_gpio_free,
707 .base = -1,
708 };
709
710
711 /* --------- register the pinctrl layer --------- */
712 static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
713 static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0};
714
715 static struct pinctrl_xway_soc {
716 int pin_count;
717 const struct ltq_mfp_pin *mfp;
718 const struct ltq_pin_group *grps;
719 unsigned int num_grps;
720 const struct ltq_pmx_func *funcs;
721 unsigned int num_funcs;
722 const unsigned *exin;
723 unsigned int num_exin;
724 } soc_cfg[] = {
725 /* legacy xway */
726 {XWAY_MAX_PIN, xway_mfp,
727 xway_grps, ARRAY_SIZE(xway_grps),
728 danube_funcs, ARRAY_SIZE(danube_funcs),
729 xway_exin_pin_map, 3},
730 /* xway xr9 series */
731 {XR9_MAX_PIN, xway_mfp,
732 xway_grps, ARRAY_SIZE(xway_grps),
733 xrx_funcs, ARRAY_SIZE(xrx_funcs),
734 xway_exin_pin_map, 6},
735 /* xway ase series */
736 {XWAY_MAX_PIN, ase_mfp,
737 ase_grps, ARRAY_SIZE(ase_grps),
738 ase_funcs, ARRAY_SIZE(ase_funcs),
739 ase_exin_pins_map, 3},
740 };
741
742 static struct pinctrl_gpio_range xway_gpio_range = {
743 .name = "XWAY GPIO",
744 .gc = &xway_chip,
745 };
746
747 static const struct of_device_id xway_match[] = {
748 { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]},
749 { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]},
750 { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]},
751 {},
752 };
753 MODULE_DEVICE_TABLE(of, xway_match);
754
755 static int pinmux_xway_probe(struct platform_device *pdev)
756 {
757 const struct of_device_id *match;
758 const struct pinctrl_xway_soc *xway_soc;
759 struct resource *res;
760 int ret, i;
761
762 /* get and remap our register range */
763 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
764 xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res);
765 if (IS_ERR(xway_info.membase[0]))
766 return PTR_ERR(xway_info.membase[0]);
767
768 match = of_match_device(xway_match, &pdev->dev);
769 if (match)
770 xway_soc = (const struct pinctrl_xway_soc *) match->data;
771 else
772 xway_soc = &soc_cfg[0];
773
774 /* find out how many pads we have */
775 xway_chip.ngpio = xway_soc->pin_count;
776
777 /* load our pad descriptors */
778 xway_info.pads = devm_kzalloc(&pdev->dev,
779 sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio,
780 GFP_KERNEL);
781 if (!xway_info.pads) {
782 dev_err(&pdev->dev, "Failed to allocate pads\n");
783 return -ENOMEM;
784 }
785 for (i = 0; i < xway_chip.ngpio; i++) {
786 /* strlen("ioXY") + 1 = 5 */
787 char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
788
789 if (!name) {
790 dev_err(&pdev->dev, "Failed to allocate pad name\n");
791 return -ENOMEM;
792 }
793 snprintf(name, 5, "io%d", i);
794 xway_info.pads[i].number = GPIO0 + i;
795 xway_info.pads[i].name = name;
796 }
797 xway_pctrl_desc.pins = xway_info.pads;
798
799 /* load the gpio chip */
800 xway_chip.dev = &pdev->dev;
801 ret = gpiochip_add(&xway_chip);
802 if (ret) {
803 dev_err(&pdev->dev, "Failed to register gpio chip\n");
804 return ret;
805 }
806
807 /* setup the data needed by pinctrl */
808 xway_pctrl_desc.name = dev_name(&pdev->dev);
809 xway_pctrl_desc.npins = xway_chip.ngpio;
810
811 xway_info.num_pads = xway_chip.ngpio;
812 xway_info.num_mfp = xway_chip.ngpio;
813 xway_info.mfp = xway_soc->mfp;
814 xway_info.grps = xway_soc->grps;
815 xway_info.num_grps = xway_soc->num_grps;
816 xway_info.funcs = xway_soc->funcs;
817 xway_info.num_funcs = xway_soc->num_funcs;
818 xway_info.exin = xway_soc->exin;
819 xway_info.num_exin = xway_soc->num_exin;
820
821 /* register with the generic lantiq layer */
822 ret = ltq_pinctrl_register(pdev, &xway_info);
823 if (ret) {
824 gpiochip_remove(&xway_chip);
825 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
826 return ret;
827 }
828
829 /* finish with registering the gpio range in pinctrl */
830 xway_gpio_range.npins = xway_chip.ngpio;
831 xway_gpio_range.base = xway_chip.base;
832 pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
833 dev_info(&pdev->dev, "Init done\n");
834 return 0;
835 }
836
837 static struct platform_driver pinmux_xway_driver = {
838 .probe = pinmux_xway_probe,
839 .driver = {
840 .name = "pinctrl-xway",
841 .of_match_table = xway_match,
842 },
843 };
844
845 static int __init pinmux_xway_init(void)
846 {
847 return platform_driver_register(&pinmux_xway_driver);
848 }
849
850 core_initcall_sync(pinmux_xway_init);
Linux with added FPC-III support