arch/arm64/boot/dts/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/memory/tegra186-mc.h>
   7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   8 #include <dt-bindings/power/tegra186-powergate.h>
   9 #include <dt-bindings/reset/tegra186-reset.h>
  10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
  11
  12 / {
  13         compatible = "nvidia,tegra186";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         misc@100000 {
  19                 compatible = "nvidia,tegra186-misc";
  20                 reg = <0x0 0x00100000 0x0 0xf000>,
  21                       <0x0 0x0010f000 0x0 0x1000>;
  22         };
  23
  24         gpio: gpio@2200000 {
  25                 compatible = "nvidia,tegra186-gpio";
  26                 reg-names = "security", "gpio";
  27                 reg = <0x0 0x2200000 0x0 0x10000>,
  28                       <0x0 0x2210000 0x0 0x10000>;
  29                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  34                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  35                 #interrupt-cells = <2>;
  36                 interrupt-controller;
  37                 #gpio-cells = <2>;
  38                 gpio-controller;
  39         };
  40
  41         ethernet@2490000 {
  42                 compatible = "nvidia,tegra186-eqos",
  43                              "snps,dwc-qos-ethernet-4.10";
  44                 reg = <0x0 0x02490000 0x0 0x10000>;
  45                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  46                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  47                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  48                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  49                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  50                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  51                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  52                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  53                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  54                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  55                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  56                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  57                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  58                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  59                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  60                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  61                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  62                 reset-names = "eqos";
  63                 iommus = <&smmu TEGRA186_SID_EQOS>;
  64                 status = "disabled";
  65
  66                 snps,write-requests = <1>;
  67                 snps,read-requests = <3>;
  68                 snps,burst-map = <0x7>;
  69                 snps,txpbl = <32>;
  70                 snps,rxpbl = <8>;
  71         };
  72
  73         aconnect {
  74                 compatible = "nvidia,tegra186-aconnect",
  75                              "nvidia,tegra210-aconnect";
  76                 clocks = <&bpmp TEGRA186_CLK_APE>,
  77                          <&bpmp TEGRA186_CLK_APB2APE>;
  78                 clock-names = "ape", "apb2ape";
  79                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges = <0x02900000 0x0 0x02900000 0x200000>;
  83                 status = "disabled";
  84
  85                 dma-controller@2930000 {
  86                         compatible = "nvidia,tegra186-adma";
  87                         reg = <0x02930000 0x20000>;
  88                         interrupt-parent = <&agic>;
  89                         interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                       <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  91                                       <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  92                                       <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  93                                       <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  94                                       <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  95                                       <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  96                                       <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  97                                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  98                                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  99                                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 100                                       <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 101                                       <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 102                                       <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 104                                       <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 105                                       <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 106                                       <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 107                                       <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 108                                       <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 109                                       <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 110                                       <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 111                                       <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 112                                       <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 113                                       <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 114                                       <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 115                                       <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 116                                       <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 117                                       <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 118                                       <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 119                                       <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 120                                       <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 121                         #dma-cells = <1>;
 122                         clocks = <&bpmp TEGRA186_CLK_AHUB>;
 123                         clock-names = "d_audio";
 124                         status = "disabled";
 125                 };
 126
 127                 agic: interrupt-controller@2a40000 {
 128                         compatible = "nvidia,tegra186-agic",
 129                                      "nvidia,tegra210-agic";
 130                         #interrupt-cells = <3>;
 131                         interrupt-controller;
 132                         reg = <0x02a41000 0x1000>,
 133                               <0x02a42000 0x2000>;
 134                         interrupts = <GIC_SPI 145
 135                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 136                         clocks = <&bpmp TEGRA186_CLK_APE>;
 137                         clock-names = "clk";
 138                         status = "disabled";
 139                 };
 140         };
 141
 142         memory-controller@2c00000 {
 143                 compatible = "nvidia,tegra186-mc";
 144                 reg = <0x0 0x02c00000 0x0 0xb0000>;
 145                 status = "disabled";
 146         };
 147
 148         uarta: serial@3100000 {
 149                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 150                 reg = <0x0 0x03100000 0x0 0x40>;
 151                 reg-shift = <2>;
 152                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 153                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
 154                 clock-names = "serial";
 155                 resets = <&bpmp TEGRA186_RESET_UARTA>;
 156                 reset-names = "serial";
 157                 status = "disabled";
 158         };
 159
 160         uartb: serial@3110000 {
 161                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 162                 reg = <0x0 0x03110000 0x0 0x40>;
 163                 reg-shift = <2>;
 164                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 165                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
 166                 clock-names = "serial";
 167                 resets = <&bpmp TEGRA186_RESET_UARTB>;
 168                 reset-names = "serial";
 169                 status = "disabled";
 170         };
 171
 172         uartd: serial@3130000 {
 173                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 174                 reg = <0x0 0x03130000 0x0 0x40>;
 175                 reg-shift = <2>;
 176                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
 178                 clock-names = "serial";
 179                 resets = <&bpmp TEGRA186_RESET_UARTD>;
 180                 reset-names = "serial";
 181                 status = "disabled";
 182         };
 183
 184         uarte: serial@3140000 {
 185                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 186                 reg = <0x0 0x03140000 0x0 0x40>;
 187                 reg-shift = <2>;
 188                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 190                 clock-names = "serial";
 191                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 192                 reset-names = "serial";
 193                 status = "disabled";
 194         };
 195
 196         uartf: serial@3150000 {
 197                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 198                 reg = <0x0 0x03150000 0x0 0x40>;
 199                 reg-shift = <2>;
 200                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 202                 clock-names = "serial";
 203                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 204                 reset-names = "serial";
 205                 status = "disabled";
 206         };
 207
 208         gen1_i2c: i2c@3160000 {
 209                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 210                 reg = <0x0 0x03160000 0x0 0x10000>;
 211                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 215                 clock-names = "div-clk";
 216                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 217                 reset-names = "i2c";
 218                 status = "disabled";
 219         };
 220
 221         cam_i2c: i2c@3180000 {
 222                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 223                 reg = <0x0 0x03180000 0x0 0x10000>;
 224                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 228                 clock-names = "div-clk";
 229                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 230                 reset-names = "i2c";
 231                 status = "disabled";
 232         };
 233
 234         /* shares pads with dpaux1 */
 235         dp_aux_ch1_i2c: i2c@3190000 {
 236                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 237                 reg = <0x0 0x03190000 0x0 0x10000>;
 238                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 242                 clock-names = "div-clk";
 243                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 244                 reset-names = "i2c";
 245                 pinctrl-names = "default", "idle";
 246                 pinctrl-0 = <&state_dpaux1_i2c>;
 247                 pinctrl-1 = <&state_dpaux1_off>;
 248                 status = "disabled";
 249         };
 250
 251         /* controlled by BPMP, should not be enabled */
 252         pwr_i2c: i2c@31a0000 {
 253                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 254                 reg = <0x0 0x031a0000 0x0 0x10000>;
 255                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 259                 clock-names = "div-clk";
 260                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 261                 reset-names = "i2c";
 262                 status = "disabled";
 263         };
 264
 265         /* shares pads with dpaux0 */
 266         dp_aux_ch0_i2c: i2c@31b0000 {
 267                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 268                 reg = <0x0 0x031b0000 0x0 0x10000>;
 269                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 273                 clock-names = "div-clk";
 274                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 275                 reset-names = "i2c";
 276                 pinctrl-names = "default", "idle";
 277                 pinctrl-0 = <&state_dpaux_i2c>;
 278                 pinctrl-1 = <&state_dpaux_off>;
 279                 status = "disabled";
 280         };
 281
 282         gen7_i2c: i2c@31c0000 {
 283                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 284                 reg = <0x0 0x031c0000 0x0 0x10000>;
 285                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 289                 clock-names = "div-clk";
 290                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 291                 reset-names = "i2c";
 292                 status = "disabled";
 293         };
 294
 295         gen9_i2c: i2c@31e0000 {
 296                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 297                 reg = <0x0 0x031e0000 0x0 0x10000>;
 298                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 302                 clock-names = "div-clk";
 303                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 304                 reset-names = "i2c";
 305                 status = "disabled";
 306         };
 307
 308         sdmmc1: sdhci@3400000 {
 309                 compatible = "nvidia,tegra186-sdhci";
 310                 reg = <0x0 0x03400000 0x0 0x10000>;
 311                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 313                 clock-names = "sdhci";
 314                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 315                 reset-names = "sdhci";
 316                 iommus = <&smmu TEGRA186_SID_SDMMC1>;
 317                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 318                 pinctrl-0 = <&sdmmc1_3v3>;
 319                 pinctrl-1 = <&sdmmc1_1v8>;
 320                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 321                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 322                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 323                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 324                 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
 325                 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
 326                 nvidia,default-tap = <0x5>;
 327                 nvidia,default-trim = <0xb>;
 328                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
 329                                   <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 330                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 331                 status = "disabled";
 332         };
 333
 334         sdmmc2: sdhci@3420000 {
 335                 compatible = "nvidia,tegra186-sdhci";
 336                 reg = <0x0 0x03420000 0x0 0x10000>;
 337                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 339                 clock-names = "sdhci";
 340                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 341                 reset-names = "sdhci";
 342                 iommus = <&smmu TEGRA186_SID_SDMMC2>;
 343                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 344                 pinctrl-0 = <&sdmmc2_3v3>;
 345                 pinctrl-1 = <&sdmmc2_1v8>;
 346                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 347                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 348                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 349                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 350                 nvidia,default-tap = <0x5>;
 351                 nvidia,default-trim = <0xb>;
 352                 status = "disabled";
 353         };
 354
 355         sdmmc3: sdhci@3440000 {
 356                 compatible = "nvidia,tegra186-sdhci";
 357                 reg = <0x0 0x03440000 0x0 0x10000>;
 358                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 360                 clock-names = "sdhci";
 361                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 362                 reset-names = "sdhci";
 363                 iommus = <&smmu TEGRA186_SID_SDMMC3>;
 364                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 365                 pinctrl-0 = <&sdmmc3_3v3>;
 366                 pinctrl-1 = <&sdmmc3_1v8>;
 367                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 368                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 369                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 370                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 371                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 372                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 373                 nvidia,default-tap = <0x5>;
 374                 nvidia,default-trim = <0xb>;
 375                 status = "disabled";
 376         };
 377
 378         sdmmc4: sdhci@3460000 {
 379                 compatible = "nvidia,tegra186-sdhci";
 380                 reg = <0x0 0x03460000 0x0 0x10000>;
 381                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 382                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 383                 clock-names = "sdhci";
 384                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
 385                                   <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 386                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 387                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 388                 reset-names = "sdhci";
 389                 iommus = <&smmu TEGRA186_SID_SDMMC4>;
 390                 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
 391                 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
 392                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 393                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
 394                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 395                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
 396                 nvidia,default-tap = <0x9>;
 397                 nvidia,default-trim = <0x5>;
 398                 nvidia,dqs-trim = <63>;
 399                 mmc-hs400-1_8v;
 400                 supports-cqe;
 401                 status = "disabled";
 402         };
 403
 404         hda@3510000 {
 405                 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
 406                 reg = <0x0 0x03510000 0x0 0x10000>;
 407                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&bpmp TEGRA186_CLK_HDA>,
 409                          <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
 410                          <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
 411                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 412                 resets = <&bpmp TEGRA186_RESET_HDA>,
 413                          <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
 414                          <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
 415                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 416                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 417                 iommus = <&smmu TEGRA186_SID_HDA>;
 418                 status = "disabled";
 419         };
 420
 421         padctl: padctl@3520000 {
 422                 compatible = "nvidia,tegra186-xusb-padctl";
 423                 reg = <0x0 0x03520000 0x0 0x1000>,
 424                       <0x0 0x03540000 0x0 0x1000>;
 425                 reg-names = "padctl", "ao";
 426
 427                 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
 428                 reset-names = "padctl";
 429
 430                 status = "disabled";
 431
 432                 pads {
 433                         usb2 {
 434                                 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
 435                                 clock-names = "trk";
 436                                 status = "disabled";
 437
 438                                 lanes {
 439                                         usb2-0 {
 440                                                 status = "disabled";
 441                                                 #phy-cells = <0>;
 442                                         };
 443
 444                                         usb2-1 {
 445                                                 status = "disabled";
 446                                                 #phy-cells = <0>;
 447                                         };
 448
 449                                         usb2-2 {
 450                                                 status = "disabled";
 451                                                 #phy-cells = <0>;
 452                                         };
 453                                 };
 454                         };
 455
 456                         hsic {
 457                                 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
 458                                 clock-names = "trk";
 459                                 status = "disabled";
 460
 461                                 lanes {
 462                                         hsic-0 {
 463                                                 status = "disabled";
 464                                                 #phy-cells = <0>;
 465                                         };
 466                                 };
 467                         };
 468
 469                         usb3 {
 470                                 status = "disabled";
 471
 472                                 lanes {
 473                                         usb3-0 {
 474                                                 status = "disabled";
 475                                                 #phy-cells = <0>;
 476                                         };
 477
 478                                         usb3-1 {
 479                                                 status = "disabled";
 480                                                 #phy-cells = <0>;
 481                                         };
 482
 483                                         usb3-2 {
 484                                                 status = "disabled";
 485                                                 #phy-cells = <0>;
 486                                         };
 487                                 };
 488                         };
 489                 };
 490
 491                 ports {
 492                         usb2-0 {
 493                                 status = "disabled";
 494                         };
 495
 496                         usb2-1 {
 497                                 status = "disabled";
 498                         };
 499
 500                         usb2-2 {
 501                                 status = "disabled";
 502                         };
 503
 504                         hsic-0 {
 505                                 status = "disabled";
 506                         };
 507
 508                         usb3-0 {
 509                                 status = "disabled";
 510                         };
 511
 512                         usb3-1 {
 513                                 status = "disabled";
 514                         };
 515
 516                         usb3-2 {
 517                                 status = "disabled";
 518                         };
 519                 };
 520         };
 521
 522         usb@3530000 {
 523                 compatible = "nvidia,tegra186-xusb";
 524                 reg = <0x0 0x03530000 0x0 0x8000>,
 525                       <0x0 0x03538000 0x0 0x1000>;
 526                 reg-names = "hcd", "fpci";
 527
 528                 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
 529                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 530                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 531                              <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 532
 533                 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
 534                          <&bpmp TEGRA186_CLK_XUSB_FALCON>,
 535                          <&bpmp TEGRA186_CLK_XUSB_SS>,
 536                          <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
 537                          <&bpmp TEGRA186_CLK_CLK_M>,
 538                          <&bpmp TEGRA186_CLK_XUSB_FS>,
 539                          <&bpmp TEGRA186_CLK_PLLU>,
 540                          <&bpmp TEGRA186_CLK_CLK_M>,
 541                          <&bpmp TEGRA186_CLK_PLLE>;
 542                 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
 543                               "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
 544                               "pll_u_480m", "clk_m", "pll_e";
 545
 546                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
 547                                 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
 548                 power-domain-names = "xusb_host", "xusb_ss";
 549                 nvidia,xusb-padctl = <&padctl>;
 550
 551                 status = "disabled";
 552
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555         };
 556
 557         fuse@3820000 {
 558                 compatible = "nvidia,tegra186-efuse";
 559                 reg = <0x0 0x03820000 0x0 0x10000>;
 560                 clocks = <&bpmp TEGRA186_CLK_FUSE>;
 561                 clock-names = "fuse";
 562         };
 563
 564         gic: interrupt-controller@3881000 {
 565                 compatible = "arm,gic-400";
 566                 #interrupt-cells = <3>;
 567                 interrupt-controller;
 568                 reg = <0x0 0x03881000 0x0 0x1000>,
 569                       <0x0 0x03882000 0x0 0x2000>;
 570                 interrupts = <GIC_PPI 9
 571                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 572                 interrupt-parent = <&gic>;
 573         };
 574
 575         cec@3960000 {
 576                 compatible = "nvidia,tegra186-cec";
 577                 reg = <0x0 0x03960000 0x0 0x10000>;
 578                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&bpmp TEGRA186_CLK_CEC>;
 580                 clock-names = "cec";
 581                 status = "disabled";
 582         };
 583
 584         hsp_top0: hsp@3c00000 {
 585                 compatible = "nvidia,tegra186-hsp";
 586                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 587                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 588                 interrupt-names = "doorbell";
 589                 #mbox-cells = <2>;
 590                 status = "disabled";
 591         };
 592
 593         gen2_i2c: i2c@c240000 {
 594                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 595                 reg = <0x0 0x0c240000 0x0 0x10000>;
 596                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 600                 clock-names = "div-clk";
 601                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 602                 reset-names = "i2c";
 603                 status = "disabled";
 604         };
 605
 606         gen8_i2c: i2c@c250000 {
 607                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 608                 reg = <0x0 0x0c250000 0x0 0x10000>;
 609                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 613                 clock-names = "div-clk";
 614                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 615                 reset-names = "i2c";
 616                 status = "disabled";
 617         };
 618
 619         uartc: serial@c280000 {
 620                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 621                 reg = <0x0 0x0c280000 0x0 0x40>;
 622                 reg-shift = <2>;
 623                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 625                 clock-names = "serial";
 626                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 627                 reset-names = "serial";
 628                 status = "disabled";
 629         };
 630
 631         uartg: serial@c290000 {
 632                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 633                 reg = <0x0 0x0c290000 0x0 0x40>;
 634                 reg-shift = <2>;
 635                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 636                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 637                 clock-names = "serial";
 638                 resets = <&bpmp TEGRA186_RESET_UARTG>;
 639                 reset-names = "serial";
 640                 status = "disabled";
 641         };
 642
 643         rtc: rtc@c2a0000 {
 644                 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
 645                 reg = <0 0x0c2a0000 0 0x10000>;
 646                 interrupt-parent = <&pmc>;
 647                 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
 649                 clock-names = "rtc";
 650                 status = "disabled";
 651         };
 652
 653         gpio_aon: gpio@c2f0000 {
 654                 compatible = "nvidia,tegra186-gpio-aon";
 655                 reg-names = "security", "gpio";
 656                 reg = <0x0 0xc2f0000 0x0 0x1000>,
 657                       <0x0 0xc2f1000 0x0 0x1000>;
 658                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 659                 gpio-controller;
 660                 #gpio-cells = <2>;
 661                 interrupt-controller;
 662                 #interrupt-cells = <2>;
 663         };
 664
 665         pmc: pmc@c360000 {
 666                 compatible = "nvidia,tegra186-pmc";
 667                 reg = <0 0x0c360000 0 0x10000>,
 668                       <0 0x0c370000 0 0x10000>,
 669                       <0 0x0c380000 0 0x10000>,
 670                       <0 0x0c390000 0 0x10000>;
 671                 reg-names = "pmc", "wake", "aotag", "scratch";
 672
 673                 #interrupt-cells = <2>;
 674                 interrupt-controller;
 675
 676                 sdmmc1_3v3: sdmmc1-3v3 {
 677                         pins = "sdmmc1-hv";
 678                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 679                 };
 680
 681                 sdmmc1_1v8: sdmmc1-1v8 {
 682                         pins = "sdmmc1-hv";
 683                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 684                 };
 685
 686                 sdmmc2_3v3: sdmmc2-3v3 {
 687                         pins = "sdmmc2-hv";
 688                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 689                 };
 690
 691                 sdmmc2_1v8: sdmmc2-1v8 {
 692                         pins = "sdmmc2-hv";
 693                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 694                 };
 695
 696                 sdmmc3_3v3: sdmmc3-3v3 {
 697                         pins = "sdmmc3-hv";
 698                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 699                 };
 700
 701                 sdmmc3_1v8: sdmmc3-1v8 {
 702                         pins = "sdmmc3-hv";
 703                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 704                 };
 705         };
 706
 707         ccplex@e000000 {
 708                 compatible = "nvidia,tegra186-ccplex-cluster";
 709                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
 710
 711                 nvidia,bpmp = <&bpmp>;
 712         };
 713
 714         pcie@10003000 {
 715                 compatible = "nvidia,tegra186-pcie";
 716                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
 717                 device_type = "pci";
 718                 reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
 719                        0x0 0x10003800 0x0 0x00000800   /* AFI registers */
 720                        0x0 0x40000000 0x0 0x10000000>; /* configuration space */
 721                 reg-names = "pads", "afi", "cs";
 722
 723                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 724                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 725                 interrupt-names = "intr", "msi";
 726
 727                 #interrupt-cells = <1>;
 728                 interrupt-map-mask = <0 0 0 0>;
 729                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 730
 731                 bus-range = <0x00 0xff>;
 732                 #address-cells = <3>;
 733                 #size-cells = <2>;
 734
 735                 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
 736                           0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
 737                           0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
 738                           0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
 739                           0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
 740                           0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
 741
 742                 clocks = <&bpmp TEGRA186_CLK_AFI>,
 743                          <&bpmp TEGRA186_CLK_PCIE>,
 744                          <&bpmp TEGRA186_CLK_PLLE>;
 745                 clock-names = "afi", "pex", "pll_e";
 746
 747                 resets = <&bpmp TEGRA186_RESET_AFI>,
 748                          <&bpmp TEGRA186_RESET_PCIE>,
 749                          <&bpmp TEGRA186_RESET_PCIEXCLK>;
 750                 reset-names = "afi", "pex", "pcie_x";
 751
 752                 iommus = <&smmu TEGRA186_SID_AFI>;
 753                 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
 754                 iommu-map-mask = <0x0>;
 755
 756                 status = "disabled";
 757
 758                 pci@1,0 {
 759                         device_type = "pci";
 760                         assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
 761                         reg = <0x000800 0 0 0 0>;
 762                         status = "disabled";
 763
 764                         #address-cells = <3>;
 765                         #size-cells = <2>;
 766                         ranges;
 767
 768                         nvidia,num-lanes = <2>;
 769                 };
 770
 771                 pci@2,0 {
 772                         device_type = "pci";
 773                         assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
 774                         reg = <0x001000 0 0 0 0>;
 775                         status = "disabled";
 776
 777                         #address-cells = <3>;
 778                         #size-cells = <2>;
 779                         ranges;
 780
 781                         nvidia,num-lanes = <1>;
 782                 };
 783
 784                 pci@3,0 {
 785                         device_type = "pci";
 786                         assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
 787                         reg = <0x001800 0 0 0 0>;
 788                         status = "disabled";
 789
 790                         #address-cells = <3>;
 791                         #size-cells = <2>;
 792                         ranges;
 793
 794                         nvidia,num-lanes = <1>;
 795                 };
 796         };
 797
 798         smmu: iommu@12000000 {
 799                 compatible = "arm,mmu-500";
 800                 reg = <0 0x12000000 0 0x800000>;
 801                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 802                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 803                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 804                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 805                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 806                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 807                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 808                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 809                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 810                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 811                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 812                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 813                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 814                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 815                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 816                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 817                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 818                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 819                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 820                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 821                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 822                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 823                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 824                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 825                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 826                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 827                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 828                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 829                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 830                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 831                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 832                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 833                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 834                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 836                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 837                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 838                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 839                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 840                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 841                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 842                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 843                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 844                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 845                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 846                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 847                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 848                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 849                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 850                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 851                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 852                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 853                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 854                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 855                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 856                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 857                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 858                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 859                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 860                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 861                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 862                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 863                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 864                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 865                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 866                 stream-match-mask = <0x7f80>;
 867                 #global-interrupts = <1>;
 868                 #iommu-cells = <1>;
 869         };
 870
 871         host1x@13e00000 {
 872                 compatible = "nvidia,tegra186-host1x", "simple-bus";
 873                 reg = <0x0 0x13e00000 0x0 0x10000>,
 874                       <0x0 0x13e10000 0x0 0x10000>;
 875                 reg-names = "hypervisor", "vm";
 876                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 877                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 878                 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
 879                 clock-names = "host1x";
 880                 resets = <&bpmp TEGRA186_RESET_HOST1X>;
 881                 reset-names = "host1x";
 882
 883                 #address-cells = <1>;
 884                 #size-cells = <1>;
 885
 886                 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
 887                 iommus = <&smmu TEGRA186_SID_HOST1X>;
 888
 889                 dpaux1: dpaux@15040000 {
 890                         compatible = "nvidia,tegra186-dpaux";
 891                         reg = <0x15040000 0x10000>;
 892                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 893                         clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
 894                                  <&bpmp TEGRA186_CLK_PLLDP>;
 895                         clock-names = "dpaux", "parent";
 896                         resets = <&bpmp TEGRA186_RESET_DPAUX1>;
 897                         reset-names = "dpaux";
 898                         status = "disabled";
 899
 900                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 901
 902                         state_dpaux1_aux: pinmux-aux {
 903                                 groups = "dpaux-io";
 904                                 function = "aux";
 905                         };
 906
 907                         state_dpaux1_i2c: pinmux-i2c {
 908                                 groups = "dpaux-io";
 909                                 function = "i2c";
 910                         };
 911
 912                         state_dpaux1_off: pinmux-off {
 913                                 groups = "dpaux-io";
 914                                 function = "off";
 915                         };
 916
 917                         i2c-bus {
 918                                 #address-cells = <1>;
 919                                 #size-cells = <0>;
 920                         };
 921                 };
 922
 923                 display-hub@15200000 {
 924                         compatible = "nvidia,tegra186-display", "simple-bus";
 925                         reg = <0x15200000 0x00040000>;
 926                         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
 927                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
 928                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
 929                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
 930                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
 931                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
 932                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
 933                         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 934                                       "wgrp3", "wgrp4", "wgrp5";
 935                         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
 936                                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
 937                                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
 938                         clock-names = "disp", "dsc", "hub";
 939                         status = "disabled";
 940
 941                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 942
 943                         #address-cells = <1>;
 944                         #size-cells = <1>;
 945
 946                         ranges = <0x15200000 0x15200000 0x40000>;
 947
 948                         display@15200000 {
 949                                 compatible = "nvidia,tegra186-dc";
 950                                 reg = <0x15200000 0x10000>;
 951                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 952                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
 953                                 clock-names = "dc";
 954                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
 955                                 reset-names = "dc";
 956
 957                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 958                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 959
 960                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 961                                 nvidia,head = <0>;
 962                         };
 963
 964                         display@15210000 {
 965                                 compatible = "nvidia,tegra186-dc";
 966                                 reg = <0x15210000 0x10000>;
 967                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 968                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
 969                                 clock-names = "dc";
 970                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
 971                                 reset-names = "dc";
 972
 973                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
 974                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 975
 976                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 977                                 nvidia,head = <1>;
 978                         };
 979
 980                         display@15220000 {
 981                                 compatible = "nvidia,tegra186-dc";
 982                                 reg = <0x15220000 0x10000>;
 983                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 984                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
 985                                 clock-names = "dc";
 986                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
 987                                 reset-names = "dc";
 988
 989                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
 990                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 991
 992                                 nvidia,outputs = <&sor0 &sor1>;
 993                                 nvidia,head = <2>;
 994                         };
 995                 };
 996
 997                 dsia: dsi@15300000 {
 998                         compatible = "nvidia,tegra186-dsi";
 999                         reg = <0x15300000 0x10000>;
1000                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1001                         clocks = <&bpmp TEGRA186_CLK_DSI>,
1002                                  <&bpmp TEGRA186_CLK_DSIA_LP>,
1003                                  <&bpmp TEGRA186_CLK_PLLD>;
1004                         clock-names = "dsi", "lp", "parent";
1005                         resets = <&bpmp TEGRA186_RESET_DSI>;
1006                         reset-names = "dsi";
1007                         status = "disabled";
1008
1009                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1010                 };
1011
1012                 vic@15340000 {
1013                         compatible = "nvidia,tegra186-vic";
1014                         reg = <0x15340000 0x40000>;
1015                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1016                         clocks = <&bpmp TEGRA186_CLK_VIC>;
1017                         clock-names = "vic";
1018                         resets = <&bpmp TEGRA186_RESET_VIC>;
1019                         reset-names = "vic";
1020
1021                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1022                         iommus = <&smmu TEGRA186_SID_VIC>;
1023                 };
1024
1025                 dsib: dsi@15400000 {
1026                         compatible = "nvidia,tegra186-dsi";
1027                         reg = <0x15400000 0x10000>;
1028                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1029                         clocks = <&bpmp TEGRA186_CLK_DSIB>,
1030                                  <&bpmp TEGRA186_CLK_DSIB_LP>,
1031                                  <&bpmp TEGRA186_CLK_PLLD>;
1032                         clock-names = "dsi", "lp", "parent";
1033                         resets = <&bpmp TEGRA186_RESET_DSIB>;
1034                         reset-names = "dsi";
1035                         status = "disabled";
1036
1037                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1038                 };
1039
1040                 sor0: sor@15540000 {
1041                         compatible = "nvidia,tegra186-sor";
1042                         reg = <0x15540000 0x10000>;
1043                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1044                         clocks = <&bpmp TEGRA186_CLK_SOR0>,
1045                                  <&bpmp TEGRA186_CLK_SOR0_OUT>,
1046                                  <&bpmp TEGRA186_CLK_PLLD2>,
1047                                  <&bpmp TEGRA186_CLK_PLLDP>,
1048                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
1049                                  <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1050                         clock-names = "sor", "out", "parent", "dp", "safe",
1051                                       "pad";
1052                         resets = <&bpmp TEGRA186_RESET_SOR0>;
1053                         reset-names = "sor";
1054                         pinctrl-0 = <&state_dpaux_aux>;
1055                         pinctrl-1 = <&state_dpaux_i2c>;
1056                         pinctrl-2 = <&state_dpaux_off>;
1057                         pinctrl-names = "aux", "i2c", "off";
1058                         status = "disabled";
1059
1060                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1061                         nvidia,interface = <0>;
1062                 };
1063
1064                 sor1: sor@15580000 {
1065                         compatible = "nvidia,tegra186-sor";
1066                         reg = <0x15580000 0x10000>;
1067                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1068                         clocks = <&bpmp TEGRA186_CLK_SOR1>,
1069                                  <&bpmp TEGRA186_CLK_SOR1_OUT>,
1070                                  <&bpmp TEGRA186_CLK_PLLD3>,
1071                                  <&bpmp TEGRA186_CLK_PLLDP>,
1072                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
1073                                  <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1074                         clock-names = "sor", "out", "parent", "dp", "safe",
1075                                       "pad";
1076                         resets = <&bpmp TEGRA186_RESET_SOR1>;
1077                         reset-names = "sor";
1078                         pinctrl-0 = <&state_dpaux1_aux>;
1079                         pinctrl-1 = <&state_dpaux1_i2c>;
1080                         pinctrl-2 = <&state_dpaux1_off>;
1081                         pinctrl-names = "aux", "i2c", "off";
1082                         status = "disabled";
1083
1084                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1085                         nvidia,interface = <1>;
1086                 };
1087
1088                 dpaux: dpaux@155c0000 {
1089                         compatible = "nvidia,tegra186-dpaux";
1090                         reg = <0x155c0000 0x10000>;
1091                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1092                         clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1093                                  <&bpmp TEGRA186_CLK_PLLDP>;
1094                         clock-names = "dpaux", "parent";
1095                         resets = <&bpmp TEGRA186_RESET_DPAUX>;
1096                         reset-names = "dpaux";
1097                         status = "disabled";
1098
1099                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1100
1101                         state_dpaux_aux: pinmux-aux {
1102                                 groups = "dpaux-io";
1103                                 function = "aux";
1104                         };
1105
1106                         state_dpaux_i2c: pinmux-i2c {
1107                                 groups = "dpaux-io";
1108                                 function = "i2c";
1109                         };
1110
1111                         state_dpaux_off: pinmux-off {
1112                                 groups = "dpaux-io";
1113                                 function = "off";
1114                         };
1115
1116                         i2c-bus {
1117                                 #address-cells = <1>;
1118                                 #size-cells = <0>;
1119                         };
1120                 };
1121
1122                 padctl@15880000 {
1123                         compatible = "nvidia,tegra186-dsi-padctl";
1124                         reg = <0x15880000 0x10000>;
1125                         resets = <&bpmp TEGRA186_RESET_DSI>;
1126                         reset-names = "dsi";
1127                         status = "disabled";
1128                 };
1129
1130                 dsic: dsi@15900000 {
1131                         compatible = "nvidia,tegra186-dsi";
1132                         reg = <0x15900000 0x10000>;
1133                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1134                         clocks = <&bpmp TEGRA186_CLK_DSIC>,
1135                                  <&bpmp TEGRA186_CLK_DSIC_LP>,
1136                                  <&bpmp TEGRA186_CLK_PLLD>;
1137                         clock-names = "dsi", "lp", "parent";
1138                         resets = <&bpmp TEGRA186_RESET_DSIC>;
1139                         reset-names = "dsi";
1140                         status = "disabled";
1141
1142                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1143                 };
1144
1145                 dsid: dsi@15940000 {
1146                         compatible = "nvidia,tegra186-dsi";
1147                         reg = <0x15940000 0x10000>;
1148                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1149                         clocks = <&bpmp TEGRA186_CLK_DSID>,
1150                                  <&bpmp TEGRA186_CLK_DSID_LP>,
1151                                  <&bpmp TEGRA186_CLK_PLLD>;
1152                         clock-names = "dsi", "lp", "parent";
1153                         resets = <&bpmp TEGRA186_RESET_DSID>;
1154                         reset-names = "dsi";
1155                         status = "disabled";
1156
1157                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1158                 };
1159         };
1160
1161         gpu@17000000 {
1162                 compatible = "nvidia,gp10b";
1163                 reg = <0x0 0x17000000 0x0 0x1000000>,
1164                       <0x0 0x18000000 0x0 0x1000000>;
1165                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
1166                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1167                 interrupt-names = "stall", "nonstall";
1168
1169                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1170                          <&bpmp TEGRA186_CLK_GPU>;
1171                 clock-names = "gpu", "pwr";
1172                 resets = <&bpmp TEGRA186_RESET_GPU>;
1173                 reset-names = "gpu";
1174                 status = "disabled";
1175
1176                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1177         };
1178
1179         sysram@30000000 {
1180                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1181                 reg = <0x0 0x30000000 0x0 0x50000>;
1182                 #address-cells = <2>;
1183                 #size-cells = <2>;
1184                 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
1185
1186                 cpu_bpmp_tx: shmem@4e000 {
1187                         compatible = "nvidia,tegra186-bpmp-shmem";
1188                         reg = <0x0 0x4e000 0x0 0x1000>;
1189                         label = "cpu-bpmp-tx";
1190                         pool;
1191                 };
1192
1193                 cpu_bpmp_rx: shmem@4f000 {
1194                         compatible = "nvidia,tegra186-bpmp-shmem";
1195                         reg = <0x0 0x4f000 0x0 0x1000>;
1196                         label = "cpu-bpmp-rx";
1197                         pool;
1198                 };
1199         };
1200
1201         bpmp: bpmp {
1202                 compatible = "nvidia,tegra186-bpmp";
1203                 iommus = <&smmu TEGRA186_SID_BPMP>;
1204                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1205                                     TEGRA_HSP_DB_MASTER_BPMP>;
1206                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1207                 #clock-cells = <1>;
1208                 #reset-cells = <1>;
1209                 #power-domain-cells = <1>;
1210
1211                 bpmp_i2c: i2c {
1212                         compatible = "nvidia,tegra186-bpmp-i2c";
1213                         nvidia,bpmp-bus-id = <5>;
1214                         #address-cells = <1>;
1215                         #size-cells = <0>;
1216                         status = "disabled";
1217                 };
1218
1219                 bpmp_thermal: thermal {
1220                         compatible = "nvidia,tegra186-bpmp-thermal";
1221                         #thermal-sensor-cells = <1>;
1222                 };
1223         };
1224
1225         cpus {
1226                 #address-cells = <1>;
1227                 #size-cells = <0>;
1228
1229                 cpu@0 {
1230                         compatible = "nvidia,tegra186-denver";
1231                         device_type = "cpu";
1232                         i-cache-size = <0x20000>;
1233                         i-cache-line-size = <64>;
1234                         i-cache-sets = <512>;
1235                         d-cache-size = <0x10000>;
1236                         d-cache-line-size = <64>;
1237                         d-cache-sets = <256>;
1238                         next-level-cache = <&L2_DENVER>;
1239                         reg = <0x000>;
1240                 };
1241
1242                 cpu@1 {
1243                         compatible = "nvidia,tegra186-denver";
1244                         device_type = "cpu";
1245                         i-cache-size = <0x20000>;
1246                         i-cache-line-size = <64>;
1247                         i-cache-sets = <512>;
1248                         d-cache-size = <0x10000>;
1249                         d-cache-line-size = <64>;
1250                         d-cache-sets = <256>;
1251                         next-level-cache = <&L2_DENVER>;
1252                         reg = <0x001>;
1253                 };
1254
1255                 cpu@2 {
1256                         compatible = "arm,cortex-a57";
1257                         device_type = "cpu";
1258                         i-cache-size = <0xC000>;
1259                         i-cache-line-size = <64>;
1260                         i-cache-sets = <256>;
1261                         d-cache-size = <0x8000>;
1262                         d-cache-line-size = <64>;
1263                         d-cache-sets = <256>;
1264                         next-level-cache = <&L2_A57>;
1265                         reg = <0x100>;
1266                 };
1267
1268                 cpu@3 {
1269                         compatible = "arm,cortex-a57";
1270                         device_type = "cpu";
1271                         i-cache-size = <0xC000>;
1272                         i-cache-line-size = <64>;
1273                         i-cache-sets = <256>;
1274                         d-cache-size = <0x8000>;
1275                         d-cache-line-size = <64>;
1276                         d-cache-sets = <256>;
1277                         next-level-cache = <&L2_A57>;
1278                         reg = <0x101>;
1279                 };
1280
1281                 cpu@4 {
1282                         compatible = "arm,cortex-a57";
1283                         device_type = "cpu";
1284                         i-cache-size = <0xC000>;
1285                         i-cache-line-size = <64>;
1286                         i-cache-sets = <256>;
1287                         d-cache-size = <0x8000>;
1288                         d-cache-line-size = <64>;
1289                         d-cache-sets = <256>;
1290                         next-level-cache = <&L2_A57>;
1291                         reg = <0x102>;
1292                 };
1293
1294                 cpu@5 {
1295                         compatible = "arm,cortex-a57";
1296                         device_type = "cpu";
1297                         i-cache-size = <0xC000>;
1298                         i-cache-line-size = <64>;
1299                         i-cache-sets = <256>;
1300                         d-cache-size = <0x8000>;
1301                         d-cache-line-size = <64>;
1302                         d-cache-sets = <256>;
1303                         next-level-cache = <&L2_A57>;
1304                         reg = <0x103>;
1305                 };
1306
1307                 L2_DENVER: l2-cache0 {
1308                         compatible = "cache";
1309                         cache-unified;
1310                         cache-level = <2>;
1311                         cache-size = <0x200000>;
1312                         cache-line-size = <64>;
1313                         cache-sets = <2048>;
1314                 };
1315
1316                 L2_A57: l2-cache1 {
1317                         compatible = "cache";
1318                         cache-unified;
1319                         cache-level = <2>;
1320                         cache-size = <0x200000>;
1321                         cache-line-size = <64>;
1322                         cache-sets = <2048>;
1323                 };
1324         };
1325
1326         thermal-zones {
1327                 a57 {
1328                         polling-delay = <0>;
1329                         polling-delay-passive = <1000>;
1330
1331                         thermal-sensors =
1332                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1333
1334                         trips {
1335                                 critical {
1336                                         temperature = <101000>;
1337                                         hysteresis = <0>;
1338                                         type = "critical";
1339                                 };
1340                         };
1341
1342                         cooling-maps {
1343                         };
1344                 };
1345
1346                 denver {
1347                         polling-delay = <0>;
1348                         polling-delay-passive = <1000>;
1349
1350                         thermal-sensors =
1351                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1352
1353                         trips {
1354                                 critical {
1355                                         temperature = <101000>;
1356                                         hysteresis = <0>;
1357                                         type = "critical";
1358                                 };
1359                         };
1360
1361                         cooling-maps {
1362                         };
1363                 };
1364
1365                 gpu {
1366                         polling-delay = <0>;
1367                         polling-delay-passive = <1000>;
1368
1369                         thermal-sensors =
1370                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1371
1372                         trips {
1373                                 critical {
1374                                         temperature = <101000>;
1375                                         hysteresis = <0>;
1376                                         type = "critical";
1377                                 };
1378                         };
1379
1380                         cooling-maps {
1381                         };
1382                 };
1383
1384                 pll {
1385                         polling-delay = <0>;
1386                         polling-delay-passive = <1000>;
1387
1388                         thermal-sensors =
1389                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1390
1391                         trips {
1392                                 critical {
1393                                         temperature = <101000>;
1394                                         hysteresis = <0>;
1395                                         type = "critical";
1396                                 };
1397                         };
1398
1399                         cooling-maps {
1400                         };
1401                 };
1402
1403                 always_on {
1404                         polling-delay = <0>;
1405                         polling-delay-passive = <1000>;
1406
1407                         thermal-sensors =
1408                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1409
1410                         trips {
1411                                 critical {
1412                                         temperature = <101000>;
1413                                         hysteresis = <0>;
1414                                         type = "critical";
1415                                 };
1416                         };
1417
1418                         cooling-maps {
1419                         };
1420                 };
1421         };
1422
1423         timer {
1424                 compatible = "arm,armv8-timer";
1425                 interrupts = <GIC_PPI 13
1426                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1427                              <GIC_PPI 14
1428                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1429                              <GIC_PPI 11
1430                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1431                              <GIC_PPI 10
1432                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1433                 interrupt-parent = <&gic>;
1434                 always-on;
1435         };
1436 };