?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: dma-api: fix max_pfn off-by-one error in __dma_supported()
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blob2d3be7f3ad67fc6b4a74cab84ec951bf38a74796
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "mmu.h"
22 #include "i8254.h"
23 #include "tss.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28 #include "hyperv.h"
29
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
33 #include <linux/fs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/export.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <linux/kvm_irqfd.h>
52 #include <linux/irqbypass.h>
53 #include <linux/sched/stat.h>
54 #include <linux/sched/isolation.h>
55 #include <linux/mem_encrypt.h>
56
57 #include <trace/events/kvm.h>
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68 #include <asm/mshyperv.h>
69 #include <asm/hypervisor.h>
70 #include <asm/intel_pt.h>
71 #include <asm/emulate_prefix.h>
72 #include <clocksource/hyperv_timer.h>
73
74 #define CREATE_TRACE_POINTS
75 #include "trace.h"
76
77 #define MAX_IO_MSRS 256
78 #define KVM_MAX_MCE_BANKS 32
79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81
82 #define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
85 /* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89 #ifdef CONFIG_X86_64
90 static
91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 #else
93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
94 #endif
95
96 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
97
98 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
99 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
100
101 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
102 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
103
104 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
105 static void process_nmi(struct kvm_vcpu *vcpu);
106 static void enter_smm(struct kvm_vcpu *vcpu);
107 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
108 static void store_regs(struct kvm_vcpu *vcpu);
109 static int sync_regs(struct kvm_vcpu *vcpu);
110
111 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
112 EXPORT_SYMBOL_GPL(kvm_x86_ops);
113
114 static bool __read_mostly ignore_msrs = 0;
115 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
116
117 static bool __read_mostly report_ignored_msrs = true;
118 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
119
120 unsigned int min_timer_period_us = 200;
121 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
122
123 static bool __read_mostly kvmclock_periodic_sync = true;
124 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
125
126 bool __read_mostly kvm_has_tsc_control;
127 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
128 u32 __read_mostly kvm_max_guest_tsc_khz;
129 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
130 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
131 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
132 u64 __read_mostly kvm_max_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
134 u64 __read_mostly kvm_default_tsc_scaling_ratio;
135 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
136
137 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
138 static u32 __read_mostly tsc_tolerance_ppm = 250;
139 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
140
141 /*
142 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
143 * adaptive tuning starting from default advancment of 1000ns. '0' disables
144 * advancement entirely. Any other value is used as-is and disables adaptive
145 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
146 */
147 static int __read_mostly lapic_timer_advance_ns = -1;
148 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
149
150 static bool __read_mostly vector_hashing = true;
151 module_param(vector_hashing, bool, S_IRUGO);
152
153 bool __read_mostly enable_vmware_backdoor = false;
154 module_param(enable_vmware_backdoor, bool, S_IRUGO);
155 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
156
157 static bool __read_mostly force_emulation_prefix = false;
158 module_param(force_emulation_prefix, bool, S_IRUGO);
159
160 int __read_mostly pi_inject_timer = -1;
161 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
162
163 #define KVM_NR_SHARED_MSRS 16
164
165 struct kvm_shared_msrs_global {
166 int nr;
167 u32 msrs[KVM_NR_SHARED_MSRS];
168 };
169
170 struct kvm_shared_msrs {
171 struct user_return_notifier urn;
172 bool registered;
173 struct kvm_shared_msr_values {
174 u64 host;
175 u64 curr;
176 } values[KVM_NR_SHARED_MSRS];
177 };
178
179 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
180 static struct kvm_shared_msrs __percpu *shared_msrs;
181
182 static u64 __read_mostly host_xss;
183
184 struct kvm_stats_debugfs_item debugfs_entries[] = {
185 { "pf_fixed", VCPU_STAT(pf_fixed) },
186 { "pf_guest", VCPU_STAT(pf_guest) },
187 { "tlb_flush", VCPU_STAT(tlb_flush) },
188 { "invlpg", VCPU_STAT(invlpg) },
189 { "exits", VCPU_STAT(exits) },
190 { "io_exits", VCPU_STAT(io_exits) },
191 { "mmio_exits", VCPU_STAT(mmio_exits) },
192 { "signal_exits", VCPU_STAT(signal_exits) },
193 { "irq_window", VCPU_STAT(irq_window_exits) },
194 { "nmi_window", VCPU_STAT(nmi_window_exits) },
195 { "halt_exits", VCPU_STAT(halt_exits) },
196 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
197 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
198 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
199 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
200 { "hypercalls", VCPU_STAT(hypercalls) },
201 { "request_irq", VCPU_STAT(request_irq_exits) },
202 { "irq_exits", VCPU_STAT(irq_exits) },
203 { "host_state_reload", VCPU_STAT(host_state_reload) },
204 { "fpu_reload", VCPU_STAT(fpu_reload) },
205 { "insn_emulation", VCPU_STAT(insn_emulation) },
206 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
207 { "irq_injections", VCPU_STAT(irq_injections) },
208 { "nmi_injections", VCPU_STAT(nmi_injections) },
209 { "req_event", VCPU_STAT(req_event) },
210 { "l1d_flush", VCPU_STAT(l1d_flush) },
211 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
212 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
213 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
214 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
215 { "mmu_flooded", VM_STAT(mmu_flooded) },
216 { "mmu_recycled", VM_STAT(mmu_recycled) },
217 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
218 { "mmu_unsync", VM_STAT(mmu_unsync) },
219 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
220 { "largepages", VM_STAT(lpages, .mode = 0444) },
221 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
222 { "max_mmu_page_hash_collisions",
223 VM_STAT(max_mmu_page_hash_collisions) },
224 { NULL }
225 };
226
227 u64 __read_mostly host_xcr0;
228
229 struct kmem_cache *x86_fpu_cache;
230 EXPORT_SYMBOL_GPL(x86_fpu_cache);
231
232 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
233
234 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
235 {
236 int i;
237 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
238 vcpu->arch.apf.gfns[i] = ~0;
239 }
240
241 static void kvm_on_user_return(struct user_return_notifier *urn)
242 {
243 unsigned slot;
244 struct kvm_shared_msrs *locals
245 = container_of(urn, struct kvm_shared_msrs, urn);
246 struct kvm_shared_msr_values *values;
247 unsigned long flags;
248
249 /*
250 * Disabling irqs at this point since the following code could be
251 * interrupted and executed through kvm_arch_hardware_disable()
252 */
253 local_irq_save(flags);
254 if (locals->registered) {
255 locals->registered = false;
256 user_return_notifier_unregister(urn);
257 }
258 local_irq_restore(flags);
259 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
260 values = &locals->values[slot];
261 if (values->host != values->curr) {
262 wrmsrl(shared_msrs_global.msrs[slot], values->host);
263 values->curr = values->host;
264 }
265 }
266 }
267
268 void kvm_define_shared_msr(unsigned slot, u32 msr)
269 {
270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
271 shared_msrs_global.msrs[slot] = msr;
272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
274 }
275 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277 static void kvm_shared_msr_cpu_online(void)
278 {
279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
281 u64 value;
282 int i;
283
284 for (i = 0; i < shared_msrs_global.nr; ++i) {
285 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
286 smsr->values[i].host = value;
287 smsr->values[i].curr = value;
288 }
289 }
290
291 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
292 {
293 unsigned int cpu = smp_processor_id();
294 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
295 int err;
296
297 value = (value & mask) | (smsr->values[slot].host & ~mask);
298 if (value == smsr->values[slot].curr)
299 return 0;
300 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
301 if (err)
302 return 1;
303
304 smsr->values[slot].curr = value;
305 if (!smsr->registered) {
306 smsr->urn.on_user_return = kvm_on_user_return;
307 user_return_notifier_register(&smsr->urn);
308 smsr->registered = true;
309 }
310 return 0;
311 }
312 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
313
314 static void drop_user_return_notifiers(void)
315 {
316 unsigned int cpu = smp_processor_id();
317 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
318
319 if (smsr->registered)
320 kvm_on_user_return(&smsr->urn);
321 }
322
323 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
324 {
325 return vcpu->arch.apic_base;
326 }
327 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
328
329 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
330 {
331 return kvm_apic_mode(kvm_get_apic_base(vcpu));
332 }
333 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
334
335 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
336 {
337 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
338 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
339 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
340 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
341
342 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
343 return 1;
344 if (!msr_info->host_initiated) {
345 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
346 return 1;
347 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
348 return 1;
349 }
350
351 kvm_lapic_set_base(vcpu, msr_info->data);
352 return 0;
353 }
354 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
355
356 asmlinkage __visible void kvm_spurious_fault(void)
357 {
358 /* Fault while not rebooting. We want the trace. */
359 BUG_ON(!kvm_rebooting);
360 }
361 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
362
363 #define EXCPT_BENIGN 0
364 #define EXCPT_CONTRIBUTORY 1
365 #define EXCPT_PF 2
366
367 static int exception_class(int vector)
368 {
369 switch (vector) {
370 case PF_VECTOR:
371 return EXCPT_PF;
372 case DE_VECTOR:
373 case TS_VECTOR:
374 case NP_VECTOR:
375 case SS_VECTOR:
376 case GP_VECTOR:
377 return EXCPT_CONTRIBUTORY;
378 default:
379 break;
380 }
381 return EXCPT_BENIGN;
382 }
383
384 #define EXCPT_FAULT 0
385 #define EXCPT_TRAP 1
386 #define EXCPT_ABORT 2
387 #define EXCPT_INTERRUPT 3
388
389 static int exception_type(int vector)
390 {
391 unsigned int mask;
392
393 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
394 return EXCPT_INTERRUPT;
395
396 mask = 1 << vector;
397
398 /* #DB is trap, as instruction watchpoints are handled elsewhere */
399 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
400 return EXCPT_TRAP;
401
402 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
403 return EXCPT_ABORT;
404
405 /* Reserved exceptions will result in fault */
406 return EXCPT_FAULT;
407 }
408
409 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
410 {
411 unsigned nr = vcpu->arch.exception.nr;
412 bool has_payload = vcpu->arch.exception.has_payload;
413 unsigned long payload = vcpu->arch.exception.payload;
414
415 if (!has_payload)
416 return;
417
418 switch (nr) {
419 case DB_VECTOR:
420 /*
421 * "Certain debug exceptions may clear bit 0-3. The
422 * remaining contents of the DR6 register are never
423 * cleared by the processor".
424 */
425 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
426 /*
427 * DR6.RTM is set by all #DB exceptions that don't clear it.
428 */
429 vcpu->arch.dr6 |= DR6_RTM;
430 vcpu->arch.dr6 |= payload;
431 /*
432 * Bit 16 should be set in the payload whenever the #DB
433 * exception should clear DR6.RTM. This makes the payload
434 * compatible with the pending debug exceptions under VMX.
435 * Though not currently documented in the SDM, this also
436 * makes the payload compatible with the exit qualification
437 * for #DB exceptions under VMX.
438 */
439 vcpu->arch.dr6 ^= payload & DR6_RTM;
440 break;
441 case PF_VECTOR:
442 vcpu->arch.cr2 = payload;
443 break;
444 }
445
446 vcpu->arch.exception.has_payload = false;
447 vcpu->arch.exception.payload = 0;
448 }
449 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
450
451 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
452 unsigned nr, bool has_error, u32 error_code,
453 bool has_payload, unsigned long payload, bool reinject)
454 {
455 u32 prev_nr;
456 int class1, class2;
457
458 kvm_make_request(KVM_REQ_EVENT, vcpu);
459
460 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
461 queue:
462 if (has_error && !is_protmode(vcpu))
463 has_error = false;
464 if (reinject) {
465 /*
466 * On vmentry, vcpu->arch.exception.pending is only
467 * true if an event injection was blocked by
468 * nested_run_pending. In that case, however,
469 * vcpu_enter_guest requests an immediate exit,
470 * and the guest shouldn't proceed far enough to
471 * need reinjection.
472 */
473 WARN_ON_ONCE(vcpu->arch.exception.pending);
474 vcpu->arch.exception.injected = true;
475 if (WARN_ON_ONCE(has_payload)) {
476 /*
477 * A reinjected event has already
478 * delivered its payload.
479 */
480 has_payload = false;
481 payload = 0;
482 }
483 } else {
484 vcpu->arch.exception.pending = true;
485 vcpu->arch.exception.injected = false;
486 }
487 vcpu->arch.exception.has_error_code = has_error;
488 vcpu->arch.exception.nr = nr;
489 vcpu->arch.exception.error_code = error_code;
490 vcpu->arch.exception.has_payload = has_payload;
491 vcpu->arch.exception.payload = payload;
492 /*
493 * In guest mode, payload delivery should be deferred,
494 * so that the L1 hypervisor can intercept #PF before
495 * CR2 is modified (or intercept #DB before DR6 is
496 * modified under nVMX). However, for ABI
497 * compatibility with KVM_GET_VCPU_EVENTS and
498 * KVM_SET_VCPU_EVENTS, we can't delay payload
499 * delivery unless userspace has enabled this
500 * functionality via the per-VM capability,
501 * KVM_CAP_EXCEPTION_PAYLOAD.
502 */
503 if (!vcpu->kvm->arch.exception_payload_enabled ||
504 !is_guest_mode(vcpu))
505 kvm_deliver_exception_payload(vcpu);
506 return;
507 }
508
509 /* to check exception */
510 prev_nr = vcpu->arch.exception.nr;
511 if (prev_nr == DF_VECTOR) {
512 /* triple fault -> shutdown */
513 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
514 return;
515 }
516 class1 = exception_class(prev_nr);
517 class2 = exception_class(nr);
518 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
519 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
520 /*
521 * Generate double fault per SDM Table 5-5. Set
522 * exception.pending = true so that the double fault
523 * can trigger a nested vmexit.
524 */
525 vcpu->arch.exception.pending = true;
526 vcpu->arch.exception.injected = false;
527 vcpu->arch.exception.has_error_code = true;
528 vcpu->arch.exception.nr = DF_VECTOR;
529 vcpu->arch.exception.error_code = 0;
530 vcpu->arch.exception.has_payload = false;
531 vcpu->arch.exception.payload = 0;
532 } else
533 /* replace previous exception with a new one in a hope
534 that instruction re-execution will regenerate lost
535 exception */
536 goto queue;
537 }
538
539 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
540 {
541 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
542 }
543 EXPORT_SYMBOL_GPL(kvm_queue_exception);
544
545 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
546 {
547 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
548 }
549 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
550
551 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
552 unsigned long payload)
553 {
554 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
555 }
556
557 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
558 u32 error_code, unsigned long payload)
559 {
560 kvm_multiple_exception(vcpu, nr, true, error_code,
561 true, payload, false);
562 }
563
564 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
565 {
566 if (err)
567 kvm_inject_gp(vcpu, 0);
568 else
569 return kvm_skip_emulated_instruction(vcpu);
570
571 return 1;
572 }
573 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
574
575 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
576 {
577 ++vcpu->stat.pf_guest;
578 vcpu->arch.exception.nested_apf =
579 is_guest_mode(vcpu) && fault->async_page_fault;
580 if (vcpu->arch.exception.nested_apf) {
581 vcpu->arch.apf.nested_apf_token = fault->address;
582 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
583 } else {
584 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
585 fault->address);
586 }
587 }
588 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
589
590 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
591 {
592 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
593 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
594 else
595 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
596
597 return fault->nested_page_fault;
598 }
599
600 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
601 {
602 atomic_inc(&vcpu->arch.nmi_queued);
603 kvm_make_request(KVM_REQ_NMI, vcpu);
604 }
605 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
606
607 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
608 {
609 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
610 }
611 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
612
613 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
614 {
615 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
616 }
617 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
618
619 /*
620 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
621 * a #GP and return false.
622 */
623 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
624 {
625 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
626 return true;
627 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
628 return false;
629 }
630 EXPORT_SYMBOL_GPL(kvm_require_cpl);
631
632 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
633 {
634 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
635 return true;
636
637 kvm_queue_exception(vcpu, UD_VECTOR);
638 return false;
639 }
640 EXPORT_SYMBOL_GPL(kvm_require_dr);
641
642 /*
643 * This function will be used to read from the physical memory of the currently
644 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
645 * can read from guest physical or from the guest's guest physical memory.
646 */
647 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
648 gfn_t ngfn, void *data, int offset, int len,
649 u32 access)
650 {
651 struct x86_exception exception;
652 gfn_t real_gfn;
653 gpa_t ngpa;
654
655 ngpa = gfn_to_gpa(ngfn);
656 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
657 if (real_gfn == UNMAPPED_GVA)
658 return -EFAULT;
659
660 real_gfn = gpa_to_gfn(real_gfn);
661
662 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
663 }
664 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
665
666 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
667 void *data, int offset, int len, u32 access)
668 {
669 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
670 data, offset, len, access);
671 }
672
673 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
674 {
675 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
676 rsvd_bits(1, 2);
677 }
678
679 /*
680 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
681 */
682 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
683 {
684 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
685 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
686 int i;
687 int ret;
688 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
689
690 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
691 offset * sizeof(u64), sizeof(pdpte),
692 PFERR_USER_MASK|PFERR_WRITE_MASK);
693 if (ret < 0) {
694 ret = 0;
695 goto out;
696 }
697 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
698 if ((pdpte[i] & PT_PRESENT_MASK) &&
699 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
700 ret = 0;
701 goto out;
702 }
703 }
704 ret = 1;
705
706 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
707 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
708
709 out:
710
711 return ret;
712 }
713 EXPORT_SYMBOL_GPL(load_pdptrs);
714
715 bool pdptrs_changed(struct kvm_vcpu *vcpu)
716 {
717 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
718 int offset;
719 gfn_t gfn;
720 int r;
721
722 if (!is_pae_paging(vcpu))
723 return false;
724
725 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
726 return true;
727
728 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
729 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
730 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
731 PFERR_USER_MASK | PFERR_WRITE_MASK);
732 if (r < 0)
733 return true;
734
735 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
736 }
737 EXPORT_SYMBOL_GPL(pdptrs_changed);
738
739 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
740 {
741 unsigned long old_cr0 = kvm_read_cr0(vcpu);
742 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
743
744 cr0 |= X86_CR0_ET;
745
746 #ifdef CONFIG_X86_64
747 if (cr0 & 0xffffffff00000000UL)
748 return 1;
749 #endif
750
751 cr0 &= ~CR0_RESERVED_BITS;
752
753 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
754 return 1;
755
756 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
757 return 1;
758
759 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
760 #ifdef CONFIG_X86_64
761 if ((vcpu->arch.efer & EFER_LME)) {
762 int cs_db, cs_l;
763
764 if (!is_pae(vcpu))
765 return 1;
766 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
767 if (cs_l)
768 return 1;
769 } else
770 #endif
771 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
772 kvm_read_cr3(vcpu)))
773 return 1;
774 }
775
776 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
777 return 1;
778
779 kvm_x86_ops->set_cr0(vcpu, cr0);
780
781 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
782 kvm_clear_async_pf_completion_queue(vcpu);
783 kvm_async_pf_hash_reset(vcpu);
784 }
785
786 if ((cr0 ^ old_cr0) & update_bits)
787 kvm_mmu_reset_context(vcpu);
788
789 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
790 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
791 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
792 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
793
794 return 0;
795 }
796 EXPORT_SYMBOL_GPL(kvm_set_cr0);
797
798 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
799 {
800 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
801 }
802 EXPORT_SYMBOL_GPL(kvm_lmsw);
803
804 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
805 {
806 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
807
808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810
811 if (vcpu->arch.xsaves_enabled &&
812 vcpu->arch.ia32_xss != host_xss)
813 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
814 }
815 }
816 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
817
818 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
819 {
820 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
821
822 if (vcpu->arch.xcr0 != host_xcr0)
823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
824
825 if (vcpu->arch.xsaves_enabled &&
826 vcpu->arch.ia32_xss != host_xss)
827 wrmsrl(MSR_IA32_XSS, host_xss);
828 }
829
830 }
831 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
832
833 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
834 {
835 u64 xcr0 = xcr;
836 u64 old_xcr0 = vcpu->arch.xcr0;
837 u64 valid_bits;
838
839 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
840 if (index != XCR_XFEATURE_ENABLED_MASK)
841 return 1;
842 if (!(xcr0 & XFEATURE_MASK_FP))
843 return 1;
844 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
845 return 1;
846
847 /*
848 * Do not allow the guest to set bits that we do not support
849 * saving. However, xcr0 bit 0 is always set, even if the
850 * emulated CPU does not support XSAVE (see fx_init).
851 */
852 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
853 if (xcr0 & ~valid_bits)
854 return 1;
855
856 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
857 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
858 return 1;
859
860 if (xcr0 & XFEATURE_MASK_AVX512) {
861 if (!(xcr0 & XFEATURE_MASK_YMM))
862 return 1;
863 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
864 return 1;
865 }
866 vcpu->arch.xcr0 = xcr0;
867
868 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
869 kvm_update_cpuid(vcpu);
870 return 0;
871 }
872
873 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
874 {
875 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
876 __kvm_set_xcr(vcpu, index, xcr)) {
877 kvm_inject_gp(vcpu, 0);
878 return 1;
879 }
880 return 0;
881 }
882 EXPORT_SYMBOL_GPL(kvm_set_xcr);
883
884 #define __cr4_reserved_bits(__cpu_has, __c) \
885 ({ \
886 u64 __reserved_bits = CR4_RESERVED_BITS; \
887 \
888 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
889 __reserved_bits |= X86_CR4_OSXSAVE; \
890 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
891 __reserved_bits |= X86_CR4_SMEP; \
892 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
893 __reserved_bits |= X86_CR4_SMAP; \
894 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
895 __reserved_bits |= X86_CR4_FSGSBASE; \
896 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
897 __reserved_bits |= X86_CR4_PKE; \
898 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
899 __reserved_bits |= X86_CR4_LA57; \
900 __reserved_bits; \
901 })
902
903 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
904 {
905 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
906
907 if (cpuid_ecx(0x7) & feature_bit(LA57))
908 reserved_bits &= ~X86_CR4_LA57;
909
910 if (kvm_x86_ops->umip_emulated())
911 reserved_bits &= ~X86_CR4_UMIP;
912
913 return reserved_bits;
914 }
915
916 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
917 {
918 if (cr4 & cr4_reserved_bits)
919 return -EINVAL;
920
921 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
922 return -EINVAL;
923
924 return 0;
925 }
926
927 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
928 {
929 unsigned long old_cr4 = kvm_read_cr4(vcpu);
930 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
931 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
932
933 if (kvm_valid_cr4(vcpu, cr4))
934 return 1;
935
936 if (is_long_mode(vcpu)) {
937 if (!(cr4 & X86_CR4_PAE))
938 return 1;
939 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
940 && ((cr4 ^ old_cr4) & pdptr_bits)
941 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
942 kvm_read_cr3(vcpu)))
943 return 1;
944
945 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
946 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
947 return 1;
948
949 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
950 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
951 return 1;
952 }
953
954 if (kvm_x86_ops->set_cr4(vcpu, cr4))
955 return 1;
956
957 if (((cr4 ^ old_cr4) & pdptr_bits) ||
958 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
959 kvm_mmu_reset_context(vcpu);
960
961 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
962 kvm_update_cpuid(vcpu);
963
964 return 0;
965 }
966 EXPORT_SYMBOL_GPL(kvm_set_cr4);
967
968 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
969 {
970 bool skip_tlb_flush = false;
971 #ifdef CONFIG_X86_64
972 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
973
974 if (pcid_enabled) {
975 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
976 cr3 &= ~X86_CR3_PCID_NOFLUSH;
977 }
978 #endif
979
980 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
981 if (!skip_tlb_flush) {
982 kvm_mmu_sync_roots(vcpu);
983 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
984 }
985 return 0;
986 }
987
988 if (is_long_mode(vcpu) &&
989 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
990 return 1;
991 else if (is_pae_paging(vcpu) &&
992 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
993 return 1;
994
995 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
996 vcpu->arch.cr3 = cr3;
997 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
998
999 return 0;
1000 }
1001 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1002
1003 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1004 {
1005 if (cr8 & CR8_RESERVED_BITS)
1006 return 1;
1007 if (lapic_in_kernel(vcpu))
1008 kvm_lapic_set_tpr(vcpu, cr8);
1009 else
1010 vcpu->arch.cr8 = cr8;
1011 return 0;
1012 }
1013 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1014
1015 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1016 {
1017 if (lapic_in_kernel(vcpu))
1018 return kvm_lapic_get_cr8(vcpu);
1019 else
1020 return vcpu->arch.cr8;
1021 }
1022 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1023
1024 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1025 {
1026 int i;
1027
1028 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1029 for (i = 0; i < KVM_NR_DB_REGS; i++)
1030 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1031 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1032 }
1033 }
1034
1035 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1036 {
1037 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1039 }
1040
1041 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1042 {
1043 unsigned long dr7;
1044
1045 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1046 dr7 = vcpu->arch.guest_debug_dr7;
1047 else
1048 dr7 = vcpu->arch.dr7;
1049 kvm_x86_ops->set_dr7(vcpu, dr7);
1050 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1051 if (dr7 & DR7_BP_EN_MASK)
1052 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1053 }
1054
1055 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1056 {
1057 u64 fixed = DR6_FIXED_1;
1058
1059 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1060 fixed |= DR6_RTM;
1061 return fixed;
1062 }
1063
1064 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1065 {
1066 size_t size = ARRAY_SIZE(vcpu->arch.db);
1067
1068 switch (dr) {
1069 case 0 ... 3:
1070 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1071 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1072 vcpu->arch.eff_db[dr] = val;
1073 break;
1074 case 4:
1075 /* fall through */
1076 case 6:
1077 if (val & 0xffffffff00000000ULL)
1078 return -1; /* #GP */
1079 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1080 kvm_update_dr6(vcpu);
1081 break;
1082 case 5:
1083 /* fall through */
1084 default: /* 7 */
1085 if (!kvm_dr7_valid(val))
1086 return -1; /* #GP */
1087 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1088 kvm_update_dr7(vcpu);
1089 break;
1090 }
1091
1092 return 0;
1093 }
1094
1095 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1096 {
1097 if (__kvm_set_dr(vcpu, dr, val)) {
1098 kvm_inject_gp(vcpu, 0);
1099 return 1;
1100 }
1101 return 0;
1102 }
1103 EXPORT_SYMBOL_GPL(kvm_set_dr);
1104
1105 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1106 {
1107 size_t size = ARRAY_SIZE(vcpu->arch.db);
1108
1109 switch (dr) {
1110 case 0 ... 3:
1111 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1112 break;
1113 case 4:
1114 /* fall through */
1115 case 6:
1116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117 *val = vcpu->arch.dr6;
1118 else
1119 *val = kvm_x86_ops->get_dr6(vcpu);
1120 break;
1121 case 5:
1122 /* fall through */
1123 default: /* 7 */
1124 *val = vcpu->arch.dr7;
1125 break;
1126 }
1127 return 0;
1128 }
1129 EXPORT_SYMBOL_GPL(kvm_get_dr);
1130
1131 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1132 {
1133 u32 ecx = kvm_rcx_read(vcpu);
1134 u64 data;
1135 int err;
1136
1137 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1138 if (err)
1139 return err;
1140 kvm_rax_write(vcpu, (u32)data);
1141 kvm_rdx_write(vcpu, data >> 32);
1142 return err;
1143 }
1144 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1145
1146 /*
1147 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1148 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1149 *
1150 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1151 * extract the supported MSRs from the related const lists.
1152 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1153 * capabilities of the host cpu. This capabilities test skips MSRs that are
1154 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1155 * may depend on host virtualization features rather than host cpu features.
1156 */
1157
1158 static const u32 msrs_to_save_all[] = {
1159 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1160 MSR_STAR,
1161 #ifdef CONFIG_X86_64
1162 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1163 #endif
1164 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1165 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1166 MSR_IA32_SPEC_CTRL,
1167 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1168 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1169 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1170 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1171 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1172 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1173 MSR_IA32_UMWAIT_CONTROL,
1174
1175 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1176 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1177 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1178 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1179 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1180 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1181 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1182 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1183 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1184 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1185 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1186 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1187 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1188 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1195 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1196 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1197 };
1198
1199 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1200 static unsigned num_msrs_to_save;
1201
1202 static const u32 emulated_msrs_all[] = {
1203 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1204 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1205 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1206 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1207 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1208 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1209 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1210 HV_X64_MSR_RESET,
1211 HV_X64_MSR_VP_INDEX,
1212 HV_X64_MSR_VP_RUNTIME,
1213 HV_X64_MSR_SCONTROL,
1214 HV_X64_MSR_STIMER0_CONFIG,
1215 HV_X64_MSR_VP_ASSIST_PAGE,
1216 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1217 HV_X64_MSR_TSC_EMULATION_STATUS,
1218
1219 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1220 MSR_KVM_PV_EOI_EN,
1221
1222 MSR_IA32_TSC_ADJUST,
1223 MSR_IA32_TSCDEADLINE,
1224 MSR_IA32_ARCH_CAPABILITIES,
1225 MSR_IA32_MISC_ENABLE,
1226 MSR_IA32_MCG_STATUS,
1227 MSR_IA32_MCG_CTL,
1228 MSR_IA32_MCG_EXT_CTL,
1229 MSR_IA32_SMBASE,
1230 MSR_SMI_COUNT,
1231 MSR_PLATFORM_INFO,
1232 MSR_MISC_FEATURES_ENABLES,
1233 MSR_AMD64_VIRT_SPEC_CTRL,
1234 MSR_IA32_POWER_CTL,
1235 MSR_IA32_UCODE_REV,
1236
1237 /*
1238 * The following list leaves out MSRs whose values are determined
1239 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1240 * We always support the "true" VMX control MSRs, even if the host
1241 * processor does not, so I am putting these registers here rather
1242 * than in msrs_to_save_all.
1243 */
1244 MSR_IA32_VMX_BASIC,
1245 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1246 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1247 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1248 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1249 MSR_IA32_VMX_MISC,
1250 MSR_IA32_VMX_CR0_FIXED0,
1251 MSR_IA32_VMX_CR4_FIXED0,
1252 MSR_IA32_VMX_VMCS_ENUM,
1253 MSR_IA32_VMX_PROCBASED_CTLS2,
1254 MSR_IA32_VMX_EPT_VPID_CAP,
1255 MSR_IA32_VMX_VMFUNC,
1256
1257 MSR_K7_HWCR,
1258 MSR_KVM_POLL_CONTROL,
1259 };
1260
1261 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1262 static unsigned num_emulated_msrs;
1263
1264 /*
1265 * List of msr numbers which are used to expose MSR-based features that
1266 * can be used by a hypervisor to validate requested CPU features.
1267 */
1268 static const u32 msr_based_features_all[] = {
1269 MSR_IA32_VMX_BASIC,
1270 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1271 MSR_IA32_VMX_PINBASED_CTLS,
1272 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1273 MSR_IA32_VMX_PROCBASED_CTLS,
1274 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1275 MSR_IA32_VMX_EXIT_CTLS,
1276 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1277 MSR_IA32_VMX_ENTRY_CTLS,
1278 MSR_IA32_VMX_MISC,
1279 MSR_IA32_VMX_CR0_FIXED0,
1280 MSR_IA32_VMX_CR0_FIXED1,
1281 MSR_IA32_VMX_CR4_FIXED0,
1282 MSR_IA32_VMX_CR4_FIXED1,
1283 MSR_IA32_VMX_VMCS_ENUM,
1284 MSR_IA32_VMX_PROCBASED_CTLS2,
1285 MSR_IA32_VMX_EPT_VPID_CAP,
1286 MSR_IA32_VMX_VMFUNC,
1287
1288 MSR_F10H_DECFG,
1289 MSR_IA32_UCODE_REV,
1290 MSR_IA32_ARCH_CAPABILITIES,
1291 };
1292
1293 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1294 static unsigned int num_msr_based_features;
1295
1296 static u64 kvm_get_arch_capabilities(void)
1297 {
1298 u64 data = 0;
1299
1300 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1301 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1302
1303 /*
1304 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1305 * the nested hypervisor runs with NX huge pages. If it is not,
1306 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1307 * L1 guests, so it need not worry about its own (L2) guests.
1308 */
1309 data |= ARCH_CAP_PSCHANGE_MC_NO;
1310
1311 /*
1312 * If we're doing cache flushes (either "always" or "cond")
1313 * we will do one whenever the guest does a vmlaunch/vmresume.
1314 * If an outer hypervisor is doing the cache flush for us
1315 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1316 * capability to the guest too, and if EPT is disabled we're not
1317 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1318 * require a nested hypervisor to do a flush of its own.
1319 */
1320 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1321 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1322
1323 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1324 data |= ARCH_CAP_RDCL_NO;
1325 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1326 data |= ARCH_CAP_SSB_NO;
1327 if (!boot_cpu_has_bug(X86_BUG_MDS))
1328 data |= ARCH_CAP_MDS_NO;
1329
1330 /*
1331 * On TAA affected systems:
1332 * - nothing to do if TSX is disabled on the host.
1333 * - we emulate TSX_CTRL if present on the host.
1334 * This lets the guest use VERW to clear CPU buffers.
1335 */
1336 if (!boot_cpu_has(X86_FEATURE_RTM))
1337 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1338 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1339 data |= ARCH_CAP_TAA_NO;
1340
1341 return data;
1342 }
1343
1344 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1345 {
1346 switch (msr->index) {
1347 case MSR_IA32_ARCH_CAPABILITIES:
1348 msr->data = kvm_get_arch_capabilities();
1349 break;
1350 case MSR_IA32_UCODE_REV:
1351 rdmsrl_safe(msr->index, &msr->data);
1352 break;
1353 default:
1354 if (kvm_x86_ops->get_msr_feature(msr))
1355 return 1;
1356 }
1357 return 0;
1358 }
1359
1360 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1361 {
1362 struct kvm_msr_entry msr;
1363 int r;
1364
1365 msr.index = index;
1366 r = kvm_get_msr_feature(&msr);
1367 if (r)
1368 return r;
1369
1370 *data = msr.data;
1371
1372 return 0;
1373 }
1374
1375 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1376 {
1377 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1378 return false;
1379
1380 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1381 return false;
1382
1383 if (efer & (EFER_LME | EFER_LMA) &&
1384 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1385 return false;
1386
1387 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1388 return false;
1389
1390 return true;
1391
1392 }
1393 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1394 {
1395 if (efer & efer_reserved_bits)
1396 return false;
1397
1398 return __kvm_valid_efer(vcpu, efer);
1399 }
1400 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1401
1402 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1403 {
1404 u64 old_efer = vcpu->arch.efer;
1405 u64 efer = msr_info->data;
1406
1407 if (efer & efer_reserved_bits)
1408 return 1;
1409
1410 if (!msr_info->host_initiated) {
1411 if (!__kvm_valid_efer(vcpu, efer))
1412 return 1;
1413
1414 if (is_paging(vcpu) &&
1415 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1416 return 1;
1417 }
1418
1419 efer &= ~EFER_LMA;
1420 efer |= vcpu->arch.efer & EFER_LMA;
1421
1422 kvm_x86_ops->set_efer(vcpu, efer);
1423
1424 /* Update reserved bits */
1425 if ((efer ^ old_efer) & EFER_NX)
1426 kvm_mmu_reset_context(vcpu);
1427
1428 return 0;
1429 }
1430
1431 void kvm_enable_efer_bits(u64 mask)
1432 {
1433 efer_reserved_bits &= ~mask;
1434 }
1435 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1436
1437 /*
1438 * Write @data into the MSR specified by @index. Select MSR specific fault
1439 * checks are bypassed if @host_initiated is %true.
1440 * Returns 0 on success, non-0 otherwise.
1441 * Assumes vcpu_load() was already called.
1442 */
1443 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1444 bool host_initiated)
1445 {
1446 struct msr_data msr;
1447
1448 switch (index) {
1449 case MSR_FS_BASE:
1450 case MSR_GS_BASE:
1451 case MSR_KERNEL_GS_BASE:
1452 case MSR_CSTAR:
1453 case MSR_LSTAR:
1454 if (is_noncanonical_address(data, vcpu))
1455 return 1;
1456 break;
1457 case MSR_IA32_SYSENTER_EIP:
1458 case MSR_IA32_SYSENTER_ESP:
1459 /*
1460 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1461 * non-canonical address is written on Intel but not on
1462 * AMD (which ignores the top 32-bits, because it does
1463 * not implement 64-bit SYSENTER).
1464 *
1465 * 64-bit code should hence be able to write a non-canonical
1466 * value on AMD. Making the address canonical ensures that
1467 * vmentry does not fail on Intel after writing a non-canonical
1468 * value, and that something deterministic happens if the guest
1469 * invokes 64-bit SYSENTER.
1470 */
1471 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1472 }
1473
1474 msr.data = data;
1475 msr.index = index;
1476 msr.host_initiated = host_initiated;
1477
1478 return kvm_x86_ops->set_msr(vcpu, &msr);
1479 }
1480
1481 /*
1482 * Read the MSR specified by @index into @data. Select MSR specific fault
1483 * checks are bypassed if @host_initiated is %true.
1484 * Returns 0 on success, non-0 otherwise.
1485 * Assumes vcpu_load() was already called.
1486 */
1487 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1488 bool host_initiated)
1489 {
1490 struct msr_data msr;
1491 int ret;
1492
1493 msr.index = index;
1494 msr.host_initiated = host_initiated;
1495
1496 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1497 if (!ret)
1498 *data = msr.data;
1499 return ret;
1500 }
1501
1502 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1503 {
1504 return __kvm_get_msr(vcpu, index, data, false);
1505 }
1506 EXPORT_SYMBOL_GPL(kvm_get_msr);
1507
1508 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1509 {
1510 return __kvm_set_msr(vcpu, index, data, false);
1511 }
1512 EXPORT_SYMBOL_GPL(kvm_set_msr);
1513
1514 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1515 {
1516 u32 ecx = kvm_rcx_read(vcpu);
1517 u64 data;
1518
1519 if (kvm_get_msr(vcpu, ecx, &data)) {
1520 trace_kvm_msr_read_ex(ecx);
1521 kvm_inject_gp(vcpu, 0);
1522 return 1;
1523 }
1524
1525 trace_kvm_msr_read(ecx, data);
1526
1527 kvm_rax_write(vcpu, data & -1u);
1528 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1529 return kvm_skip_emulated_instruction(vcpu);
1530 }
1531 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1532
1533 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1534 {
1535 u32 ecx = kvm_rcx_read(vcpu);
1536 u64 data = kvm_read_edx_eax(vcpu);
1537
1538 if (kvm_set_msr(vcpu, ecx, data)) {
1539 trace_kvm_msr_write_ex(ecx, data);
1540 kvm_inject_gp(vcpu, 0);
1541 return 1;
1542 }
1543
1544 trace_kvm_msr_write(ecx, data);
1545 return kvm_skip_emulated_instruction(vcpu);
1546 }
1547 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1548
1549 /*
1550 * The fast path for frequent and performance sensitive wrmsr emulation,
1551 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1552 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1553 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1554 * other cases which must be called after interrupts are enabled on the host.
1555 */
1556 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1557 {
1558 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1559 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1560 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1561
1562 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1563 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1564 }
1565
1566 return 1;
1567 }
1568
1569 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1570 {
1571 u32 msr = kvm_rcx_read(vcpu);
1572 u64 data = kvm_read_edx_eax(vcpu);
1573 int ret = 0;
1574
1575 switch (msr) {
1576 case APIC_BASE_MSR + (APIC_ICR >> 4):
1577 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1578 break;
1579 default:
1580 return EXIT_FASTPATH_NONE;
1581 }
1582
1583 if (!ret) {
1584 trace_kvm_msr_write(msr, data);
1585 return EXIT_FASTPATH_SKIP_EMUL_INS;
1586 }
1587
1588 return EXIT_FASTPATH_NONE;
1589 }
1590 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1591
1592 /*
1593 * Adapt set_msr() to msr_io()'s calling convention
1594 */
1595 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1596 {
1597 return __kvm_get_msr(vcpu, index, data, true);
1598 }
1599
1600 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1601 {
1602 return __kvm_set_msr(vcpu, index, *data, true);
1603 }
1604
1605 #ifdef CONFIG_X86_64
1606 struct pvclock_clock {
1607 int vclock_mode;
1608 u64 cycle_last;
1609 u64 mask;
1610 u32 mult;
1611 u32 shift;
1612 };
1613
1614 struct pvclock_gtod_data {
1615 seqcount_t seq;
1616
1617 struct pvclock_clock clock; /* extract of a clocksource struct */
1618 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1619
1620 u64 boot_ns_raw;
1621 u64 boot_ns;
1622 u64 nsec_base;
1623 u64 wall_time_sec;
1624 u64 monotonic_raw_nsec;
1625 };
1626
1627 static struct pvclock_gtod_data pvclock_gtod_data;
1628
1629 static void update_pvclock_gtod(struct timekeeper *tk)
1630 {
1631 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1632 u64 boot_ns, boot_ns_raw;
1633
1634 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1635 boot_ns_raw = ktime_to_ns(ktime_add(tk->tkr_raw.base, tk->offs_boot));
1636
1637 write_seqcount_begin(&vdata->seq);
1638
1639 /* copy pvclock gtod data */
1640 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1641 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1642 vdata->clock.mask = tk->tkr_mono.mask;
1643 vdata->clock.mult = tk->tkr_mono.mult;
1644 vdata->clock.shift = tk->tkr_mono.shift;
1645
1646 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1647 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1648 vdata->raw_clock.mask = tk->tkr_raw.mask;
1649 vdata->raw_clock.mult = tk->tkr_raw.mult;
1650 vdata->raw_clock.shift = tk->tkr_raw.shift;
1651
1652 vdata->boot_ns = boot_ns;
1653 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1654
1655 vdata->wall_time_sec = tk->xtime_sec;
1656
1657 vdata->boot_ns_raw = boot_ns_raw;
1658 vdata->monotonic_raw_nsec = tk->tkr_raw.xtime_nsec;
1659
1660 write_seqcount_end(&vdata->seq);
1661 }
1662 #endif
1663
1664 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1665 {
1666 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1667 kvm_vcpu_kick(vcpu);
1668 }
1669
1670 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1671 {
1672 int version;
1673 int r;
1674 struct pvclock_wall_clock wc;
1675 struct timespec64 boot;
1676
1677 if (!wall_clock)
1678 return;
1679
1680 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1681 if (r)
1682 return;
1683
1684 if (version & 1)
1685 ++version; /* first time write, random junk */
1686
1687 ++version;
1688
1689 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1690 return;
1691
1692 /*
1693 * The guest calculates current wall clock time by adding
1694 * system time (updated by kvm_guest_time_update below) to the
1695 * wall clock specified here. guest system time equals host
1696 * system time for us, thus we must fill in host boot time here.
1697 */
1698 getboottime64(&boot);
1699
1700 if (kvm->arch.kvmclock_offset) {
1701 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1702 boot = timespec64_sub(boot, ts);
1703 }
1704 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1705 wc.nsec = boot.tv_nsec;
1706 wc.version = version;
1707
1708 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1709
1710 version++;
1711 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1712 }
1713
1714 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1715 {
1716 do_shl32_div32(dividend, divisor);
1717 return dividend;
1718 }
1719
1720 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1721 s8 *pshift, u32 *pmultiplier)
1722 {
1723 uint64_t scaled64;
1724 int32_t shift = 0;
1725 uint64_t tps64;
1726 uint32_t tps32;
1727
1728 tps64 = base_hz;
1729 scaled64 = scaled_hz;
1730 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1731 tps64 >>= 1;
1732 shift--;
1733 }
1734
1735 tps32 = (uint32_t)tps64;
1736 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1737 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1738 scaled64 >>= 1;
1739 else
1740 tps32 <<= 1;
1741 shift++;
1742 }
1743
1744 *pshift = shift;
1745 *pmultiplier = div_frac(scaled64, tps32);
1746 }
1747
1748 #ifdef CONFIG_X86_64
1749 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1750 #endif
1751
1752 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1753 static unsigned long max_tsc_khz;
1754
1755 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1756 {
1757 u64 v = (u64)khz * (1000000 + ppm);
1758 do_div(v, 1000000);
1759 return v;
1760 }
1761
1762 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1763 {
1764 u64 ratio;
1765
1766 /* Guest TSC same frequency as host TSC? */
1767 if (!scale) {
1768 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1769 return 0;
1770 }
1771
1772 /* TSC scaling supported? */
1773 if (!kvm_has_tsc_control) {
1774 if (user_tsc_khz > tsc_khz) {
1775 vcpu->arch.tsc_catchup = 1;
1776 vcpu->arch.tsc_always_catchup = 1;
1777 return 0;
1778 } else {
1779 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1780 return -1;
1781 }
1782 }
1783
1784 /* TSC scaling required - calculate ratio */
1785 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1786 user_tsc_khz, tsc_khz);
1787
1788 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1789 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1790 user_tsc_khz);
1791 return -1;
1792 }
1793
1794 vcpu->arch.tsc_scaling_ratio = ratio;
1795 return 0;
1796 }
1797
1798 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1799 {
1800 u32 thresh_lo, thresh_hi;
1801 int use_scaling = 0;
1802
1803 /* tsc_khz can be zero if TSC calibration fails */
1804 if (user_tsc_khz == 0) {
1805 /* set tsc_scaling_ratio to a safe value */
1806 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1807 return -1;
1808 }
1809
1810 /* Compute a scale to convert nanoseconds in TSC cycles */
1811 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1812 &vcpu->arch.virtual_tsc_shift,
1813 &vcpu->arch.virtual_tsc_mult);
1814 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1815
1816 /*
1817 * Compute the variation in TSC rate which is acceptable
1818 * within the range of tolerance and decide if the
1819 * rate being applied is within that bounds of the hardware
1820 * rate. If so, no scaling or compensation need be done.
1821 */
1822 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1823 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1824 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1825 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1826 use_scaling = 1;
1827 }
1828 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1829 }
1830
1831 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1832 {
1833 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1834 vcpu->arch.virtual_tsc_mult,
1835 vcpu->arch.virtual_tsc_shift);
1836 tsc += vcpu->arch.this_tsc_write;
1837 return tsc;
1838 }
1839
1840 static inline int gtod_is_based_on_tsc(int mode)
1841 {
1842 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1843 }
1844
1845 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1846 {
1847 #ifdef CONFIG_X86_64
1848 bool vcpus_matched;
1849 struct kvm_arch *ka = &vcpu->kvm->arch;
1850 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1851
1852 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1853 atomic_read(&vcpu->kvm->online_vcpus));
1854
1855 /*
1856 * Once the masterclock is enabled, always perform request in
1857 * order to update it.
1858 *
1859 * In order to enable masterclock, the host clocksource must be TSC
1860 * and the vcpus need to have matched TSCs. When that happens,
1861 * perform request to enable masterclock.
1862 */
1863 if (ka->use_master_clock ||
1864 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1865 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1866
1867 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1868 atomic_read(&vcpu->kvm->online_vcpus),
1869 ka->use_master_clock, gtod->clock.vclock_mode);
1870 #endif
1871 }
1872
1873 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1874 {
1875 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1876 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1877 }
1878
1879 /*
1880 * Multiply tsc by a fixed point number represented by ratio.
1881 *
1882 * The most significant 64-N bits (mult) of ratio represent the
1883 * integral part of the fixed point number; the remaining N bits
1884 * (frac) represent the fractional part, ie. ratio represents a fixed
1885 * point number (mult + frac * 2^(-N)).
1886 *
1887 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1888 */
1889 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1890 {
1891 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1892 }
1893
1894 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1895 {
1896 u64 _tsc = tsc;
1897 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1898
1899 if (ratio != kvm_default_tsc_scaling_ratio)
1900 _tsc = __scale_tsc(ratio, tsc);
1901
1902 return _tsc;
1903 }
1904 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1905
1906 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1907 {
1908 u64 tsc;
1909
1910 tsc = kvm_scale_tsc(vcpu, rdtsc());
1911
1912 return target_tsc - tsc;
1913 }
1914
1915 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1916 {
1917 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1918
1919 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1920 }
1921 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1922
1923 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1924 {
1925 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1926 }
1927
1928 static inline bool kvm_check_tsc_unstable(void)
1929 {
1930 #ifdef CONFIG_X86_64
1931 /*
1932 * TSC is marked unstable when we're running on Hyper-V,
1933 * 'TSC page' clocksource is good.
1934 */
1935 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1936 return false;
1937 #endif
1938 return check_tsc_unstable();
1939 }
1940
1941 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1942 {
1943 struct kvm *kvm = vcpu->kvm;
1944 u64 offset, ns, elapsed;
1945 unsigned long flags;
1946 bool matched;
1947 bool already_matched;
1948 u64 data = msr->data;
1949 bool synchronizing = false;
1950
1951 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1952 offset = kvm_compute_tsc_offset(vcpu, data);
1953 ns = ktime_get_boottime_ns();
1954 elapsed = ns - kvm->arch.last_tsc_nsec;
1955
1956 if (vcpu->arch.virtual_tsc_khz) {
1957 if (data == 0 && msr->host_initiated) {
1958 /*
1959 * detection of vcpu initialization -- need to sync
1960 * with other vCPUs. This particularly helps to keep
1961 * kvm_clock stable after CPU hotplug
1962 */
1963 synchronizing = true;
1964 } else {
1965 u64 tsc_exp = kvm->arch.last_tsc_write +
1966 nsec_to_cycles(vcpu, elapsed);
1967 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1968 /*
1969 * Special case: TSC write with a small delta (1 second)
1970 * of virtual cycle time against real time is
1971 * interpreted as an attempt to synchronize the CPU.
1972 */
1973 synchronizing = data < tsc_exp + tsc_hz &&
1974 data + tsc_hz > tsc_exp;
1975 }
1976 }
1977
1978 /*
1979 * For a reliable TSC, we can match TSC offsets, and for an unstable
1980 * TSC, we add elapsed time in this computation. We could let the
1981 * compensation code attempt to catch up if we fall behind, but
1982 * it's better to try to match offsets from the beginning.
1983 */
1984 if (synchronizing &&
1985 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1986 if (!kvm_check_tsc_unstable()) {
1987 offset = kvm->arch.cur_tsc_offset;
1988 } else {
1989 u64 delta = nsec_to_cycles(vcpu, elapsed);
1990 data += delta;
1991 offset = kvm_compute_tsc_offset(vcpu, data);
1992 }
1993 matched = true;
1994 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1995 } else {
1996 /*
1997 * We split periods of matched TSC writes into generations.
1998 * For each generation, we track the original measured
1999 * nanosecond time, offset, and write, so if TSCs are in
2000 * sync, we can match exact offset, and if not, we can match
2001 * exact software computation in compute_guest_tsc()
2002 *
2003 * These values are tracked in kvm->arch.cur_xxx variables.
2004 */
2005 kvm->arch.cur_tsc_generation++;
2006 kvm->arch.cur_tsc_nsec = ns;
2007 kvm->arch.cur_tsc_write = data;
2008 kvm->arch.cur_tsc_offset = offset;
2009 matched = false;
2010 }
2011
2012 /*
2013 * We also track th most recent recorded KHZ, write and time to
2014 * allow the matching interval to be extended at each write.
2015 */
2016 kvm->arch.last_tsc_nsec = ns;
2017 kvm->arch.last_tsc_write = data;
2018 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2019
2020 vcpu->arch.last_guest_tsc = data;
2021
2022 /* Keep track of which generation this VCPU has synchronized to */
2023 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2024 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2025 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2026
2027 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2028 update_ia32_tsc_adjust_msr(vcpu, offset);
2029
2030 kvm_vcpu_write_tsc_offset(vcpu, offset);
2031 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2032
2033 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2034 if (!matched) {
2035 kvm->arch.nr_vcpus_matched_tsc = 0;
2036 } else if (!already_matched) {
2037 kvm->arch.nr_vcpus_matched_tsc++;
2038 }
2039
2040 kvm_track_tsc_matching(vcpu);
2041 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2042 }
2043
2044 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2045
2046 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2047 s64 adjustment)
2048 {
2049 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2050 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2051 }
2052
2053 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2054 {
2055 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2056 WARN_ON(adjustment < 0);
2057 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2058 adjust_tsc_offset_guest(vcpu, adjustment);
2059 }
2060
2061 #ifdef CONFIG_X86_64
2062
2063 static u64 read_tsc(void)
2064 {
2065 u64 ret = (u64)rdtsc_ordered();
2066 u64 last = pvclock_gtod_data.clock.cycle_last;
2067
2068 if (likely(ret >= last))
2069 return ret;
2070
2071 /*
2072 * GCC likes to generate cmov here, but this branch is extremely
2073 * predictable (it's just a function of time and the likely is
2074 * very likely) and there's a data dependence, so force GCC
2075 * to generate a branch instead. I don't barrier() because
2076 * we don't actually need a barrier, and if this function
2077 * ever gets inlined it will generate worse code.
2078 */
2079 asm volatile ("");
2080 return last;
2081 }
2082
2083 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2084 int *mode)
2085 {
2086 long v;
2087 u64 tsc_pg_val;
2088
2089 switch (clock->vclock_mode) {
2090 case VCLOCK_HVCLOCK:
2091 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2092 tsc_timestamp);
2093 if (tsc_pg_val != U64_MAX) {
2094 /* TSC page valid */
2095 *mode = VCLOCK_HVCLOCK;
2096 v = (tsc_pg_val - clock->cycle_last) &
2097 clock->mask;
2098 } else {
2099 /* TSC page invalid */
2100 *mode = VCLOCK_NONE;
2101 }
2102 break;
2103 case VCLOCK_TSC:
2104 *mode = VCLOCK_TSC;
2105 *tsc_timestamp = read_tsc();
2106 v = (*tsc_timestamp - clock->cycle_last) &
2107 clock->mask;
2108 break;
2109 default:
2110 *mode = VCLOCK_NONE;
2111 }
2112
2113 if (*mode == VCLOCK_NONE)
2114 *tsc_timestamp = v = 0;
2115
2116 return v * clock->mult;
2117 }
2118
2119 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2120 {
2121 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2122 unsigned long seq;
2123 int mode;
2124 u64 ns;
2125
2126 do {
2127 seq = read_seqcount_begin(&gtod->seq);
2128 ns = gtod->monotonic_raw_nsec;
2129 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2130 ns >>= gtod->clock.shift;
2131 ns += gtod->boot_ns_raw;
2132 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2133 *t = ns;
2134
2135 return mode;
2136 }
2137
2138 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2139 {
2140 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2141 unsigned long seq;
2142 int mode;
2143 u64 ns;
2144
2145 do {
2146 seq = read_seqcount_begin(&gtod->seq);
2147 ts->tv_sec = gtod->wall_time_sec;
2148 ns = gtod->nsec_base;
2149 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2150 ns >>= gtod->clock.shift;
2151 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2152
2153 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2154 ts->tv_nsec = ns;
2155
2156 return mode;
2157 }
2158
2159 /* returns true if host is using TSC based clocksource */
2160 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2161 {
2162 /* checked again under seqlock below */
2163 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2164 return false;
2165
2166 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2167 tsc_timestamp));
2168 }
2169
2170 /* returns true if host is using TSC based clocksource */
2171 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2172 u64 *tsc_timestamp)
2173 {
2174 /* checked again under seqlock below */
2175 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2176 return false;
2177
2178 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2179 }
2180 #endif
2181
2182 /*
2183 *
2184 * Assuming a stable TSC across physical CPUS, and a stable TSC
2185 * across virtual CPUs, the following condition is possible.
2186 * Each numbered line represents an event visible to both
2187 * CPUs at the next numbered event.
2188 *
2189 * "timespecX" represents host monotonic time. "tscX" represents
2190 * RDTSC value.
2191 *
2192 * VCPU0 on CPU0 | VCPU1 on CPU1
2193 *
2194 * 1. read timespec0,tsc0
2195 * 2. | timespec1 = timespec0 + N
2196 * | tsc1 = tsc0 + M
2197 * 3. transition to guest | transition to guest
2198 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2199 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2200 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2201 *
2202 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2203 *
2204 * - ret0 < ret1
2205 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2206 * ...
2207 * - 0 < N - M => M < N
2208 *
2209 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2210 * always the case (the difference between two distinct xtime instances
2211 * might be smaller then the difference between corresponding TSC reads,
2212 * when updating guest vcpus pvclock areas).
2213 *
2214 * To avoid that problem, do not allow visibility of distinct
2215 * system_timestamp/tsc_timestamp values simultaneously: use a master
2216 * copy of host monotonic time values. Update that master copy
2217 * in lockstep.
2218 *
2219 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2220 *
2221 */
2222
2223 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2224 {
2225 #ifdef CONFIG_X86_64
2226 struct kvm_arch *ka = &kvm->arch;
2227 int vclock_mode;
2228 bool host_tsc_clocksource, vcpus_matched;
2229
2230 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2231 atomic_read(&kvm->online_vcpus));
2232
2233 /*
2234 * If the host uses TSC clock, then passthrough TSC as stable
2235 * to the guest.
2236 */
2237 host_tsc_clocksource = kvm_get_time_and_clockread(
2238 &ka->master_kernel_ns,
2239 &ka->master_cycle_now);
2240
2241 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2242 && !ka->backwards_tsc_observed
2243 && !ka->boot_vcpu_runs_old_kvmclock;
2244
2245 if (ka->use_master_clock)
2246 atomic_set(&kvm_guest_has_master_clock, 1);
2247
2248 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2249 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2250 vcpus_matched);
2251 #endif
2252 }
2253
2254 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2255 {
2256 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2257 }
2258
2259 static void kvm_gen_update_masterclock(struct kvm *kvm)
2260 {
2261 #ifdef CONFIG_X86_64
2262 int i;
2263 struct kvm_vcpu *vcpu;
2264 struct kvm_arch *ka = &kvm->arch;
2265
2266 spin_lock(&ka->pvclock_gtod_sync_lock);
2267 kvm_make_mclock_inprogress_request(kvm);
2268 /* no guest entries from this point */
2269 pvclock_update_vm_gtod_copy(kvm);
2270
2271 kvm_for_each_vcpu(i, vcpu, kvm)
2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2273
2274 /* guest entries allowed */
2275 kvm_for_each_vcpu(i, vcpu, kvm)
2276 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2277
2278 spin_unlock(&ka->pvclock_gtod_sync_lock);
2279 #endif
2280 }
2281
2282 u64 get_kvmclock_ns(struct kvm *kvm)
2283 {
2284 struct kvm_arch *ka = &kvm->arch;
2285 struct pvclock_vcpu_time_info hv_clock;
2286 u64 ret;
2287
2288 spin_lock(&ka->pvclock_gtod_sync_lock);
2289 if (!ka->use_master_clock) {
2290 spin_unlock(&ka->pvclock_gtod_sync_lock);
2291 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2292 }
2293
2294 hv_clock.tsc_timestamp = ka->master_cycle_now;
2295 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2296 spin_unlock(&ka->pvclock_gtod_sync_lock);
2297
2298 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2299 get_cpu();
2300
2301 if (__this_cpu_read(cpu_tsc_khz)) {
2302 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2303 &hv_clock.tsc_shift,
2304 &hv_clock.tsc_to_system_mul);
2305 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2306 } else
2307 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2308
2309 put_cpu();
2310
2311 return ret;
2312 }
2313
2314 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2315 {
2316 struct kvm_vcpu_arch *vcpu = &v->arch;
2317 struct pvclock_vcpu_time_info guest_hv_clock;
2318
2319 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2320 &guest_hv_clock, sizeof(guest_hv_clock))))
2321 return;
2322
2323 /* This VCPU is paused, but it's legal for a guest to read another
2324 * VCPU's kvmclock, so we really have to follow the specification where
2325 * it says that version is odd if data is being modified, and even after
2326 * it is consistent.
2327 *
2328 * Version field updates must be kept separate. This is because
2329 * kvm_write_guest_cached might use a "rep movs" instruction, and
2330 * writes within a string instruction are weakly ordered. So there
2331 * are three writes overall.
2332 *
2333 * As a small optimization, only write the version field in the first
2334 * and third write. The vcpu->pv_time cache is still valid, because the
2335 * version field is the first in the struct.
2336 */
2337 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2338
2339 if (guest_hv_clock.version & 1)
2340 ++guest_hv_clock.version; /* first time write, random junk */
2341
2342 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2343 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2344 &vcpu->hv_clock,
2345 sizeof(vcpu->hv_clock.version));
2346
2347 smp_wmb();
2348
2349 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2350 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2351
2352 if (vcpu->pvclock_set_guest_stopped_request) {
2353 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2354 vcpu->pvclock_set_guest_stopped_request = false;
2355 }
2356
2357 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2358
2359 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2360 &vcpu->hv_clock,
2361 sizeof(vcpu->hv_clock));
2362
2363 smp_wmb();
2364
2365 vcpu->hv_clock.version++;
2366 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2367 &vcpu->hv_clock,
2368 sizeof(vcpu->hv_clock.version));
2369 }
2370
2371 static int kvm_guest_time_update(struct kvm_vcpu *v)
2372 {
2373 unsigned long flags, tgt_tsc_khz;
2374 struct kvm_vcpu_arch *vcpu = &v->arch;
2375 struct kvm_arch *ka = &v->kvm->arch;
2376 s64 kernel_ns;
2377 u64 tsc_timestamp, host_tsc;
2378 u8 pvclock_flags;
2379 bool use_master_clock;
2380
2381 kernel_ns = 0;
2382 host_tsc = 0;
2383
2384 /*
2385 * If the host uses TSC clock, then passthrough TSC as stable
2386 * to the guest.
2387 */
2388 spin_lock(&ka->pvclock_gtod_sync_lock);
2389 use_master_clock = ka->use_master_clock;
2390 if (use_master_clock) {
2391 host_tsc = ka->master_cycle_now;
2392 kernel_ns = ka->master_kernel_ns;
2393 }
2394 spin_unlock(&ka->pvclock_gtod_sync_lock);
2395
2396 /* Keep irq disabled to prevent changes to the clock */
2397 local_irq_save(flags);
2398 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2399 if (unlikely(tgt_tsc_khz == 0)) {
2400 local_irq_restore(flags);
2401 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2402 return 1;
2403 }
2404 if (!use_master_clock) {
2405 host_tsc = rdtsc();
2406 kernel_ns = ktime_get_boottime_ns();
2407 }
2408
2409 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2410
2411 /*
2412 * We may have to catch up the TSC to match elapsed wall clock
2413 * time for two reasons, even if kvmclock is used.
2414 * 1) CPU could have been running below the maximum TSC rate
2415 * 2) Broken TSC compensation resets the base at each VCPU
2416 * entry to avoid unknown leaps of TSC even when running
2417 * again on the same CPU. This may cause apparent elapsed
2418 * time to disappear, and the guest to stand still or run
2419 * very slowly.
2420 */
2421 if (vcpu->tsc_catchup) {
2422 u64 tsc = compute_guest_tsc(v, kernel_ns);
2423 if (tsc > tsc_timestamp) {
2424 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2425 tsc_timestamp = tsc;
2426 }
2427 }
2428
2429 local_irq_restore(flags);
2430
2431 /* With all the info we got, fill in the values */
2432
2433 if (kvm_has_tsc_control)
2434 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2435
2436 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2437 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2438 &vcpu->hv_clock.tsc_shift,
2439 &vcpu->hv_clock.tsc_to_system_mul);
2440 vcpu->hw_tsc_khz = tgt_tsc_khz;
2441 }
2442
2443 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2444 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2445 vcpu->last_guest_tsc = tsc_timestamp;
2446
2447 /* If the host uses TSC clocksource, then it is stable */
2448 pvclock_flags = 0;
2449 if (use_master_clock)
2450 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2451
2452 vcpu->hv_clock.flags = pvclock_flags;
2453
2454 if (vcpu->pv_time_enabled)
2455 kvm_setup_pvclock_page(v);
2456 if (v == kvm_get_vcpu(v->kvm, 0))
2457 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2458 return 0;
2459 }
2460
2461 /*
2462 * kvmclock updates which are isolated to a given vcpu, such as
2463 * vcpu->cpu migration, should not allow system_timestamp from
2464 * the rest of the vcpus to remain static. Otherwise ntp frequency
2465 * correction applies to one vcpu's system_timestamp but not
2466 * the others.
2467 *
2468 * So in those cases, request a kvmclock update for all vcpus.
2469 * We need to rate-limit these requests though, as they can
2470 * considerably slow guests that have a large number of vcpus.
2471 * The time for a remote vcpu to update its kvmclock is bound
2472 * by the delay we use to rate-limit the updates.
2473 */
2474
2475 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2476
2477 static void kvmclock_update_fn(struct work_struct *work)
2478 {
2479 int i;
2480 struct delayed_work *dwork = to_delayed_work(work);
2481 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2482 kvmclock_update_work);
2483 struct kvm *kvm = container_of(ka, struct kvm, arch);
2484 struct kvm_vcpu *vcpu;
2485
2486 kvm_for_each_vcpu(i, vcpu, kvm) {
2487 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2488 kvm_vcpu_kick(vcpu);
2489 }
2490 }
2491
2492 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2493 {
2494 struct kvm *kvm = v->kvm;
2495
2496 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2497 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2498 KVMCLOCK_UPDATE_DELAY);
2499 }
2500
2501 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2502
2503 static void kvmclock_sync_fn(struct work_struct *work)
2504 {
2505 struct delayed_work *dwork = to_delayed_work(work);
2506 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2507 kvmclock_sync_work);
2508 struct kvm *kvm = container_of(ka, struct kvm, arch);
2509
2510 if (!kvmclock_periodic_sync)
2511 return;
2512
2513 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2514 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2515 KVMCLOCK_SYNC_PERIOD);
2516 }
2517
2518 /*
2519 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2520 */
2521 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2522 {
2523 /* McStatusWrEn enabled? */
2524 if (guest_cpuid_is_amd(vcpu))
2525 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2526
2527 return false;
2528 }
2529
2530 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2531 {
2532 u64 mcg_cap = vcpu->arch.mcg_cap;
2533 unsigned bank_num = mcg_cap & 0xff;
2534 u32 msr = msr_info->index;
2535 u64 data = msr_info->data;
2536
2537 switch (msr) {
2538 case MSR_IA32_MCG_STATUS:
2539 vcpu->arch.mcg_status = data;
2540 break;
2541 case MSR_IA32_MCG_CTL:
2542 if (!(mcg_cap & MCG_CTL_P) &&
2543 (data || !msr_info->host_initiated))
2544 return 1;
2545 if (data != 0 && data != ~(u64)0)
2546 return 1;
2547 vcpu->arch.mcg_ctl = data;
2548 break;
2549 default:
2550 if (msr >= MSR_IA32_MC0_CTL &&
2551 msr < MSR_IA32_MCx_CTL(bank_num)) {
2552 u32 offset = array_index_nospec(
2553 msr - MSR_IA32_MC0_CTL,
2554 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2555
2556 /* only 0 or all 1s can be written to IA32_MCi_CTL
2557 * some Linux kernels though clear bit 10 in bank 4 to
2558 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2559 * this to avoid an uncatched #GP in the guest
2560 */
2561 if ((offset & 0x3) == 0 &&
2562 data != 0 && (data | (1 << 10)) != ~(u64)0)
2563 return -1;
2564
2565 /* MCi_STATUS */
2566 if (!msr_info->host_initiated &&
2567 (offset & 0x3) == 1 && data != 0) {
2568 if (!can_set_mci_status(vcpu))
2569 return -1;
2570 }
2571
2572 vcpu->arch.mce_banks[offset] = data;
2573 break;
2574 }
2575 return 1;
2576 }
2577 return 0;
2578 }
2579
2580 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2581 {
2582 struct kvm *kvm = vcpu->kvm;
2583 int lm = is_long_mode(vcpu);
2584 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2585 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2586 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2587 : kvm->arch.xen_hvm_config.blob_size_32;
2588 u32 page_num = data & ~PAGE_MASK;
2589 u64 page_addr = data & PAGE_MASK;
2590 u8 *page;
2591 int r;
2592
2593 r = -E2BIG;
2594 if (page_num >= blob_size)
2595 goto out;
2596 r = -ENOMEM;
2597 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2598 if (IS_ERR(page)) {
2599 r = PTR_ERR(page);
2600 goto out;
2601 }
2602 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2603 goto out_free;
2604 r = 0;
2605 out_free:
2606 kfree(page);
2607 out:
2608 return r;
2609 }
2610
2611 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2612 {
2613 gpa_t gpa = data & ~0x3f;
2614
2615 /* Bits 3:5 are reserved, Should be zero */
2616 if (data & 0x38)
2617 return 1;
2618
2619 vcpu->arch.apf.msr_val = data;
2620
2621 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2622 kvm_clear_async_pf_completion_queue(vcpu);
2623 kvm_async_pf_hash_reset(vcpu);
2624 return 0;
2625 }
2626
2627 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2628 sizeof(u32)))
2629 return 1;
2630
2631 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2632 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2633 kvm_async_pf_wakeup_all(vcpu);
2634 return 0;
2635 }
2636
2637 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2638 {
2639 vcpu->arch.pv_time_enabled = false;
2640 vcpu->arch.time = 0;
2641 }
2642
2643 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2644 {
2645 ++vcpu->stat.tlb_flush;
2646 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2647 }
2648
2649 static void record_steal_time(struct kvm_vcpu *vcpu)
2650 {
2651 struct kvm_host_map map;
2652 struct kvm_steal_time *st;
2653
2654 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2655 return;
2656
2657 /* -EAGAIN is returned in atomic context so we can just return. */
2658 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2659 &map, &vcpu->arch.st.cache, false))
2660 return;
2661
2662 st = map.hva +
2663 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2664
2665 /*
2666 * Doing a TLB flush here, on the guest's behalf, can avoid
2667 * expensive IPIs.
2668 */
2669 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2670 st->preempted & KVM_VCPU_FLUSH_TLB);
2671 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2672 kvm_vcpu_flush_tlb(vcpu, false);
2673
2674 vcpu->arch.st.preempted = 0;
2675
2676 if (st->version & 1)
2677 st->version += 1; /* first time write, random junk */
2678
2679 st->version += 1;
2680
2681 smp_wmb();
2682
2683 st->steal += current->sched_info.run_delay -
2684 vcpu->arch.st.last_steal;
2685 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2686
2687 smp_wmb();
2688
2689 st->version += 1;
2690
2691 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2692 }
2693
2694 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2695 {
2696 bool pr = false;
2697 u32 msr = msr_info->index;
2698 u64 data = msr_info->data;
2699
2700 switch (msr) {
2701 case MSR_AMD64_NB_CFG:
2702 case MSR_IA32_UCODE_WRITE:
2703 case MSR_VM_HSAVE_PA:
2704 case MSR_AMD64_PATCH_LOADER:
2705 case MSR_AMD64_BU_CFG2:
2706 case MSR_AMD64_DC_CFG:
2707 case MSR_F15H_EX_CFG:
2708 break;
2709
2710 case MSR_IA32_UCODE_REV:
2711 if (msr_info->host_initiated)
2712 vcpu->arch.microcode_version = data;
2713 break;
2714 case MSR_IA32_ARCH_CAPABILITIES:
2715 if (!msr_info->host_initiated)
2716 return 1;
2717 vcpu->arch.arch_capabilities = data;
2718 break;
2719 case MSR_EFER:
2720 return set_efer(vcpu, msr_info);
2721 case MSR_K7_HWCR:
2722 data &= ~(u64)0x40; /* ignore flush filter disable */
2723 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2724 data &= ~(u64)0x8; /* ignore TLB cache disable */
2725
2726 /* Handle McStatusWrEn */
2727 if (data == BIT_ULL(18)) {
2728 vcpu->arch.msr_hwcr = data;
2729 } else if (data != 0) {
2730 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2731 data);
2732 return 1;
2733 }
2734 break;
2735 case MSR_FAM10H_MMIO_CONF_BASE:
2736 if (data != 0) {
2737 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2738 "0x%llx\n", data);
2739 return 1;
2740 }
2741 break;
2742 case MSR_IA32_DEBUGCTLMSR:
2743 if (!data) {
2744 /* We support the non-activated case already */
2745 break;
2746 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2747 /* Values other than LBR and BTF are vendor-specific,
2748 thus reserved and should throw a #GP */
2749 return 1;
2750 }
2751 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2752 __func__, data);
2753 break;
2754 case 0x200 ... 0x2ff:
2755 return kvm_mtrr_set_msr(vcpu, msr, data);
2756 case MSR_IA32_APICBASE:
2757 return kvm_set_apic_base(vcpu, msr_info);
2758 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2759 return kvm_x2apic_msr_write(vcpu, msr, data);
2760 case MSR_IA32_TSCDEADLINE:
2761 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2762 break;
2763 case MSR_IA32_TSC_ADJUST:
2764 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2765 if (!msr_info->host_initiated) {
2766 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2767 adjust_tsc_offset_guest(vcpu, adj);
2768 }
2769 vcpu->arch.ia32_tsc_adjust_msr = data;
2770 }
2771 break;
2772 case MSR_IA32_MISC_ENABLE:
2773 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2774 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2775 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2776 return 1;
2777 vcpu->arch.ia32_misc_enable_msr = data;
2778 kvm_update_cpuid(vcpu);
2779 } else {
2780 vcpu->arch.ia32_misc_enable_msr = data;
2781 }
2782 break;
2783 case MSR_IA32_SMBASE:
2784 if (!msr_info->host_initiated)
2785 return 1;
2786 vcpu->arch.smbase = data;
2787 break;
2788 case MSR_IA32_POWER_CTL:
2789 vcpu->arch.msr_ia32_power_ctl = data;
2790 break;
2791 case MSR_IA32_TSC:
2792 kvm_write_tsc(vcpu, msr_info);
2793 break;
2794 case MSR_IA32_XSS:
2795 if (!msr_info->host_initiated &&
2796 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2797 return 1;
2798 /*
2799 * We do support PT if kvm_x86_ops->pt_supported(), but we do
2800 * not support IA32_XSS[bit 8]. Guests will have to use
2801 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2802 * MSRs.
2803 */
2804 if (data != 0)
2805 return 1;
2806 vcpu->arch.ia32_xss = data;
2807 break;
2808 case MSR_SMI_COUNT:
2809 if (!msr_info->host_initiated)
2810 return 1;
2811 vcpu->arch.smi_count = data;
2812 break;
2813 case MSR_KVM_WALL_CLOCK_NEW:
2814 case MSR_KVM_WALL_CLOCK:
2815 vcpu->kvm->arch.wall_clock = data;
2816 kvm_write_wall_clock(vcpu->kvm, data);
2817 break;
2818 case MSR_KVM_SYSTEM_TIME_NEW:
2819 case MSR_KVM_SYSTEM_TIME: {
2820 struct kvm_arch *ka = &vcpu->kvm->arch;
2821
2822 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2823 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2824
2825 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2826 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2827
2828 ka->boot_vcpu_runs_old_kvmclock = tmp;
2829 }
2830
2831 vcpu->arch.time = data;
2832 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2833
2834 /* we verify if the enable bit is set... */
2835 vcpu->arch.pv_time_enabled = false;
2836 if (!(data & 1))
2837 break;
2838
2839 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2840 &vcpu->arch.pv_time, data & ~1ULL,
2841 sizeof(struct pvclock_vcpu_time_info)))
2842 vcpu->arch.pv_time_enabled = true;
2843
2844 break;
2845 }
2846 case MSR_KVM_ASYNC_PF_EN:
2847 if (kvm_pv_enable_async_pf(vcpu, data))
2848 return 1;
2849 break;
2850 case MSR_KVM_STEAL_TIME:
2851
2852 if (unlikely(!sched_info_on()))
2853 return 1;
2854
2855 if (data & KVM_STEAL_RESERVED_MASK)
2856 return 1;
2857
2858 vcpu->arch.st.msr_val = data;
2859
2860 if (!(data & KVM_MSR_ENABLED))
2861 break;
2862
2863 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2864
2865 break;
2866 case MSR_KVM_PV_EOI_EN:
2867 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2868 return 1;
2869 break;
2870
2871 case MSR_KVM_POLL_CONTROL:
2872 /* only enable bit supported */
2873 if (data & (-1ULL << 1))
2874 return 1;
2875
2876 vcpu->arch.msr_kvm_poll_control = data;
2877 break;
2878
2879 case MSR_IA32_MCG_CTL:
2880 case MSR_IA32_MCG_STATUS:
2881 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2882 return set_msr_mce(vcpu, msr_info);
2883
2884 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2885 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2886 pr = true; /* fall through */
2887 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2888 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2889 if (kvm_pmu_is_valid_msr(vcpu, msr))
2890 return kvm_pmu_set_msr(vcpu, msr_info);
2891
2892 if (pr || data != 0)
2893 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2894 "0x%x data 0x%llx\n", msr, data);
2895 break;
2896 case MSR_K7_CLK_CTL:
2897 /*
2898 * Ignore all writes to this no longer documented MSR.
2899 * Writes are only relevant for old K7 processors,
2900 * all pre-dating SVM, but a recommended workaround from
2901 * AMD for these chips. It is possible to specify the
2902 * affected processor models on the command line, hence
2903 * the need to ignore the workaround.
2904 */
2905 break;
2906 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2907 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2908 case HV_X64_MSR_CRASH_CTL:
2909 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2910 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2911 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2912 case HV_X64_MSR_TSC_EMULATION_STATUS:
2913 return kvm_hv_set_msr_common(vcpu, msr, data,
2914 msr_info->host_initiated);
2915 case MSR_IA32_BBL_CR_CTL3:
2916 /* Drop writes to this legacy MSR -- see rdmsr
2917 * counterpart for further detail.
2918 */
2919 if (report_ignored_msrs)
2920 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2921 msr, data);
2922 break;
2923 case MSR_AMD64_OSVW_ID_LENGTH:
2924 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2925 return 1;
2926 vcpu->arch.osvw.length = data;
2927 break;
2928 case MSR_AMD64_OSVW_STATUS:
2929 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2930 return 1;
2931 vcpu->arch.osvw.status = data;
2932 break;
2933 case MSR_PLATFORM_INFO:
2934 if (!msr_info->host_initiated ||
2935 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2936 cpuid_fault_enabled(vcpu)))
2937 return 1;
2938 vcpu->arch.msr_platform_info = data;
2939 break;
2940 case MSR_MISC_FEATURES_ENABLES:
2941 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2942 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2943 !supports_cpuid_fault(vcpu)))
2944 return 1;
2945 vcpu->arch.msr_misc_features_enables = data;
2946 break;
2947 default:
2948 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2949 return xen_hvm_config(vcpu, data);
2950 if (kvm_pmu_is_valid_msr(vcpu, msr))
2951 return kvm_pmu_set_msr(vcpu, msr_info);
2952 if (!ignore_msrs) {
2953 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2954 msr, data);
2955 return 1;
2956 } else {
2957 if (report_ignored_msrs)
2958 vcpu_unimpl(vcpu,
2959 "ignored wrmsr: 0x%x data 0x%llx\n",
2960 msr, data);
2961 break;
2962 }
2963 }
2964 return 0;
2965 }
2966 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2967
2968 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2969 {
2970 u64 data;
2971 u64 mcg_cap = vcpu->arch.mcg_cap;
2972 unsigned bank_num = mcg_cap & 0xff;
2973
2974 switch (msr) {
2975 case MSR_IA32_P5_MC_ADDR:
2976 case MSR_IA32_P5_MC_TYPE:
2977 data = 0;
2978 break;
2979 case MSR_IA32_MCG_CAP:
2980 data = vcpu->arch.mcg_cap;
2981 break;
2982 case MSR_IA32_MCG_CTL:
2983 if (!(mcg_cap & MCG_CTL_P) && !host)
2984 return 1;
2985 data = vcpu->arch.mcg_ctl;
2986 break;
2987 case MSR_IA32_MCG_STATUS:
2988 data = vcpu->arch.mcg_status;
2989 break;
2990 default:
2991 if (msr >= MSR_IA32_MC0_CTL &&
2992 msr < MSR_IA32_MCx_CTL(bank_num)) {
2993 u32 offset = array_index_nospec(
2994 msr - MSR_IA32_MC0_CTL,
2995 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2996
2997 data = vcpu->arch.mce_banks[offset];
2998 break;
2999 }
3000 return 1;
3001 }
3002 *pdata = data;
3003 return 0;
3004 }
3005
3006 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3007 {
3008 switch (msr_info->index) {
3009 case MSR_IA32_PLATFORM_ID:
3010 case MSR_IA32_EBL_CR_POWERON:
3011 case MSR_IA32_DEBUGCTLMSR:
3012 case MSR_IA32_LASTBRANCHFROMIP:
3013 case MSR_IA32_LASTBRANCHTOIP:
3014 case MSR_IA32_LASTINTFROMIP:
3015 case MSR_IA32_LASTINTTOIP:
3016 case MSR_K8_SYSCFG:
3017 case MSR_K8_TSEG_ADDR:
3018 case MSR_K8_TSEG_MASK:
3019 case MSR_VM_HSAVE_PA:
3020 case MSR_K8_INT_PENDING_MSG:
3021 case MSR_AMD64_NB_CFG:
3022 case MSR_FAM10H_MMIO_CONF_BASE:
3023 case MSR_AMD64_BU_CFG2:
3024 case MSR_IA32_PERF_CTL:
3025 case MSR_AMD64_DC_CFG:
3026 case MSR_F15H_EX_CFG:
3027 msr_info->data = 0;
3028 break;
3029 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3030 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3031 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3032 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3033 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3034 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3035 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3036 msr_info->data = 0;
3037 break;
3038 case MSR_IA32_UCODE_REV:
3039 msr_info->data = vcpu->arch.microcode_version;
3040 break;
3041 case MSR_IA32_ARCH_CAPABILITIES:
3042 if (!msr_info->host_initiated &&
3043 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3044 return 1;
3045 msr_info->data = vcpu->arch.arch_capabilities;
3046 break;
3047 case MSR_IA32_POWER_CTL:
3048 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3049 break;
3050 case MSR_IA32_TSC:
3051 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3052 break;
3053 case MSR_MTRRcap:
3054 case 0x200 ... 0x2ff:
3055 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3056 case 0xcd: /* fsb frequency */
3057 msr_info->data = 3;
3058 break;
3059 /*
3060 * MSR_EBC_FREQUENCY_ID
3061 * Conservative value valid for even the basic CPU models.
3062 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3063 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3064 * and 266MHz for model 3, or 4. Set Core Clock
3065 * Frequency to System Bus Frequency Ratio to 1 (bits
3066 * 31:24) even though these are only valid for CPU
3067 * models > 2, however guests may end up dividing or
3068 * multiplying by zero otherwise.
3069 */
3070 case MSR_EBC_FREQUENCY_ID:
3071 msr_info->data = 1 << 24;
3072 break;
3073 case MSR_IA32_APICBASE:
3074 msr_info->data = kvm_get_apic_base(vcpu);
3075 break;
3076 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3077 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3078 break;
3079 case MSR_IA32_TSCDEADLINE:
3080 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3081 break;
3082 case MSR_IA32_TSC_ADJUST:
3083 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3084 break;
3085 case MSR_IA32_MISC_ENABLE:
3086 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3087 break;
3088 case MSR_IA32_SMBASE:
3089 if (!msr_info->host_initiated)
3090 return 1;
3091 msr_info->data = vcpu->arch.smbase;
3092 break;
3093 case MSR_SMI_COUNT:
3094 msr_info->data = vcpu->arch.smi_count;
3095 break;
3096 case MSR_IA32_PERF_STATUS:
3097 /* TSC increment by tick */
3098 msr_info->data = 1000ULL;
3099 /* CPU multiplier */
3100 msr_info->data |= (((uint64_t)4ULL) << 40);
3101 break;
3102 case MSR_EFER:
3103 msr_info->data = vcpu->arch.efer;
3104 break;
3105 case MSR_KVM_WALL_CLOCK:
3106 case MSR_KVM_WALL_CLOCK_NEW:
3107 msr_info->data = vcpu->kvm->arch.wall_clock;
3108 break;
3109 case MSR_KVM_SYSTEM_TIME:
3110 case MSR_KVM_SYSTEM_TIME_NEW:
3111 msr_info->data = vcpu->arch.time;
3112 break;
3113 case MSR_KVM_ASYNC_PF_EN:
3114 msr_info->data = vcpu->arch.apf.msr_val;
3115 break;
3116 case MSR_KVM_STEAL_TIME:
3117 msr_info->data = vcpu->arch.st.msr_val;
3118 break;
3119 case MSR_KVM_PV_EOI_EN:
3120 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3121 break;
3122 case MSR_KVM_POLL_CONTROL:
3123 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3124 break;
3125 case MSR_IA32_P5_MC_ADDR:
3126 case MSR_IA32_P5_MC_TYPE:
3127 case MSR_IA32_MCG_CAP:
3128 case MSR_IA32_MCG_CTL:
3129 case MSR_IA32_MCG_STATUS:
3130 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3131 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3132 msr_info->host_initiated);
3133 case MSR_IA32_XSS:
3134 if (!msr_info->host_initiated &&
3135 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3136 return 1;
3137 msr_info->data = vcpu->arch.ia32_xss;
3138 break;
3139 case MSR_K7_CLK_CTL:
3140 /*
3141 * Provide expected ramp-up count for K7. All other
3142 * are set to zero, indicating minimum divisors for
3143 * every field.
3144 *
3145 * This prevents guest kernels on AMD host with CPU
3146 * type 6, model 8 and higher from exploding due to
3147 * the rdmsr failing.
3148 */
3149 msr_info->data = 0x20000000;
3150 break;
3151 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3152 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3153 case HV_X64_MSR_CRASH_CTL:
3154 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3155 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3156 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3157 case HV_X64_MSR_TSC_EMULATION_STATUS:
3158 return kvm_hv_get_msr_common(vcpu,
3159 msr_info->index, &msr_info->data,
3160 msr_info->host_initiated);
3161 break;
3162 case MSR_IA32_BBL_CR_CTL3:
3163 /* This legacy MSR exists but isn't fully documented in current
3164 * silicon. It is however accessed by winxp in very narrow
3165 * scenarios where it sets bit #19, itself documented as
3166 * a "reserved" bit. Best effort attempt to source coherent
3167 * read data here should the balance of the register be
3168 * interpreted by the guest:
3169 *
3170 * L2 cache control register 3: 64GB range, 256KB size,
3171 * enabled, latency 0x1, configured
3172 */
3173 msr_info->data = 0xbe702111;
3174 break;
3175 case MSR_AMD64_OSVW_ID_LENGTH:
3176 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3177 return 1;
3178 msr_info->data = vcpu->arch.osvw.length;
3179 break;
3180 case MSR_AMD64_OSVW_STATUS:
3181 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3182 return 1;
3183 msr_info->data = vcpu->arch.osvw.status;
3184 break;
3185 case MSR_PLATFORM_INFO:
3186 if (!msr_info->host_initiated &&
3187 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3188 return 1;
3189 msr_info->data = vcpu->arch.msr_platform_info;
3190 break;
3191 case MSR_MISC_FEATURES_ENABLES:
3192 msr_info->data = vcpu->arch.msr_misc_features_enables;
3193 break;
3194 case MSR_K7_HWCR:
3195 msr_info->data = vcpu->arch.msr_hwcr;
3196 break;
3197 default:
3198 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3199 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3200 if (!ignore_msrs) {
3201 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3202 msr_info->index);
3203 return 1;
3204 } else {
3205 if (report_ignored_msrs)
3206 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3207 msr_info->index);
3208 msr_info->data = 0;
3209 }
3210 break;
3211 }
3212 return 0;
3213 }
3214 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3215
3216 /*
3217 * Read or write a bunch of msrs. All parameters are kernel addresses.
3218 *
3219 * @return number of msrs set successfully.
3220 */
3221 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3222 struct kvm_msr_entry *entries,
3223 int (*do_msr)(struct kvm_vcpu *vcpu,
3224 unsigned index, u64 *data))
3225 {
3226 int i;
3227
3228 for (i = 0; i < msrs->nmsrs; ++i)
3229 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3230 break;
3231
3232 return i;
3233 }
3234
3235 /*
3236 * Read or write a bunch of msrs. Parameters are user addresses.
3237 *
3238 * @return number of msrs set successfully.
3239 */
3240 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3241 int (*do_msr)(struct kvm_vcpu *vcpu,
3242 unsigned index, u64 *data),
3243 int writeback)
3244 {
3245 struct kvm_msrs msrs;
3246 struct kvm_msr_entry *entries;
3247 int r, n;
3248 unsigned size;
3249
3250 r = -EFAULT;
3251 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3252 goto out;
3253
3254 r = -E2BIG;
3255 if (msrs.nmsrs >= MAX_IO_MSRS)
3256 goto out;
3257
3258 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3259 entries = memdup_user(user_msrs->entries, size);
3260 if (IS_ERR(entries)) {
3261 r = PTR_ERR(entries);
3262 goto out;
3263 }
3264
3265 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3266 if (r < 0)
3267 goto out_free;
3268
3269 r = -EFAULT;
3270 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3271 goto out_free;
3272
3273 r = n;
3274
3275 out_free:
3276 kfree(entries);
3277 out:
3278 return r;
3279 }
3280
3281 static inline bool kvm_can_mwait_in_guest(void)
3282 {
3283 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3284 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3285 boot_cpu_has(X86_FEATURE_ARAT);
3286 }
3287
3288 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3289 {
3290 int r = 0;
3291
3292 switch (ext) {
3293 case KVM_CAP_IRQCHIP:
3294 case KVM_CAP_HLT:
3295 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3296 case KVM_CAP_SET_TSS_ADDR:
3297 case KVM_CAP_EXT_CPUID:
3298 case KVM_CAP_EXT_EMUL_CPUID:
3299 case KVM_CAP_CLOCKSOURCE:
3300 case KVM_CAP_PIT:
3301 case KVM_CAP_NOP_IO_DELAY:
3302 case KVM_CAP_MP_STATE:
3303 case KVM_CAP_SYNC_MMU:
3304 case KVM_CAP_USER_NMI:
3305 case KVM_CAP_REINJECT_CONTROL:
3306 case KVM_CAP_IRQ_INJECT_STATUS:
3307 case KVM_CAP_IOEVENTFD:
3308 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3309 case KVM_CAP_PIT2:
3310 case KVM_CAP_PIT_STATE2:
3311 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3312 case KVM_CAP_XEN_HVM:
3313 case KVM_CAP_VCPU_EVENTS:
3314 case KVM_CAP_HYPERV:
3315 case KVM_CAP_HYPERV_VAPIC:
3316 case KVM_CAP_HYPERV_SPIN:
3317 case KVM_CAP_HYPERV_SYNIC:
3318 case KVM_CAP_HYPERV_SYNIC2:
3319 case KVM_CAP_HYPERV_VP_INDEX:
3320 case KVM_CAP_HYPERV_EVENTFD:
3321 case KVM_CAP_HYPERV_TLBFLUSH:
3322 case KVM_CAP_HYPERV_SEND_IPI:
3323 case KVM_CAP_HYPERV_CPUID:
3324 case KVM_CAP_PCI_SEGMENT:
3325 case KVM_CAP_DEBUGREGS:
3326 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3327 case KVM_CAP_XSAVE:
3328 case KVM_CAP_ASYNC_PF:
3329 case KVM_CAP_GET_TSC_KHZ:
3330 case KVM_CAP_KVMCLOCK_CTRL:
3331 case KVM_CAP_READONLY_MEM:
3332 case KVM_CAP_HYPERV_TIME:
3333 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3334 case KVM_CAP_TSC_DEADLINE_TIMER:
3335 case KVM_CAP_DISABLE_QUIRKS:
3336 case KVM_CAP_SET_BOOT_CPU_ID:
3337 case KVM_CAP_SPLIT_IRQCHIP:
3338 case KVM_CAP_IMMEDIATE_EXIT:
3339 case KVM_CAP_PMU_EVENT_FILTER:
3340 case KVM_CAP_GET_MSR_FEATURES:
3341 case KVM_CAP_MSR_PLATFORM_INFO:
3342 case KVM_CAP_EXCEPTION_PAYLOAD:
3343 r = 1;
3344 break;
3345 case KVM_CAP_SYNC_REGS:
3346 r = KVM_SYNC_X86_VALID_FIELDS;
3347 break;
3348 case KVM_CAP_ADJUST_CLOCK:
3349 r = KVM_CLOCK_TSC_STABLE;
3350 break;
3351 case KVM_CAP_X86_DISABLE_EXITS:
3352 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3353 KVM_X86_DISABLE_EXITS_CSTATE;
3354 if(kvm_can_mwait_in_guest())
3355 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3356 break;
3357 case KVM_CAP_X86_SMM:
3358 /* SMBASE is usually relocated above 1M on modern chipsets,
3359 * and SMM handlers might indeed rely on 4G segment limits,
3360 * so do not report SMM to be available if real mode is
3361 * emulated via vm86 mode. Still, do not go to great lengths
3362 * to avoid userspace's usage of the feature, because it is a
3363 * fringe case that is not enabled except via specific settings
3364 * of the module parameters.
3365 */
3366 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3367 break;
3368 case KVM_CAP_VAPIC:
3369 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3370 break;
3371 case KVM_CAP_NR_VCPUS:
3372 r = KVM_SOFT_MAX_VCPUS;
3373 break;
3374 case KVM_CAP_MAX_VCPUS:
3375 r = KVM_MAX_VCPUS;
3376 break;
3377 case KVM_CAP_MAX_VCPU_ID:
3378 r = KVM_MAX_VCPU_ID;
3379 break;
3380 case KVM_CAP_PV_MMU: /* obsolete */
3381 r = 0;
3382 break;
3383 case KVM_CAP_MCE:
3384 r = KVM_MAX_MCE_BANKS;
3385 break;
3386 case KVM_CAP_XCRS:
3387 r = boot_cpu_has(X86_FEATURE_XSAVE);
3388 break;
3389 case KVM_CAP_TSC_CONTROL:
3390 r = kvm_has_tsc_control;
3391 break;
3392 case KVM_CAP_X2APIC_API:
3393 r = KVM_X2APIC_API_VALID_FLAGS;
3394 break;
3395 case KVM_CAP_NESTED_STATE:
3396 r = kvm_x86_ops->get_nested_state ?
3397 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3398 break;
3399 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3400 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3401 break;
3402 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3403 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3404 break;
3405 default:
3406 break;
3407 }
3408 return r;
3409
3410 }
3411
3412 long kvm_arch_dev_ioctl(struct file *filp,
3413 unsigned int ioctl, unsigned long arg)
3414 {
3415 void __user *argp = (void __user *)arg;
3416 long r;
3417
3418 switch (ioctl) {
3419 case KVM_GET_MSR_INDEX_LIST: {
3420 struct kvm_msr_list __user *user_msr_list = argp;
3421 struct kvm_msr_list msr_list;
3422 unsigned n;
3423
3424 r = -EFAULT;
3425 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3426 goto out;
3427 n = msr_list.nmsrs;
3428 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3429 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3430 goto out;
3431 r = -E2BIG;
3432 if (n < msr_list.nmsrs)
3433 goto out;
3434 r = -EFAULT;
3435 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3436 num_msrs_to_save * sizeof(u32)))
3437 goto out;
3438 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3439 &emulated_msrs,
3440 num_emulated_msrs * sizeof(u32)))
3441 goto out;
3442 r = 0;
3443 break;
3444 }
3445 case KVM_GET_SUPPORTED_CPUID:
3446 case KVM_GET_EMULATED_CPUID: {
3447 struct kvm_cpuid2 __user *cpuid_arg = argp;
3448 struct kvm_cpuid2 cpuid;
3449
3450 r = -EFAULT;
3451 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3452 goto out;
3453
3454 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3455 ioctl);
3456 if (r)
3457 goto out;
3458
3459 r = -EFAULT;
3460 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3461 goto out;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3466 r = -EFAULT;
3467 if (copy_to_user(argp, &kvm_mce_cap_supported,
3468 sizeof(kvm_mce_cap_supported)))
3469 goto out;
3470 r = 0;
3471 break;
3472 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3473 struct kvm_msr_list __user *user_msr_list = argp;
3474 struct kvm_msr_list msr_list;
3475 unsigned int n;
3476
3477 r = -EFAULT;
3478 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3479 goto out;
3480 n = msr_list.nmsrs;
3481 msr_list.nmsrs = num_msr_based_features;
3482 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3483 goto out;
3484 r = -E2BIG;
3485 if (n < msr_list.nmsrs)
3486 goto out;
3487 r = -EFAULT;
3488 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3489 num_msr_based_features * sizeof(u32)))
3490 goto out;
3491 r = 0;
3492 break;
3493 }
3494 case KVM_GET_MSRS:
3495 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3496 break;
3497 }
3498 default:
3499 r = -EINVAL;
3500 }
3501 out:
3502 return r;
3503 }
3504
3505 static void wbinvd_ipi(void *garbage)
3506 {
3507 wbinvd();
3508 }
3509
3510 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3511 {
3512 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3513 }
3514
3515 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3516 {
3517 /* Address WBINVD may be executed by guest */
3518 if (need_emulate_wbinvd(vcpu)) {
3519 if (kvm_x86_ops->has_wbinvd_exit())
3520 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3521 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3522 smp_call_function_single(vcpu->cpu,
3523 wbinvd_ipi, NULL, 1);
3524 }
3525
3526 kvm_x86_ops->vcpu_load(vcpu, cpu);
3527
3528 /* Apply any externally detected TSC adjustments (due to suspend) */
3529 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3530 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3531 vcpu->arch.tsc_offset_adjustment = 0;
3532 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3533 }
3534
3535 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3536 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3537 rdtsc() - vcpu->arch.last_host_tsc;
3538 if (tsc_delta < 0)
3539 mark_tsc_unstable("KVM discovered backwards TSC");
3540
3541 if (kvm_check_tsc_unstable()) {
3542 u64 offset = kvm_compute_tsc_offset(vcpu,
3543 vcpu->arch.last_guest_tsc);
3544 kvm_vcpu_write_tsc_offset(vcpu, offset);
3545 vcpu->arch.tsc_catchup = 1;
3546 }
3547
3548 if (kvm_lapic_hv_timer_in_use(vcpu))
3549 kvm_lapic_restart_hv_timer(vcpu);
3550
3551 /*
3552 * On a host with synchronized TSC, there is no need to update
3553 * kvmclock on vcpu->cpu migration
3554 */
3555 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3556 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3557 if (vcpu->cpu != cpu)
3558 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3559 vcpu->cpu = cpu;
3560 }
3561
3562 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3563 }
3564
3565 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3566 {
3567 struct kvm_host_map map;
3568 struct kvm_steal_time *st;
3569
3570 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3571 return;
3572
3573 if (vcpu->arch.st.preempted)
3574 return;
3575
3576 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3577 &vcpu->arch.st.cache, true))
3578 return;
3579
3580 st = map.hva +
3581 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3582
3583 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3584
3585 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3586 }
3587
3588 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3589 {
3590 int idx;
3591
3592 if (vcpu->preempted)
3593 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3594
3595 /*
3596 * Disable page faults because we're in atomic context here.
3597 * kvm_write_guest_offset_cached() would call might_fault()
3598 * that relies on pagefault_disable() to tell if there's a
3599 * bug. NOTE: the write to guest memory may not go through if
3600 * during postcopy live migration or if there's heavy guest
3601 * paging.
3602 */
3603 pagefault_disable();
3604 /*
3605 * kvm_memslots() will be called by
3606 * kvm_write_guest_offset_cached() so take the srcu lock.
3607 */
3608 idx = srcu_read_lock(&vcpu->kvm->srcu);
3609 kvm_steal_time_set_preempted(vcpu);
3610 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3611 pagefault_enable();
3612 kvm_x86_ops->vcpu_put(vcpu);
3613 vcpu->arch.last_host_tsc = rdtsc();
3614 /*
3615 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3616 * on every vmexit, but if not, we might have a stale dr6 from the
3617 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3618 */
3619 set_debugreg(0, 6);
3620 }
3621
3622 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3623 struct kvm_lapic_state *s)
3624 {
3625 if (vcpu->arch.apicv_active)
3626 kvm_x86_ops->sync_pir_to_irr(vcpu);
3627
3628 return kvm_apic_get_state(vcpu, s);
3629 }
3630
3631 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3632 struct kvm_lapic_state *s)
3633 {
3634 int r;
3635
3636 r = kvm_apic_set_state(vcpu, s);
3637 if (r)
3638 return r;
3639 update_cr8_intercept(vcpu);
3640
3641 return 0;
3642 }
3643
3644 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3645 {
3646 return (!lapic_in_kernel(vcpu) ||
3647 kvm_apic_accept_pic_intr(vcpu));
3648 }
3649
3650 /*
3651 * if userspace requested an interrupt window, check that the
3652 * interrupt window is open.
3653 *
3654 * No need to exit to userspace if we already have an interrupt queued.
3655 */
3656 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3657 {
3658 return kvm_arch_interrupt_allowed(vcpu) &&
3659 !kvm_cpu_has_interrupt(vcpu) &&
3660 !kvm_event_needs_reinjection(vcpu) &&
3661 kvm_cpu_accept_dm_intr(vcpu);
3662 }
3663
3664 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3665 struct kvm_interrupt *irq)
3666 {
3667 if (irq->irq >= KVM_NR_INTERRUPTS)
3668 return -EINVAL;
3669
3670 if (!irqchip_in_kernel(vcpu->kvm)) {
3671 kvm_queue_interrupt(vcpu, irq->irq, false);
3672 kvm_make_request(KVM_REQ_EVENT, vcpu);
3673 return 0;
3674 }
3675
3676 /*
3677 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3678 * fail for in-kernel 8259.
3679 */
3680 if (pic_in_kernel(vcpu->kvm))
3681 return -ENXIO;
3682
3683 if (vcpu->arch.pending_external_vector != -1)
3684 return -EEXIST;
3685
3686 vcpu->arch.pending_external_vector = irq->irq;
3687 kvm_make_request(KVM_REQ_EVENT, vcpu);
3688 return 0;
3689 }
3690
3691 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3692 {
3693 kvm_inject_nmi(vcpu);
3694
3695 return 0;
3696 }
3697
3698 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3699 {
3700 kvm_make_request(KVM_REQ_SMI, vcpu);
3701
3702 return 0;
3703 }
3704
3705 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3706 struct kvm_tpr_access_ctl *tac)
3707 {
3708 if (tac->flags)
3709 return -EINVAL;
3710 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3711 return 0;
3712 }
3713
3714 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3715 u64 mcg_cap)
3716 {
3717 int r;
3718 unsigned bank_num = mcg_cap & 0xff, bank;
3719
3720 r = -EINVAL;
3721 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3722 goto out;
3723 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3724 goto out;
3725 r = 0;
3726 vcpu->arch.mcg_cap = mcg_cap;
3727 /* Init IA32_MCG_CTL to all 1s */
3728 if (mcg_cap & MCG_CTL_P)
3729 vcpu->arch.mcg_ctl = ~(u64)0;
3730 /* Init IA32_MCi_CTL to all 1s */
3731 for (bank = 0; bank < bank_num; bank++)
3732 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3733
3734 kvm_x86_ops->setup_mce(vcpu);
3735 out:
3736 return r;
3737 }
3738
3739 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3740 struct kvm_x86_mce *mce)
3741 {
3742 u64 mcg_cap = vcpu->arch.mcg_cap;
3743 unsigned bank_num = mcg_cap & 0xff;
3744 u64 *banks = vcpu->arch.mce_banks;
3745
3746 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3747 return -EINVAL;
3748 /*
3749 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3750 * reporting is disabled
3751 */
3752 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3753 vcpu->arch.mcg_ctl != ~(u64)0)
3754 return 0;
3755 banks += 4 * mce->bank;
3756 /*
3757 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3758 * reporting is disabled for the bank
3759 */
3760 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3761 return 0;
3762 if (mce->status & MCI_STATUS_UC) {
3763 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3764 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3765 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3766 return 0;
3767 }
3768 if (banks[1] & MCI_STATUS_VAL)
3769 mce->status |= MCI_STATUS_OVER;
3770 banks[2] = mce->addr;
3771 banks[3] = mce->misc;
3772 vcpu->arch.mcg_status = mce->mcg_status;
3773 banks[1] = mce->status;
3774 kvm_queue_exception(vcpu, MC_VECTOR);
3775 } else if (!(banks[1] & MCI_STATUS_VAL)
3776 || !(banks[1] & MCI_STATUS_UC)) {
3777 if (banks[1] & MCI_STATUS_VAL)
3778 mce->status |= MCI_STATUS_OVER;
3779 banks[2] = mce->addr;
3780 banks[3] = mce->misc;
3781 banks[1] = mce->status;
3782 } else
3783 banks[1] |= MCI_STATUS_OVER;
3784 return 0;
3785 }
3786
3787 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3788 struct kvm_vcpu_events *events)
3789 {
3790 process_nmi(vcpu);
3791
3792 /*
3793 * The API doesn't provide the instruction length for software
3794 * exceptions, so don't report them. As long as the guest RIP
3795 * isn't advanced, we should expect to encounter the exception
3796 * again.
3797 */
3798 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3799 events->exception.injected = 0;
3800 events->exception.pending = 0;
3801 } else {
3802 events->exception.injected = vcpu->arch.exception.injected;
3803 events->exception.pending = vcpu->arch.exception.pending;
3804 /*
3805 * For ABI compatibility, deliberately conflate
3806 * pending and injected exceptions when
3807 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3808 */
3809 if (!vcpu->kvm->arch.exception_payload_enabled)
3810 events->exception.injected |=
3811 vcpu->arch.exception.pending;
3812 }
3813 events->exception.nr = vcpu->arch.exception.nr;
3814 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3815 events->exception.error_code = vcpu->arch.exception.error_code;
3816 events->exception_has_payload = vcpu->arch.exception.has_payload;
3817 events->exception_payload = vcpu->arch.exception.payload;
3818
3819 events->interrupt.injected =
3820 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3821 events->interrupt.nr = vcpu->arch.interrupt.nr;
3822 events->interrupt.soft = 0;
3823 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3824
3825 events->nmi.injected = vcpu->arch.nmi_injected;
3826 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3827 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3828 events->nmi.pad = 0;
3829
3830 events->sipi_vector = 0; /* never valid when reporting to user space */
3831
3832 events->smi.smm = is_smm(vcpu);
3833 events->smi.pending = vcpu->arch.smi_pending;
3834 events->smi.smm_inside_nmi =
3835 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3836 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3837
3838 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3839 | KVM_VCPUEVENT_VALID_SHADOW
3840 | KVM_VCPUEVENT_VALID_SMM);
3841 if (vcpu->kvm->arch.exception_payload_enabled)
3842 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3843
3844 memset(&events->reserved, 0, sizeof(events->reserved));
3845 }
3846
3847 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3848
3849 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3850 struct kvm_vcpu_events *events)
3851 {
3852 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3853 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3854 | KVM_VCPUEVENT_VALID_SHADOW
3855 | KVM_VCPUEVENT_VALID_SMM
3856 | KVM_VCPUEVENT_VALID_PAYLOAD))
3857 return -EINVAL;
3858
3859 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3860 if (!vcpu->kvm->arch.exception_payload_enabled)
3861 return -EINVAL;
3862 if (events->exception.pending)
3863 events->exception.injected = 0;
3864 else
3865 events->exception_has_payload = 0;
3866 } else {
3867 events->exception.pending = 0;
3868 events->exception_has_payload = 0;
3869 }
3870
3871 if ((events->exception.injected || events->exception.pending) &&
3872 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3873 return -EINVAL;
3874
3875 /* INITs are latched while in SMM */
3876 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3877 (events->smi.smm || events->smi.pending) &&
3878 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3879 return -EINVAL;
3880
3881 process_nmi(vcpu);
3882 vcpu->arch.exception.injected = events->exception.injected;
3883 vcpu->arch.exception.pending = events->exception.pending;
3884 vcpu->arch.exception.nr = events->exception.nr;
3885 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3886 vcpu->arch.exception.error_code = events->exception.error_code;
3887 vcpu->arch.exception.has_payload = events->exception_has_payload;
3888 vcpu->arch.exception.payload = events->exception_payload;
3889
3890 vcpu->arch.interrupt.injected = events->interrupt.injected;
3891 vcpu->arch.interrupt.nr = events->interrupt.nr;
3892 vcpu->arch.interrupt.soft = events->interrupt.soft;
3893 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3894 kvm_x86_ops->set_interrupt_shadow(vcpu,
3895 events->interrupt.shadow);
3896
3897 vcpu->arch.nmi_injected = events->nmi.injected;
3898 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3899 vcpu->arch.nmi_pending = events->nmi.pending;
3900 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3901
3902 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3903 lapic_in_kernel(vcpu))
3904 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3905
3906 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3907 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3908 if (events->smi.smm)
3909 vcpu->arch.hflags |= HF_SMM_MASK;
3910 else
3911 vcpu->arch.hflags &= ~HF_SMM_MASK;
3912 kvm_smm_changed(vcpu);
3913 }
3914
3915 vcpu->arch.smi_pending = events->smi.pending;
3916
3917 if (events->smi.smm) {
3918 if (events->smi.smm_inside_nmi)
3919 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3920 else
3921 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3922 }
3923
3924 if (lapic_in_kernel(vcpu)) {
3925 if (events->smi.latched_init)
3926 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3927 else
3928 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3929 }
3930 }
3931
3932 kvm_make_request(KVM_REQ_EVENT, vcpu);
3933
3934 return 0;
3935 }
3936
3937 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3938 struct kvm_debugregs *dbgregs)
3939 {
3940 unsigned long val;
3941
3942 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3943 kvm_get_dr(vcpu, 6, &val);
3944 dbgregs->dr6 = val;
3945 dbgregs->dr7 = vcpu->arch.dr7;
3946 dbgregs->flags = 0;
3947 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3948 }
3949
3950 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3951 struct kvm_debugregs *dbgregs)
3952 {
3953 if (dbgregs->flags)
3954 return -EINVAL;
3955
3956 if (dbgregs->dr6 & ~0xffffffffull)
3957 return -EINVAL;
3958 if (dbgregs->dr7 & ~0xffffffffull)
3959 return -EINVAL;
3960
3961 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3962 kvm_update_dr0123(vcpu);
3963 vcpu->arch.dr6 = dbgregs->dr6;
3964 kvm_update_dr6(vcpu);
3965 vcpu->arch.dr7 = dbgregs->dr7;
3966 kvm_update_dr7(vcpu);
3967
3968 return 0;
3969 }
3970
3971 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3972
3973 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3974 {
3975 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3976 u64 xstate_bv = xsave->header.xfeatures;
3977 u64 valid;
3978
3979 /*
3980 * Copy legacy XSAVE area, to avoid complications with CPUID
3981 * leaves 0 and 1 in the loop below.
3982 */
3983 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3984
3985 /* Set XSTATE_BV */
3986 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3987 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3988
3989 /*
3990 * Copy each region from the possibly compacted offset to the
3991 * non-compacted offset.
3992 */
3993 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3994 while (valid) {
3995 u64 xfeature_mask = valid & -valid;
3996 int xfeature_nr = fls64(xfeature_mask) - 1;
3997 void *src = get_xsave_addr(xsave, xfeature_nr);
3998
3999 if (src) {
4000 u32 size, offset, ecx, edx;
4001 cpuid_count(XSTATE_CPUID, xfeature_nr,
4002 &size, &offset, &ecx, &edx);
4003 if (xfeature_nr == XFEATURE_PKRU)
4004 memcpy(dest + offset, &vcpu->arch.pkru,
4005 sizeof(vcpu->arch.pkru));
4006 else
4007 memcpy(dest + offset, src, size);
4008
4009 }
4010
4011 valid -= xfeature_mask;
4012 }
4013 }
4014
4015 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4016 {
4017 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4018 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4019 u64 valid;
4020
4021 /*
4022 * Copy legacy XSAVE area, to avoid complications with CPUID
4023 * leaves 0 and 1 in the loop below.
4024 */
4025 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4026
4027 /* Set XSTATE_BV and possibly XCOMP_BV. */
4028 xsave->header.xfeatures = xstate_bv;
4029 if (boot_cpu_has(X86_FEATURE_XSAVES))
4030 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4031
4032 /*
4033 * Copy each region from the non-compacted offset to the
4034 * possibly compacted offset.
4035 */
4036 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4037 while (valid) {
4038 u64 xfeature_mask = valid & -valid;
4039 int xfeature_nr = fls64(xfeature_mask) - 1;
4040 void *dest = get_xsave_addr(xsave, xfeature_nr);
4041
4042 if (dest) {
4043 u32 size, offset, ecx, edx;
4044 cpuid_count(XSTATE_CPUID, xfeature_nr,
4045 &size, &offset, &ecx, &edx);
4046 if (xfeature_nr == XFEATURE_PKRU)
4047 memcpy(&vcpu->arch.pkru, src + offset,
4048 sizeof(vcpu->arch.pkru));
4049 else
4050 memcpy(dest, src + offset, size);
4051 }
4052
4053 valid -= xfeature_mask;
4054 }
4055 }
4056
4057 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4058 struct kvm_xsave *guest_xsave)
4059 {
4060 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4061 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4062 fill_xsave((u8 *) guest_xsave->region, vcpu);
4063 } else {
4064 memcpy(guest_xsave->region,
4065 &vcpu->arch.guest_fpu->state.fxsave,
4066 sizeof(struct fxregs_state));
4067 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4068 XFEATURE_MASK_FPSSE;
4069 }
4070 }
4071
4072 #define XSAVE_MXCSR_OFFSET 24
4073
4074 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4075 struct kvm_xsave *guest_xsave)
4076 {
4077 u64 xstate_bv =
4078 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4079 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4080
4081 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4082 /*
4083 * Here we allow setting states that are not present in
4084 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4085 * with old userspace.
4086 */
4087 if (xstate_bv & ~kvm_supported_xcr0() ||
4088 mxcsr & ~mxcsr_feature_mask)
4089 return -EINVAL;
4090 load_xsave(vcpu, (u8 *)guest_xsave->region);
4091 } else {
4092 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4093 mxcsr & ~mxcsr_feature_mask)
4094 return -EINVAL;
4095 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4096 guest_xsave->region, sizeof(struct fxregs_state));
4097 }
4098 return 0;
4099 }
4100
4101 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4102 struct kvm_xcrs *guest_xcrs)
4103 {
4104 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4105 guest_xcrs->nr_xcrs = 0;
4106 return;
4107 }
4108
4109 guest_xcrs->nr_xcrs = 1;
4110 guest_xcrs->flags = 0;
4111 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4112 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4113 }
4114
4115 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4116 struct kvm_xcrs *guest_xcrs)
4117 {
4118 int i, r = 0;
4119
4120 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4121 return -EINVAL;
4122
4123 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4124 return -EINVAL;
4125
4126 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4127 /* Only support XCR0 currently */
4128 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4129 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4130 guest_xcrs->xcrs[i].value);
4131 break;
4132 }
4133 if (r)
4134 r = -EINVAL;
4135 return r;
4136 }
4137
4138 /*
4139 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4140 * stopped by the hypervisor. This function will be called from the host only.
4141 * EINVAL is returned when the host attempts to set the flag for a guest that
4142 * does not support pv clocks.
4143 */
4144 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4145 {
4146 if (!vcpu->arch.pv_time_enabled)
4147 return -EINVAL;
4148 vcpu->arch.pvclock_set_guest_stopped_request = true;
4149 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4150 return 0;
4151 }
4152
4153 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4154 struct kvm_enable_cap *cap)
4155 {
4156 int r;
4157 uint16_t vmcs_version;
4158 void __user *user_ptr;
4159
4160 if (cap->flags)
4161 return -EINVAL;
4162
4163 switch (cap->cap) {
4164 case KVM_CAP_HYPERV_SYNIC2:
4165 if (cap->args[0])
4166 return -EINVAL;
4167 /* fall through */
4168
4169 case KVM_CAP_HYPERV_SYNIC:
4170 if (!irqchip_in_kernel(vcpu->kvm))
4171 return -EINVAL;
4172 return kvm_hv_activate_synic(vcpu, cap->cap ==
4173 KVM_CAP_HYPERV_SYNIC2);
4174 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4175 if (!kvm_x86_ops->nested_enable_evmcs)
4176 return -ENOTTY;
4177 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4178 if (!r) {
4179 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4180 if (copy_to_user(user_ptr, &vmcs_version,
4181 sizeof(vmcs_version)))
4182 r = -EFAULT;
4183 }
4184 return r;
4185 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4186 if (!kvm_x86_ops->enable_direct_tlbflush)
4187 return -ENOTTY;
4188
4189 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4190
4191 default:
4192 return -EINVAL;
4193 }
4194 }
4195
4196 long kvm_arch_vcpu_ioctl(struct file *filp,
4197 unsigned int ioctl, unsigned long arg)
4198 {
4199 struct kvm_vcpu *vcpu = filp->private_data;
4200 void __user *argp = (void __user *)arg;
4201 int r;
4202 union {
4203 struct kvm_lapic_state *lapic;
4204 struct kvm_xsave *xsave;
4205 struct kvm_xcrs *xcrs;
4206 void *buffer;
4207 } u;
4208
4209 vcpu_load(vcpu);
4210
4211 u.buffer = NULL;
4212 switch (ioctl) {
4213 case KVM_GET_LAPIC: {
4214 r = -EINVAL;
4215 if (!lapic_in_kernel(vcpu))
4216 goto out;
4217 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4218 GFP_KERNEL_ACCOUNT);
4219
4220 r = -ENOMEM;
4221 if (!u.lapic)
4222 goto out;
4223 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4224 if (r)
4225 goto out;
4226 r = -EFAULT;
4227 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4228 goto out;
4229 r = 0;
4230 break;
4231 }
4232 case KVM_SET_LAPIC: {
4233 r = -EINVAL;
4234 if (!lapic_in_kernel(vcpu))
4235 goto out;
4236 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4237 if (IS_ERR(u.lapic)) {
4238 r = PTR_ERR(u.lapic);
4239 goto out_nofree;
4240 }
4241
4242 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4243 break;
4244 }
4245 case KVM_INTERRUPT: {
4246 struct kvm_interrupt irq;
4247
4248 r = -EFAULT;
4249 if (copy_from_user(&irq, argp, sizeof(irq)))
4250 goto out;
4251 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4252 break;
4253 }
4254 case KVM_NMI: {
4255 r = kvm_vcpu_ioctl_nmi(vcpu);
4256 break;
4257 }
4258 case KVM_SMI: {
4259 r = kvm_vcpu_ioctl_smi(vcpu);
4260 break;
4261 }
4262 case KVM_SET_CPUID: {
4263 struct kvm_cpuid __user *cpuid_arg = argp;
4264 struct kvm_cpuid cpuid;
4265
4266 r = -EFAULT;
4267 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4268 goto out;
4269 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4270 break;
4271 }
4272 case KVM_SET_CPUID2: {
4273 struct kvm_cpuid2 __user *cpuid_arg = argp;
4274 struct kvm_cpuid2 cpuid;
4275
4276 r = -EFAULT;
4277 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4278 goto out;
4279 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4280 cpuid_arg->entries);
4281 break;
4282 }
4283 case KVM_GET_CPUID2: {
4284 struct kvm_cpuid2 __user *cpuid_arg = argp;
4285 struct kvm_cpuid2 cpuid;
4286
4287 r = -EFAULT;
4288 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4289 goto out;
4290 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4291 cpuid_arg->entries);
4292 if (r)
4293 goto out;
4294 r = -EFAULT;
4295 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4296 goto out;
4297 r = 0;
4298 break;
4299 }
4300 case KVM_GET_MSRS: {
4301 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4302 r = msr_io(vcpu, argp, do_get_msr, 1);
4303 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4304 break;
4305 }
4306 case KVM_SET_MSRS: {
4307 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4308 r = msr_io(vcpu, argp, do_set_msr, 0);
4309 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4310 break;
4311 }
4312 case KVM_TPR_ACCESS_REPORTING: {
4313 struct kvm_tpr_access_ctl tac;
4314
4315 r = -EFAULT;
4316 if (copy_from_user(&tac, argp, sizeof(tac)))
4317 goto out;
4318 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4319 if (r)
4320 goto out;
4321 r = -EFAULT;
4322 if (copy_to_user(argp, &tac, sizeof(tac)))
4323 goto out;
4324 r = 0;
4325 break;
4326 };
4327 case KVM_SET_VAPIC_ADDR: {
4328 struct kvm_vapic_addr va;
4329 int idx;
4330
4331 r = -EINVAL;
4332 if (!lapic_in_kernel(vcpu))
4333 goto out;
4334 r = -EFAULT;
4335 if (copy_from_user(&va, argp, sizeof(va)))
4336 goto out;
4337 idx = srcu_read_lock(&vcpu->kvm->srcu);
4338 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4339 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4340 break;
4341 }
4342 case KVM_X86_SETUP_MCE: {
4343 u64 mcg_cap;
4344
4345 r = -EFAULT;
4346 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4347 goto out;
4348 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4349 break;
4350 }
4351 case KVM_X86_SET_MCE: {
4352 struct kvm_x86_mce mce;
4353
4354 r = -EFAULT;
4355 if (copy_from_user(&mce, argp, sizeof(mce)))
4356 goto out;
4357 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4358 break;
4359 }
4360 case KVM_GET_VCPU_EVENTS: {
4361 struct kvm_vcpu_events events;
4362
4363 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4364
4365 r = -EFAULT;
4366 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4367 break;
4368 r = 0;
4369 break;
4370 }
4371 case KVM_SET_VCPU_EVENTS: {
4372 struct kvm_vcpu_events events;
4373
4374 r = -EFAULT;
4375 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4376 break;
4377
4378 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4379 break;
4380 }
4381 case KVM_GET_DEBUGREGS: {
4382 struct kvm_debugregs dbgregs;
4383
4384 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4385
4386 r = -EFAULT;
4387 if (copy_to_user(argp, &dbgregs,
4388 sizeof(struct kvm_debugregs)))
4389 break;
4390 r = 0;
4391 break;
4392 }
4393 case KVM_SET_DEBUGREGS: {
4394 struct kvm_debugregs dbgregs;
4395
4396 r = -EFAULT;
4397 if (copy_from_user(&dbgregs, argp,
4398 sizeof(struct kvm_debugregs)))
4399 break;
4400
4401 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4402 break;
4403 }
4404 case KVM_GET_XSAVE: {
4405 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4406 r = -ENOMEM;
4407 if (!u.xsave)
4408 break;
4409
4410 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4411
4412 r = -EFAULT;
4413 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4414 break;
4415 r = 0;
4416 break;
4417 }
4418 case KVM_SET_XSAVE: {
4419 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4420 if (IS_ERR(u.xsave)) {
4421 r = PTR_ERR(u.xsave);
4422 goto out_nofree;
4423 }
4424
4425 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4426 break;
4427 }
4428 case KVM_GET_XCRS: {
4429 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4430 r = -ENOMEM;
4431 if (!u.xcrs)
4432 break;
4433
4434 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4435
4436 r = -EFAULT;
4437 if (copy_to_user(argp, u.xcrs,
4438 sizeof(struct kvm_xcrs)))
4439 break;
4440 r = 0;
4441 break;
4442 }
4443 case KVM_SET_XCRS: {
4444 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4445 if (IS_ERR(u.xcrs)) {
4446 r = PTR_ERR(u.xcrs);
4447 goto out_nofree;
4448 }
4449
4450 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4451 break;
4452 }
4453 case KVM_SET_TSC_KHZ: {
4454 u32 user_tsc_khz;
4455
4456 r = -EINVAL;
4457 user_tsc_khz = (u32)arg;
4458
4459 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4460 goto out;
4461
4462 if (user_tsc_khz == 0)
4463 user_tsc_khz = tsc_khz;
4464
4465 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4466 r = 0;
4467
4468 goto out;
4469 }
4470 case KVM_GET_TSC_KHZ: {
4471 r = vcpu->arch.virtual_tsc_khz;
4472 goto out;
4473 }
4474 case KVM_KVMCLOCK_CTRL: {
4475 r = kvm_set_guest_paused(vcpu);
4476 goto out;
4477 }
4478 case KVM_ENABLE_CAP: {
4479 struct kvm_enable_cap cap;
4480
4481 r = -EFAULT;
4482 if (copy_from_user(&cap, argp, sizeof(cap)))
4483 goto out;
4484 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4485 break;
4486 }
4487 case KVM_GET_NESTED_STATE: {
4488 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4489 u32 user_data_size;
4490
4491 r = -EINVAL;
4492 if (!kvm_x86_ops->get_nested_state)
4493 break;
4494
4495 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4496 r = -EFAULT;
4497 if (get_user(user_data_size, &user_kvm_nested_state->size))
4498 break;
4499
4500 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4501 user_data_size);
4502 if (r < 0)
4503 break;
4504
4505 if (r > user_data_size) {
4506 if (put_user(r, &user_kvm_nested_state->size))
4507 r = -EFAULT;
4508 else
4509 r = -E2BIG;
4510 break;
4511 }
4512
4513 r = 0;
4514 break;
4515 }
4516 case KVM_SET_NESTED_STATE: {
4517 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4518 struct kvm_nested_state kvm_state;
4519 int idx;
4520
4521 r = -EINVAL;
4522 if (!kvm_x86_ops->set_nested_state)
4523 break;
4524
4525 r = -EFAULT;
4526 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4527 break;
4528
4529 r = -EINVAL;
4530 if (kvm_state.size < sizeof(kvm_state))
4531 break;
4532
4533 if (kvm_state.flags &
4534 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4535 | KVM_STATE_NESTED_EVMCS))
4536 break;
4537
4538 /* nested_run_pending implies guest_mode. */
4539 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4540 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4541 break;
4542
4543 idx = srcu_read_lock(&vcpu->kvm->srcu);
4544 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4545 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4546 break;
4547 }
4548 case KVM_GET_SUPPORTED_HV_CPUID: {
4549 struct kvm_cpuid2 __user *cpuid_arg = argp;
4550 struct kvm_cpuid2 cpuid;
4551
4552 r = -EFAULT;
4553 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4554 goto out;
4555
4556 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4557 cpuid_arg->entries);
4558 if (r)
4559 goto out;
4560
4561 r = -EFAULT;
4562 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4563 goto out;
4564 r = 0;
4565 break;
4566 }
4567 default:
4568 r = -EINVAL;
4569 }
4570 out:
4571 kfree(u.buffer);
4572 out_nofree:
4573 vcpu_put(vcpu);
4574 return r;
4575 }
4576
4577 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4578 {
4579 return VM_FAULT_SIGBUS;
4580 }
4581
4582 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4583 {
4584 int ret;
4585
4586 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4587 return -EINVAL;
4588 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4589 return ret;
4590 }
4591
4592 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4593 u64 ident_addr)
4594 {
4595 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4596 }
4597
4598 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4599 unsigned long kvm_nr_mmu_pages)
4600 {
4601 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4602 return -EINVAL;
4603
4604 mutex_lock(&kvm->slots_lock);
4605
4606 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4607 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4608
4609 mutex_unlock(&kvm->slots_lock);
4610 return 0;
4611 }
4612
4613 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4614 {
4615 return kvm->arch.n_max_mmu_pages;
4616 }
4617
4618 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4619 {
4620 struct kvm_pic *pic = kvm->arch.vpic;
4621 int r;
4622
4623 r = 0;
4624 switch (chip->chip_id) {
4625 case KVM_IRQCHIP_PIC_MASTER:
4626 memcpy(&chip->chip.pic, &pic->pics[0],
4627 sizeof(struct kvm_pic_state));
4628 break;
4629 case KVM_IRQCHIP_PIC_SLAVE:
4630 memcpy(&chip->chip.pic, &pic->pics[1],
4631 sizeof(struct kvm_pic_state));
4632 break;
4633 case KVM_IRQCHIP_IOAPIC:
4634 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4635 break;
4636 default:
4637 r = -EINVAL;
4638 break;
4639 }
4640 return r;
4641 }
4642
4643 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4644 {
4645 struct kvm_pic *pic = kvm->arch.vpic;
4646 int r;
4647
4648 r = 0;
4649 switch (chip->chip_id) {
4650 case KVM_IRQCHIP_PIC_MASTER:
4651 spin_lock(&pic->lock);
4652 memcpy(&pic->pics[0], &chip->chip.pic,
4653 sizeof(struct kvm_pic_state));
4654 spin_unlock(&pic->lock);
4655 break;
4656 case KVM_IRQCHIP_PIC_SLAVE:
4657 spin_lock(&pic->lock);
4658 memcpy(&pic->pics[1], &chip->chip.pic,
4659 sizeof(struct kvm_pic_state));
4660 spin_unlock(&pic->lock);
4661 break;
4662 case KVM_IRQCHIP_IOAPIC:
4663 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4664 break;
4665 default:
4666 r = -EINVAL;
4667 break;
4668 }
4669 kvm_pic_update_irq(pic);
4670 return r;
4671 }
4672
4673 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4674 {
4675 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4676
4677 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4678
4679 mutex_lock(&kps->lock);
4680 memcpy(ps, &kps->channels, sizeof(*ps));
4681 mutex_unlock(&kps->lock);
4682 return 0;
4683 }
4684
4685 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4686 {
4687 int i;
4688 struct kvm_pit *pit = kvm->arch.vpit;
4689
4690 mutex_lock(&pit->pit_state.lock);
4691 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4692 for (i = 0; i < 3; i++)
4693 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4694 mutex_unlock(&pit->pit_state.lock);
4695 return 0;
4696 }
4697
4698 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4699 {
4700 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4701 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4702 sizeof(ps->channels));
4703 ps->flags = kvm->arch.vpit->pit_state.flags;
4704 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4705 memset(&ps->reserved, 0, sizeof(ps->reserved));
4706 return 0;
4707 }
4708
4709 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4710 {
4711 int start = 0;
4712 int i;
4713 u32 prev_legacy, cur_legacy;
4714 struct kvm_pit *pit = kvm->arch.vpit;
4715
4716 mutex_lock(&pit->pit_state.lock);
4717 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4718 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4719 if (!prev_legacy && cur_legacy)
4720 start = 1;
4721 memcpy(&pit->pit_state.channels, &ps->channels,
4722 sizeof(pit->pit_state.channels));
4723 pit->pit_state.flags = ps->flags;
4724 for (i = 0; i < 3; i++)
4725 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4726 start && i == 0);
4727 mutex_unlock(&pit->pit_state.lock);
4728 return 0;
4729 }
4730
4731 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4732 struct kvm_reinject_control *control)
4733 {
4734 struct kvm_pit *pit = kvm->arch.vpit;
4735
4736 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4737 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4738 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4739 */
4740 mutex_lock(&pit->pit_state.lock);
4741 kvm_pit_set_reinject(pit, control->pit_reinject);
4742 mutex_unlock(&pit->pit_state.lock);
4743
4744 return 0;
4745 }
4746
4747 /**
4748 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4749 * @kvm: kvm instance
4750 * @log: slot id and address to which we copy the log
4751 *
4752 * Steps 1-4 below provide general overview of dirty page logging. See
4753 * kvm_get_dirty_log_protect() function description for additional details.
4754 *
4755 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4756 * always flush the TLB (step 4) even if previous step failed and the dirty
4757 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4758 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4759 * writes will be marked dirty for next log read.
4760 *
4761 * 1. Take a snapshot of the bit and clear it if needed.
4762 * 2. Write protect the corresponding page.
4763 * 3. Copy the snapshot to the userspace.
4764 * 4. Flush TLB's if needed.
4765 */
4766 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4767 {
4768 bool flush = false;
4769 int r;
4770
4771 mutex_lock(&kvm->slots_lock);
4772
4773 /*
4774 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4775 */
4776 if (kvm_x86_ops->flush_log_dirty)
4777 kvm_x86_ops->flush_log_dirty(kvm);
4778
4779 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4780
4781 /*
4782 * All the TLBs can be flushed out of mmu lock, see the comments in
4783 * kvm_mmu_slot_remove_write_access().
4784 */
4785 lockdep_assert_held(&kvm->slots_lock);
4786 if (flush)
4787 kvm_flush_remote_tlbs(kvm);
4788
4789 mutex_unlock(&kvm->slots_lock);
4790 return r;
4791 }
4792
4793 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4794 {
4795 bool flush = false;
4796 int r;
4797
4798 mutex_lock(&kvm->slots_lock);
4799
4800 /*
4801 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4802 */
4803 if (kvm_x86_ops->flush_log_dirty)
4804 kvm_x86_ops->flush_log_dirty(kvm);
4805
4806 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4807
4808 /*
4809 * All the TLBs can be flushed out of mmu lock, see the comments in
4810 * kvm_mmu_slot_remove_write_access().
4811 */
4812 lockdep_assert_held(&kvm->slots_lock);
4813 if (flush)
4814 kvm_flush_remote_tlbs(kvm);
4815
4816 mutex_unlock(&kvm->slots_lock);
4817 return r;
4818 }
4819
4820 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4821 bool line_status)
4822 {
4823 if (!irqchip_in_kernel(kvm))
4824 return -ENXIO;
4825
4826 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4827 irq_event->irq, irq_event->level,
4828 line_status);
4829 return 0;
4830 }
4831
4832 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4833 struct kvm_enable_cap *cap)
4834 {
4835 int r;
4836
4837 if (cap->flags)
4838 return -EINVAL;
4839
4840 switch (cap->cap) {
4841 case KVM_CAP_DISABLE_QUIRKS:
4842 kvm->arch.disabled_quirks = cap->args[0];
4843 r = 0;
4844 break;
4845 case KVM_CAP_SPLIT_IRQCHIP: {
4846 mutex_lock(&kvm->lock);
4847 r = -EINVAL;
4848 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4849 goto split_irqchip_unlock;
4850 r = -EEXIST;
4851 if (irqchip_in_kernel(kvm))
4852 goto split_irqchip_unlock;
4853 if (kvm->created_vcpus)
4854 goto split_irqchip_unlock;
4855 r = kvm_setup_empty_irq_routing(kvm);
4856 if (r)
4857 goto split_irqchip_unlock;
4858 /* Pairs with irqchip_in_kernel. */
4859 smp_wmb();
4860 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4861 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4862 r = 0;
4863 split_irqchip_unlock:
4864 mutex_unlock(&kvm->lock);
4865 break;
4866 }
4867 case KVM_CAP_X2APIC_API:
4868 r = -EINVAL;
4869 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4870 break;
4871
4872 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4873 kvm->arch.x2apic_format = true;
4874 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4875 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4876
4877 r = 0;
4878 break;
4879 case KVM_CAP_X86_DISABLE_EXITS:
4880 r = -EINVAL;
4881 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4882 break;
4883
4884 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4885 kvm_can_mwait_in_guest())
4886 kvm->arch.mwait_in_guest = true;
4887 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4888 kvm->arch.hlt_in_guest = true;
4889 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4890 kvm->arch.pause_in_guest = true;
4891 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4892 kvm->arch.cstate_in_guest = true;
4893 r = 0;
4894 break;
4895 case KVM_CAP_MSR_PLATFORM_INFO:
4896 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4897 r = 0;
4898 break;
4899 case KVM_CAP_EXCEPTION_PAYLOAD:
4900 kvm->arch.exception_payload_enabled = cap->args[0];
4901 r = 0;
4902 break;
4903 default:
4904 r = -EINVAL;
4905 break;
4906 }
4907 return r;
4908 }
4909
4910 long kvm_arch_vm_ioctl(struct file *filp,
4911 unsigned int ioctl, unsigned long arg)
4912 {
4913 struct kvm *kvm = filp->private_data;
4914 void __user *argp = (void __user *)arg;
4915 int r = -ENOTTY;
4916 /*
4917 * This union makes it completely explicit to gcc-3.x
4918 * that these two variables' stack usage should be
4919 * combined, not added together.
4920 */
4921 union {
4922 struct kvm_pit_state ps;
4923 struct kvm_pit_state2 ps2;
4924 struct kvm_pit_config pit_config;
4925 } u;
4926
4927 switch (ioctl) {
4928 case KVM_SET_TSS_ADDR:
4929 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4930 break;
4931 case KVM_SET_IDENTITY_MAP_ADDR: {
4932 u64 ident_addr;
4933
4934 mutex_lock(&kvm->lock);
4935 r = -EINVAL;
4936 if (kvm->created_vcpus)
4937 goto set_identity_unlock;
4938 r = -EFAULT;
4939 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4940 goto set_identity_unlock;
4941 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4942 set_identity_unlock:
4943 mutex_unlock(&kvm->lock);
4944 break;
4945 }
4946 case KVM_SET_NR_MMU_PAGES:
4947 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4948 break;
4949 case KVM_GET_NR_MMU_PAGES:
4950 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4951 break;
4952 case KVM_CREATE_IRQCHIP: {
4953 mutex_lock(&kvm->lock);
4954
4955 r = -EEXIST;
4956 if (irqchip_in_kernel(kvm))
4957 goto create_irqchip_unlock;
4958
4959 r = -EINVAL;
4960 if (kvm->created_vcpus)
4961 goto create_irqchip_unlock;
4962
4963 r = kvm_pic_init(kvm);
4964 if (r)
4965 goto create_irqchip_unlock;
4966
4967 r = kvm_ioapic_init(kvm);
4968 if (r) {
4969 kvm_pic_destroy(kvm);
4970 goto create_irqchip_unlock;
4971 }
4972
4973 r = kvm_setup_default_irq_routing(kvm);
4974 if (r) {
4975 kvm_ioapic_destroy(kvm);
4976 kvm_pic_destroy(kvm);
4977 goto create_irqchip_unlock;
4978 }
4979 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4980 smp_wmb();
4981 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4982 create_irqchip_unlock:
4983 mutex_unlock(&kvm->lock);
4984 break;
4985 }
4986 case KVM_CREATE_PIT:
4987 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4988 goto create_pit;
4989 case KVM_CREATE_PIT2:
4990 r = -EFAULT;
4991 if (copy_from_user(&u.pit_config, argp,
4992 sizeof(struct kvm_pit_config)))
4993 goto out;
4994 create_pit:
4995 mutex_lock(&kvm->lock);
4996 r = -EEXIST;
4997 if (kvm->arch.vpit)
4998 goto create_pit_unlock;
4999 r = -ENOMEM;
5000 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5001 if (kvm->arch.vpit)
5002 r = 0;
5003 create_pit_unlock:
5004 mutex_unlock(&kvm->lock);
5005 break;
5006 case KVM_GET_IRQCHIP: {
5007 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5008 struct kvm_irqchip *chip;
5009
5010 chip = memdup_user(argp, sizeof(*chip));
5011 if (IS_ERR(chip)) {
5012 r = PTR_ERR(chip);
5013 goto out;
5014 }
5015
5016 r = -ENXIO;
5017 if (!irqchip_kernel(kvm))
5018 goto get_irqchip_out;
5019 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5020 if (r)
5021 goto get_irqchip_out;
5022 r = -EFAULT;
5023 if (copy_to_user(argp, chip, sizeof(*chip)))
5024 goto get_irqchip_out;
5025 r = 0;
5026 get_irqchip_out:
5027 kfree(chip);
5028 break;
5029 }
5030 case KVM_SET_IRQCHIP: {
5031 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5032 struct kvm_irqchip *chip;
5033
5034 chip = memdup_user(argp, sizeof(*chip));
5035 if (IS_ERR(chip)) {
5036 r = PTR_ERR(chip);
5037 goto out;
5038 }
5039
5040 r = -ENXIO;
5041 if (!irqchip_kernel(kvm))
5042 goto set_irqchip_out;
5043 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5044 set_irqchip_out:
5045 kfree(chip);
5046 break;
5047 }
5048 case KVM_GET_PIT: {
5049 r = -EFAULT;
5050 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5051 goto out;
5052 r = -ENXIO;
5053 if (!kvm->arch.vpit)
5054 goto out;
5055 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5056 if (r)
5057 goto out;
5058 r = -EFAULT;
5059 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5060 goto out;
5061 r = 0;
5062 break;
5063 }
5064 case KVM_SET_PIT: {
5065 r = -EFAULT;
5066 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5067 goto out;
5068 r = -ENXIO;
5069 if (!kvm->arch.vpit)
5070 goto out;
5071 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5072 break;
5073 }
5074 case KVM_GET_PIT2: {
5075 r = -ENXIO;
5076 if (!kvm->arch.vpit)
5077 goto out;
5078 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5079 if (r)
5080 goto out;
5081 r = -EFAULT;
5082 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5083 goto out;
5084 r = 0;
5085 break;
5086 }
5087 case KVM_SET_PIT2: {
5088 r = -EFAULT;
5089 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5090 goto out;
5091 r = -ENXIO;
5092 if (!kvm->arch.vpit)
5093 goto out;
5094 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5095 break;
5096 }
5097 case KVM_REINJECT_CONTROL: {
5098 struct kvm_reinject_control control;
5099 r = -EFAULT;
5100 if (copy_from_user(&control, argp, sizeof(control)))
5101 goto out;
5102 r = -ENXIO;
5103 if (!kvm->arch.vpit)
5104 goto out;
5105 r = kvm_vm_ioctl_reinject(kvm, &control);
5106 break;
5107 }
5108 case KVM_SET_BOOT_CPU_ID:
5109 r = 0;
5110 mutex_lock(&kvm->lock);
5111 if (kvm->created_vcpus)
5112 r = -EBUSY;
5113 else
5114 kvm->arch.bsp_vcpu_id = arg;
5115 mutex_unlock(&kvm->lock);
5116 break;
5117 case KVM_XEN_HVM_CONFIG: {
5118 struct kvm_xen_hvm_config xhc;
5119 r = -EFAULT;
5120 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5121 goto out;
5122 r = -EINVAL;
5123 if (xhc.flags)
5124 goto out;
5125 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5126 r = 0;
5127 break;
5128 }
5129 case KVM_SET_CLOCK: {
5130 struct kvm_clock_data user_ns;
5131 u64 now_ns;
5132
5133 r = -EFAULT;
5134 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5135 goto out;
5136
5137 r = -EINVAL;
5138 if (user_ns.flags)
5139 goto out;
5140
5141 r = 0;
5142 /*
5143 * TODO: userspace has to take care of races with VCPU_RUN, so
5144 * kvm_gen_update_masterclock() can be cut down to locked
5145 * pvclock_update_vm_gtod_copy().
5146 */
5147 kvm_gen_update_masterclock(kvm);
5148 now_ns = get_kvmclock_ns(kvm);
5149 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5150 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5151 break;
5152 }
5153 case KVM_GET_CLOCK: {
5154 struct kvm_clock_data user_ns;
5155 u64 now_ns;
5156
5157 now_ns = get_kvmclock_ns(kvm);
5158 user_ns.clock = now_ns;
5159 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5160 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5161
5162 r = -EFAULT;
5163 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5164 goto out;
5165 r = 0;
5166 break;
5167 }
5168 case KVM_MEMORY_ENCRYPT_OP: {
5169 r = -ENOTTY;
5170 if (kvm_x86_ops->mem_enc_op)
5171 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5172 break;
5173 }
5174 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5175 struct kvm_enc_region region;
5176
5177 r = -EFAULT;
5178 if (copy_from_user(&region, argp, sizeof(region)))
5179 goto out;
5180
5181 r = -ENOTTY;
5182 if (kvm_x86_ops->mem_enc_reg_region)
5183 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5184 break;
5185 }
5186 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5187 struct kvm_enc_region region;
5188
5189 r = -EFAULT;
5190 if (copy_from_user(&region, argp, sizeof(region)))
5191 goto out;
5192
5193 r = -ENOTTY;
5194 if (kvm_x86_ops->mem_enc_unreg_region)
5195 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5196 break;
5197 }
5198 case KVM_HYPERV_EVENTFD: {
5199 struct kvm_hyperv_eventfd hvevfd;
5200
5201 r = -EFAULT;
5202 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5203 goto out;
5204 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5205 break;
5206 }
5207 case KVM_SET_PMU_EVENT_FILTER:
5208 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5209 break;
5210 default:
5211 r = -ENOTTY;
5212 }
5213 out:
5214 return r;
5215 }
5216
5217 static void kvm_init_msr_list(void)
5218 {
5219 struct x86_pmu_capability x86_pmu;
5220 u32 dummy[2];
5221 unsigned i;
5222
5223 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5224 "Please update the fixed PMCs in msrs_to_saved_all[]");
5225
5226 perf_get_x86_pmu_capability(&x86_pmu);
5227
5228 num_msrs_to_save = 0;
5229 num_emulated_msrs = 0;
5230 num_msr_based_features = 0;
5231
5232 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5233 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5234 continue;
5235
5236 /*
5237 * Even MSRs that are valid in the host may not be exposed
5238 * to the guests in some cases.
5239 */
5240 switch (msrs_to_save_all[i]) {
5241 case MSR_IA32_BNDCFGS:
5242 if (!kvm_mpx_supported())
5243 continue;
5244 break;
5245 case MSR_TSC_AUX:
5246 if (!kvm_x86_ops->rdtscp_supported())
5247 continue;
5248 break;
5249 case MSR_IA32_RTIT_CTL:
5250 case MSR_IA32_RTIT_STATUS:
5251 if (!kvm_x86_ops->pt_supported())
5252 continue;
5253 break;
5254 case MSR_IA32_RTIT_CR3_MATCH:
5255 if (!kvm_x86_ops->pt_supported() ||
5256 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5257 continue;
5258 break;
5259 case MSR_IA32_RTIT_OUTPUT_BASE:
5260 case MSR_IA32_RTIT_OUTPUT_MASK:
5261 if (!kvm_x86_ops->pt_supported() ||
5262 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5263 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5264 continue;
5265 break;
5266 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5267 if (!kvm_x86_ops->pt_supported() ||
5268 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5269 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5270 continue;
5271 break;
5272 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5273 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5274 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5275 continue;
5276 break;
5277 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5278 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5279 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5280 continue;
5281 }
5282 default:
5283 break;
5284 }
5285
5286 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5287 }
5288
5289 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5290 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
5291 continue;
5292
5293 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5294 }
5295
5296 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5297 struct kvm_msr_entry msr;
5298
5299 msr.index = msr_based_features_all[i];
5300 if (kvm_get_msr_feature(&msr))
5301 continue;
5302
5303 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5304 }
5305 }
5306
5307 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5308 const void *v)
5309 {
5310 int handled = 0;
5311 int n;
5312
5313 do {
5314 n = min(len, 8);
5315 if (!(lapic_in_kernel(vcpu) &&
5316 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5317 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5318 break;
5319 handled += n;
5320 addr += n;
5321 len -= n;
5322 v += n;
5323 } while (len);
5324
5325 return handled;
5326 }
5327
5328 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5329 {
5330 int handled = 0;
5331 int n;
5332
5333 do {
5334 n = min(len, 8);
5335 if (!(lapic_in_kernel(vcpu) &&
5336 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5337 addr, n, v))
5338 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5339 break;
5340 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5341 handled += n;
5342 addr += n;
5343 len -= n;
5344 v += n;
5345 } while (len);
5346
5347 return handled;
5348 }
5349
5350 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5351 struct kvm_segment *var, int seg)
5352 {
5353 kvm_x86_ops->set_segment(vcpu, var, seg);
5354 }
5355
5356 void kvm_get_segment(struct kvm_vcpu *vcpu,
5357 struct kvm_segment *var, int seg)
5358 {
5359 kvm_x86_ops->get_segment(vcpu, var, seg);
5360 }
5361
5362 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5363 struct x86_exception *exception)
5364 {
5365 gpa_t t_gpa;
5366
5367 BUG_ON(!mmu_is_nested(vcpu));
5368
5369 /* NPT walks are always user-walks */
5370 access |= PFERR_USER_MASK;
5371 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5372
5373 return t_gpa;
5374 }
5375
5376 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5377 struct x86_exception *exception)
5378 {
5379 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5381 }
5382
5383 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5384 struct x86_exception *exception)
5385 {
5386 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5387 access |= PFERR_FETCH_MASK;
5388 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5389 }
5390
5391 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5392 struct x86_exception *exception)
5393 {
5394 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5395 access |= PFERR_WRITE_MASK;
5396 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5397 }
5398
5399 /* uses this to access any guest's mapped memory without checking CPL */
5400 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5401 struct x86_exception *exception)
5402 {
5403 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5404 }
5405
5406 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5407 struct kvm_vcpu *vcpu, u32 access,
5408 struct x86_exception *exception)
5409 {
5410 void *data = val;
5411 int r = X86EMUL_CONTINUE;
5412
5413 while (bytes) {
5414 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5415 exception);
5416 unsigned offset = addr & (PAGE_SIZE-1);
5417 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5418 int ret;
5419
5420 if (gpa == UNMAPPED_GVA)
5421 return X86EMUL_PROPAGATE_FAULT;
5422 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5423 offset, toread);
5424 if (ret < 0) {
5425 r = X86EMUL_IO_NEEDED;
5426 goto out;
5427 }
5428
5429 bytes -= toread;
5430 data += toread;
5431 addr += toread;
5432 }
5433 out:
5434 return r;
5435 }
5436
5437 /* used for instruction fetching */
5438 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5439 gva_t addr, void *val, unsigned int bytes,
5440 struct x86_exception *exception)
5441 {
5442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5443 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5444 unsigned offset;
5445 int ret;
5446
5447 /* Inline kvm_read_guest_virt_helper for speed. */
5448 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5449 exception);
5450 if (unlikely(gpa == UNMAPPED_GVA))
5451 return X86EMUL_PROPAGATE_FAULT;
5452
5453 offset = addr & (PAGE_SIZE-1);
5454 if (WARN_ON(offset + bytes > PAGE_SIZE))
5455 bytes = (unsigned)PAGE_SIZE - offset;
5456 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5457 offset, bytes);
5458 if (unlikely(ret < 0))
5459 return X86EMUL_IO_NEEDED;
5460
5461 return X86EMUL_CONTINUE;
5462 }
5463
5464 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5465 gva_t addr, void *val, unsigned int bytes,
5466 struct x86_exception *exception)
5467 {
5468 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5469
5470 /*
5471 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5472 * is returned, but our callers are not ready for that and they blindly
5473 * call kvm_inject_page_fault. Ensure that they at least do not leak
5474 * uninitialized kernel stack memory into cr2 and error code.
5475 */
5476 memset(exception, 0, sizeof(*exception));
5477 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5478 exception);
5479 }
5480 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5481
5482 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5483 gva_t addr, void *val, unsigned int bytes,
5484 struct x86_exception *exception, bool system)
5485 {
5486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5487 u32 access = 0;
5488
5489 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5490 access |= PFERR_USER_MASK;
5491
5492 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5493 }
5494
5495 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5496 unsigned long addr, void *val, unsigned int bytes)
5497 {
5498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5499 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5500
5501 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5502 }
5503
5504 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5505 struct kvm_vcpu *vcpu, u32 access,
5506 struct x86_exception *exception)
5507 {
5508 void *data = val;
5509 int r = X86EMUL_CONTINUE;
5510
5511 while (bytes) {
5512 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5513 access,
5514 exception);
5515 unsigned offset = addr & (PAGE_SIZE-1);
5516 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5517 int ret;
5518
5519 if (gpa == UNMAPPED_GVA)
5520 return X86EMUL_PROPAGATE_FAULT;
5521 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5522 if (ret < 0) {
5523 r = X86EMUL_IO_NEEDED;
5524 goto out;
5525 }
5526
5527 bytes -= towrite;
5528 data += towrite;
5529 addr += towrite;
5530 }
5531 out:
5532 return r;
5533 }
5534
5535 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5536 unsigned int bytes, struct x86_exception *exception,
5537 bool system)
5538 {
5539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5540 u32 access = PFERR_WRITE_MASK;
5541
5542 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5543 access |= PFERR_USER_MASK;
5544
5545 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5546 access, exception);
5547 }
5548
5549 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5550 unsigned int bytes, struct x86_exception *exception)
5551 {
5552 /* kvm_write_guest_virt_system can pull in tons of pages. */
5553 vcpu->arch.l1tf_flush_l1d = true;
5554
5555 /*
5556 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5557 * is returned, but our callers are not ready for that and they blindly
5558 * call kvm_inject_page_fault. Ensure that they at least do not leak
5559 * uninitialized kernel stack memory into cr2 and error code.
5560 */
5561 memset(exception, 0, sizeof(*exception));
5562 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5563 PFERR_WRITE_MASK, exception);
5564 }
5565 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5566
5567 int handle_ud(struct kvm_vcpu *vcpu)
5568 {
5569 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5570 int emul_type = EMULTYPE_TRAP_UD;
5571 char sig[5]; /* ud2; .ascii "kvm" */
5572 struct x86_exception e;
5573
5574 if (force_emulation_prefix &&
5575 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5576 sig, sizeof(sig), &e) == 0 &&
5577 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5578 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5579 emul_type = EMULTYPE_TRAP_UD_FORCED;
5580 }
5581
5582 return kvm_emulate_instruction(vcpu, emul_type);
5583 }
5584 EXPORT_SYMBOL_GPL(handle_ud);
5585
5586 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5587 gpa_t gpa, bool write)
5588 {
5589 /* For APIC access vmexit */
5590 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5591 return 1;
5592
5593 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5594 trace_vcpu_match_mmio(gva, gpa, write, true);
5595 return 1;
5596 }
5597
5598 return 0;
5599 }
5600
5601 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5602 gpa_t *gpa, struct x86_exception *exception,
5603 bool write)
5604 {
5605 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5606 | (write ? PFERR_WRITE_MASK : 0);
5607
5608 /*
5609 * currently PKRU is only applied to ept enabled guest so
5610 * there is no pkey in EPT page table for L1 guest or EPT
5611 * shadow page table for L2 guest.
5612 */
5613 if (vcpu_match_mmio_gva(vcpu, gva)
5614 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5615 vcpu->arch.mmio_access, 0, access)) {
5616 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5617 (gva & (PAGE_SIZE - 1));
5618 trace_vcpu_match_mmio(gva, *gpa, write, false);
5619 return 1;
5620 }
5621
5622 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5623
5624 if (*gpa == UNMAPPED_GVA)
5625 return -1;
5626
5627 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5628 }
5629
5630 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5631 const void *val, int bytes)
5632 {
5633 int ret;
5634
5635 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5636 if (ret < 0)
5637 return 0;
5638 kvm_page_track_write(vcpu, gpa, val, bytes);
5639 return 1;
5640 }
5641
5642 struct read_write_emulator_ops {
5643 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5644 int bytes);
5645 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5646 void *val, int bytes);
5647 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5648 int bytes, void *val);
5649 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5650 void *val, int bytes);
5651 bool write;
5652 };
5653
5654 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5655 {
5656 if (vcpu->mmio_read_completed) {
5657 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5658 vcpu->mmio_fragments[0].gpa, val);
5659 vcpu->mmio_read_completed = 0;
5660 return 1;
5661 }
5662
5663 return 0;
5664 }
5665
5666 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5667 void *val, int bytes)
5668 {
5669 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5670 }
5671
5672 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5673 void *val, int bytes)
5674 {
5675 return emulator_write_phys(vcpu, gpa, val, bytes);
5676 }
5677
5678 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5679 {
5680 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5681 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5682 }
5683
5684 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5685 void *val, int bytes)
5686 {
5687 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5688 return X86EMUL_IO_NEEDED;
5689 }
5690
5691 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5692 void *val, int bytes)
5693 {
5694 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5695
5696 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5697 return X86EMUL_CONTINUE;
5698 }
5699
5700 static const struct read_write_emulator_ops read_emultor = {
5701 .read_write_prepare = read_prepare,
5702 .read_write_emulate = read_emulate,
5703 .read_write_mmio = vcpu_mmio_read,
5704 .read_write_exit_mmio = read_exit_mmio,
5705 };
5706
5707 static const struct read_write_emulator_ops write_emultor = {
5708 .read_write_emulate = write_emulate,
5709 .read_write_mmio = write_mmio,
5710 .read_write_exit_mmio = write_exit_mmio,
5711 .write = true,
5712 };
5713
5714 static int emulator_read_write_onepage(unsigned long addr, void *val,
5715 unsigned int bytes,
5716 struct x86_exception *exception,
5717 struct kvm_vcpu *vcpu,
5718 const struct read_write_emulator_ops *ops)
5719 {
5720 gpa_t gpa;
5721 int handled, ret;
5722 bool write = ops->write;
5723 struct kvm_mmio_fragment *frag;
5724 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5725
5726 /*
5727 * If the exit was due to a NPF we may already have a GPA.
5728 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5729 * Note, this cannot be used on string operations since string
5730 * operation using rep will only have the initial GPA from the NPF
5731 * occurred.
5732 */
5733 if (vcpu->arch.gpa_available &&
5734 emulator_can_use_gpa(ctxt) &&
5735 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5736 gpa = vcpu->arch.gpa_val;
5737 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5738 } else {
5739 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5740 if (ret < 0)
5741 return X86EMUL_PROPAGATE_FAULT;
5742 }
5743
5744 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5745 return X86EMUL_CONTINUE;
5746
5747 /*
5748 * Is this MMIO handled locally?
5749 */
5750 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5751 if (handled == bytes)
5752 return X86EMUL_CONTINUE;
5753
5754 gpa += handled;
5755 bytes -= handled;
5756 val += handled;
5757
5758 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5759 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5760 frag->gpa = gpa;
5761 frag->data = val;
5762 frag->len = bytes;
5763 return X86EMUL_CONTINUE;
5764 }
5765
5766 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5767 unsigned long addr,
5768 void *val, unsigned int bytes,
5769 struct x86_exception *exception,
5770 const struct read_write_emulator_ops *ops)
5771 {
5772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5773 gpa_t gpa;
5774 int rc;
5775
5776 if (ops->read_write_prepare &&
5777 ops->read_write_prepare(vcpu, val, bytes))
5778 return X86EMUL_CONTINUE;
5779
5780 vcpu->mmio_nr_fragments = 0;
5781
5782 /* Crossing a page boundary? */
5783 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5784 int now;
5785
5786 now = -addr & ~PAGE_MASK;
5787 rc = emulator_read_write_onepage(addr, val, now, exception,
5788 vcpu, ops);
5789
5790 if (rc != X86EMUL_CONTINUE)
5791 return rc;
5792 addr += now;
5793 if (ctxt->mode != X86EMUL_MODE_PROT64)
5794 addr = (u32)addr;
5795 val += now;
5796 bytes -= now;
5797 }
5798
5799 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5800 vcpu, ops);
5801 if (rc != X86EMUL_CONTINUE)
5802 return rc;
5803
5804 if (!vcpu->mmio_nr_fragments)
5805 return rc;
5806
5807 gpa = vcpu->mmio_fragments[0].gpa;
5808
5809 vcpu->mmio_needed = 1;
5810 vcpu->mmio_cur_fragment = 0;
5811
5812 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5813 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5814 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5815 vcpu->run->mmio.phys_addr = gpa;
5816
5817 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5818 }
5819
5820 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5821 unsigned long addr,
5822 void *val,
5823 unsigned int bytes,
5824 struct x86_exception *exception)
5825 {
5826 return emulator_read_write(ctxt, addr, val, bytes,
5827 exception, &read_emultor);
5828 }
5829
5830 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5831 unsigned long addr,
5832 const void *val,
5833 unsigned int bytes,
5834 struct x86_exception *exception)
5835 {
5836 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5837 exception, &write_emultor);
5838 }
5839
5840 #define CMPXCHG_TYPE(t, ptr, old, new) \
5841 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5842
5843 #ifdef CONFIG_X86_64
5844 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5845 #else
5846 # define CMPXCHG64(ptr, old, new) \
5847 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5848 #endif
5849
5850 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5851 unsigned long addr,
5852 const void *old,
5853 const void *new,
5854 unsigned int bytes,
5855 struct x86_exception *exception)
5856 {
5857 struct kvm_host_map map;
5858 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5859 gpa_t gpa;
5860 char *kaddr;
5861 bool exchanged;
5862
5863 /* guests cmpxchg8b have to be emulated atomically */
5864 if (bytes > 8 || (bytes & (bytes - 1)))
5865 goto emul_write;
5866
5867 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5868
5869 if (gpa == UNMAPPED_GVA ||
5870 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5871 goto emul_write;
5872
5873 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5874 goto emul_write;
5875
5876 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5877 goto emul_write;
5878
5879 kaddr = map.hva + offset_in_page(gpa);
5880
5881 switch (bytes) {
5882 case 1:
5883 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5884 break;
5885 case 2:
5886 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5887 break;
5888 case 4:
5889 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5890 break;
5891 case 8:
5892 exchanged = CMPXCHG64(kaddr, old, new);
5893 break;
5894 default:
5895 BUG();
5896 }
5897
5898 kvm_vcpu_unmap(vcpu, &map, true);
5899
5900 if (!exchanged)
5901 return X86EMUL_CMPXCHG_FAILED;
5902
5903 kvm_page_track_write(vcpu, gpa, new, bytes);
5904
5905 return X86EMUL_CONTINUE;
5906
5907 emul_write:
5908 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5909
5910 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5911 }
5912
5913 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5914 {
5915 int r = 0, i;
5916
5917 for (i = 0; i < vcpu->arch.pio.count; i++) {
5918 if (vcpu->arch.pio.in)
5919 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5920 vcpu->arch.pio.size, pd);
5921 else
5922 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5923 vcpu->arch.pio.port, vcpu->arch.pio.size,
5924 pd);
5925 if (r)
5926 break;
5927 pd += vcpu->arch.pio.size;
5928 }
5929 return r;
5930 }
5931
5932 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5933 unsigned short port, void *val,
5934 unsigned int count, bool in)
5935 {
5936 vcpu->arch.pio.port = port;
5937 vcpu->arch.pio.in = in;
5938 vcpu->arch.pio.count = count;
5939 vcpu->arch.pio.size = size;
5940
5941 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5942 vcpu->arch.pio.count = 0;
5943 return 1;
5944 }
5945
5946 vcpu->run->exit_reason = KVM_EXIT_IO;
5947 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5948 vcpu->run->io.size = size;
5949 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5950 vcpu->run->io.count = count;
5951 vcpu->run->io.port = port;
5952
5953 return 0;
5954 }
5955
5956 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5957 int size, unsigned short port, void *val,
5958 unsigned int count)
5959 {
5960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5961 int ret;
5962
5963 if (vcpu->arch.pio.count)
5964 goto data_avail;
5965
5966 memset(vcpu->arch.pio_data, 0, size * count);
5967
5968 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5969 if (ret) {
5970 data_avail:
5971 memcpy(val, vcpu->arch.pio_data, size * count);
5972 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5973 vcpu->arch.pio.count = 0;
5974 return 1;
5975 }
5976
5977 return 0;
5978 }
5979
5980 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5981 int size, unsigned short port,
5982 const void *val, unsigned int count)
5983 {
5984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5985
5986 memcpy(vcpu->arch.pio_data, val, size * count);
5987 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5988 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5989 }
5990
5991 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5992 {
5993 return kvm_x86_ops->get_segment_base(vcpu, seg);
5994 }
5995
5996 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5997 {
5998 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5999 }
6000
6001 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6002 {
6003 if (!need_emulate_wbinvd(vcpu))
6004 return X86EMUL_CONTINUE;
6005
6006 if (kvm_x86_ops->has_wbinvd_exit()) {
6007 int cpu = get_cpu();
6008
6009 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6010 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6011 wbinvd_ipi, NULL, 1);
6012 put_cpu();
6013 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6014 } else
6015 wbinvd();
6016 return X86EMUL_CONTINUE;
6017 }
6018
6019 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6020 {
6021 kvm_emulate_wbinvd_noskip(vcpu);
6022 return kvm_skip_emulated_instruction(vcpu);
6023 }
6024 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6025
6026
6027
6028 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6029 {
6030 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6031 }
6032
6033 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6034 unsigned long *dest)
6035 {
6036 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6037 }
6038
6039 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6040 unsigned long value)
6041 {
6042
6043 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6044 }
6045
6046 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6047 {
6048 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6049 }
6050
6051 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6052 {
6053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6054 unsigned long value;
6055
6056 switch (cr) {
6057 case 0:
6058 value = kvm_read_cr0(vcpu);
6059 break;
6060 case 2:
6061 value = vcpu->arch.cr2;
6062 break;
6063 case 3:
6064 value = kvm_read_cr3(vcpu);
6065 break;
6066 case 4:
6067 value = kvm_read_cr4(vcpu);
6068 break;
6069 case 8:
6070 value = kvm_get_cr8(vcpu);
6071 break;
6072 default:
6073 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6074 return 0;
6075 }
6076
6077 return value;
6078 }
6079
6080 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6081 {
6082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6083 int res = 0;
6084
6085 switch (cr) {
6086 case 0:
6087 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6088 break;
6089 case 2:
6090 vcpu->arch.cr2 = val;
6091 break;
6092 case 3:
6093 res = kvm_set_cr3(vcpu, val);
6094 break;
6095 case 4:
6096 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6097 break;
6098 case 8:
6099 res = kvm_set_cr8(vcpu, val);
6100 break;
6101 default:
6102 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6103 res = -1;
6104 }
6105
6106 return res;
6107 }
6108
6109 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6110 {
6111 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
6112 }
6113
6114 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6115 {
6116 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6117 }
6118
6119 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6120 {
6121 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6122 }
6123
6124 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6125 {
6126 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6127 }
6128
6129 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6130 {
6131 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6132 }
6133
6134 static unsigned long emulator_get_cached_segment_base(
6135 struct x86_emulate_ctxt *ctxt, int seg)
6136 {
6137 return get_segment_base(emul_to_vcpu(ctxt), seg);
6138 }
6139
6140 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6141 struct desc_struct *desc, u32 *base3,
6142 int seg)
6143 {
6144 struct kvm_segment var;
6145
6146 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6147 *selector = var.selector;
6148
6149 if (var.unusable) {
6150 memset(desc, 0, sizeof(*desc));
6151 if (base3)
6152 *base3 = 0;
6153 return false;
6154 }
6155
6156 if (var.g)
6157 var.limit >>= 12;
6158 set_desc_limit(desc, var.limit);
6159 set_desc_base(desc, (unsigned long)var.base);
6160 #ifdef CONFIG_X86_64
6161 if (base3)
6162 *base3 = var.base >> 32;
6163 #endif
6164 desc->type = var.type;
6165 desc->s = var.s;
6166 desc->dpl = var.dpl;
6167 desc->p = var.present;
6168 desc->avl = var.avl;
6169 desc->l = var.l;
6170 desc->d = var.db;
6171 desc->g = var.g;
6172
6173 return true;
6174 }
6175
6176 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6177 struct desc_struct *desc, u32 base3,
6178 int seg)
6179 {
6180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6181 struct kvm_segment var;
6182
6183 var.selector = selector;
6184 var.base = get_desc_base(desc);
6185 #ifdef CONFIG_X86_64
6186 var.base |= ((u64)base3) << 32;
6187 #endif
6188 var.limit = get_desc_limit(desc);
6189 if (desc->g)
6190 var.limit = (var.limit << 12) | 0xfff;
6191 var.type = desc->type;
6192 var.dpl = desc->dpl;
6193 var.db = desc->d;
6194 var.s = desc->s;
6195 var.l = desc->l;
6196 var.g = desc->g;
6197 var.avl = desc->avl;
6198 var.present = desc->p;
6199 var.unusable = !var.present;
6200 var.padding = 0;
6201
6202 kvm_set_segment(vcpu, &var, seg);
6203 return;
6204 }
6205
6206 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6207 u32 msr_index, u64 *pdata)
6208 {
6209 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6210 }
6211
6212 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6213 u32 msr_index, u64 data)
6214 {
6215 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6216 }
6217
6218 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6219 {
6220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6221
6222 return vcpu->arch.smbase;
6223 }
6224
6225 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6226 {
6227 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6228
6229 vcpu->arch.smbase = smbase;
6230 }
6231
6232 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6233 u32 pmc)
6234 {
6235 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6236 }
6237
6238 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6239 u32 pmc, u64 *pdata)
6240 {
6241 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6242 }
6243
6244 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6245 {
6246 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6247 }
6248
6249 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6250 struct x86_instruction_info *info,
6251 enum x86_intercept_stage stage)
6252 {
6253 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6254 }
6255
6256 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6257 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6258 {
6259 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6260 }
6261
6262 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6263 {
6264 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6265 }
6266
6267 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6268 {
6269 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6270 }
6271
6272 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6273 {
6274 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6275 }
6276
6277 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6278 {
6279 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6280 }
6281
6282 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6283 {
6284 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6285 }
6286
6287 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6288 {
6289 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6290 }
6291
6292 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6293 {
6294 return emul_to_vcpu(ctxt)->arch.hflags;
6295 }
6296
6297 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6298 {
6299 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6300 }
6301
6302 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6303 const char *smstate)
6304 {
6305 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6306 }
6307
6308 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6309 {
6310 kvm_smm_changed(emul_to_vcpu(ctxt));
6311 }
6312
6313 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6314 {
6315 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6316 }
6317
6318 static const struct x86_emulate_ops emulate_ops = {
6319 .read_gpr = emulator_read_gpr,
6320 .write_gpr = emulator_write_gpr,
6321 .read_std = emulator_read_std,
6322 .write_std = emulator_write_std,
6323 .read_phys = kvm_read_guest_phys_system,
6324 .fetch = kvm_fetch_guest_virt,
6325 .read_emulated = emulator_read_emulated,
6326 .write_emulated = emulator_write_emulated,
6327 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6328 .invlpg = emulator_invlpg,
6329 .pio_in_emulated = emulator_pio_in_emulated,
6330 .pio_out_emulated = emulator_pio_out_emulated,
6331 .get_segment = emulator_get_segment,
6332 .set_segment = emulator_set_segment,
6333 .get_cached_segment_base = emulator_get_cached_segment_base,
6334 .get_gdt = emulator_get_gdt,
6335 .get_idt = emulator_get_idt,
6336 .set_gdt = emulator_set_gdt,
6337 .set_idt = emulator_set_idt,
6338 .get_cr = emulator_get_cr,
6339 .set_cr = emulator_set_cr,
6340 .cpl = emulator_get_cpl,
6341 .get_dr = emulator_get_dr,
6342 .set_dr = emulator_set_dr,
6343 .get_smbase = emulator_get_smbase,
6344 .set_smbase = emulator_set_smbase,
6345 .set_msr = emulator_set_msr,
6346 .get_msr = emulator_get_msr,
6347 .check_pmc = emulator_check_pmc,
6348 .read_pmc = emulator_read_pmc,
6349 .halt = emulator_halt,
6350 .wbinvd = emulator_wbinvd,
6351 .fix_hypercall = emulator_fix_hypercall,
6352 .intercept = emulator_intercept,
6353 .get_cpuid = emulator_get_cpuid,
6354 .guest_has_long_mode = emulator_guest_has_long_mode,
6355 .guest_has_movbe = emulator_guest_has_movbe,
6356 .guest_has_fxsr = emulator_guest_has_fxsr,
6357 .set_nmi_mask = emulator_set_nmi_mask,
6358 .get_hflags = emulator_get_hflags,
6359 .set_hflags = emulator_set_hflags,
6360 .pre_leave_smm = emulator_pre_leave_smm,
6361 .post_leave_smm = emulator_post_leave_smm,
6362 .set_xcr = emulator_set_xcr,
6363 };
6364
6365 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6366 {
6367 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6368 /*
6369 * an sti; sti; sequence only disable interrupts for the first
6370 * instruction. So, if the last instruction, be it emulated or
6371 * not, left the system with the INT_STI flag enabled, it
6372 * means that the last instruction is an sti. We should not
6373 * leave the flag on in this case. The same goes for mov ss
6374 */
6375 if (int_shadow & mask)
6376 mask = 0;
6377 if (unlikely(int_shadow || mask)) {
6378 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6379 if (!mask)
6380 kvm_make_request(KVM_REQ_EVENT, vcpu);
6381 }
6382 }
6383
6384 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6385 {
6386 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6387 if (ctxt->exception.vector == PF_VECTOR)
6388 return kvm_propagate_fault(vcpu, &ctxt->exception);
6389
6390 if (ctxt->exception.error_code_valid)
6391 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6392 ctxt->exception.error_code);
6393 else
6394 kvm_queue_exception(vcpu, ctxt->exception.vector);
6395 return false;
6396 }
6397
6398 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6399 {
6400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6401 int cs_db, cs_l;
6402
6403 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6404
6405 ctxt->eflags = kvm_get_rflags(vcpu);
6406 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6407
6408 ctxt->eip = kvm_rip_read(vcpu);
6409 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6410 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6411 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6412 cs_db ? X86EMUL_MODE_PROT32 :
6413 X86EMUL_MODE_PROT16;
6414 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6415 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6416 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6417
6418 init_decode_cache(ctxt);
6419 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6420 }
6421
6422 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6423 {
6424 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6425 int ret;
6426
6427 init_emulate_ctxt(vcpu);
6428
6429 ctxt->op_bytes = 2;
6430 ctxt->ad_bytes = 2;
6431 ctxt->_eip = ctxt->eip + inc_eip;
6432 ret = emulate_int_real(ctxt, irq);
6433
6434 if (ret != X86EMUL_CONTINUE) {
6435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6436 } else {
6437 ctxt->eip = ctxt->_eip;
6438 kvm_rip_write(vcpu, ctxt->eip);
6439 kvm_set_rflags(vcpu, ctxt->eflags);
6440 }
6441 }
6442 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6443
6444 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6445 {
6446 ++vcpu->stat.insn_emulation_fail;
6447 trace_kvm_emulate_insn_failed(vcpu);
6448
6449 if (emulation_type & EMULTYPE_VMWARE_GP) {
6450 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6451 return 1;
6452 }
6453
6454 if (emulation_type & EMULTYPE_SKIP) {
6455 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6456 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6457 vcpu->run->internal.ndata = 0;
6458 return 0;
6459 }
6460
6461 kvm_queue_exception(vcpu, UD_VECTOR);
6462
6463 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6464 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6465 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6466 vcpu->run->internal.ndata = 0;
6467 return 0;
6468 }
6469
6470 return 1;
6471 }
6472
6473 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6474 bool write_fault_to_shadow_pgtable,
6475 int emulation_type)
6476 {
6477 gpa_t gpa = cr2_or_gpa;
6478 kvm_pfn_t pfn;
6479
6480 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6481 return false;
6482
6483 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6484 return false;
6485
6486 if (!vcpu->arch.mmu->direct_map) {
6487 /*
6488 * Write permission should be allowed since only
6489 * write access need to be emulated.
6490 */
6491 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6492
6493 /*
6494 * If the mapping is invalid in guest, let cpu retry
6495 * it to generate fault.
6496 */
6497 if (gpa == UNMAPPED_GVA)
6498 return true;
6499 }
6500
6501 /*
6502 * Do not retry the unhandleable instruction if it faults on the
6503 * readonly host memory, otherwise it will goto a infinite loop:
6504 * retry instruction -> write #PF -> emulation fail -> retry
6505 * instruction -> ...
6506 */
6507 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6508
6509 /*
6510 * If the instruction failed on the error pfn, it can not be fixed,
6511 * report the error to userspace.
6512 */
6513 if (is_error_noslot_pfn(pfn))
6514 return false;
6515
6516 kvm_release_pfn_clean(pfn);
6517
6518 /* The instructions are well-emulated on direct mmu. */
6519 if (vcpu->arch.mmu->direct_map) {
6520 unsigned int indirect_shadow_pages;
6521
6522 spin_lock(&vcpu->kvm->mmu_lock);
6523 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6524 spin_unlock(&vcpu->kvm->mmu_lock);
6525
6526 if (indirect_shadow_pages)
6527 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6528
6529 return true;
6530 }
6531
6532 /*
6533 * if emulation was due to access to shadowed page table
6534 * and it failed try to unshadow page and re-enter the
6535 * guest to let CPU execute the instruction.
6536 */
6537 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6538
6539 /*
6540 * If the access faults on its page table, it can not
6541 * be fixed by unprotecting shadow page and it should
6542 * be reported to userspace.
6543 */
6544 return !write_fault_to_shadow_pgtable;
6545 }
6546
6547 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6548 gpa_t cr2_or_gpa, int emulation_type)
6549 {
6550 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6551 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6552
6553 last_retry_eip = vcpu->arch.last_retry_eip;
6554 last_retry_addr = vcpu->arch.last_retry_addr;
6555
6556 /*
6557 * If the emulation is caused by #PF and it is non-page_table
6558 * writing instruction, it means the VM-EXIT is caused by shadow
6559 * page protected, we can zap the shadow page and retry this
6560 * instruction directly.
6561 *
6562 * Note: if the guest uses a non-page-table modifying instruction
6563 * on the PDE that points to the instruction, then we will unmap
6564 * the instruction and go to an infinite loop. So, we cache the
6565 * last retried eip and the last fault address, if we meet the eip
6566 * and the address again, we can break out of the potential infinite
6567 * loop.
6568 */
6569 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6570
6571 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6572 return false;
6573
6574 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6575 return false;
6576
6577 if (x86_page_table_writing_insn(ctxt))
6578 return false;
6579
6580 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6581 return false;
6582
6583 vcpu->arch.last_retry_eip = ctxt->eip;
6584 vcpu->arch.last_retry_addr = cr2_or_gpa;
6585
6586 if (!vcpu->arch.mmu->direct_map)
6587 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6588
6589 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6590
6591 return true;
6592 }
6593
6594 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6595 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6596
6597 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6598 {
6599 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6600 /* This is a good place to trace that we are exiting SMM. */
6601 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6602
6603 /* Process a latched INIT or SMI, if any. */
6604 kvm_make_request(KVM_REQ_EVENT, vcpu);
6605 }
6606
6607 kvm_mmu_reset_context(vcpu);
6608 }
6609
6610 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6611 unsigned long *db)
6612 {
6613 u32 dr6 = 0;
6614 int i;
6615 u32 enable, rwlen;
6616
6617 enable = dr7;
6618 rwlen = dr7 >> 16;
6619 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6620 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6621 dr6 |= (1 << i);
6622 return dr6;
6623 }
6624
6625 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6626 {
6627 struct kvm_run *kvm_run = vcpu->run;
6628
6629 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6630 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6631 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6632 kvm_run->debug.arch.exception = DB_VECTOR;
6633 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6634 return 0;
6635 }
6636 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6637 return 1;
6638 }
6639
6640 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6641 {
6642 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6643 int r;
6644
6645 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6646 if (unlikely(!r))
6647 return 0;
6648
6649 /*
6650 * rflags is the old, "raw" value of the flags. The new value has
6651 * not been saved yet.
6652 *
6653 * This is correct even for TF set by the guest, because "the
6654 * processor will not generate this exception after the instruction
6655 * that sets the TF flag".
6656 */
6657 if (unlikely(rflags & X86_EFLAGS_TF))
6658 r = kvm_vcpu_do_singlestep(vcpu);
6659 return r;
6660 }
6661 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6662
6663 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6664 {
6665 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6666 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6667 struct kvm_run *kvm_run = vcpu->run;
6668 unsigned long eip = kvm_get_linear_rip(vcpu);
6669 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6670 vcpu->arch.guest_debug_dr7,
6671 vcpu->arch.eff_db);
6672
6673 if (dr6 != 0) {
6674 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6675 kvm_run->debug.arch.pc = eip;
6676 kvm_run->debug.arch.exception = DB_VECTOR;
6677 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6678 *r = 0;
6679 return true;
6680 }
6681 }
6682
6683 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6684 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6685 unsigned long eip = kvm_get_linear_rip(vcpu);
6686 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6687 vcpu->arch.dr7,
6688 vcpu->arch.db);
6689
6690 if (dr6 != 0) {
6691 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6692 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6693 kvm_queue_exception(vcpu, DB_VECTOR);
6694 *r = 1;
6695 return true;
6696 }
6697 }
6698
6699 return false;
6700 }
6701
6702 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6703 {
6704 switch (ctxt->opcode_len) {
6705 case 1:
6706 switch (ctxt->b) {
6707 case 0xe4: /* IN */
6708 case 0xe5:
6709 case 0xec:
6710 case 0xed:
6711 case 0xe6: /* OUT */
6712 case 0xe7:
6713 case 0xee:
6714 case 0xef:
6715 case 0x6c: /* INS */
6716 case 0x6d:
6717 case 0x6e: /* OUTS */
6718 case 0x6f:
6719 return true;
6720 }
6721 break;
6722 case 2:
6723 switch (ctxt->b) {
6724 case 0x33: /* RDPMC */
6725 return true;
6726 }
6727 break;
6728 }
6729
6730 return false;
6731 }
6732
6733 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6734 int emulation_type, void *insn, int insn_len)
6735 {
6736 int r;
6737 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6738 bool writeback = true;
6739 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6740
6741 vcpu->arch.l1tf_flush_l1d = true;
6742
6743 /*
6744 * Clear write_fault_to_shadow_pgtable here to ensure it is
6745 * never reused.
6746 */
6747 vcpu->arch.write_fault_to_shadow_pgtable = false;
6748 kvm_clear_exception_queue(vcpu);
6749
6750 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6751 init_emulate_ctxt(vcpu);
6752
6753 /*
6754 * We will reenter on the same instruction since
6755 * we do not set complete_userspace_io. This does not
6756 * handle watchpoints yet, those would be handled in
6757 * the emulate_ops.
6758 */
6759 if (!(emulation_type & EMULTYPE_SKIP) &&
6760 kvm_vcpu_check_breakpoint(vcpu, &r))
6761 return r;
6762
6763 ctxt->interruptibility = 0;
6764 ctxt->have_exception = false;
6765 ctxt->exception.vector = -1;
6766 ctxt->perm_ok = false;
6767
6768 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6769
6770 r = x86_decode_insn(ctxt, insn, insn_len);
6771
6772 trace_kvm_emulate_insn_start(vcpu);
6773 ++vcpu->stat.insn_emulation;
6774 if (r != EMULATION_OK) {
6775 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6776 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6777 kvm_queue_exception(vcpu, UD_VECTOR);
6778 return 1;
6779 }
6780 if (reexecute_instruction(vcpu, cr2_or_gpa,
6781 write_fault_to_spt,
6782 emulation_type))
6783 return 1;
6784 if (ctxt->have_exception) {
6785 /*
6786 * #UD should result in just EMULATION_FAILED, and trap-like
6787 * exception should not be encountered during decode.
6788 */
6789 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6790 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6791 inject_emulated_exception(vcpu);
6792 return 1;
6793 }
6794 return handle_emulation_failure(vcpu, emulation_type);
6795 }
6796 }
6797
6798 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6799 !is_vmware_backdoor_opcode(ctxt)) {
6800 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6801 return 1;
6802 }
6803
6804 /*
6805 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6806 * for kvm_skip_emulated_instruction(). The caller is responsible for
6807 * updating interruptibility state and injecting single-step #DBs.
6808 */
6809 if (emulation_type & EMULTYPE_SKIP) {
6810 kvm_rip_write(vcpu, ctxt->_eip);
6811 if (ctxt->eflags & X86_EFLAGS_RF)
6812 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6813 return 1;
6814 }
6815
6816 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6817 return 1;
6818
6819 /* this is needed for vmware backdoor interface to work since it
6820 changes registers values during IO operation */
6821 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6822 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6823 emulator_invalidate_register_cache(ctxt);
6824 }
6825
6826 restart:
6827 /* Save the faulting GPA (cr2) in the address field */
6828 ctxt->exception.address = cr2_or_gpa;
6829
6830 r = x86_emulate_insn(ctxt);
6831
6832 if (r == EMULATION_INTERCEPTED)
6833 return 1;
6834
6835 if (r == EMULATION_FAILED) {
6836 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6837 emulation_type))
6838 return 1;
6839
6840 return handle_emulation_failure(vcpu, emulation_type);
6841 }
6842
6843 if (ctxt->have_exception) {
6844 r = 1;
6845 if (inject_emulated_exception(vcpu))
6846 return r;
6847 } else if (vcpu->arch.pio.count) {
6848 if (!vcpu->arch.pio.in) {
6849 /* FIXME: return into emulator if single-stepping. */
6850 vcpu->arch.pio.count = 0;
6851 } else {
6852 writeback = false;
6853 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6854 }
6855 r = 0;
6856 } else if (vcpu->mmio_needed) {
6857 ++vcpu->stat.mmio_exits;
6858
6859 if (!vcpu->mmio_is_write)
6860 writeback = false;
6861 r = 0;
6862 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6863 } else if (r == EMULATION_RESTART)
6864 goto restart;
6865 else
6866 r = 1;
6867
6868 if (writeback) {
6869 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6870 toggle_interruptibility(vcpu, ctxt->interruptibility);
6871 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6872 if (!ctxt->have_exception ||
6873 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6874 kvm_rip_write(vcpu, ctxt->eip);
6875 if (r && ctxt->tf)
6876 r = kvm_vcpu_do_singlestep(vcpu);
6877 __kvm_set_rflags(vcpu, ctxt->eflags);
6878 }
6879
6880 /*
6881 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6882 * do nothing, and it will be requested again as soon as
6883 * the shadow expires. But we still need to check here,
6884 * because POPF has no interrupt shadow.
6885 */
6886 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6887 kvm_make_request(KVM_REQ_EVENT, vcpu);
6888 } else
6889 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6890
6891 return r;
6892 }
6893
6894 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6895 {
6896 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6897 }
6898 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6899
6900 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6901 void *insn, int insn_len)
6902 {
6903 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6904 }
6905 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6906
6907 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6908 {
6909 vcpu->arch.pio.count = 0;
6910 return 1;
6911 }
6912
6913 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6914 {
6915 vcpu->arch.pio.count = 0;
6916
6917 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6918 return 1;
6919
6920 return kvm_skip_emulated_instruction(vcpu);
6921 }
6922
6923 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6924 unsigned short port)
6925 {
6926 unsigned long val = kvm_rax_read(vcpu);
6927 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6928 size, port, &val, 1);
6929 if (ret)
6930 return ret;
6931
6932 /*
6933 * Workaround userspace that relies on old KVM behavior of %rip being
6934 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6935 */
6936 if (port == 0x7e &&
6937 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6938 vcpu->arch.complete_userspace_io =
6939 complete_fast_pio_out_port_0x7e;
6940 kvm_skip_emulated_instruction(vcpu);
6941 } else {
6942 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6943 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6944 }
6945 return 0;
6946 }
6947
6948 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6949 {
6950 unsigned long val;
6951
6952 /* We should only ever be called with arch.pio.count equal to 1 */
6953 BUG_ON(vcpu->arch.pio.count != 1);
6954
6955 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6956 vcpu->arch.pio.count = 0;
6957 return 1;
6958 }
6959
6960 /* For size less than 4 we merge, else we zero extend */
6961 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6962
6963 /*
6964 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6965 * the copy and tracing
6966 */
6967 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6968 vcpu->arch.pio.port, &val, 1);
6969 kvm_rax_write(vcpu, val);
6970
6971 return kvm_skip_emulated_instruction(vcpu);
6972 }
6973
6974 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6975 unsigned short port)
6976 {
6977 unsigned long val;
6978 int ret;
6979
6980 /* For size less than 4 we merge, else we zero extend */
6981 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6982
6983 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6984 &val, 1);
6985 if (ret) {
6986 kvm_rax_write(vcpu, val);
6987 return ret;
6988 }
6989
6990 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6991 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6992
6993 return 0;
6994 }
6995
6996 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6997 {
6998 int ret;
6999
7000 if (in)
7001 ret = kvm_fast_pio_in(vcpu, size, port);
7002 else
7003 ret = kvm_fast_pio_out(vcpu, size, port);
7004 return ret && kvm_skip_emulated_instruction(vcpu);
7005 }
7006 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7007
7008 static int kvmclock_cpu_down_prep(unsigned int cpu)
7009 {
7010 __this_cpu_write(cpu_tsc_khz, 0);
7011 return 0;
7012 }
7013
7014 static void tsc_khz_changed(void *data)
7015 {
7016 struct cpufreq_freqs *freq = data;
7017 unsigned long khz = 0;
7018
7019 if (data)
7020 khz = freq->new;
7021 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7022 khz = cpufreq_quick_get(raw_smp_processor_id());
7023 if (!khz)
7024 khz = tsc_khz;
7025 __this_cpu_write(cpu_tsc_khz, khz);
7026 }
7027
7028 #ifdef CONFIG_X86_64
7029 static void kvm_hyperv_tsc_notifier(void)
7030 {
7031 struct kvm *kvm;
7032 struct kvm_vcpu *vcpu;
7033 int cpu;
7034
7035 mutex_lock(&kvm_lock);
7036 list_for_each_entry(kvm, &vm_list, vm_list)
7037 kvm_make_mclock_inprogress_request(kvm);
7038
7039 hyperv_stop_tsc_emulation();
7040
7041 /* TSC frequency always matches when on Hyper-V */
7042 for_each_present_cpu(cpu)
7043 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7044 kvm_max_guest_tsc_khz = tsc_khz;
7045
7046 list_for_each_entry(kvm, &vm_list, vm_list) {
7047 struct kvm_arch *ka = &kvm->arch;
7048
7049 spin_lock(&ka->pvclock_gtod_sync_lock);
7050
7051 pvclock_update_vm_gtod_copy(kvm);
7052
7053 kvm_for_each_vcpu(cpu, vcpu, kvm)
7054 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7055
7056 kvm_for_each_vcpu(cpu, vcpu, kvm)
7057 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7058
7059 spin_unlock(&ka->pvclock_gtod_sync_lock);
7060 }
7061 mutex_unlock(&kvm_lock);
7062 }
7063 #endif
7064
7065 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7066 {
7067 struct kvm *kvm;
7068 struct kvm_vcpu *vcpu;
7069 int i, send_ipi = 0;
7070
7071 /*
7072 * We allow guests to temporarily run on slowing clocks,
7073 * provided we notify them after, or to run on accelerating
7074 * clocks, provided we notify them before. Thus time never
7075 * goes backwards.
7076 *
7077 * However, we have a problem. We can't atomically update
7078 * the frequency of a given CPU from this function; it is
7079 * merely a notifier, which can be called from any CPU.
7080 * Changing the TSC frequency at arbitrary points in time
7081 * requires a recomputation of local variables related to
7082 * the TSC for each VCPU. We must flag these local variables
7083 * to be updated and be sure the update takes place with the
7084 * new frequency before any guests proceed.
7085 *
7086 * Unfortunately, the combination of hotplug CPU and frequency
7087 * change creates an intractable locking scenario; the order
7088 * of when these callouts happen is undefined with respect to
7089 * CPU hotplug, and they can race with each other. As such,
7090 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7091 * undefined; you can actually have a CPU frequency change take
7092 * place in between the computation of X and the setting of the
7093 * variable. To protect against this problem, all updates of
7094 * the per_cpu tsc_khz variable are done in an interrupt
7095 * protected IPI, and all callers wishing to update the value
7096 * must wait for a synchronous IPI to complete (which is trivial
7097 * if the caller is on the CPU already). This establishes the
7098 * necessary total order on variable updates.
7099 *
7100 * Note that because a guest time update may take place
7101 * anytime after the setting of the VCPU's request bit, the
7102 * correct TSC value must be set before the request. However,
7103 * to ensure the update actually makes it to any guest which
7104 * starts running in hardware virtualization between the set
7105 * and the acquisition of the spinlock, we must also ping the
7106 * CPU after setting the request bit.
7107 *
7108 */
7109
7110 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7111
7112 mutex_lock(&kvm_lock);
7113 list_for_each_entry(kvm, &vm_list, vm_list) {
7114 kvm_for_each_vcpu(i, vcpu, kvm) {
7115 if (vcpu->cpu != cpu)
7116 continue;
7117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7118 if (vcpu->cpu != raw_smp_processor_id())
7119 send_ipi = 1;
7120 }
7121 }
7122 mutex_unlock(&kvm_lock);
7123
7124 if (freq->old < freq->new && send_ipi) {
7125 /*
7126 * We upscale the frequency. Must make the guest
7127 * doesn't see old kvmclock values while running with
7128 * the new frequency, otherwise we risk the guest sees
7129 * time go backwards.
7130 *
7131 * In case we update the frequency for another cpu
7132 * (which might be in guest context) send an interrupt
7133 * to kick the cpu out of guest context. Next time
7134 * guest context is entered kvmclock will be updated,
7135 * so the guest will not see stale values.
7136 */
7137 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7138 }
7139 }
7140
7141 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7142 void *data)
7143 {
7144 struct cpufreq_freqs *freq = data;
7145 int cpu;
7146
7147 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7148 return 0;
7149 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7150 return 0;
7151
7152 for_each_cpu(cpu, freq->policy->cpus)
7153 __kvmclock_cpufreq_notifier(freq, cpu);
7154
7155 return 0;
7156 }
7157
7158 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7159 .notifier_call = kvmclock_cpufreq_notifier
7160 };
7161
7162 static int kvmclock_cpu_online(unsigned int cpu)
7163 {
7164 tsc_khz_changed(NULL);
7165 return 0;
7166 }
7167
7168 static void kvm_timer_init(void)
7169 {
7170 max_tsc_khz = tsc_khz;
7171
7172 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7173 #ifdef CONFIG_CPU_FREQ
7174 struct cpufreq_policy policy;
7175 int cpu;
7176
7177 memset(&policy, 0, sizeof(policy));
7178 cpu = get_cpu();
7179 cpufreq_get_policy(&policy, cpu);
7180 if (policy.cpuinfo.max_freq)
7181 max_tsc_khz = policy.cpuinfo.max_freq;
7182 put_cpu();
7183 #endif
7184 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7185 CPUFREQ_TRANSITION_NOTIFIER);
7186 }
7187
7188 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7189 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7190 }
7191
7192 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7193 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7194
7195 int kvm_is_in_guest(void)
7196 {
7197 return __this_cpu_read(current_vcpu) != NULL;
7198 }
7199
7200 static int kvm_is_user_mode(void)
7201 {
7202 int user_mode = 3;
7203
7204 if (__this_cpu_read(current_vcpu))
7205 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7206
7207 return user_mode != 0;
7208 }
7209
7210 static unsigned long kvm_get_guest_ip(void)
7211 {
7212 unsigned long ip = 0;
7213
7214 if (__this_cpu_read(current_vcpu))
7215 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7216
7217 return ip;
7218 }
7219
7220 static void kvm_handle_intel_pt_intr(void)
7221 {
7222 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7223
7224 kvm_make_request(KVM_REQ_PMI, vcpu);
7225 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7226 (unsigned long *)&vcpu->arch.pmu.global_status);
7227 }
7228
7229 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7230 .is_in_guest = kvm_is_in_guest,
7231 .is_user_mode = kvm_is_user_mode,
7232 .get_guest_ip = kvm_get_guest_ip,
7233 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7234 };
7235
7236 #ifdef CONFIG_X86_64
7237 static void pvclock_gtod_update_fn(struct work_struct *work)
7238 {
7239 struct kvm *kvm;
7240
7241 struct kvm_vcpu *vcpu;
7242 int i;
7243
7244 mutex_lock(&kvm_lock);
7245 list_for_each_entry(kvm, &vm_list, vm_list)
7246 kvm_for_each_vcpu(i, vcpu, kvm)
7247 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7248 atomic_set(&kvm_guest_has_master_clock, 0);
7249 mutex_unlock(&kvm_lock);
7250 }
7251
7252 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7253
7254 /*
7255 * Notification about pvclock gtod data update.
7256 */
7257 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7258 void *priv)
7259 {
7260 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7261 struct timekeeper *tk = priv;
7262
7263 update_pvclock_gtod(tk);
7264
7265 /* disable master clock if host does not trust, or does not
7266 * use, TSC based clocksource.
7267 */
7268 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7269 atomic_read(&kvm_guest_has_master_clock) != 0)
7270 queue_work(system_long_wq, &pvclock_gtod_work);
7271
7272 return 0;
7273 }
7274
7275 static struct notifier_block pvclock_gtod_notifier = {
7276 .notifier_call = pvclock_gtod_notify,
7277 };
7278 #endif
7279
7280 int kvm_arch_init(void *opaque)
7281 {
7282 int r;
7283 struct kvm_x86_ops *ops = opaque;
7284
7285 if (kvm_x86_ops) {
7286 printk(KERN_ERR "kvm: already loaded the other module\n");
7287 r = -EEXIST;
7288 goto out;
7289 }
7290
7291 if (!ops->cpu_has_kvm_support()) {
7292 printk(KERN_ERR "kvm: no hardware support\n");
7293 r = -EOPNOTSUPP;
7294 goto out;
7295 }
7296 if (ops->disabled_by_bios()) {
7297 printk(KERN_ERR "kvm: disabled by bios\n");
7298 r = -EOPNOTSUPP;
7299 goto out;
7300 }
7301
7302 /*
7303 * KVM explicitly assumes that the guest has an FPU and
7304 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7305 * vCPU's FPU state as a fxregs_state struct.
7306 */
7307 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7308 printk(KERN_ERR "kvm: inadequate fpu\n");
7309 r = -EOPNOTSUPP;
7310 goto out;
7311 }
7312
7313 r = -ENOMEM;
7314 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7315 __alignof__(struct fpu), SLAB_ACCOUNT,
7316 NULL);
7317 if (!x86_fpu_cache) {
7318 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7319 goto out;
7320 }
7321
7322 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7323 if (!shared_msrs) {
7324 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7325 goto out_free_x86_fpu_cache;
7326 }
7327
7328 r = kvm_mmu_module_init();
7329 if (r)
7330 goto out_free_percpu;
7331
7332 kvm_x86_ops = ops;
7333
7334 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7335 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7336 PT_PRESENT_MASK, 0, sme_me_mask);
7337 kvm_timer_init();
7338
7339 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7340
7341 if (boot_cpu_has(X86_FEATURE_XSAVE))
7342 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7343
7344 kvm_lapic_init();
7345 if (pi_inject_timer == -1)
7346 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7347 #ifdef CONFIG_X86_64
7348 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7349
7350 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7351 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7352 #endif
7353
7354 return 0;
7355
7356 out_free_percpu:
7357 free_percpu(shared_msrs);
7358 out_free_x86_fpu_cache:
7359 kmem_cache_destroy(x86_fpu_cache);
7360 out:
7361 return r;
7362 }
7363
7364 void kvm_arch_exit(void)
7365 {
7366 #ifdef CONFIG_X86_64
7367 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7368 clear_hv_tscchange_cb();
7369 #endif
7370 kvm_lapic_exit();
7371 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7372
7373 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7374 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7375 CPUFREQ_TRANSITION_NOTIFIER);
7376 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7377 #ifdef CONFIG_X86_64
7378 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7379 #endif
7380 kvm_x86_ops = NULL;
7381 kvm_mmu_module_exit();
7382 free_percpu(shared_msrs);
7383 kmem_cache_destroy(x86_fpu_cache);
7384 }
7385
7386 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7387 {
7388 ++vcpu->stat.halt_exits;
7389 if (lapic_in_kernel(vcpu)) {
7390 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7391 return 1;
7392 } else {
7393 vcpu->run->exit_reason = KVM_EXIT_HLT;
7394 return 0;
7395 }
7396 }
7397 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7398
7399 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7400 {
7401 int ret = kvm_skip_emulated_instruction(vcpu);
7402 /*
7403 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7404 * KVM_EXIT_DEBUG here.
7405 */
7406 return kvm_vcpu_halt(vcpu) && ret;
7407 }
7408 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7409
7410 #ifdef CONFIG_X86_64
7411 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7412 unsigned long clock_type)
7413 {
7414 struct kvm_clock_pairing clock_pairing;
7415 struct timespec64 ts;
7416 u64 cycle;
7417 int ret;
7418
7419 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7420 return -KVM_EOPNOTSUPP;
7421
7422 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7423 return -KVM_EOPNOTSUPP;
7424
7425 clock_pairing.sec = ts.tv_sec;
7426 clock_pairing.nsec = ts.tv_nsec;
7427 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7428 clock_pairing.flags = 0;
7429 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7430
7431 ret = 0;
7432 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7433 sizeof(struct kvm_clock_pairing)))
7434 ret = -KVM_EFAULT;
7435
7436 return ret;
7437 }
7438 #endif
7439
7440 /*
7441 * kvm_pv_kick_cpu_op: Kick a vcpu.
7442 *
7443 * @apicid - apicid of vcpu to be kicked.
7444 */
7445 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7446 {
7447 struct kvm_lapic_irq lapic_irq;
7448
7449 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7450 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7451 lapic_irq.level = 0;
7452 lapic_irq.dest_id = apicid;
7453 lapic_irq.msi_redir_hint = false;
7454
7455 lapic_irq.delivery_mode = APIC_DM_REMRD;
7456 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7457 }
7458
7459 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7460 {
7461 if (!lapic_in_kernel(vcpu)) {
7462 WARN_ON_ONCE(vcpu->arch.apicv_active);
7463 return;
7464 }
7465 if (!vcpu->arch.apicv_active)
7466 return;
7467
7468 vcpu->arch.apicv_active = false;
7469 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7470 }
7471
7472 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7473 {
7474 struct kvm_vcpu *target = NULL;
7475 struct kvm_apic_map *map;
7476
7477 rcu_read_lock();
7478 map = rcu_dereference(kvm->arch.apic_map);
7479
7480 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7481 target = map->phys_map[dest_id]->vcpu;
7482
7483 rcu_read_unlock();
7484
7485 if (target && READ_ONCE(target->ready))
7486 kvm_vcpu_yield_to(target);
7487 }
7488
7489 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7490 {
7491 unsigned long nr, a0, a1, a2, a3, ret;
7492 int op_64_bit;
7493
7494 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7495 return kvm_hv_hypercall(vcpu);
7496
7497 nr = kvm_rax_read(vcpu);
7498 a0 = kvm_rbx_read(vcpu);
7499 a1 = kvm_rcx_read(vcpu);
7500 a2 = kvm_rdx_read(vcpu);
7501 a3 = kvm_rsi_read(vcpu);
7502
7503 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7504
7505 op_64_bit = is_64_bit_mode(vcpu);
7506 if (!op_64_bit) {
7507 nr &= 0xFFFFFFFF;
7508 a0 &= 0xFFFFFFFF;
7509 a1 &= 0xFFFFFFFF;
7510 a2 &= 0xFFFFFFFF;
7511 a3 &= 0xFFFFFFFF;
7512 }
7513
7514 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7515 ret = -KVM_EPERM;
7516 goto out;
7517 }
7518
7519 switch (nr) {
7520 case KVM_HC_VAPIC_POLL_IRQ:
7521 ret = 0;
7522 break;
7523 case KVM_HC_KICK_CPU:
7524 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7525 kvm_sched_yield(vcpu->kvm, a1);
7526 ret = 0;
7527 break;
7528 #ifdef CONFIG_X86_64
7529 case KVM_HC_CLOCK_PAIRING:
7530 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7531 break;
7532 #endif
7533 case KVM_HC_SEND_IPI:
7534 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7535 break;
7536 case KVM_HC_SCHED_YIELD:
7537 kvm_sched_yield(vcpu->kvm, a0);
7538 ret = 0;
7539 break;
7540 default:
7541 ret = -KVM_ENOSYS;
7542 break;
7543 }
7544 out:
7545 if (!op_64_bit)
7546 ret = (u32)ret;
7547 kvm_rax_write(vcpu, ret);
7548
7549 ++vcpu->stat.hypercalls;
7550 return kvm_skip_emulated_instruction(vcpu);
7551 }
7552 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7553
7554 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7555 {
7556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7557 char instruction[3];
7558 unsigned long rip = kvm_rip_read(vcpu);
7559
7560 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7561
7562 return emulator_write_emulated(ctxt, rip, instruction, 3,
7563 &ctxt->exception);
7564 }
7565
7566 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7567 {
7568 return vcpu->run->request_interrupt_window &&
7569 likely(!pic_in_kernel(vcpu->kvm));
7570 }
7571
7572 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7573 {
7574 struct kvm_run *kvm_run = vcpu->run;
7575
7576 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7577 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7578 kvm_run->cr8 = kvm_get_cr8(vcpu);
7579 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7580 kvm_run->ready_for_interrupt_injection =
7581 pic_in_kernel(vcpu->kvm) ||
7582 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7583 }
7584
7585 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7586 {
7587 int max_irr, tpr;
7588
7589 if (!kvm_x86_ops->update_cr8_intercept)
7590 return;
7591
7592 if (!lapic_in_kernel(vcpu))
7593 return;
7594
7595 if (vcpu->arch.apicv_active)
7596 return;
7597
7598 if (!vcpu->arch.apic->vapic_addr)
7599 max_irr = kvm_lapic_find_highest_irr(vcpu);
7600 else
7601 max_irr = -1;
7602
7603 if (max_irr != -1)
7604 max_irr >>= 4;
7605
7606 tpr = kvm_lapic_get_cr8(vcpu);
7607
7608 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7609 }
7610
7611 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7612 {
7613 int r;
7614
7615 /* try to reinject previous events if any */
7616
7617 if (vcpu->arch.exception.injected)
7618 kvm_x86_ops->queue_exception(vcpu);
7619 /*
7620 * Do not inject an NMI or interrupt if there is a pending
7621 * exception. Exceptions and interrupts are recognized at
7622 * instruction boundaries, i.e. the start of an instruction.
7623 * Trap-like exceptions, e.g. #DB, have higher priority than
7624 * NMIs and interrupts, i.e. traps are recognized before an
7625 * NMI/interrupt that's pending on the same instruction.
7626 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7627 * priority, but are only generated (pended) during instruction
7628 * execution, i.e. a pending fault-like exception means the
7629 * fault occurred on the *previous* instruction and must be
7630 * serviced prior to recognizing any new events in order to
7631 * fully complete the previous instruction.
7632 */
7633 else if (!vcpu->arch.exception.pending) {
7634 if (vcpu->arch.nmi_injected)
7635 kvm_x86_ops->set_nmi(vcpu);
7636 else if (vcpu->arch.interrupt.injected)
7637 kvm_x86_ops->set_irq(vcpu);
7638 }
7639
7640 /*
7641 * Call check_nested_events() even if we reinjected a previous event
7642 * in order for caller to determine if it should require immediate-exit
7643 * from L2 to L1 due to pending L1 events which require exit
7644 * from L2 to L1.
7645 */
7646 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7647 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7648 if (r != 0)
7649 return r;
7650 }
7651
7652 /* try to inject new event if pending */
7653 if (vcpu->arch.exception.pending) {
7654 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7655 vcpu->arch.exception.has_error_code,
7656 vcpu->arch.exception.error_code);
7657
7658 WARN_ON_ONCE(vcpu->arch.exception.injected);
7659 vcpu->arch.exception.pending = false;
7660 vcpu->arch.exception.injected = true;
7661
7662 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7663 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7664 X86_EFLAGS_RF);
7665
7666 if (vcpu->arch.exception.nr == DB_VECTOR) {
7667 /*
7668 * This code assumes that nSVM doesn't use
7669 * check_nested_events(). If it does, the
7670 * DR6/DR7 changes should happen before L1
7671 * gets a #VMEXIT for an intercepted #DB in
7672 * L2. (Under VMX, on the other hand, the
7673 * DR6/DR7 changes should not happen in the
7674 * event of a VM-exit to L1 for an intercepted
7675 * #DB in L2.)
7676 */
7677 kvm_deliver_exception_payload(vcpu);
7678 if (vcpu->arch.dr7 & DR7_GD) {
7679 vcpu->arch.dr7 &= ~DR7_GD;
7680 kvm_update_dr7(vcpu);
7681 }
7682 }
7683
7684 kvm_x86_ops->queue_exception(vcpu);
7685 }
7686
7687 /* Don't consider new event if we re-injected an event */
7688 if (kvm_event_needs_reinjection(vcpu))
7689 return 0;
7690
7691 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7692 kvm_x86_ops->smi_allowed(vcpu)) {
7693 vcpu->arch.smi_pending = false;
7694 ++vcpu->arch.smi_count;
7695 enter_smm(vcpu);
7696 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7697 --vcpu->arch.nmi_pending;
7698 vcpu->arch.nmi_injected = true;
7699 kvm_x86_ops->set_nmi(vcpu);
7700 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7701 /*
7702 * Because interrupts can be injected asynchronously, we are
7703 * calling check_nested_events again here to avoid a race condition.
7704 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7705 * proposal and current concerns. Perhaps we should be setting
7706 * KVM_REQ_EVENT only on certain events and not unconditionally?
7707 */
7708 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7709 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7710 if (r != 0)
7711 return r;
7712 }
7713 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7714 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7715 false);
7716 kvm_x86_ops->set_irq(vcpu);
7717 }
7718 }
7719
7720 return 0;
7721 }
7722
7723 static void process_nmi(struct kvm_vcpu *vcpu)
7724 {
7725 unsigned limit = 2;
7726
7727 /*
7728 * x86 is limited to one NMI running, and one NMI pending after it.
7729 * If an NMI is already in progress, limit further NMIs to just one.
7730 * Otherwise, allow two (and we'll inject the first one immediately).
7731 */
7732 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7733 limit = 1;
7734
7735 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7736 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7737 kvm_make_request(KVM_REQ_EVENT, vcpu);
7738 }
7739
7740 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7741 {
7742 u32 flags = 0;
7743 flags |= seg->g << 23;
7744 flags |= seg->db << 22;
7745 flags |= seg->l << 21;
7746 flags |= seg->avl << 20;
7747 flags |= seg->present << 15;
7748 flags |= seg->dpl << 13;
7749 flags |= seg->s << 12;
7750 flags |= seg->type << 8;
7751 return flags;
7752 }
7753
7754 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7755 {
7756 struct kvm_segment seg;
7757 int offset;
7758
7759 kvm_get_segment(vcpu, &seg, n);
7760 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7761
7762 if (n < 3)
7763 offset = 0x7f84 + n * 12;
7764 else
7765 offset = 0x7f2c + (n - 3) * 12;
7766
7767 put_smstate(u32, buf, offset + 8, seg.base);
7768 put_smstate(u32, buf, offset + 4, seg.limit);
7769 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7770 }
7771
7772 #ifdef CONFIG_X86_64
7773 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7774 {
7775 struct kvm_segment seg;
7776 int offset;
7777 u16 flags;
7778
7779 kvm_get_segment(vcpu, &seg, n);
7780 offset = 0x7e00 + n * 16;
7781
7782 flags = enter_smm_get_segment_flags(&seg) >> 8;
7783 put_smstate(u16, buf, offset, seg.selector);
7784 put_smstate(u16, buf, offset + 2, flags);
7785 put_smstate(u32, buf, offset + 4, seg.limit);
7786 put_smstate(u64, buf, offset + 8, seg.base);
7787 }
7788 #endif
7789
7790 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7791 {
7792 struct desc_ptr dt;
7793 struct kvm_segment seg;
7794 unsigned long val;
7795 int i;
7796
7797 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7798 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7799 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7800 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7801
7802 for (i = 0; i < 8; i++)
7803 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7804
7805 kvm_get_dr(vcpu, 6, &val);
7806 put_smstate(u32, buf, 0x7fcc, (u32)val);
7807 kvm_get_dr(vcpu, 7, &val);
7808 put_smstate(u32, buf, 0x7fc8, (u32)val);
7809
7810 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7811 put_smstate(u32, buf, 0x7fc4, seg.selector);
7812 put_smstate(u32, buf, 0x7f64, seg.base);
7813 put_smstate(u32, buf, 0x7f60, seg.limit);
7814 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7815
7816 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7817 put_smstate(u32, buf, 0x7fc0, seg.selector);
7818 put_smstate(u32, buf, 0x7f80, seg.base);
7819 put_smstate(u32, buf, 0x7f7c, seg.limit);
7820 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7821
7822 kvm_x86_ops->get_gdt(vcpu, &dt);
7823 put_smstate(u32, buf, 0x7f74, dt.address);
7824 put_smstate(u32, buf, 0x7f70, dt.size);
7825
7826 kvm_x86_ops->get_idt(vcpu, &dt);
7827 put_smstate(u32, buf, 0x7f58, dt.address);
7828 put_smstate(u32, buf, 0x7f54, dt.size);
7829
7830 for (i = 0; i < 6; i++)
7831 enter_smm_save_seg_32(vcpu, buf, i);
7832
7833 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7834
7835 /* revision id */
7836 put_smstate(u32, buf, 0x7efc, 0x00020000);
7837 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7838 }
7839
7840 #ifdef CONFIG_X86_64
7841 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7842 {
7843 struct desc_ptr dt;
7844 struct kvm_segment seg;
7845 unsigned long val;
7846 int i;
7847
7848 for (i = 0; i < 16; i++)
7849 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7850
7851 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7852 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7853
7854 kvm_get_dr(vcpu, 6, &val);
7855 put_smstate(u64, buf, 0x7f68, val);
7856 kvm_get_dr(vcpu, 7, &val);
7857 put_smstate(u64, buf, 0x7f60, val);
7858
7859 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7860 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7861 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7862
7863 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7864
7865 /* revision id */
7866 put_smstate(u32, buf, 0x7efc, 0x00020064);
7867
7868 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7869
7870 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7871 put_smstate(u16, buf, 0x7e90, seg.selector);
7872 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7873 put_smstate(u32, buf, 0x7e94, seg.limit);
7874 put_smstate(u64, buf, 0x7e98, seg.base);
7875
7876 kvm_x86_ops->get_idt(vcpu, &dt);
7877 put_smstate(u32, buf, 0x7e84, dt.size);
7878 put_smstate(u64, buf, 0x7e88, dt.address);
7879
7880 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7881 put_smstate(u16, buf, 0x7e70, seg.selector);
7882 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7883 put_smstate(u32, buf, 0x7e74, seg.limit);
7884 put_smstate(u64, buf, 0x7e78, seg.base);
7885
7886 kvm_x86_ops->get_gdt(vcpu, &dt);
7887 put_smstate(u32, buf, 0x7e64, dt.size);
7888 put_smstate(u64, buf, 0x7e68, dt.address);
7889
7890 for (i = 0; i < 6; i++)
7891 enter_smm_save_seg_64(vcpu, buf, i);
7892 }
7893 #endif
7894
7895 static void enter_smm(struct kvm_vcpu *vcpu)
7896 {
7897 struct kvm_segment cs, ds;
7898 struct desc_ptr dt;
7899 char buf[512];
7900 u32 cr0;
7901
7902 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7903 memset(buf, 0, 512);
7904 #ifdef CONFIG_X86_64
7905 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7906 enter_smm_save_state_64(vcpu, buf);
7907 else
7908 #endif
7909 enter_smm_save_state_32(vcpu, buf);
7910
7911 /*
7912 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7913 * vCPU state (e.g. leave guest mode) after we've saved the state into
7914 * the SMM state-save area.
7915 */
7916 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7917
7918 vcpu->arch.hflags |= HF_SMM_MASK;
7919 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7920
7921 if (kvm_x86_ops->get_nmi_mask(vcpu))
7922 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7923 else
7924 kvm_x86_ops->set_nmi_mask(vcpu, true);
7925
7926 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7927 kvm_rip_write(vcpu, 0x8000);
7928
7929 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7930 kvm_x86_ops->set_cr0(vcpu, cr0);
7931 vcpu->arch.cr0 = cr0;
7932
7933 kvm_x86_ops->set_cr4(vcpu, 0);
7934
7935 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7936 dt.address = dt.size = 0;
7937 kvm_x86_ops->set_idt(vcpu, &dt);
7938
7939 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7940
7941 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7942 cs.base = vcpu->arch.smbase;
7943
7944 ds.selector = 0;
7945 ds.base = 0;
7946
7947 cs.limit = ds.limit = 0xffffffff;
7948 cs.type = ds.type = 0x3;
7949 cs.dpl = ds.dpl = 0;
7950 cs.db = ds.db = 0;
7951 cs.s = ds.s = 1;
7952 cs.l = ds.l = 0;
7953 cs.g = ds.g = 1;
7954 cs.avl = ds.avl = 0;
7955 cs.present = ds.present = 1;
7956 cs.unusable = ds.unusable = 0;
7957 cs.padding = ds.padding = 0;
7958
7959 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7960 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7961 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7962 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7963 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7964 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7965
7966 #ifdef CONFIG_X86_64
7967 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7968 kvm_x86_ops->set_efer(vcpu, 0);
7969 #endif
7970
7971 kvm_update_cpuid(vcpu);
7972 kvm_mmu_reset_context(vcpu);
7973 }
7974
7975 static void process_smi(struct kvm_vcpu *vcpu)
7976 {
7977 vcpu->arch.smi_pending = true;
7978 kvm_make_request(KVM_REQ_EVENT, vcpu);
7979 }
7980
7981 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
7982 unsigned long *vcpu_bitmap)
7983 {
7984 cpumask_var_t cpus;
7985
7986 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
7987
7988 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
7989 vcpu_bitmap, cpus);
7990
7991 free_cpumask_var(cpus);
7992 }
7993
7994 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7995 {
7996 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7997 }
7998
7999 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8000 {
8001 if (!kvm_apic_present(vcpu))
8002 return;
8003
8004 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8005
8006 if (irqchip_split(vcpu->kvm))
8007 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8008 else {
8009 if (vcpu->arch.apicv_active)
8010 kvm_x86_ops->sync_pir_to_irr(vcpu);
8011 if (ioapic_in_kernel(vcpu->kvm))
8012 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8013 }
8014
8015 if (is_guest_mode(vcpu))
8016 vcpu->arch.load_eoi_exitmap_pending = true;
8017 else
8018 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8019 }
8020
8021 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8022 {
8023 u64 eoi_exit_bitmap[4];
8024
8025 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8026 return;
8027
8028 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8029 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8030 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8031 }
8032
8033 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8034 unsigned long start, unsigned long end,
8035 bool blockable)
8036 {
8037 unsigned long apic_address;
8038
8039 /*
8040 * The physical address of apic access page is stored in the VMCS.
8041 * Update it when it becomes invalid.
8042 */
8043 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8044 if (start <= apic_address && apic_address < end)
8045 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8046
8047 return 0;
8048 }
8049
8050 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8051 {
8052 struct page *page = NULL;
8053
8054 if (!lapic_in_kernel(vcpu))
8055 return;
8056
8057 if (!kvm_x86_ops->set_apic_access_page_addr)
8058 return;
8059
8060 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8061 if (is_error_page(page))
8062 return;
8063 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8064
8065 /*
8066 * Do not pin apic access page in memory, the MMU notifier
8067 * will call us again if it is migrated or swapped out.
8068 */
8069 put_page(page);
8070 }
8071
8072 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8073 {
8074 smp_send_reschedule(vcpu->cpu);
8075 }
8076 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8077
8078 /*
8079 * Returns 1 to let vcpu_run() continue the guest execution loop without
8080 * exiting to the userspace. Otherwise, the value will be returned to the
8081 * userspace.
8082 */
8083 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8084 {
8085 int r;
8086 bool req_int_win =
8087 dm_request_for_irq_injection(vcpu) &&
8088 kvm_cpu_accept_dm_intr(vcpu);
8089 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8090
8091 bool req_immediate_exit = false;
8092
8093 if (kvm_request_pending(vcpu)) {
8094 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8095 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8096 r = 0;
8097 goto out;
8098 }
8099 }
8100 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8101 kvm_mmu_unload(vcpu);
8102 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8103 __kvm_migrate_timers(vcpu);
8104 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8105 kvm_gen_update_masterclock(vcpu->kvm);
8106 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8107 kvm_gen_kvmclock_update(vcpu);
8108 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8109 r = kvm_guest_time_update(vcpu);
8110 if (unlikely(r))
8111 goto out;
8112 }
8113 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8114 kvm_mmu_sync_roots(vcpu);
8115 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8116 kvm_mmu_load_cr3(vcpu);
8117 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8118 kvm_vcpu_flush_tlb(vcpu, true);
8119 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8120 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8121 r = 0;
8122 goto out;
8123 }
8124 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8125 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8126 vcpu->mmio_needed = 0;
8127 r = 0;
8128 goto out;
8129 }
8130 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8131 /* Page is swapped out. Do synthetic halt */
8132 vcpu->arch.apf.halted = true;
8133 r = 1;
8134 goto out;
8135 }
8136 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8137 record_steal_time(vcpu);
8138 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8139 process_smi(vcpu);
8140 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8141 process_nmi(vcpu);
8142 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8143 kvm_pmu_handle_event(vcpu);
8144 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8145 kvm_pmu_deliver_pmi(vcpu);
8146 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8147 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8148 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8149 vcpu->arch.ioapic_handled_vectors)) {
8150 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8151 vcpu->run->eoi.vector =
8152 vcpu->arch.pending_ioapic_eoi;
8153 r = 0;
8154 goto out;
8155 }
8156 }
8157 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8158 vcpu_scan_ioapic(vcpu);
8159 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8160 vcpu_load_eoi_exitmap(vcpu);
8161 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8162 kvm_vcpu_reload_apic_access_page(vcpu);
8163 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8164 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8165 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8166 r = 0;
8167 goto out;
8168 }
8169 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8170 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8171 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8172 r = 0;
8173 goto out;
8174 }
8175 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8176 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8177 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8178 r = 0;
8179 goto out;
8180 }
8181
8182 /*
8183 * KVM_REQ_HV_STIMER has to be processed after
8184 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8185 * depend on the guest clock being up-to-date
8186 */
8187 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8188 kvm_hv_process_stimers(vcpu);
8189 }
8190
8191 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8192 ++vcpu->stat.req_event;
8193 kvm_apic_accept_events(vcpu);
8194 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8195 r = 1;
8196 goto out;
8197 }
8198
8199 if (inject_pending_event(vcpu, req_int_win) != 0)
8200 req_immediate_exit = true;
8201 else {
8202 /* Enable SMI/NMI/IRQ window open exits if needed.
8203 *
8204 * SMIs have three cases:
8205 * 1) They can be nested, and then there is nothing to
8206 * do here because RSM will cause a vmexit anyway.
8207 * 2) There is an ISA-specific reason why SMI cannot be
8208 * injected, and the moment when this changes can be
8209 * intercepted.
8210 * 3) Or the SMI can be pending because
8211 * inject_pending_event has completed the injection
8212 * of an IRQ or NMI from the previous vmexit, and
8213 * then we request an immediate exit to inject the
8214 * SMI.
8215 */
8216 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8217 if (!kvm_x86_ops->enable_smi_window(vcpu))
8218 req_immediate_exit = true;
8219 if (vcpu->arch.nmi_pending)
8220 kvm_x86_ops->enable_nmi_window(vcpu);
8221 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8222 kvm_x86_ops->enable_irq_window(vcpu);
8223 WARN_ON(vcpu->arch.exception.pending);
8224 }
8225
8226 if (kvm_lapic_enabled(vcpu)) {
8227 update_cr8_intercept(vcpu);
8228 kvm_lapic_sync_to_vapic(vcpu);
8229 }
8230 }
8231
8232 r = kvm_mmu_reload(vcpu);
8233 if (unlikely(r)) {
8234 goto cancel_injection;
8235 }
8236
8237 preempt_disable();
8238
8239 kvm_x86_ops->prepare_guest_switch(vcpu);
8240
8241 /*
8242 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8243 * IPI are then delayed after guest entry, which ensures that they
8244 * result in virtual interrupt delivery.
8245 */
8246 local_irq_disable();
8247 vcpu->mode = IN_GUEST_MODE;
8248
8249 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8250
8251 /*
8252 * 1) We should set ->mode before checking ->requests. Please see
8253 * the comment in kvm_vcpu_exiting_guest_mode().
8254 *
8255 * 2) For APICv, we should set ->mode before checking PID.ON. This
8256 * pairs with the memory barrier implicit in pi_test_and_set_on
8257 * (see vmx_deliver_posted_interrupt).
8258 *
8259 * 3) This also orders the write to mode from any reads to the page
8260 * tables done while the VCPU is running. Please see the comment
8261 * in kvm_flush_remote_tlbs.
8262 */
8263 smp_mb__after_srcu_read_unlock();
8264
8265 /*
8266 * This handles the case where a posted interrupt was
8267 * notified with kvm_vcpu_kick.
8268 */
8269 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8270 kvm_x86_ops->sync_pir_to_irr(vcpu);
8271
8272 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8273 || need_resched() || signal_pending(current)) {
8274 vcpu->mode = OUTSIDE_GUEST_MODE;
8275 smp_wmb();
8276 local_irq_enable();
8277 preempt_enable();
8278 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8279 r = 1;
8280 goto cancel_injection;
8281 }
8282
8283 if (req_immediate_exit) {
8284 kvm_make_request(KVM_REQ_EVENT, vcpu);
8285 kvm_x86_ops->request_immediate_exit(vcpu);
8286 }
8287
8288 trace_kvm_entry(vcpu->vcpu_id);
8289 guest_enter_irqoff();
8290
8291 fpregs_assert_state_consistent();
8292 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8293 switch_fpu_return();
8294
8295 if (unlikely(vcpu->arch.switch_db_regs)) {
8296 set_debugreg(0, 7);
8297 set_debugreg(vcpu->arch.eff_db[0], 0);
8298 set_debugreg(vcpu->arch.eff_db[1], 1);
8299 set_debugreg(vcpu->arch.eff_db[2], 2);
8300 set_debugreg(vcpu->arch.eff_db[3], 3);
8301 set_debugreg(vcpu->arch.dr6, 6);
8302 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8303 }
8304
8305 kvm_x86_ops->run(vcpu);
8306
8307 /*
8308 * Do this here before restoring debug registers on the host. And
8309 * since we do this before handling the vmexit, a DR access vmexit
8310 * can (a) read the correct value of the debug registers, (b) set
8311 * KVM_DEBUGREG_WONT_EXIT again.
8312 */
8313 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8314 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8315 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8316 kvm_update_dr0123(vcpu);
8317 kvm_update_dr6(vcpu);
8318 kvm_update_dr7(vcpu);
8319 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8320 }
8321
8322 /*
8323 * If the guest has used debug registers, at least dr7
8324 * will be disabled while returning to the host.
8325 * If we don't have active breakpoints in the host, we don't
8326 * care about the messed up debug address registers. But if
8327 * we have some of them active, restore the old state.
8328 */
8329 if (hw_breakpoint_active())
8330 hw_breakpoint_restore();
8331
8332 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8333
8334 vcpu->mode = OUTSIDE_GUEST_MODE;
8335 smp_wmb();
8336
8337 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
8338
8339 /*
8340 * Consume any pending interrupts, including the possible source of
8341 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8342 * An instruction is required after local_irq_enable() to fully unblock
8343 * interrupts on processors that implement an interrupt shadow, the
8344 * stat.exits increment will do nicely.
8345 */
8346 kvm_before_interrupt(vcpu);
8347 local_irq_enable();
8348 ++vcpu->stat.exits;
8349 local_irq_disable();
8350 kvm_after_interrupt(vcpu);
8351
8352 guest_exit_irqoff();
8353 if (lapic_in_kernel(vcpu)) {
8354 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8355 if (delta != S64_MIN) {
8356 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8357 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8358 }
8359 }
8360
8361 local_irq_enable();
8362 preempt_enable();
8363
8364 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8365
8366 /*
8367 * Profile KVM exit RIPs:
8368 */
8369 if (unlikely(prof_on == KVM_PROFILING)) {
8370 unsigned long rip = kvm_rip_read(vcpu);
8371 profile_hit(KVM_PROFILING, (void *)rip);
8372 }
8373
8374 if (unlikely(vcpu->arch.tsc_always_catchup))
8375 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8376
8377 if (vcpu->arch.apic_attention)
8378 kvm_lapic_sync_from_vapic(vcpu);
8379
8380 vcpu->arch.gpa_available = false;
8381 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
8382 return r;
8383
8384 cancel_injection:
8385 kvm_x86_ops->cancel_injection(vcpu);
8386 if (unlikely(vcpu->arch.apic_attention))
8387 kvm_lapic_sync_from_vapic(vcpu);
8388 out:
8389 return r;
8390 }
8391
8392 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8393 {
8394 if (!kvm_arch_vcpu_runnable(vcpu) &&
8395 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8396 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8397 kvm_vcpu_block(vcpu);
8398 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8399
8400 if (kvm_x86_ops->post_block)
8401 kvm_x86_ops->post_block(vcpu);
8402
8403 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8404 return 1;
8405 }
8406
8407 kvm_apic_accept_events(vcpu);
8408 switch(vcpu->arch.mp_state) {
8409 case KVM_MP_STATE_HALTED:
8410 vcpu->arch.pv.pv_unhalted = false;
8411 vcpu->arch.mp_state =
8412 KVM_MP_STATE_RUNNABLE;
8413 /* fall through */
8414 case KVM_MP_STATE_RUNNABLE:
8415 vcpu->arch.apf.halted = false;
8416 break;
8417 case KVM_MP_STATE_INIT_RECEIVED:
8418 break;
8419 default:
8420 return -EINTR;
8421 break;
8422 }
8423 return 1;
8424 }
8425
8426 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8427 {
8428 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8429 kvm_x86_ops->check_nested_events(vcpu, false);
8430
8431 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8432 !vcpu->arch.apf.halted);
8433 }
8434
8435 static int vcpu_run(struct kvm_vcpu *vcpu)
8436 {
8437 int r;
8438 struct kvm *kvm = vcpu->kvm;
8439
8440 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8441 vcpu->arch.l1tf_flush_l1d = true;
8442
8443 for (;;) {
8444 if (kvm_vcpu_running(vcpu)) {
8445 r = vcpu_enter_guest(vcpu);
8446 } else {
8447 r = vcpu_block(kvm, vcpu);
8448 }
8449
8450 if (r <= 0)
8451 break;
8452
8453 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8454 if (kvm_cpu_has_pending_timer(vcpu))
8455 kvm_inject_pending_timer_irqs(vcpu);
8456
8457 if (dm_request_for_irq_injection(vcpu) &&
8458 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8459 r = 0;
8460 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8461 ++vcpu->stat.request_irq_exits;
8462 break;
8463 }
8464
8465 kvm_check_async_pf_completion(vcpu);
8466
8467 if (signal_pending(current)) {
8468 r = -EINTR;
8469 vcpu->run->exit_reason = KVM_EXIT_INTR;
8470 ++vcpu->stat.signal_exits;
8471 break;
8472 }
8473 if (need_resched()) {
8474 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8475 cond_resched();
8476 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8477 }
8478 }
8479
8480 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8481
8482 return r;
8483 }
8484
8485 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8486 {
8487 int r;
8488
8489 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8490 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8491 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8492 return r;
8493 }
8494
8495 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8496 {
8497 BUG_ON(!vcpu->arch.pio.count);
8498
8499 return complete_emulated_io(vcpu);
8500 }
8501
8502 /*
8503 * Implements the following, as a state machine:
8504 *
8505 * read:
8506 * for each fragment
8507 * for each mmio piece in the fragment
8508 * write gpa, len
8509 * exit
8510 * copy data
8511 * execute insn
8512 *
8513 * write:
8514 * for each fragment
8515 * for each mmio piece in the fragment
8516 * write gpa, len
8517 * copy data
8518 * exit
8519 */
8520 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8521 {
8522 struct kvm_run *run = vcpu->run;
8523 struct kvm_mmio_fragment *frag;
8524 unsigned len;
8525
8526 BUG_ON(!vcpu->mmio_needed);
8527
8528 /* Complete previous fragment */
8529 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8530 len = min(8u, frag->len);
8531 if (!vcpu->mmio_is_write)
8532 memcpy(frag->data, run->mmio.data, len);
8533
8534 if (frag->len <= 8) {
8535 /* Switch to the next fragment. */
8536 frag++;
8537 vcpu->mmio_cur_fragment++;
8538 } else {
8539 /* Go forward to the next mmio piece. */
8540 frag->data += len;
8541 frag->gpa += len;
8542 frag->len -= len;
8543 }
8544
8545 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8546 vcpu->mmio_needed = 0;
8547
8548 /* FIXME: return into emulator if single-stepping. */
8549 if (vcpu->mmio_is_write)
8550 return 1;
8551 vcpu->mmio_read_completed = 1;
8552 return complete_emulated_io(vcpu);
8553 }
8554
8555 run->exit_reason = KVM_EXIT_MMIO;
8556 run->mmio.phys_addr = frag->gpa;
8557 if (vcpu->mmio_is_write)
8558 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8559 run->mmio.len = min(8u, frag->len);
8560 run->mmio.is_write = vcpu->mmio_is_write;
8561 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8562 return 0;
8563 }
8564
8565 static void kvm_save_current_fpu(struct fpu *fpu)
8566 {
8567 /*
8568 * If the target FPU state is not resident in the CPU registers, just
8569 * memcpy() from current, else save CPU state directly to the target.
8570 */
8571 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8572 memcpy(&fpu->state, &current->thread.fpu.state,
8573 fpu_kernel_xstate_size);
8574 else
8575 copy_fpregs_to_fpstate(fpu);
8576 }
8577
8578 /* Swap (qemu) user FPU context for the guest FPU context. */
8579 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8580 {
8581 fpregs_lock();
8582
8583 kvm_save_current_fpu(vcpu->arch.user_fpu);
8584
8585 /* PKRU is separately restored in kvm_x86_ops->run. */
8586 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8587 ~XFEATURE_MASK_PKRU);
8588
8589 fpregs_mark_activate();
8590 fpregs_unlock();
8591
8592 trace_kvm_fpu(1);
8593 }
8594
8595 /* When vcpu_run ends, restore user space FPU context. */
8596 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8597 {
8598 fpregs_lock();
8599
8600 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8601
8602 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8603
8604 fpregs_mark_activate();
8605 fpregs_unlock();
8606
8607 ++vcpu->stat.fpu_reload;
8608 trace_kvm_fpu(0);
8609 }
8610
8611 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8612 {
8613 int r;
8614
8615 vcpu_load(vcpu);
8616 kvm_sigset_activate(vcpu);
8617 kvm_load_guest_fpu(vcpu);
8618
8619 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8620 if (kvm_run->immediate_exit) {
8621 r = -EINTR;
8622 goto out;
8623 }
8624 kvm_vcpu_block(vcpu);
8625 kvm_apic_accept_events(vcpu);
8626 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8627 r = -EAGAIN;
8628 if (signal_pending(current)) {
8629 r = -EINTR;
8630 vcpu->run->exit_reason = KVM_EXIT_INTR;
8631 ++vcpu->stat.signal_exits;
8632 }
8633 goto out;
8634 }
8635
8636 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8637 r = -EINVAL;
8638 goto out;
8639 }
8640
8641 if (vcpu->run->kvm_dirty_regs) {
8642 r = sync_regs(vcpu);
8643 if (r != 0)
8644 goto out;
8645 }
8646
8647 /* re-sync apic's tpr */
8648 if (!lapic_in_kernel(vcpu)) {
8649 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8650 r = -EINVAL;
8651 goto out;
8652 }
8653 }
8654
8655 if (unlikely(vcpu->arch.complete_userspace_io)) {
8656 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8657 vcpu->arch.complete_userspace_io = NULL;
8658 r = cui(vcpu);
8659 if (r <= 0)
8660 goto out;
8661 } else
8662 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8663
8664 if (kvm_run->immediate_exit)
8665 r = -EINTR;
8666 else
8667 r = vcpu_run(vcpu);
8668
8669 out:
8670 kvm_put_guest_fpu(vcpu);
8671 if (vcpu->run->kvm_valid_regs)
8672 store_regs(vcpu);
8673 post_kvm_run_save(vcpu);
8674 kvm_sigset_deactivate(vcpu);
8675
8676 vcpu_put(vcpu);
8677 return r;
8678 }
8679
8680 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8681 {
8682 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8683 /*
8684 * We are here if userspace calls get_regs() in the middle of
8685 * instruction emulation. Registers state needs to be copied
8686 * back from emulation context to vcpu. Userspace shouldn't do
8687 * that usually, but some bad designed PV devices (vmware
8688 * backdoor interface) need this to work
8689 */
8690 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8691 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8692 }
8693 regs->rax = kvm_rax_read(vcpu);
8694 regs->rbx = kvm_rbx_read(vcpu);
8695 regs->rcx = kvm_rcx_read(vcpu);
8696 regs->rdx = kvm_rdx_read(vcpu);
8697 regs->rsi = kvm_rsi_read(vcpu);
8698 regs->rdi = kvm_rdi_read(vcpu);
8699 regs->rsp = kvm_rsp_read(vcpu);
8700 regs->rbp = kvm_rbp_read(vcpu);
8701 #ifdef CONFIG_X86_64
8702 regs->r8 = kvm_r8_read(vcpu);
8703 regs->r9 = kvm_r9_read(vcpu);
8704 regs->r10 = kvm_r10_read(vcpu);
8705 regs->r11 = kvm_r11_read(vcpu);
8706 regs->r12 = kvm_r12_read(vcpu);
8707 regs->r13 = kvm_r13_read(vcpu);
8708 regs->r14 = kvm_r14_read(vcpu);
8709 regs->r15 = kvm_r15_read(vcpu);
8710 #endif
8711
8712 regs->rip = kvm_rip_read(vcpu);
8713 regs->rflags = kvm_get_rflags(vcpu);
8714 }
8715
8716 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8717 {
8718 vcpu_load(vcpu);
8719 __get_regs(vcpu, regs);
8720 vcpu_put(vcpu);
8721 return 0;
8722 }
8723
8724 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8725 {
8726 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8727 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8728
8729 kvm_rax_write(vcpu, regs->rax);
8730 kvm_rbx_write(vcpu, regs->rbx);
8731 kvm_rcx_write(vcpu, regs->rcx);
8732 kvm_rdx_write(vcpu, regs->rdx);
8733 kvm_rsi_write(vcpu, regs->rsi);
8734 kvm_rdi_write(vcpu, regs->rdi);
8735 kvm_rsp_write(vcpu, regs->rsp);
8736 kvm_rbp_write(vcpu, regs->rbp);
8737 #ifdef CONFIG_X86_64
8738 kvm_r8_write(vcpu, regs->r8);
8739 kvm_r9_write(vcpu, regs->r9);
8740 kvm_r10_write(vcpu, regs->r10);
8741 kvm_r11_write(vcpu, regs->r11);
8742 kvm_r12_write(vcpu, regs->r12);
8743 kvm_r13_write(vcpu, regs->r13);
8744 kvm_r14_write(vcpu, regs->r14);
8745 kvm_r15_write(vcpu, regs->r15);
8746 #endif
8747
8748 kvm_rip_write(vcpu, regs->rip);
8749 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8750
8751 vcpu->arch.exception.pending = false;
8752
8753 kvm_make_request(KVM_REQ_EVENT, vcpu);
8754 }
8755
8756 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8757 {
8758 vcpu_load(vcpu);
8759 __set_regs(vcpu, regs);
8760 vcpu_put(vcpu);
8761 return 0;
8762 }
8763
8764 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8765 {
8766 struct kvm_segment cs;
8767
8768 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8769 *db = cs.db;
8770 *l = cs.l;
8771 }
8772 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8773
8774 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8775 {
8776 struct desc_ptr dt;
8777
8778 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8779 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8780 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8781 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8782 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8783 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8784
8785 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8786 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8787
8788 kvm_x86_ops->get_idt(vcpu, &dt);
8789 sregs->idt.limit = dt.size;
8790 sregs->idt.base = dt.address;
8791 kvm_x86_ops->get_gdt(vcpu, &dt);
8792 sregs->gdt.limit = dt.size;
8793 sregs->gdt.base = dt.address;
8794
8795 sregs->cr0 = kvm_read_cr0(vcpu);
8796 sregs->cr2 = vcpu->arch.cr2;
8797 sregs->cr3 = kvm_read_cr3(vcpu);
8798 sregs->cr4 = kvm_read_cr4(vcpu);
8799 sregs->cr8 = kvm_get_cr8(vcpu);
8800 sregs->efer = vcpu->arch.efer;
8801 sregs->apic_base = kvm_get_apic_base(vcpu);
8802
8803 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8804
8805 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8806 set_bit(vcpu->arch.interrupt.nr,
8807 (unsigned long *)sregs->interrupt_bitmap);
8808 }
8809
8810 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8811 struct kvm_sregs *sregs)
8812 {
8813 vcpu_load(vcpu);
8814 __get_sregs(vcpu, sregs);
8815 vcpu_put(vcpu);
8816 return 0;
8817 }
8818
8819 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8820 struct kvm_mp_state *mp_state)
8821 {
8822 vcpu_load(vcpu);
8823 if (kvm_mpx_supported())
8824 kvm_load_guest_fpu(vcpu);
8825
8826 kvm_apic_accept_events(vcpu);
8827 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8828 vcpu->arch.pv.pv_unhalted)
8829 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8830 else
8831 mp_state->mp_state = vcpu->arch.mp_state;
8832
8833 if (kvm_mpx_supported())
8834 kvm_put_guest_fpu(vcpu);
8835 vcpu_put(vcpu);
8836 return 0;
8837 }
8838
8839 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8840 struct kvm_mp_state *mp_state)
8841 {
8842 int ret = -EINVAL;
8843
8844 vcpu_load(vcpu);
8845
8846 if (!lapic_in_kernel(vcpu) &&
8847 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8848 goto out;
8849
8850 /*
8851 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8852 * INIT state; latched init should be reported using
8853 * KVM_SET_VCPU_EVENTS, so reject it here.
8854 */
8855 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8856 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8857 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8858 goto out;
8859
8860 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8861 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8862 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8863 } else
8864 vcpu->arch.mp_state = mp_state->mp_state;
8865 kvm_make_request(KVM_REQ_EVENT, vcpu);
8866
8867 ret = 0;
8868 out:
8869 vcpu_put(vcpu);
8870 return ret;
8871 }
8872
8873 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8874 int reason, bool has_error_code, u32 error_code)
8875 {
8876 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8877 int ret;
8878
8879 init_emulate_ctxt(vcpu);
8880
8881 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8882 has_error_code, error_code);
8883 if (ret) {
8884 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8885 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8886 vcpu->run->internal.ndata = 0;
8887 return 0;
8888 }
8889
8890 kvm_rip_write(vcpu, ctxt->eip);
8891 kvm_set_rflags(vcpu, ctxt->eflags);
8892 kvm_make_request(KVM_REQ_EVENT, vcpu);
8893 return 1;
8894 }
8895 EXPORT_SYMBOL_GPL(kvm_task_switch);
8896
8897 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8898 {
8899 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8900 /*
8901 * When EFER.LME and CR0.PG are set, the processor is in
8902 * 64-bit mode (though maybe in a 32-bit code segment).
8903 * CR4.PAE and EFER.LMA must be set.
8904 */
8905 if (!(sregs->cr4 & X86_CR4_PAE)
8906 || !(sregs->efer & EFER_LMA))
8907 return -EINVAL;
8908 } else {
8909 /*
8910 * Not in 64-bit mode: EFER.LMA is clear and the code
8911 * segment cannot be 64-bit.
8912 */
8913 if (sregs->efer & EFER_LMA || sregs->cs.l)
8914 return -EINVAL;
8915 }
8916
8917 return kvm_valid_cr4(vcpu, sregs->cr4);
8918 }
8919
8920 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8921 {
8922 struct msr_data apic_base_msr;
8923 int mmu_reset_needed = 0;
8924 int cpuid_update_needed = 0;
8925 int pending_vec, max_bits, idx;
8926 struct desc_ptr dt;
8927 int ret = -EINVAL;
8928
8929 if (kvm_valid_sregs(vcpu, sregs))
8930 goto out;
8931
8932 apic_base_msr.data = sregs->apic_base;
8933 apic_base_msr.host_initiated = true;
8934 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8935 goto out;
8936
8937 dt.size = sregs->idt.limit;
8938 dt.address = sregs->idt.base;
8939 kvm_x86_ops->set_idt(vcpu, &dt);
8940 dt.size = sregs->gdt.limit;
8941 dt.address = sregs->gdt.base;
8942 kvm_x86_ops->set_gdt(vcpu, &dt);
8943
8944 vcpu->arch.cr2 = sregs->cr2;
8945 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8946 vcpu->arch.cr3 = sregs->cr3;
8947 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
8948
8949 kvm_set_cr8(vcpu, sregs->cr8);
8950
8951 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8952 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8953
8954 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8955 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8956 vcpu->arch.cr0 = sregs->cr0;
8957
8958 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8959 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8960 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8961 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8962 if (cpuid_update_needed)
8963 kvm_update_cpuid(vcpu);
8964
8965 idx = srcu_read_lock(&vcpu->kvm->srcu);
8966 if (is_pae_paging(vcpu)) {
8967 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8968 mmu_reset_needed = 1;
8969 }
8970 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8971
8972 if (mmu_reset_needed)
8973 kvm_mmu_reset_context(vcpu);
8974
8975 max_bits = KVM_NR_INTERRUPTS;
8976 pending_vec = find_first_bit(
8977 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8978 if (pending_vec < max_bits) {
8979 kvm_queue_interrupt(vcpu, pending_vec, false);
8980 pr_debug("Set back pending irq %d\n", pending_vec);
8981 }
8982
8983 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8984 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8985 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8986 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8987 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8988 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8989
8990 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8991 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8992
8993 update_cr8_intercept(vcpu);
8994
8995 /* Older userspace won't unhalt the vcpu on reset. */
8996 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8997 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8998 !is_protmode(vcpu))
8999 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9000
9001 kvm_make_request(KVM_REQ_EVENT, vcpu);
9002
9003 ret = 0;
9004 out:
9005 return ret;
9006 }
9007
9008 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9009 struct kvm_sregs *sregs)
9010 {
9011 int ret;
9012
9013 vcpu_load(vcpu);
9014 ret = __set_sregs(vcpu, sregs);
9015 vcpu_put(vcpu);
9016 return ret;
9017 }
9018
9019 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9020 struct kvm_guest_debug *dbg)
9021 {
9022 unsigned long rflags;
9023 int i, r;
9024
9025 vcpu_load(vcpu);
9026
9027 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9028 r = -EBUSY;
9029 if (vcpu->arch.exception.pending)
9030 goto out;
9031 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9032 kvm_queue_exception(vcpu, DB_VECTOR);
9033 else
9034 kvm_queue_exception(vcpu, BP_VECTOR);
9035 }
9036
9037 /*
9038 * Read rflags as long as potentially injected trace flags are still
9039 * filtered out.
9040 */
9041 rflags = kvm_get_rflags(vcpu);
9042
9043 vcpu->guest_debug = dbg->control;
9044 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9045 vcpu->guest_debug = 0;
9046
9047 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9048 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9049 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9050 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9051 } else {
9052 for (i = 0; i < KVM_NR_DB_REGS; i++)
9053 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9054 }
9055 kvm_update_dr7(vcpu);
9056
9057 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9058 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9059 get_segment_base(vcpu, VCPU_SREG_CS);
9060
9061 /*
9062 * Trigger an rflags update that will inject or remove the trace
9063 * flags.
9064 */
9065 kvm_set_rflags(vcpu, rflags);
9066
9067 kvm_x86_ops->update_bp_intercept(vcpu);
9068
9069 r = 0;
9070
9071 out:
9072 vcpu_put(vcpu);
9073 return r;
9074 }
9075
9076 /*
9077 * Translate a guest virtual address to a guest physical address.
9078 */
9079 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9080 struct kvm_translation *tr)
9081 {
9082 unsigned long vaddr = tr->linear_address;
9083 gpa_t gpa;
9084 int idx;
9085
9086 vcpu_load(vcpu);
9087
9088 idx = srcu_read_lock(&vcpu->kvm->srcu);
9089 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9090 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9091 tr->physical_address = gpa;
9092 tr->valid = gpa != UNMAPPED_GVA;
9093 tr->writeable = 1;
9094 tr->usermode = 0;
9095
9096 vcpu_put(vcpu);
9097 return 0;
9098 }
9099
9100 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9101 {
9102 struct fxregs_state *fxsave;
9103
9104 vcpu_load(vcpu);
9105
9106 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9107 memcpy(fpu->fpr, fxsave->st_space, 128);
9108 fpu->fcw = fxsave->cwd;
9109 fpu->fsw = fxsave->swd;
9110 fpu->ftwx = fxsave->twd;
9111 fpu->last_opcode = fxsave->fop;
9112 fpu->last_ip = fxsave->rip;
9113 fpu->last_dp = fxsave->rdp;
9114 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9115
9116 vcpu_put(vcpu);
9117 return 0;
9118 }
9119
9120 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9121 {
9122 struct fxregs_state *fxsave;
9123
9124 vcpu_load(vcpu);
9125
9126 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9127
9128 memcpy(fxsave->st_space, fpu->fpr, 128);
9129 fxsave->cwd = fpu->fcw;
9130 fxsave->swd = fpu->fsw;
9131 fxsave->twd = fpu->ftwx;
9132 fxsave->fop = fpu->last_opcode;
9133 fxsave->rip = fpu->last_ip;
9134 fxsave->rdp = fpu->last_dp;
9135 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9136
9137 vcpu_put(vcpu);
9138 return 0;
9139 }
9140
9141 static void store_regs(struct kvm_vcpu *vcpu)
9142 {
9143 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9144
9145 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9146 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9147
9148 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9149 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9150
9151 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9152 kvm_vcpu_ioctl_x86_get_vcpu_events(
9153 vcpu, &vcpu->run->s.regs.events);
9154 }
9155
9156 static int sync_regs(struct kvm_vcpu *vcpu)
9157 {
9158 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9159 return -EINVAL;
9160
9161 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9162 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9163 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9164 }
9165 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9166 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9167 return -EINVAL;
9168 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9169 }
9170 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9171 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9172 vcpu, &vcpu->run->s.regs.events))
9173 return -EINVAL;
9174 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9175 }
9176
9177 return 0;
9178 }
9179
9180 static void fx_init(struct kvm_vcpu *vcpu)
9181 {
9182 fpstate_init(&vcpu->arch.guest_fpu->state);
9183 if (boot_cpu_has(X86_FEATURE_XSAVES))
9184 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9185 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9186
9187 /*
9188 * Ensure guest xcr0 is valid for loading
9189 */
9190 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9191
9192 vcpu->arch.cr0 |= X86_CR0_ET;
9193 }
9194
9195 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9196 {
9197 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9198 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9199 "guest TSC will not be reliable\n");
9200
9201 return 0;
9202 }
9203
9204 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9205 {
9206 struct page *page;
9207 int r;
9208
9209 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9210 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9211 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9212 else
9213 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9214
9215 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9216
9217 r = kvm_mmu_create(vcpu);
9218 if (r < 0)
9219 return r;
9220
9221 if (irqchip_in_kernel(vcpu->kvm)) {
9222 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu->kvm);
9223 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9224 if (r < 0)
9225 goto fail_mmu_destroy;
9226 } else
9227 static_key_slow_inc(&kvm_no_apic_vcpu);
9228
9229 r = -ENOMEM;
9230
9231 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9232 if (!page)
9233 goto fail_free_lapic;
9234 vcpu->arch.pio_data = page_address(page);
9235
9236 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9237 GFP_KERNEL_ACCOUNT);
9238 if (!vcpu->arch.mce_banks)
9239 goto fail_free_pio_data;
9240 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9241
9242 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9243 GFP_KERNEL_ACCOUNT))
9244 goto fail_free_mce_banks;
9245
9246 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9247 GFP_KERNEL_ACCOUNT);
9248 if (!vcpu->arch.user_fpu) {
9249 pr_err("kvm: failed to allocate userspace's fpu\n");
9250 goto free_wbinvd_dirty_mask;
9251 }
9252
9253 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9254 GFP_KERNEL_ACCOUNT);
9255 if (!vcpu->arch.guest_fpu) {
9256 pr_err("kvm: failed to allocate vcpu's fpu\n");
9257 goto free_user_fpu;
9258 }
9259 fx_init(vcpu);
9260
9261 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9262
9263 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9264
9265 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9266
9267 kvm_async_pf_hash_reset(vcpu);
9268 kvm_pmu_init(vcpu);
9269
9270 vcpu->arch.pending_external_vector = -1;
9271 vcpu->arch.preempted_in_kernel = false;
9272
9273 kvm_hv_vcpu_init(vcpu);
9274
9275 r = kvm_x86_ops->vcpu_create(vcpu);
9276 if (r)
9277 goto free_guest_fpu;
9278
9279 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9280 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9281 kvm_vcpu_mtrr_init(vcpu);
9282 vcpu_load(vcpu);
9283 kvm_vcpu_reset(vcpu, false);
9284 kvm_init_mmu(vcpu, false);
9285 vcpu_put(vcpu);
9286 return 0;
9287
9288 free_guest_fpu:
9289 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9290 free_user_fpu:
9291 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9292 free_wbinvd_dirty_mask:
9293 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9294 fail_free_mce_banks:
9295 kfree(vcpu->arch.mce_banks);
9296 fail_free_pio_data:
9297 free_page((unsigned long)vcpu->arch.pio_data);
9298 fail_free_lapic:
9299 kvm_free_lapic(vcpu);
9300 fail_mmu_destroy:
9301 kvm_mmu_destroy(vcpu);
9302 return r;
9303 }
9304
9305 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9306 {
9307 struct msr_data msr;
9308 struct kvm *kvm = vcpu->kvm;
9309
9310 kvm_hv_vcpu_postcreate(vcpu);
9311
9312 if (mutex_lock_killable(&vcpu->mutex))
9313 return;
9314 vcpu_load(vcpu);
9315 msr.data = 0x0;
9316 msr.index = MSR_IA32_TSC;
9317 msr.host_initiated = true;
9318 kvm_write_tsc(vcpu, &msr);
9319 vcpu_put(vcpu);
9320
9321 /* poll control enabled by default */
9322 vcpu->arch.msr_kvm_poll_control = 1;
9323
9324 mutex_unlock(&vcpu->mutex);
9325
9326 if (!kvmclock_periodic_sync)
9327 return;
9328
9329 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9330 KVMCLOCK_SYNC_PERIOD);
9331 }
9332
9333 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9334 {
9335 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9336 int idx;
9337
9338 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9339
9340 kvmclock_reset(vcpu);
9341
9342 kvm_x86_ops->vcpu_free(vcpu);
9343
9344 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9345 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9346 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9347
9348 kvm_hv_vcpu_uninit(vcpu);
9349 kvm_pmu_destroy(vcpu);
9350 kfree(vcpu->arch.mce_banks);
9351 kvm_free_lapic(vcpu);
9352 idx = srcu_read_lock(&vcpu->kvm->srcu);
9353 kvm_mmu_destroy(vcpu);
9354 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9355 free_page((unsigned long)vcpu->arch.pio_data);
9356 if (!lapic_in_kernel(vcpu))
9357 static_key_slow_dec(&kvm_no_apic_vcpu);
9358 }
9359
9360 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9361 {
9362 kvm_lapic_reset(vcpu, init_event);
9363
9364 vcpu->arch.hflags = 0;
9365
9366 vcpu->arch.smi_pending = 0;
9367 vcpu->arch.smi_count = 0;
9368 atomic_set(&vcpu->arch.nmi_queued, 0);
9369 vcpu->arch.nmi_pending = 0;
9370 vcpu->arch.nmi_injected = false;
9371 kvm_clear_interrupt_queue(vcpu);
9372 kvm_clear_exception_queue(vcpu);
9373
9374 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9375 kvm_update_dr0123(vcpu);
9376 vcpu->arch.dr6 = DR6_INIT;
9377 kvm_update_dr6(vcpu);
9378 vcpu->arch.dr7 = DR7_FIXED_1;
9379 kvm_update_dr7(vcpu);
9380
9381 vcpu->arch.cr2 = 0;
9382
9383 kvm_make_request(KVM_REQ_EVENT, vcpu);
9384 vcpu->arch.apf.msr_val = 0;
9385 vcpu->arch.st.msr_val = 0;
9386
9387 kvmclock_reset(vcpu);
9388
9389 kvm_clear_async_pf_completion_queue(vcpu);
9390 kvm_async_pf_hash_reset(vcpu);
9391 vcpu->arch.apf.halted = false;
9392
9393 if (kvm_mpx_supported()) {
9394 void *mpx_state_buffer;
9395
9396 /*
9397 * To avoid have the INIT path from kvm_apic_has_events() that be
9398 * called with loaded FPU and does not let userspace fix the state.
9399 */
9400 if (init_event)
9401 kvm_put_guest_fpu(vcpu);
9402 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9403 XFEATURE_BNDREGS);
9404 if (mpx_state_buffer)
9405 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9406 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9407 XFEATURE_BNDCSR);
9408 if (mpx_state_buffer)
9409 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9410 if (init_event)
9411 kvm_load_guest_fpu(vcpu);
9412 }
9413
9414 if (!init_event) {
9415 kvm_pmu_reset(vcpu);
9416 vcpu->arch.smbase = 0x30000;
9417
9418 vcpu->arch.msr_misc_features_enables = 0;
9419
9420 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9421 }
9422
9423 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9424 vcpu->arch.regs_avail = ~0;
9425 vcpu->arch.regs_dirty = ~0;
9426
9427 vcpu->arch.ia32_xss = 0;
9428
9429 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9430 }
9431
9432 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9433 {
9434 struct kvm_segment cs;
9435
9436 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9437 cs.selector = vector << 8;
9438 cs.base = vector << 12;
9439 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9440 kvm_rip_write(vcpu, 0);
9441 }
9442
9443 int kvm_arch_hardware_enable(void)
9444 {
9445 struct kvm *kvm;
9446 struct kvm_vcpu *vcpu;
9447 int i;
9448 int ret;
9449 u64 local_tsc;
9450 u64 max_tsc = 0;
9451 bool stable, backwards_tsc = false;
9452
9453 kvm_shared_msr_cpu_online();
9454 ret = kvm_x86_ops->hardware_enable();
9455 if (ret != 0)
9456 return ret;
9457
9458 local_tsc = rdtsc();
9459 stable = !kvm_check_tsc_unstable();
9460 list_for_each_entry(kvm, &vm_list, vm_list) {
9461 kvm_for_each_vcpu(i, vcpu, kvm) {
9462 if (!stable && vcpu->cpu == smp_processor_id())
9463 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9464 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9465 backwards_tsc = true;
9466 if (vcpu->arch.last_host_tsc > max_tsc)
9467 max_tsc = vcpu->arch.last_host_tsc;
9468 }
9469 }
9470 }
9471
9472 /*
9473 * Sometimes, even reliable TSCs go backwards. This happens on
9474 * platforms that reset TSC during suspend or hibernate actions, but
9475 * maintain synchronization. We must compensate. Fortunately, we can
9476 * detect that condition here, which happens early in CPU bringup,
9477 * before any KVM threads can be running. Unfortunately, we can't
9478 * bring the TSCs fully up to date with real time, as we aren't yet far
9479 * enough into CPU bringup that we know how much real time has actually
9480 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9481 * variables that haven't been updated yet.
9482 *
9483 * So we simply find the maximum observed TSC above, then record the
9484 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9485 * the adjustment will be applied. Note that we accumulate
9486 * adjustments, in case multiple suspend cycles happen before some VCPU
9487 * gets a chance to run again. In the event that no KVM threads get a
9488 * chance to run, we will miss the entire elapsed period, as we'll have
9489 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9490 * loose cycle time. This isn't too big a deal, since the loss will be
9491 * uniform across all VCPUs (not to mention the scenario is extremely
9492 * unlikely). It is possible that a second hibernate recovery happens
9493 * much faster than a first, causing the observed TSC here to be
9494 * smaller; this would require additional padding adjustment, which is
9495 * why we set last_host_tsc to the local tsc observed here.
9496 *
9497 * N.B. - this code below runs only on platforms with reliable TSC,
9498 * as that is the only way backwards_tsc is set above. Also note
9499 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9500 * have the same delta_cyc adjustment applied if backwards_tsc
9501 * is detected. Note further, this adjustment is only done once,
9502 * as we reset last_host_tsc on all VCPUs to stop this from being
9503 * called multiple times (one for each physical CPU bringup).
9504 *
9505 * Platforms with unreliable TSCs don't have to deal with this, they
9506 * will be compensated by the logic in vcpu_load, which sets the TSC to
9507 * catchup mode. This will catchup all VCPUs to real time, but cannot
9508 * guarantee that they stay in perfect synchronization.
9509 */
9510 if (backwards_tsc) {
9511 u64 delta_cyc = max_tsc - local_tsc;
9512 list_for_each_entry(kvm, &vm_list, vm_list) {
9513 kvm->arch.backwards_tsc_observed = true;
9514 kvm_for_each_vcpu(i, vcpu, kvm) {
9515 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9516 vcpu->arch.last_host_tsc = local_tsc;
9517 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9518 }
9519
9520 /*
9521 * We have to disable TSC offset matching.. if you were
9522 * booting a VM while issuing an S4 host suspend....
9523 * you may have some problem. Solving this issue is
9524 * left as an exercise to the reader.
9525 */
9526 kvm->arch.last_tsc_nsec = 0;
9527 kvm->arch.last_tsc_write = 0;
9528 }
9529
9530 }
9531 return 0;
9532 }
9533
9534 void kvm_arch_hardware_disable(void)
9535 {
9536 kvm_x86_ops->hardware_disable();
9537 drop_user_return_notifiers();
9538 }
9539
9540 int kvm_arch_hardware_setup(void)
9541 {
9542 int r;
9543
9544 r = kvm_x86_ops->hardware_setup();
9545 if (r != 0)
9546 return r;
9547
9548 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9549
9550 if (kvm_has_tsc_control) {
9551 /*
9552 * Make sure the user can only configure tsc_khz values that
9553 * fit into a signed integer.
9554 * A min value is not calculated because it will always
9555 * be 1 on all machines.
9556 */
9557 u64 max = min(0x7fffffffULL,
9558 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9559 kvm_max_guest_tsc_khz = max;
9560
9561 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9562 }
9563
9564 if (boot_cpu_has(X86_FEATURE_XSAVES))
9565 rdmsrl(MSR_IA32_XSS, host_xss);
9566
9567 kvm_init_msr_list();
9568 return 0;
9569 }
9570
9571 void kvm_arch_hardware_unsetup(void)
9572 {
9573 kvm_x86_ops->hardware_unsetup();
9574 }
9575
9576 int kvm_arch_check_processor_compat(void)
9577 {
9578 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9579
9580 WARN_ON(!irqs_disabled());
9581
9582 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9583 return -EIO;
9584
9585 return kvm_x86_ops->check_processor_compatibility();
9586 }
9587
9588 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9589 {
9590 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9591 }
9592 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9593
9594 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9595 {
9596 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9597 }
9598
9599 struct static_key kvm_no_apic_vcpu __read_mostly;
9600 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9601
9602 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9603 {
9604 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9605
9606 vcpu->arch.l1tf_flush_l1d = true;
9607 if (pmu->version && unlikely(pmu->event_count)) {
9608 pmu->need_cleanup = true;
9609 kvm_make_request(KVM_REQ_PMU, vcpu);
9610 }
9611 kvm_x86_ops->sched_in(vcpu, cpu);
9612 }
9613
9614 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9615 {
9616 if (type)
9617 return -EINVAL;
9618
9619 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9620 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9621 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9622 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9623 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9624 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9625
9626 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9627 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9628 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9629 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9630 &kvm->arch.irq_sources_bitmap);
9631
9632 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9633 mutex_init(&kvm->arch.apic_map_lock);
9634 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9635
9636 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9637 pvclock_update_vm_gtod_copy(kvm);
9638
9639 kvm->arch.guest_can_read_msr_platform_info = true;
9640
9641 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9642 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9643
9644 kvm_hv_init_vm(kvm);
9645 kvm_page_track_init(kvm);
9646 kvm_mmu_init_vm(kvm);
9647
9648 return kvm_x86_ops->vm_init(kvm);
9649 }
9650
9651 int kvm_arch_post_init_vm(struct kvm *kvm)
9652 {
9653 return kvm_mmu_post_init_vm(kvm);
9654 }
9655
9656 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9657 {
9658 vcpu_load(vcpu);
9659 kvm_mmu_unload(vcpu);
9660 vcpu_put(vcpu);
9661 }
9662
9663 static void kvm_free_vcpus(struct kvm *kvm)
9664 {
9665 unsigned int i;
9666 struct kvm_vcpu *vcpu;
9667
9668 /*
9669 * Unpin any mmu pages first.
9670 */
9671 kvm_for_each_vcpu(i, vcpu, kvm) {
9672 kvm_clear_async_pf_completion_queue(vcpu);
9673 kvm_unload_vcpu_mmu(vcpu);
9674 }
9675 kvm_for_each_vcpu(i, vcpu, kvm)
9676 kvm_vcpu_destroy(vcpu);
9677
9678 mutex_lock(&kvm->lock);
9679 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9680 kvm->vcpus[i] = NULL;
9681
9682 atomic_set(&kvm->online_vcpus, 0);
9683 mutex_unlock(&kvm->lock);
9684 }
9685
9686 void kvm_arch_sync_events(struct kvm *kvm)
9687 {
9688 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9689 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9690 kvm_free_pit(kvm);
9691 }
9692
9693 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9694 {
9695 int i, r;
9696 unsigned long hva;
9697 struct kvm_memslots *slots = kvm_memslots(kvm);
9698 struct kvm_memory_slot *slot, old;
9699
9700 /* Called with kvm->slots_lock held. */
9701 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9702 return -EINVAL;
9703
9704 slot = id_to_memslot(slots, id);
9705 if (size) {
9706 if (slot->npages)
9707 return -EEXIST;
9708
9709 /*
9710 * MAP_SHARED to prevent internal slot pages from being moved
9711 * by fork()/COW.
9712 */
9713 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9714 MAP_SHARED | MAP_ANONYMOUS, 0);
9715 if (IS_ERR((void *)hva))
9716 return PTR_ERR((void *)hva);
9717 } else {
9718 if (!slot->npages)
9719 return 0;
9720
9721 hva = 0;
9722 }
9723
9724 old = *slot;
9725 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9726 struct kvm_userspace_memory_region m;
9727
9728 m.slot = id | (i << 16);
9729 m.flags = 0;
9730 m.guest_phys_addr = gpa;
9731 m.userspace_addr = hva;
9732 m.memory_size = size;
9733 r = __kvm_set_memory_region(kvm, &m);
9734 if (r < 0)
9735 return r;
9736 }
9737
9738 if (!size)
9739 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9740
9741 return 0;
9742 }
9743 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9744
9745 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9746 {
9747 kvm_mmu_pre_destroy_vm(kvm);
9748 }
9749
9750 void kvm_arch_destroy_vm(struct kvm *kvm)
9751 {
9752 if (current->mm == kvm->mm) {
9753 /*
9754 * Free memory regions allocated on behalf of userspace,
9755 * unless the the memory map has changed due to process exit
9756 * or fd copying.
9757 */
9758 mutex_lock(&kvm->slots_lock);
9759 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9760 0, 0);
9761 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9762 0, 0);
9763 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9764 mutex_unlock(&kvm->slots_lock);
9765 }
9766 if (kvm_x86_ops->vm_destroy)
9767 kvm_x86_ops->vm_destroy(kvm);
9768 kvm_pic_destroy(kvm);
9769 kvm_ioapic_destroy(kvm);
9770 kvm_free_vcpus(kvm);
9771 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9772 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9773 kvm_mmu_uninit_vm(kvm);
9774 kvm_page_track_cleanup(kvm);
9775 kvm_hv_destroy_vm(kvm);
9776 }
9777
9778 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9779 struct kvm_memory_slot *dont)
9780 {
9781 int i;
9782
9783 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9784 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9785 kvfree(free->arch.rmap[i]);
9786 free->arch.rmap[i] = NULL;
9787 }
9788 if (i == 0)
9789 continue;
9790
9791 if (!dont || free->arch.lpage_info[i - 1] !=
9792 dont->arch.lpage_info[i - 1]) {
9793 kvfree(free->arch.lpage_info[i - 1]);
9794 free->arch.lpage_info[i - 1] = NULL;
9795 }
9796 }
9797
9798 kvm_page_track_free_memslot(free, dont);
9799 }
9800
9801 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9802 unsigned long npages)
9803 {
9804 int i;
9805
9806 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9807 struct kvm_lpage_info *linfo;
9808 unsigned long ugfn;
9809 int lpages;
9810 int level = i + 1;
9811
9812 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9813 slot->base_gfn, level) + 1;
9814
9815 slot->arch.rmap[i] =
9816 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9817 GFP_KERNEL_ACCOUNT);
9818 if (!slot->arch.rmap[i])
9819 goto out_free;
9820 if (i == 0)
9821 continue;
9822
9823 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9824 if (!linfo)
9825 goto out_free;
9826
9827 slot->arch.lpage_info[i - 1] = linfo;
9828
9829 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9830 linfo[0].disallow_lpage = 1;
9831 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9832 linfo[lpages - 1].disallow_lpage = 1;
9833 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9834 /*
9835 * If the gfn and userspace address are not aligned wrt each
9836 * other, or if explicitly asked to, disable large page
9837 * support for this slot
9838 */
9839 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9840 !kvm_largepages_enabled()) {
9841 unsigned long j;
9842
9843 for (j = 0; j < lpages; ++j)
9844 linfo[j].disallow_lpage = 1;
9845 }
9846 }
9847
9848 if (kvm_page_track_create_memslot(slot, npages))
9849 goto out_free;
9850
9851 return 0;
9852
9853 out_free:
9854 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9855 kvfree(slot->arch.rmap[i]);
9856 slot->arch.rmap[i] = NULL;
9857 if (i == 0)
9858 continue;
9859
9860 kvfree(slot->arch.lpage_info[i - 1]);
9861 slot->arch.lpage_info[i - 1] = NULL;
9862 }
9863 return -ENOMEM;
9864 }
9865
9866 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9867 {
9868 struct kvm_vcpu *vcpu;
9869 int i;
9870
9871 /*
9872 * memslots->generation has been incremented.
9873 * mmio generation may have reached its maximum value.
9874 */
9875 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9876
9877 /* Force re-initialization of steal_time cache */
9878 kvm_for_each_vcpu(i, vcpu, kvm)
9879 kvm_vcpu_kick(vcpu);
9880 }
9881
9882 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9883 struct kvm_memory_slot *memslot,
9884 const struct kvm_userspace_memory_region *mem,
9885 enum kvm_mr_change change)
9886 {
9887 return 0;
9888 }
9889
9890 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9891 struct kvm_memory_slot *new)
9892 {
9893 /* Still write protect RO slot */
9894 if (new->flags & KVM_MEM_READONLY) {
9895 kvm_mmu_slot_remove_write_access(kvm, new);
9896 return;
9897 }
9898
9899 /*
9900 * Call kvm_x86_ops dirty logging hooks when they are valid.
9901 *
9902 * kvm_x86_ops->slot_disable_log_dirty is called when:
9903 *
9904 * - KVM_MR_CREATE with dirty logging is disabled
9905 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9906 *
9907 * The reason is, in case of PML, we need to set D-bit for any slots
9908 * with dirty logging disabled in order to eliminate unnecessary GPA
9909 * logging in PML buffer (and potential PML buffer full VMEXIT). This
9910 * guarantees leaving PML enabled during guest's lifetime won't have
9911 * any additional overhead from PML when guest is running with dirty
9912 * logging disabled for memory slots.
9913 *
9914 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9915 * to dirty logging mode.
9916 *
9917 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9918 *
9919 * In case of write protect:
9920 *
9921 * Write protect all pages for dirty logging.
9922 *
9923 * All the sptes including the large sptes which point to this
9924 * slot are set to readonly. We can not create any new large
9925 * spte on this slot until the end of the logging.
9926 *
9927 * See the comments in fast_page_fault().
9928 */
9929 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9930 if (kvm_x86_ops->slot_enable_log_dirty)
9931 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9932 else
9933 kvm_mmu_slot_remove_write_access(kvm, new);
9934 } else {
9935 if (kvm_x86_ops->slot_disable_log_dirty)
9936 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9937 }
9938 }
9939
9940 void kvm_arch_commit_memory_region(struct kvm *kvm,
9941 const struct kvm_userspace_memory_region *mem,
9942 const struct kvm_memory_slot *old,
9943 const struct kvm_memory_slot *new,
9944 enum kvm_mr_change change)
9945 {
9946 if (!kvm->arch.n_requested_mmu_pages)
9947 kvm_mmu_change_mmu_pages(kvm,
9948 kvm_mmu_calculate_default_mmu_pages(kvm));
9949
9950 /*
9951 * Dirty logging tracks sptes in 4k granularity, meaning that large
9952 * sptes have to be split. If live migration is successful, the guest
9953 * in the source machine will be destroyed and large sptes will be
9954 * created in the destination. However, if the guest continues to run
9955 * in the source machine (for example if live migration fails), small
9956 * sptes will remain around and cause bad performance.
9957 *
9958 * Scan sptes if dirty logging has been stopped, dropping those
9959 * which can be collapsed into a single large-page spte. Later
9960 * page faults will create the large-page sptes.
9961 *
9962 * There is no need to do this in any of the following cases:
9963 * CREATE: No dirty mappings will already exist.
9964 * MOVE/DELETE: The old mappings will already have been cleaned up by
9965 * kvm_arch_flush_shadow_memslot()
9966 */
9967 if (change == KVM_MR_FLAGS_ONLY &&
9968 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9969 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9970 kvm_mmu_zap_collapsible_sptes(kvm, new);
9971
9972 /*
9973 * Set up write protection and/or dirty logging for the new slot.
9974 *
9975 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9976 * been zapped so no dirty logging staff is needed for old slot. For
9977 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9978 * new and it's also covered when dealing with the new slot.
9979 *
9980 * FIXME: const-ify all uses of struct kvm_memory_slot.
9981 */
9982 if (change != KVM_MR_DELETE)
9983 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9984 }
9985
9986 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9987 {
9988 kvm_mmu_zap_all(kvm);
9989 }
9990
9991 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9992 struct kvm_memory_slot *slot)
9993 {
9994 kvm_page_track_flush_slot(kvm, slot);
9995 }
9996
9997 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9998 {
9999 return (is_guest_mode(vcpu) &&
10000 kvm_x86_ops->guest_apic_has_interrupt &&
10001 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10002 }
10003
10004 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10005 {
10006 if (!list_empty_careful(&vcpu->async_pf.done))
10007 return true;
10008
10009 if (kvm_apic_has_events(vcpu))
10010 return true;
10011
10012 if (vcpu->arch.pv.pv_unhalted)
10013 return true;
10014
10015 if (vcpu->arch.exception.pending)
10016 return true;
10017
10018 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10019 (vcpu->arch.nmi_pending &&
10020 kvm_x86_ops->nmi_allowed(vcpu)))
10021 return true;
10022
10023 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10024 (vcpu->arch.smi_pending && !is_smm(vcpu)))
10025 return true;
10026
10027 if (kvm_arch_interrupt_allowed(vcpu) &&
10028 (kvm_cpu_has_interrupt(vcpu) ||
10029 kvm_guest_apic_has_interrupt(vcpu)))
10030 return true;
10031
10032 if (kvm_hv_has_stimer_pending(vcpu))
10033 return true;
10034
10035 return false;
10036 }
10037
10038 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10039 {
10040 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10041 }
10042
10043 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10044 {
10045 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10046 return true;
10047
10048 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10049 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10050 kvm_test_request(KVM_REQ_EVENT, vcpu))
10051 return true;
10052
10053 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10054 return true;
10055
10056 return false;
10057 }
10058
10059 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10060 {
10061 return vcpu->arch.preempted_in_kernel;
10062 }
10063
10064 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10065 {
10066 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10067 }
10068
10069 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10070 {
10071 return kvm_x86_ops->interrupt_allowed(vcpu);
10072 }
10073
10074 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10075 {
10076 if (is_64_bit_mode(vcpu))
10077 return kvm_rip_read(vcpu);
10078 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10079 kvm_rip_read(vcpu));
10080 }
10081 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10082
10083 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10084 {
10085 return kvm_get_linear_rip(vcpu) == linear_rip;
10086 }
10087 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10088
10089 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10090 {
10091 unsigned long rflags;
10092
10093 rflags = kvm_x86_ops->get_rflags(vcpu);
10094 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10095 rflags &= ~X86_EFLAGS_TF;
10096 return rflags;
10097 }
10098 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10099
10100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10101 {
10102 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10103 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10104 rflags |= X86_EFLAGS_TF;
10105 kvm_x86_ops->set_rflags(vcpu, rflags);
10106 }
10107
10108 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10109 {
10110 __kvm_set_rflags(vcpu, rflags);
10111 kvm_make_request(KVM_REQ_EVENT, vcpu);
10112 }
10113 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10114
10115 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10116 {
10117 int r;
10118
10119 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10120 work->wakeup_all)
10121 return;
10122
10123 r = kvm_mmu_reload(vcpu);
10124 if (unlikely(r))
10125 return;
10126
10127 if (!vcpu->arch.mmu->direct_map &&
10128 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
10129 return;
10130
10131 vcpu->arch.mmu->page_fault(vcpu, work->cr2_or_gpa, 0, true);
10132 }
10133
10134 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10135 {
10136 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10137 }
10138
10139 static inline u32 kvm_async_pf_next_probe(u32 key)
10140 {
10141 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10142 }
10143
10144 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10145 {
10146 u32 key = kvm_async_pf_hash_fn(gfn);
10147
10148 while (vcpu->arch.apf.gfns[key] != ~0)
10149 key = kvm_async_pf_next_probe(key);
10150
10151 vcpu->arch.apf.gfns[key] = gfn;
10152 }
10153
10154 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10155 {
10156 int i;
10157 u32 key = kvm_async_pf_hash_fn(gfn);
10158
10159 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10160 (vcpu->arch.apf.gfns[key] != gfn &&
10161 vcpu->arch.apf.gfns[key] != ~0); i++)
10162 key = kvm_async_pf_next_probe(key);
10163
10164 return key;
10165 }
10166
10167 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10168 {
10169 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10170 }
10171
10172 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10173 {
10174 u32 i, j, k;
10175
10176 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10177 while (true) {
10178 vcpu->arch.apf.gfns[i] = ~0;
10179 do {
10180 j = kvm_async_pf_next_probe(j);
10181 if (vcpu->arch.apf.gfns[j] == ~0)
10182 return;
10183 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10184 /*
10185 * k lies cyclically in ]i,j]
10186 * | i.k.j |
10187 * |....j i.k.| or |.k..j i...|
10188 */
10189 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10190 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10191 i = j;
10192 }
10193 }
10194
10195 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10196 {
10197
10198 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10199 sizeof(val));
10200 }
10201
10202 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10203 {
10204
10205 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10206 sizeof(u32));
10207 }
10208
10209 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10210 {
10211 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10212 return false;
10213
10214 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10215 (vcpu->arch.apf.send_user_only &&
10216 kvm_x86_ops->get_cpl(vcpu) == 0))
10217 return false;
10218
10219 return true;
10220 }
10221
10222 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10223 {
10224 if (unlikely(!lapic_in_kernel(vcpu) ||
10225 kvm_event_needs_reinjection(vcpu) ||
10226 vcpu->arch.exception.pending))
10227 return false;
10228
10229 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10230 return false;
10231
10232 /*
10233 * If interrupts are off we cannot even use an artificial
10234 * halt state.
10235 */
10236 return kvm_x86_ops->interrupt_allowed(vcpu);
10237 }
10238
10239 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10240 struct kvm_async_pf *work)
10241 {
10242 struct x86_exception fault;
10243
10244 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10245 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10246
10247 if (kvm_can_deliver_async_pf(vcpu) &&
10248 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10249 fault.vector = PF_VECTOR;
10250 fault.error_code_valid = true;
10251 fault.error_code = 0;
10252 fault.nested_page_fault = false;
10253 fault.address = work->arch.token;
10254 fault.async_page_fault = true;
10255 kvm_inject_page_fault(vcpu, &fault);
10256 } else {
10257 /*
10258 * It is not possible to deliver a paravirtualized asynchronous
10259 * page fault, but putting the guest in an artificial halt state
10260 * can be beneficial nevertheless: if an interrupt arrives, we
10261 * can deliver it timely and perhaps the guest will schedule
10262 * another process. When the instruction that triggered a page
10263 * fault is retried, hopefully the page will be ready in the host.
10264 */
10265 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10266 }
10267 }
10268
10269 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10270 struct kvm_async_pf *work)
10271 {
10272 struct x86_exception fault;
10273 u32 val;
10274
10275 if (work->wakeup_all)
10276 work->arch.token = ~0; /* broadcast wakeup */
10277 else
10278 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10279 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10280
10281 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10282 !apf_get_user(vcpu, &val)) {
10283 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10284 vcpu->arch.exception.pending &&
10285 vcpu->arch.exception.nr == PF_VECTOR &&
10286 !apf_put_user(vcpu, 0)) {
10287 vcpu->arch.exception.injected = false;
10288 vcpu->arch.exception.pending = false;
10289 vcpu->arch.exception.nr = 0;
10290 vcpu->arch.exception.has_error_code = false;
10291 vcpu->arch.exception.error_code = 0;
10292 vcpu->arch.exception.has_payload = false;
10293 vcpu->arch.exception.payload = 0;
10294 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10295 fault.vector = PF_VECTOR;
10296 fault.error_code_valid = true;
10297 fault.error_code = 0;
10298 fault.nested_page_fault = false;
10299 fault.address = work->arch.token;
10300 fault.async_page_fault = true;
10301 kvm_inject_page_fault(vcpu, &fault);
10302 }
10303 }
10304 vcpu->arch.apf.halted = false;
10305 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10306 }
10307
10308 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10309 {
10310 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10311 return true;
10312 else
10313 return kvm_can_do_async_pf(vcpu);
10314 }
10315
10316 void kvm_arch_start_assignment(struct kvm *kvm)
10317 {
10318 atomic_inc(&kvm->arch.assigned_device_count);
10319 }
10320 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10321
10322 void kvm_arch_end_assignment(struct kvm *kvm)
10323 {
10324 atomic_dec(&kvm->arch.assigned_device_count);
10325 }
10326 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10327
10328 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10329 {
10330 return atomic_read(&kvm->arch.assigned_device_count);
10331 }
10332 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10333
10334 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10335 {
10336 atomic_inc(&kvm->arch.noncoherent_dma_count);
10337 }
10338 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10339
10340 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10341 {
10342 atomic_dec(&kvm->arch.noncoherent_dma_count);
10343 }
10344 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10345
10346 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10347 {
10348 return atomic_read(&kvm->arch.noncoherent_dma_count);
10349 }
10350 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10351
10352 bool kvm_arch_has_irq_bypass(void)
10353 {
10354 return true;
10355 }
10356
10357 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10358 struct irq_bypass_producer *prod)
10359 {
10360 struct kvm_kernel_irqfd *irqfd =
10361 container_of(cons, struct kvm_kernel_irqfd, consumer);
10362
10363 irqfd->producer = prod;
10364
10365 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10366 prod->irq, irqfd->gsi, 1);
10367 }
10368
10369 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10370 struct irq_bypass_producer *prod)
10371 {
10372 int ret;
10373 struct kvm_kernel_irqfd *irqfd =
10374 container_of(cons, struct kvm_kernel_irqfd, consumer);
10375
10376 WARN_ON(irqfd->producer != prod);
10377 irqfd->producer = NULL;
10378
10379 /*
10380 * When producer of consumer is unregistered, we change back to
10381 * remapped mode, so we can re-use the current implementation
10382 * when the irq is masked/disabled or the consumer side (KVM
10383 * int this case doesn't want to receive the interrupts.
10384 */
10385 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10386 if (ret)
10387 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10388 " fails: %d\n", irqfd->consumer.token, ret);
10389 }
10390
10391 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10392 uint32_t guest_irq, bool set)
10393 {
10394 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10395 }
10396
10397 bool kvm_vector_hashing_enabled(void)
10398 {
10399 return vector_hashing;
10400 }
10401
10402 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10403 {
10404 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10405 }
10406 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10407
10408 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10409 {
10410 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10411
10412 /* The STIBP bit doesn't fault even if it's not advertised */
10413 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10414 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10415 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10416 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10417 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10418 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10419
10420 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10421 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10422 bits &= ~SPEC_CTRL_SSBD;
10423 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10424 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10425 bits &= ~SPEC_CTRL_SSBD;
10426
10427 return bits;
10428 }
10429 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10430
10431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10434 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10435 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10436 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10437 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10438 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10439 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10440 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10441 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10442 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10443 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10444 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10445 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10446 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10447 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10448 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10449 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10450 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux with added FPC-III support