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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / net / ethernet / realtek / r8169.c
blob799387570766b6642ad4fdbc13f917acd358887a
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54
55 #ifdef RTL8169_DEBUG
56 #define assert(expr) \
57 if (!(expr)) { \
58 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
59 #expr,__FILE__,__func__,__LINE__); \
60 }
61 #define dprintk(fmt, args...) \
62 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
63 #else
64 #define assert(expr) do {} while (0)
65 #define dprintk(fmt, args...) do {} while (0)
66 #endif /* RTL8169_DEBUG */
67
68 #define R8169_MSG_DEFAULT \
69 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
70
71 #define TX_SLOTS_AVAIL(tp) \
72 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
73
74 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
75 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
76 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
77
78 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
79 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
80 static const int multicast_filter_limit = 32;
81
82 #define MAX_READ_REQUEST_SHIFT 12
83 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85
86 #define R8169_REGS_SIZE 256
87 #define R8169_NAPI_WEIGHT 64
88 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
89 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
90 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
91 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
92
93 #define RTL8169_TX_TIMEOUT (6*HZ)
94 #define RTL8169_PHY_TIMEOUT (10*HZ)
95
96 /* write/read MMIO register */
97 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
98 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
99 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
100 #define RTL_R8(reg) readb (ioaddr + (reg))
101 #define RTL_R16(reg) readw (ioaddr + (reg))
102 #define RTL_R32(reg) readl (ioaddr + (reg))
103
104 enum mac_version {
105 RTL_GIGA_MAC_VER_01 = 0,
106 RTL_GIGA_MAC_VER_02,
107 RTL_GIGA_MAC_VER_03,
108 RTL_GIGA_MAC_VER_04,
109 RTL_GIGA_MAC_VER_05,
110 RTL_GIGA_MAC_VER_06,
111 RTL_GIGA_MAC_VER_07,
112 RTL_GIGA_MAC_VER_08,
113 RTL_GIGA_MAC_VER_09,
114 RTL_GIGA_MAC_VER_10,
115 RTL_GIGA_MAC_VER_11,
116 RTL_GIGA_MAC_VER_12,
117 RTL_GIGA_MAC_VER_13,
118 RTL_GIGA_MAC_VER_14,
119 RTL_GIGA_MAC_VER_15,
120 RTL_GIGA_MAC_VER_16,
121 RTL_GIGA_MAC_VER_17,
122 RTL_GIGA_MAC_VER_18,
123 RTL_GIGA_MAC_VER_19,
124 RTL_GIGA_MAC_VER_20,
125 RTL_GIGA_MAC_VER_21,
126 RTL_GIGA_MAC_VER_22,
127 RTL_GIGA_MAC_VER_23,
128 RTL_GIGA_MAC_VER_24,
129 RTL_GIGA_MAC_VER_25,
130 RTL_GIGA_MAC_VER_26,
131 RTL_GIGA_MAC_VER_27,
132 RTL_GIGA_MAC_VER_28,
133 RTL_GIGA_MAC_VER_29,
134 RTL_GIGA_MAC_VER_30,
135 RTL_GIGA_MAC_VER_31,
136 RTL_GIGA_MAC_VER_32,
137 RTL_GIGA_MAC_VER_33,
138 RTL_GIGA_MAC_VER_34,
139 RTL_GIGA_MAC_VER_35,
140 RTL_GIGA_MAC_VER_36,
141 RTL_GIGA_MAC_VER_37,
142 RTL_GIGA_MAC_VER_38,
143 RTL_GIGA_MAC_VER_39,
144 RTL_GIGA_MAC_VER_40,
145 RTL_GIGA_MAC_VER_41,
146 RTL_GIGA_MAC_VER_42,
147 RTL_GIGA_MAC_VER_43,
148 RTL_GIGA_MAC_VER_44,
149 RTL_GIGA_MAC_NONE = 0xff,
150 };
151
152 enum rtl_tx_desc_version {
153 RTL_TD_0 = 0,
154 RTL_TD_1 = 1,
155 };
156
157 #define JUMBO_1K ETH_DATA_LEN
158 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
159 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
160 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
161 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
162
163 #define _R(NAME,TD,FW,SZ,B) { \
164 .name = NAME, \
165 .txd_version = TD, \
166 .fw_name = FW, \
167 .jumbo_max = SZ, \
168 .jumbo_tx_csum = B \
169 }
170
171 static const struct {
172 const char *name;
173 enum rtl_tx_desc_version txd_version;
174 const char *fw_name;
175 u16 jumbo_max;
176 bool jumbo_tx_csum;
177 } rtl_chip_infos[] = {
178 /* PCI devices. */
179 [RTL_GIGA_MAC_VER_01] =
180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
181 [RTL_GIGA_MAC_VER_02] =
182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_03] =
184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
185 [RTL_GIGA_MAC_VER_04] =
186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
187 [RTL_GIGA_MAC_VER_05] =
188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
189 [RTL_GIGA_MAC_VER_06] =
190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
191 /* PCI-E devices. */
192 [RTL_GIGA_MAC_VER_07] =
193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_08] =
195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_09] =
197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_10] =
199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
200 [RTL_GIGA_MAC_VER_11] =
201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
202 [RTL_GIGA_MAC_VER_12] =
203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
204 [RTL_GIGA_MAC_VER_13] =
205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_14] =
207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_15] =
209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_16] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_17] =
213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_18] =
215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_19] =
217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
218 [RTL_GIGA_MAC_VER_20] =
219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
220 [RTL_GIGA_MAC_VER_21] =
221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
222 [RTL_GIGA_MAC_VER_22] =
223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
224 [RTL_GIGA_MAC_VER_23] =
225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
226 [RTL_GIGA_MAC_VER_24] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_25] =
229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
230 JUMBO_9K, false),
231 [RTL_GIGA_MAC_VER_26] =
232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
233 JUMBO_9K, false),
234 [RTL_GIGA_MAC_VER_27] =
235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
236 [RTL_GIGA_MAC_VER_28] =
237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
238 [RTL_GIGA_MAC_VER_29] =
239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
240 JUMBO_1K, true),
241 [RTL_GIGA_MAC_VER_30] =
242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
243 JUMBO_1K, true),
244 [RTL_GIGA_MAC_VER_31] =
245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_32] =
247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
248 JUMBO_9K, false),
249 [RTL_GIGA_MAC_VER_33] =
250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
251 JUMBO_9K, false),
252 [RTL_GIGA_MAC_VER_34] =
253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
254 JUMBO_9K, false),
255 [RTL_GIGA_MAC_VER_35] =
256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
257 JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_36] =
259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
263 JUMBO_1K, true),
264 [RTL_GIGA_MAC_VER_38] =
265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_39] =
268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
269 JUMBO_1K, true),
270 [RTL_GIGA_MAC_VER_40] =
271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_41] =
274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
275 [RTL_GIGA_MAC_VER_42] =
276 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
277 JUMBO_9K, false),
278 [RTL_GIGA_MAC_VER_43] =
279 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
280 JUMBO_1K, true),
281 [RTL_GIGA_MAC_VER_44] =
282 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
283 JUMBO_9K, false),
284 };
285 #undef _R
286
287 enum cfg_version {
288 RTL_CFG_0 = 0x00,
289 RTL_CFG_1,
290 RTL_CFG_2
291 };
292
293 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
294 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
298 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
299 { PCI_VENDOR_ID_DLINK, 0x4300,
300 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
301 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
302 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
303 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
304 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
305 { PCI_VENDOR_ID_LINKSYS, 0x1032,
306 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
307 { 0x0001, 0x8168,
308 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
309 {0,},
310 };
311
312 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
313
314 static int rx_buf_sz = 16383;
315 static int use_dac;
316 static struct {
317 u32 msg_enable;
318 } debug = { -1 };
319
320 enum rtl_registers {
321 MAC0 = 0, /* Ethernet hardware address. */
322 MAC4 = 4,
323 MAR0 = 8, /* Multicast filter. */
324 CounterAddrLow = 0x10,
325 CounterAddrHigh = 0x14,
326 TxDescStartAddrLow = 0x20,
327 TxDescStartAddrHigh = 0x24,
328 TxHDescStartAddrLow = 0x28,
329 TxHDescStartAddrHigh = 0x2c,
330 FLASH = 0x30,
331 ERSR = 0x36,
332 ChipCmd = 0x37,
333 TxPoll = 0x38,
334 IntrMask = 0x3c,
335 IntrStatus = 0x3e,
336
337 TxConfig = 0x40,
338 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
339 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
340
341 RxConfig = 0x44,
342 #define RX128_INT_EN (1 << 15) /* 8111c and later */
343 #define RX_MULTI_EN (1 << 14) /* 8111c only */
344 #define RXCFG_FIFO_SHIFT 13
345 /* No threshold before first PCI xfer */
346 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
347 #define RX_EARLY_OFF (1 << 11)
348 #define RXCFG_DMA_SHIFT 8
349 /* Unlimited maximum PCI burst. */
350 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
351
352 RxMissed = 0x4c,
353 Cfg9346 = 0x50,
354 Config0 = 0x51,
355 Config1 = 0x52,
356 Config2 = 0x53,
357 #define PME_SIGNAL (1 << 5) /* 8168c and later */
358
359 Config3 = 0x54,
360 Config4 = 0x55,
361 Config5 = 0x56,
362 MultiIntr = 0x5c,
363 PHYAR = 0x60,
364 PHYstatus = 0x6c,
365 RxMaxSize = 0xda,
366 CPlusCmd = 0xe0,
367 IntrMitigate = 0xe2,
368 RxDescAddrLow = 0xe4,
369 RxDescAddrHigh = 0xe8,
370 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
371
372 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
373
374 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
375
376 #define TxPacketMax (8064 >> 7)
377 #define EarlySize 0x27
378
379 FuncEvent = 0xf0,
380 FuncEventMask = 0xf4,
381 FuncPresetState = 0xf8,
382 FuncForceEvent = 0xfc,
383 };
384
385 enum rtl8110_registers {
386 TBICSR = 0x64,
387 TBI_ANAR = 0x68,
388 TBI_LPAR = 0x6a,
389 };
390
391 enum rtl8168_8101_registers {
392 CSIDR = 0x64,
393 CSIAR = 0x68,
394 #define CSIAR_FLAG 0x80000000
395 #define CSIAR_WRITE_CMD 0x80000000
396 #define CSIAR_BYTE_ENABLE 0x0f
397 #define CSIAR_BYTE_ENABLE_SHIFT 12
398 #define CSIAR_ADDR_MASK 0x0fff
399 #define CSIAR_FUNC_CARD 0x00000000
400 #define CSIAR_FUNC_SDIO 0x00010000
401 #define CSIAR_FUNC_NIC 0x00020000
402 #define CSIAR_FUNC_NIC2 0x00010000
403 PMCH = 0x6f,
404 EPHYAR = 0x80,
405 #define EPHYAR_FLAG 0x80000000
406 #define EPHYAR_WRITE_CMD 0x80000000
407 #define EPHYAR_REG_MASK 0x1f
408 #define EPHYAR_REG_SHIFT 16
409 #define EPHYAR_DATA_MASK 0xffff
410 DLLPR = 0xd0,
411 #define PFM_EN (1 << 6)
412 DBG_REG = 0xd1,
413 #define FIX_NAK_1 (1 << 4)
414 #define FIX_NAK_2 (1 << 3)
415 TWSI = 0xd2,
416 MCU = 0xd3,
417 #define NOW_IS_OOB (1 << 7)
418 #define TX_EMPTY (1 << 5)
419 #define RX_EMPTY (1 << 4)
420 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
421 #define EN_NDP (1 << 3)
422 #define EN_OOB_RESET (1 << 2)
423 #define LINK_LIST_RDY (1 << 1)
424 EFUSEAR = 0xdc,
425 #define EFUSEAR_FLAG 0x80000000
426 #define EFUSEAR_WRITE_CMD 0x80000000
427 #define EFUSEAR_READ_CMD 0x00000000
428 #define EFUSEAR_REG_MASK 0x03ff
429 #define EFUSEAR_REG_SHIFT 8
430 #define EFUSEAR_DATA_MASK 0xff
431 };
432
433 enum rtl8168_registers {
434 LED_FREQ = 0x1a,
435 EEE_LED = 0x1b,
436 ERIDR = 0x70,
437 ERIAR = 0x74,
438 #define ERIAR_FLAG 0x80000000
439 #define ERIAR_WRITE_CMD 0x80000000
440 #define ERIAR_READ_CMD 0x00000000
441 #define ERIAR_ADDR_BYTE_ALIGN 4
442 #define ERIAR_TYPE_SHIFT 16
443 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
444 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
445 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
446 #define ERIAR_MASK_SHIFT 12
447 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
448 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
449 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
450 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
451 EPHY_RXER_NUM = 0x7c,
452 OCPDR = 0xb0, /* OCP GPHY access */
453 #define OCPDR_WRITE_CMD 0x80000000
454 #define OCPDR_READ_CMD 0x00000000
455 #define OCPDR_REG_MASK 0x7f
456 #define OCPDR_GPHY_REG_SHIFT 16
457 #define OCPDR_DATA_MASK 0xffff
458 OCPAR = 0xb4,
459 #define OCPAR_FLAG 0x80000000
460 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
461 #define OCPAR_GPHY_READ_CMD 0x0000f060
462 GPHY_OCP = 0xb8,
463 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
464 MISC = 0xf0, /* 8168e only. */
465 #define TXPLA_RST (1 << 29)
466 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
467 #define PWM_EN (1 << 22)
468 #define RXDV_GATED_EN (1 << 19)
469 #define EARLY_TALLY_EN (1 << 16)
470 };
471
472 enum rtl_register_content {
473 /* InterruptStatusBits */
474 SYSErr = 0x8000,
475 PCSTimeout = 0x4000,
476 SWInt = 0x0100,
477 TxDescUnavail = 0x0080,
478 RxFIFOOver = 0x0040,
479 LinkChg = 0x0020,
480 RxOverflow = 0x0010,
481 TxErr = 0x0008,
482 TxOK = 0x0004,
483 RxErr = 0x0002,
484 RxOK = 0x0001,
485
486 /* RxStatusDesc */
487 RxBOVF = (1 << 24),
488 RxFOVF = (1 << 23),
489 RxRWT = (1 << 22),
490 RxRES = (1 << 21),
491 RxRUNT = (1 << 20),
492 RxCRC = (1 << 19),
493
494 /* ChipCmdBits */
495 StopReq = 0x80,
496 CmdReset = 0x10,
497 CmdRxEnb = 0x08,
498 CmdTxEnb = 0x04,
499 RxBufEmpty = 0x01,
500
501 /* TXPoll register p.5 */
502 HPQ = 0x80, /* Poll cmd on the high prio queue */
503 NPQ = 0x40, /* Poll cmd on the low prio queue */
504 FSWInt = 0x01, /* Forced software interrupt */
505
506 /* Cfg9346Bits */
507 Cfg9346_Lock = 0x00,
508 Cfg9346_Unlock = 0xc0,
509
510 /* rx_mode_bits */
511 AcceptErr = 0x20,
512 AcceptRunt = 0x10,
513 AcceptBroadcast = 0x08,
514 AcceptMulticast = 0x04,
515 AcceptMyPhys = 0x02,
516 AcceptAllPhys = 0x01,
517 #define RX_CONFIG_ACCEPT_MASK 0x3f
518
519 /* TxConfigBits */
520 TxInterFrameGapShift = 24,
521 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
522
523 /* Config1 register p.24 */
524 LEDS1 = (1 << 7),
525 LEDS0 = (1 << 6),
526 Speed_down = (1 << 4),
527 MEMMAP = (1 << 3),
528 IOMAP = (1 << 2),
529 VPD = (1 << 1),
530 PMEnable = (1 << 0), /* Power Management Enable */
531
532 /* Config2 register p. 25 */
533 ClkReqEn = (1 << 7), /* Clock Request Enable */
534 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
535 PCI_Clock_66MHz = 0x01,
536 PCI_Clock_33MHz = 0x00,
537
538 /* Config3 register p.25 */
539 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
540 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
541 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
542 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
543
544 /* Config4 register */
545 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
546
547 /* Config5 register p.27 */
548 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
549 MWF = (1 << 5), /* Accept Multicast wakeup frame */
550 UWF = (1 << 4), /* Accept Unicast wakeup frame */
551 Spi_en = (1 << 3),
552 LanWake = (1 << 1), /* LanWake enable/disable */
553 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
554 ASPM_en = (1 << 0), /* ASPM enable */
555
556 /* TBICSR p.28 */
557 TBIReset = 0x80000000,
558 TBILoopback = 0x40000000,
559 TBINwEnable = 0x20000000,
560 TBINwRestart = 0x10000000,
561 TBILinkOk = 0x02000000,
562 TBINwComplete = 0x01000000,
563
564 /* CPlusCmd p.31 */
565 EnableBist = (1 << 15), // 8168 8101
566 Mac_dbgo_oe = (1 << 14), // 8168 8101
567 Normal_mode = (1 << 13), // unused
568 Force_half_dup = (1 << 12), // 8168 8101
569 Force_rxflow_en = (1 << 11), // 8168 8101
570 Force_txflow_en = (1 << 10), // 8168 8101
571 Cxpl_dbg_sel = (1 << 9), // 8168 8101
572 ASF = (1 << 8), // 8168 8101
573 PktCntrDisable = (1 << 7), // 8168 8101
574 Mac_dbgo_sel = 0x001c, // 8168
575 RxVlan = (1 << 6),
576 RxChkSum = (1 << 5),
577 PCIDAC = (1 << 4),
578 PCIMulRW = (1 << 3),
579 INTT_0 = 0x0000, // 8168
580 INTT_1 = 0x0001, // 8168
581 INTT_2 = 0x0002, // 8168
582 INTT_3 = 0x0003, // 8168
583
584 /* rtl8169_PHYstatus */
585 TBI_Enable = 0x80,
586 TxFlowCtrl = 0x40,
587 RxFlowCtrl = 0x20,
588 _1000bpsF = 0x10,
589 _100bps = 0x08,
590 _10bps = 0x04,
591 LinkStatus = 0x02,
592 FullDup = 0x01,
593
594 /* _TBICSRBit */
595 TBILinkOK = 0x02000000,
596
597 /* DumpCounterCommand */
598 CounterDump = 0x8,
599 };
600
601 enum rtl_desc_bit {
602 /* First doubleword. */
603 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
604 RingEnd = (1 << 30), /* End of descriptor ring */
605 FirstFrag = (1 << 29), /* First segment of a packet */
606 LastFrag = (1 << 28), /* Final segment of a packet */
607 };
608
609 /* Generic case. */
610 enum rtl_tx_desc_bit {
611 /* First doubleword. */
612 TD_LSO = (1 << 27), /* Large Send Offload */
613 #define TD_MSS_MAX 0x07ffu /* MSS value */
614
615 /* Second doubleword. */
616 TxVlanTag = (1 << 17), /* Add VLAN tag */
617 };
618
619 /* 8169, 8168b and 810x except 8102e. */
620 enum rtl_tx_desc_bit_0 {
621 /* First doubleword. */
622 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
623 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
624 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
625 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
626 };
627
628 /* 8102e, 8168c and beyond. */
629 enum rtl_tx_desc_bit_1 {
630 /* Second doubleword. */
631 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
632 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
633 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
634 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
635 };
636
637 static const struct rtl_tx_desc_info {
638 struct {
639 u32 udp;
640 u32 tcp;
641 } checksum;
642 u16 mss_shift;
643 u16 opts_offset;
644 } tx_desc_info [] = {
645 [RTL_TD_0] = {
646 .checksum = {
647 .udp = TD0_IP_CS | TD0_UDP_CS,
648 .tcp = TD0_IP_CS | TD0_TCP_CS
649 },
650 .mss_shift = TD0_MSS_SHIFT,
651 .opts_offset = 0
652 },
653 [RTL_TD_1] = {
654 .checksum = {
655 .udp = TD1_IP_CS | TD1_UDP_CS,
656 .tcp = TD1_IP_CS | TD1_TCP_CS
657 },
658 .mss_shift = TD1_MSS_SHIFT,
659 .opts_offset = 1
660 }
661 };
662
663 enum rtl_rx_desc_bit {
664 /* Rx private */
665 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
666 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
667
668 #define RxProtoUDP (PID1)
669 #define RxProtoTCP (PID0)
670 #define RxProtoIP (PID1 | PID0)
671 #define RxProtoMask RxProtoIP
672
673 IPFail = (1 << 16), /* IP checksum failed */
674 UDPFail = (1 << 15), /* UDP/IP checksum failed */
675 TCPFail = (1 << 14), /* TCP/IP checksum failed */
676 RxVlanTag = (1 << 16), /* VLAN tag available */
677 };
678
679 #define RsvdMask 0x3fffc000
680
681 struct TxDesc {
682 __le32 opts1;
683 __le32 opts2;
684 __le64 addr;
685 };
686
687 struct RxDesc {
688 __le32 opts1;
689 __le32 opts2;
690 __le64 addr;
691 };
692
693 struct ring_info {
694 struct sk_buff *skb;
695 u32 len;
696 u8 __pad[sizeof(void *) - sizeof(u32)];
697 };
698
699 enum features {
700 RTL_FEATURE_WOL = (1 << 0),
701 RTL_FEATURE_MSI = (1 << 1),
702 RTL_FEATURE_GMII = (1 << 2),
703 };
704
705 struct rtl8169_counters {
706 __le64 tx_packets;
707 __le64 rx_packets;
708 __le64 tx_errors;
709 __le32 rx_errors;
710 __le16 rx_missed;
711 __le16 align_errors;
712 __le32 tx_one_collision;
713 __le32 tx_multi_collision;
714 __le64 rx_unicast;
715 __le64 rx_broadcast;
716 __le32 rx_multicast;
717 __le16 tx_aborted;
718 __le16 tx_underun;
719 };
720
721 enum rtl_flag {
722 RTL_FLAG_TASK_ENABLED,
723 RTL_FLAG_TASK_SLOW_PENDING,
724 RTL_FLAG_TASK_RESET_PENDING,
725 RTL_FLAG_TASK_PHY_PENDING,
726 RTL_FLAG_MAX
727 };
728
729 struct rtl8169_stats {
730 u64 packets;
731 u64 bytes;
732 struct u64_stats_sync syncp;
733 };
734
735 struct rtl8169_private {
736 void __iomem *mmio_addr; /* memory map physical address */
737 struct pci_dev *pci_dev;
738 struct net_device *dev;
739 struct napi_struct napi;
740 u32 msg_enable;
741 u16 txd_version;
742 u16 mac_version;
743 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
744 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
745 u32 dirty_tx;
746 struct rtl8169_stats rx_stats;
747 struct rtl8169_stats tx_stats;
748 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
749 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
750 dma_addr_t TxPhyAddr;
751 dma_addr_t RxPhyAddr;
752 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
753 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
754 struct timer_list timer;
755 u16 cp_cmd;
756
757 u16 event_slow;
758
759 struct mdio_ops {
760 void (*write)(struct rtl8169_private *, int, int);
761 int (*read)(struct rtl8169_private *, int);
762 } mdio_ops;
763
764 struct pll_power_ops {
765 void (*down)(struct rtl8169_private *);
766 void (*up)(struct rtl8169_private *);
767 } pll_power_ops;
768
769 struct jumbo_ops {
770 void (*enable)(struct rtl8169_private *);
771 void (*disable)(struct rtl8169_private *);
772 } jumbo_ops;
773
774 struct csi_ops {
775 void (*write)(struct rtl8169_private *, int, int);
776 u32 (*read)(struct rtl8169_private *, int);
777 } csi_ops;
778
779 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
780 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
781 void (*phy_reset_enable)(struct rtl8169_private *tp);
782 void (*hw_start)(struct net_device *);
783 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
784 unsigned int (*link_ok)(void __iomem *);
785 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
786
787 struct {
788 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
789 struct mutex mutex;
790 struct work_struct work;
791 } wk;
792
793 unsigned features;
794
795 struct mii_if_info mii;
796 struct rtl8169_counters counters;
797 u32 saved_wolopts;
798 u32 opts1_mask;
799
800 struct rtl_fw {
801 const struct firmware *fw;
802
803 #define RTL_VER_SIZE 32
804
805 char version[RTL_VER_SIZE];
806
807 struct rtl_fw_phy_action {
808 __le32 *code;
809 size_t size;
810 } phy_action;
811 } *rtl_fw;
812 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
813
814 u32 ocp_base;
815 };
816
817 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
818 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
819 module_param(use_dac, int, 0);
820 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
821 module_param_named(debug, debug.msg_enable, int, 0);
822 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
823 MODULE_LICENSE("GPL");
824 MODULE_VERSION(RTL8169_VERSION);
825 MODULE_FIRMWARE(FIRMWARE_8168D_1);
826 MODULE_FIRMWARE(FIRMWARE_8168D_2);
827 MODULE_FIRMWARE(FIRMWARE_8168E_1);
828 MODULE_FIRMWARE(FIRMWARE_8168E_2);
829 MODULE_FIRMWARE(FIRMWARE_8168E_3);
830 MODULE_FIRMWARE(FIRMWARE_8105E_1);
831 MODULE_FIRMWARE(FIRMWARE_8168F_1);
832 MODULE_FIRMWARE(FIRMWARE_8168F_2);
833 MODULE_FIRMWARE(FIRMWARE_8402_1);
834 MODULE_FIRMWARE(FIRMWARE_8411_1);
835 MODULE_FIRMWARE(FIRMWARE_8411_2);
836 MODULE_FIRMWARE(FIRMWARE_8106E_1);
837 MODULE_FIRMWARE(FIRMWARE_8106E_2);
838 MODULE_FIRMWARE(FIRMWARE_8168G_2);
839 MODULE_FIRMWARE(FIRMWARE_8168G_3);
840
841 static void rtl_lock_work(struct rtl8169_private *tp)
842 {
843 mutex_lock(&tp->wk.mutex);
844 }
845
846 static void rtl_unlock_work(struct rtl8169_private *tp)
847 {
848 mutex_unlock(&tp->wk.mutex);
849 }
850
851 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
852 {
853 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
854 PCI_EXP_DEVCTL_READRQ, force);
855 }
856
857 struct rtl_cond {
858 bool (*check)(struct rtl8169_private *);
859 const char *msg;
860 };
861
862 static void rtl_udelay(unsigned int d)
863 {
864 udelay(d);
865 }
866
867 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
868 void (*delay)(unsigned int), unsigned int d, int n,
869 bool high)
870 {
871 int i;
872
873 for (i = 0; i < n; i++) {
874 delay(d);
875 if (c->check(tp) == high)
876 return true;
877 }
878 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
879 c->msg, !high, n, d);
880 return false;
881 }
882
883 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
886 {
887 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
888 }
889
890 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
893 {
894 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
895 }
896
897 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
898 const struct rtl_cond *c,
899 unsigned int d, int n)
900 {
901 return rtl_loop_wait(tp, c, msleep, d, n, true);
902 }
903
904 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
905 const struct rtl_cond *c,
906 unsigned int d, int n)
907 {
908 return rtl_loop_wait(tp, c, msleep, d, n, false);
909 }
910
911 #define DECLARE_RTL_COND(name) \
912 static bool name ## _check(struct rtl8169_private *); \
913 \
914 static const struct rtl_cond name = { \
915 .check = name ## _check, \
916 .msg = #name \
917 }; \
918 \
919 static bool name ## _check(struct rtl8169_private *tp)
920
921 DECLARE_RTL_COND(rtl_ocpar_cond)
922 {
923 void __iomem *ioaddr = tp->mmio_addr;
924
925 return RTL_R32(OCPAR) & OCPAR_FLAG;
926 }
927
928 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
929 {
930 void __iomem *ioaddr = tp->mmio_addr;
931
932 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
933
934 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
935 RTL_R32(OCPDR) : ~0;
936 }
937
938 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
939 {
940 void __iomem *ioaddr = tp->mmio_addr;
941
942 RTL_W32(OCPDR, data);
943 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
944
945 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
946 }
947
948 DECLARE_RTL_COND(rtl_eriar_cond)
949 {
950 void __iomem *ioaddr = tp->mmio_addr;
951
952 return RTL_R32(ERIAR) & ERIAR_FLAG;
953 }
954
955 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
956 {
957 void __iomem *ioaddr = tp->mmio_addr;
958
959 RTL_W8(ERIDR, cmd);
960 RTL_W32(ERIAR, 0x800010e8);
961 msleep(2);
962
963 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
964 return;
965
966 ocp_write(tp, 0x1, 0x30, 0x00000001);
967 }
968
969 #define OOB_CMD_RESET 0x00
970 #define OOB_CMD_DRIVER_START 0x05
971 #define OOB_CMD_DRIVER_STOP 0x06
972
973 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
974 {
975 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
976 }
977
978 DECLARE_RTL_COND(rtl_ocp_read_cond)
979 {
980 u16 reg;
981
982 reg = rtl8168_get_ocp_reg(tp);
983
984 return ocp_read(tp, 0x0f, reg) & 0x00000800;
985 }
986
987 static void rtl8168_driver_start(struct rtl8169_private *tp)
988 {
989 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
990
991 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
992 }
993
994 static void rtl8168_driver_stop(struct rtl8169_private *tp)
995 {
996 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
997
998 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
999 }
1000
1001 static int r8168dp_check_dash(struct rtl8169_private *tp)
1002 {
1003 u16 reg = rtl8168_get_ocp_reg(tp);
1004
1005 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1006 }
1007
1008 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1009 {
1010 if (reg & 0xffff0001) {
1011 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1012 return true;
1013 }
1014 return false;
1015 }
1016
1017 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1018 {
1019 void __iomem *ioaddr = tp->mmio_addr;
1020
1021 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1022 }
1023
1024 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1025 {
1026 void __iomem *ioaddr = tp->mmio_addr;
1027
1028 if (rtl_ocp_reg_failure(tp, reg))
1029 return;
1030
1031 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1032
1033 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1034 }
1035
1036 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1037 {
1038 void __iomem *ioaddr = tp->mmio_addr;
1039
1040 if (rtl_ocp_reg_failure(tp, reg))
1041 return 0;
1042
1043 RTL_W32(GPHY_OCP, reg << 15);
1044
1045 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1046 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1047 }
1048
1049 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1050 {
1051 void __iomem *ioaddr = tp->mmio_addr;
1052
1053 if (rtl_ocp_reg_failure(tp, reg))
1054 return;
1055
1056 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1057 }
1058
1059 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1060 {
1061 void __iomem *ioaddr = tp->mmio_addr;
1062
1063 if (rtl_ocp_reg_failure(tp, reg))
1064 return 0;
1065
1066 RTL_W32(OCPDR, reg << 15);
1067
1068 return RTL_R32(OCPDR);
1069 }
1070
1071 #define OCP_STD_PHY_BASE 0xa400
1072
1073 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1074 {
1075 if (reg == 0x1f) {
1076 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1077 return;
1078 }
1079
1080 if (tp->ocp_base != OCP_STD_PHY_BASE)
1081 reg -= 0x10;
1082
1083 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1084 }
1085
1086 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1087 {
1088 if (tp->ocp_base != OCP_STD_PHY_BASE)
1089 reg -= 0x10;
1090
1091 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1092 }
1093
1094 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1095 {
1096 if (reg == 0x1f) {
1097 tp->ocp_base = value << 4;
1098 return;
1099 }
1100
1101 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1102 }
1103
1104 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1105 {
1106 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1107 }
1108
1109 DECLARE_RTL_COND(rtl_phyar_cond)
1110 {
1111 void __iomem *ioaddr = tp->mmio_addr;
1112
1113 return RTL_R32(PHYAR) & 0x80000000;
1114 }
1115
1116 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1117 {
1118 void __iomem *ioaddr = tp->mmio_addr;
1119
1120 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1121
1122 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1123 /*
1124 * According to hardware specs a 20us delay is required after write
1125 * complete indication, but before sending next command.
1126 */
1127 udelay(20);
1128 }
1129
1130 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1131 {
1132 void __iomem *ioaddr = tp->mmio_addr;
1133 int value;
1134
1135 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1136
1137 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1138 RTL_R32(PHYAR) & 0xffff : ~0;
1139
1140 /*
1141 * According to hardware specs a 20us delay is required after read
1142 * complete indication, but before sending next command.
1143 */
1144 udelay(20);
1145
1146 return value;
1147 }
1148
1149 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1150 {
1151 void __iomem *ioaddr = tp->mmio_addr;
1152
1153 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1154 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1155 RTL_W32(EPHY_RXER_NUM, 0);
1156
1157 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1158 }
1159
1160 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1161 {
1162 r8168dp_1_mdio_access(tp, reg,
1163 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1164 }
1165
1166 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1167 {
1168 void __iomem *ioaddr = tp->mmio_addr;
1169
1170 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1171
1172 mdelay(1);
1173 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1174 RTL_W32(EPHY_RXER_NUM, 0);
1175
1176 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1177 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1178 }
1179
1180 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1181
1182 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1183 {
1184 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1185 }
1186
1187 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1188 {
1189 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1190 }
1191
1192 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1193 {
1194 void __iomem *ioaddr = tp->mmio_addr;
1195
1196 r8168dp_2_mdio_start(ioaddr);
1197
1198 r8169_mdio_write(tp, reg, value);
1199
1200 r8168dp_2_mdio_stop(ioaddr);
1201 }
1202
1203 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1204 {
1205 void __iomem *ioaddr = tp->mmio_addr;
1206 int value;
1207
1208 r8168dp_2_mdio_start(ioaddr);
1209
1210 value = r8169_mdio_read(tp, reg);
1211
1212 r8168dp_2_mdio_stop(ioaddr);
1213
1214 return value;
1215 }
1216
1217 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1218 {
1219 tp->mdio_ops.write(tp, location, val);
1220 }
1221
1222 static int rtl_readphy(struct rtl8169_private *tp, int location)
1223 {
1224 return tp->mdio_ops.read(tp, location);
1225 }
1226
1227 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1228 {
1229 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1230 }
1231
1232 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1233 {
1234 int val;
1235
1236 val = rtl_readphy(tp, reg_addr);
1237 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1238 }
1239
1240 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1241 int val)
1242 {
1243 struct rtl8169_private *tp = netdev_priv(dev);
1244
1245 rtl_writephy(tp, location, val);
1246 }
1247
1248 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1249 {
1250 struct rtl8169_private *tp = netdev_priv(dev);
1251
1252 return rtl_readphy(tp, location);
1253 }
1254
1255 DECLARE_RTL_COND(rtl_ephyar_cond)
1256 {
1257 void __iomem *ioaddr = tp->mmio_addr;
1258
1259 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1260 }
1261
1262 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1263 {
1264 void __iomem *ioaddr = tp->mmio_addr;
1265
1266 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1267 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1268
1269 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1270
1271 udelay(10);
1272 }
1273
1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1275 {
1276 void __iomem *ioaddr = tp->mmio_addr;
1277
1278 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1279
1280 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1281 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1282 }
1283
1284 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1285 u32 val, int type)
1286 {
1287 void __iomem *ioaddr = tp->mmio_addr;
1288
1289 BUG_ON((addr & 3) || (mask == 0));
1290 RTL_W32(ERIDR, val);
1291 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1292
1293 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1294 }
1295
1296 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1297 {
1298 void __iomem *ioaddr = tp->mmio_addr;
1299
1300 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1301
1302 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1303 RTL_R32(ERIDR) : ~0;
1304 }
1305
1306 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1307 u32 m, int type)
1308 {
1309 u32 val;
1310
1311 val = rtl_eri_read(tp, addr, type);
1312 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1313 }
1314
1315 struct exgmac_reg {
1316 u16 addr;
1317 u16 mask;
1318 u32 val;
1319 };
1320
1321 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1322 const struct exgmac_reg *r, int len)
1323 {
1324 while (len-- > 0) {
1325 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1326 r++;
1327 }
1328 }
1329
1330 DECLARE_RTL_COND(rtl_efusear_cond)
1331 {
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1335 }
1336
1337 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1338 {
1339 void __iomem *ioaddr = tp->mmio_addr;
1340
1341 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1342
1343 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1344 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1345 }
1346
1347 static u16 rtl_get_events(struct rtl8169_private *tp)
1348 {
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 return RTL_R16(IntrStatus);
1352 }
1353
1354 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1355 {
1356 void __iomem *ioaddr = tp->mmio_addr;
1357
1358 RTL_W16(IntrStatus, bits);
1359 mmiowb();
1360 }
1361
1362 static void rtl_irq_disable(struct rtl8169_private *tp)
1363 {
1364 void __iomem *ioaddr = tp->mmio_addr;
1365
1366 RTL_W16(IntrMask, 0);
1367 mmiowb();
1368 }
1369
1370 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1371 {
1372 void __iomem *ioaddr = tp->mmio_addr;
1373
1374 RTL_W16(IntrMask, bits);
1375 }
1376
1377 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1378 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1379 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1380
1381 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1382 {
1383 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1384 }
1385
1386 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1387 {
1388 void __iomem *ioaddr = tp->mmio_addr;
1389
1390 rtl_irq_disable(tp);
1391 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1392 RTL_R8(ChipCmd);
1393 }
1394
1395 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1396 {
1397 void __iomem *ioaddr = tp->mmio_addr;
1398
1399 return RTL_R32(TBICSR) & TBIReset;
1400 }
1401
1402 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1403 {
1404 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1405 }
1406
1407 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1408 {
1409 return RTL_R32(TBICSR) & TBILinkOk;
1410 }
1411
1412 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1413 {
1414 return RTL_R8(PHYstatus) & LinkStatus;
1415 }
1416
1417 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1418 {
1419 void __iomem *ioaddr = tp->mmio_addr;
1420
1421 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1422 }
1423
1424 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1425 {
1426 unsigned int val;
1427
1428 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1429 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1430 }
1431
1432 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1433 {
1434 void __iomem *ioaddr = tp->mmio_addr;
1435 struct net_device *dev = tp->dev;
1436
1437 if (!netif_running(dev))
1438 return;
1439
1440 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1441 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1442 if (RTL_R8(PHYstatus) & _1000bpsF) {
1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1444 ERIAR_EXGMAC);
1445 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1446 ERIAR_EXGMAC);
1447 } else if (RTL_R8(PHYstatus) & _100bps) {
1448 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1449 ERIAR_EXGMAC);
1450 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1451 ERIAR_EXGMAC);
1452 } else {
1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1454 ERIAR_EXGMAC);
1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1456 ERIAR_EXGMAC);
1457 }
1458 /* Reset packet filter */
1459 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1460 ERIAR_EXGMAC);
1461 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1462 ERIAR_EXGMAC);
1463 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1464 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1465 if (RTL_R8(PHYstatus) & _1000bpsF) {
1466 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1467 ERIAR_EXGMAC);
1468 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1469 ERIAR_EXGMAC);
1470 } else {
1471 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1472 ERIAR_EXGMAC);
1473 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1474 ERIAR_EXGMAC);
1475 }
1476 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1477 if (RTL_R8(PHYstatus) & _10bps) {
1478 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1479 ERIAR_EXGMAC);
1480 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1481 ERIAR_EXGMAC);
1482 } else {
1483 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1484 ERIAR_EXGMAC);
1485 }
1486 }
1487 }
1488
1489 static void __rtl8169_check_link_status(struct net_device *dev,
1490 struct rtl8169_private *tp,
1491 void __iomem *ioaddr, bool pm)
1492 {
1493 if (tp->link_ok(ioaddr)) {
1494 rtl_link_chg_patch(tp);
1495 /* This is to cancel a scheduled suspend if there's one. */
1496 if (pm)
1497 pm_request_resume(&tp->pci_dev->dev);
1498 netif_carrier_on(dev);
1499 if (net_ratelimit())
1500 netif_info(tp, ifup, dev, "link up\n");
1501 } else {
1502 netif_carrier_off(dev);
1503 netif_info(tp, ifdown, dev, "link down\n");
1504 if (pm)
1505 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1506 }
1507 }
1508
1509 static void rtl8169_check_link_status(struct net_device *dev,
1510 struct rtl8169_private *tp,
1511 void __iomem *ioaddr)
1512 {
1513 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1514 }
1515
1516 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1517
1518 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1519 {
1520 void __iomem *ioaddr = tp->mmio_addr;
1521 u8 options;
1522 u32 wolopts = 0;
1523
1524 options = RTL_R8(Config1);
1525 if (!(options & PMEnable))
1526 return 0;
1527
1528 options = RTL_R8(Config3);
1529 if (options & LinkUp)
1530 wolopts |= WAKE_PHY;
1531 if (options & MagicPacket)
1532 wolopts |= WAKE_MAGIC;
1533
1534 options = RTL_R8(Config5);
1535 if (options & UWF)
1536 wolopts |= WAKE_UCAST;
1537 if (options & BWF)
1538 wolopts |= WAKE_BCAST;
1539 if (options & MWF)
1540 wolopts |= WAKE_MCAST;
1541
1542 return wolopts;
1543 }
1544
1545 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1546 {
1547 struct rtl8169_private *tp = netdev_priv(dev);
1548
1549 rtl_lock_work(tp);
1550
1551 wol->supported = WAKE_ANY;
1552 wol->wolopts = __rtl8169_get_wol(tp);
1553
1554 rtl_unlock_work(tp);
1555 }
1556
1557 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1558 {
1559 void __iomem *ioaddr = tp->mmio_addr;
1560 unsigned int i;
1561 static const struct {
1562 u32 opt;
1563 u16 reg;
1564 u8 mask;
1565 } cfg[] = {
1566 { WAKE_PHY, Config3, LinkUp },
1567 { WAKE_MAGIC, Config3, MagicPacket },
1568 { WAKE_UCAST, Config5, UWF },
1569 { WAKE_BCAST, Config5, BWF },
1570 { WAKE_MCAST, Config5, MWF },
1571 { WAKE_ANY, Config5, LanWake }
1572 };
1573 u8 options;
1574
1575 RTL_W8(Cfg9346, Cfg9346_Unlock);
1576
1577 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1578 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1579 if (wolopts & cfg[i].opt)
1580 options |= cfg[i].mask;
1581 RTL_W8(cfg[i].reg, options);
1582 }
1583
1584 switch (tp->mac_version) {
1585 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1586 options = RTL_R8(Config1) & ~PMEnable;
1587 if (wolopts)
1588 options |= PMEnable;
1589 RTL_W8(Config1, options);
1590 break;
1591 default:
1592 options = RTL_R8(Config2) & ~PME_SIGNAL;
1593 if (wolopts)
1594 options |= PME_SIGNAL;
1595 RTL_W8(Config2, options);
1596 break;
1597 }
1598
1599 RTL_W8(Cfg9346, Cfg9346_Lock);
1600 }
1601
1602 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1603 {
1604 struct rtl8169_private *tp = netdev_priv(dev);
1605
1606 rtl_lock_work(tp);
1607
1608 if (wol->wolopts)
1609 tp->features |= RTL_FEATURE_WOL;
1610 else
1611 tp->features &= ~RTL_FEATURE_WOL;
1612 __rtl8169_set_wol(tp, wol->wolopts);
1613
1614 rtl_unlock_work(tp);
1615
1616 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1617
1618 return 0;
1619 }
1620
1621 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1622 {
1623 return rtl_chip_infos[tp->mac_version].fw_name;
1624 }
1625
1626 static void rtl8169_get_drvinfo(struct net_device *dev,
1627 struct ethtool_drvinfo *info)
1628 {
1629 struct rtl8169_private *tp = netdev_priv(dev);
1630 struct rtl_fw *rtl_fw = tp->rtl_fw;
1631
1632 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1633 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1634 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1635 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1636 if (!IS_ERR_OR_NULL(rtl_fw))
1637 strlcpy(info->fw_version, rtl_fw->version,
1638 sizeof(info->fw_version));
1639 }
1640
1641 static int rtl8169_get_regs_len(struct net_device *dev)
1642 {
1643 return R8169_REGS_SIZE;
1644 }
1645
1646 static int rtl8169_set_speed_tbi(struct net_device *dev,
1647 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1648 {
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650 void __iomem *ioaddr = tp->mmio_addr;
1651 int ret = 0;
1652 u32 reg;
1653
1654 reg = RTL_R32(TBICSR);
1655 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1656 (duplex == DUPLEX_FULL)) {
1657 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1658 } else if (autoneg == AUTONEG_ENABLE)
1659 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1660 else {
1661 netif_warn(tp, link, dev,
1662 "incorrect speed setting refused in TBI mode\n");
1663 ret = -EOPNOTSUPP;
1664 }
1665
1666 return ret;
1667 }
1668
1669 static int rtl8169_set_speed_xmii(struct net_device *dev,
1670 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1671 {
1672 struct rtl8169_private *tp = netdev_priv(dev);
1673 int giga_ctrl, bmcr;
1674 int rc = -EINVAL;
1675
1676 rtl_writephy(tp, 0x1f, 0x0000);
1677
1678 if (autoneg == AUTONEG_ENABLE) {
1679 int auto_nego;
1680
1681 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1682 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1683 ADVERTISE_100HALF | ADVERTISE_100FULL);
1684
1685 if (adv & ADVERTISED_10baseT_Half)
1686 auto_nego |= ADVERTISE_10HALF;
1687 if (adv & ADVERTISED_10baseT_Full)
1688 auto_nego |= ADVERTISE_10FULL;
1689 if (adv & ADVERTISED_100baseT_Half)
1690 auto_nego |= ADVERTISE_100HALF;
1691 if (adv & ADVERTISED_100baseT_Full)
1692 auto_nego |= ADVERTISE_100FULL;
1693
1694 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1695
1696 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1698
1699 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1700 if (tp->mii.supports_gmii) {
1701 if (adv & ADVERTISED_1000baseT_Half)
1702 giga_ctrl |= ADVERTISE_1000HALF;
1703 if (adv & ADVERTISED_1000baseT_Full)
1704 giga_ctrl |= ADVERTISE_1000FULL;
1705 } else if (adv & (ADVERTISED_1000baseT_Half |
1706 ADVERTISED_1000baseT_Full)) {
1707 netif_info(tp, link, dev,
1708 "PHY does not support 1000Mbps\n");
1709 goto out;
1710 }
1711
1712 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1713
1714 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1715 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1716 } else {
1717 giga_ctrl = 0;
1718
1719 if (speed == SPEED_10)
1720 bmcr = 0;
1721 else if (speed == SPEED_100)
1722 bmcr = BMCR_SPEED100;
1723 else
1724 goto out;
1725
1726 if (duplex == DUPLEX_FULL)
1727 bmcr |= BMCR_FULLDPLX;
1728 }
1729
1730 rtl_writephy(tp, MII_BMCR, bmcr);
1731
1732 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1733 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1734 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1735 rtl_writephy(tp, 0x17, 0x2138);
1736 rtl_writephy(tp, 0x0e, 0x0260);
1737 } else {
1738 rtl_writephy(tp, 0x17, 0x2108);
1739 rtl_writephy(tp, 0x0e, 0x0000);
1740 }
1741 }
1742
1743 rc = 0;
1744 out:
1745 return rc;
1746 }
1747
1748 static int rtl8169_set_speed(struct net_device *dev,
1749 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1750 {
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 int ret;
1753
1754 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1755 if (ret < 0)
1756 goto out;
1757
1758 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1759 (advertising & ADVERTISED_1000baseT_Full)) {
1760 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1761 }
1762 out:
1763 return ret;
1764 }
1765
1766 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1767 {
1768 struct rtl8169_private *tp = netdev_priv(dev);
1769 int ret;
1770
1771 del_timer_sync(&tp->timer);
1772
1773 rtl_lock_work(tp);
1774 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1775 cmd->duplex, cmd->advertising);
1776 rtl_unlock_work(tp);
1777
1778 return ret;
1779 }
1780
1781 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1782 netdev_features_t features)
1783 {
1784 struct rtl8169_private *tp = netdev_priv(dev);
1785
1786 if (dev->mtu > TD_MSS_MAX)
1787 features &= ~NETIF_F_ALL_TSO;
1788
1789 if (dev->mtu > JUMBO_1K &&
1790 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1791 features &= ~NETIF_F_IP_CSUM;
1792
1793 return features;
1794 }
1795
1796 static void __rtl8169_set_features(struct net_device *dev,
1797 netdev_features_t features)
1798 {
1799 struct rtl8169_private *tp = netdev_priv(dev);
1800 netdev_features_t changed = features ^ dev->features;
1801 void __iomem *ioaddr = tp->mmio_addr;
1802
1803 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1804 NETIF_F_HW_VLAN_CTAG_RX)))
1805 return;
1806
1807 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1808 if (features & NETIF_F_RXCSUM)
1809 tp->cp_cmd |= RxChkSum;
1810 else
1811 tp->cp_cmd &= ~RxChkSum;
1812
1813 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1814 tp->cp_cmd |= RxVlan;
1815 else
1816 tp->cp_cmd &= ~RxVlan;
1817
1818 RTL_W16(CPlusCmd, tp->cp_cmd);
1819 RTL_R16(CPlusCmd);
1820 }
1821 if (changed & NETIF_F_RXALL) {
1822 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1823 if (features & NETIF_F_RXALL)
1824 tmp |= (AcceptErr | AcceptRunt);
1825 RTL_W32(RxConfig, tmp);
1826 }
1827 }
1828
1829 static int rtl8169_set_features(struct net_device *dev,
1830 netdev_features_t features)
1831 {
1832 struct rtl8169_private *tp = netdev_priv(dev);
1833
1834 rtl_lock_work(tp);
1835 __rtl8169_set_features(dev, features);
1836 rtl_unlock_work(tp);
1837
1838 return 0;
1839 }
1840
1841
1842 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1843 {
1844 return (vlan_tx_tag_present(skb)) ?
1845 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1846 }
1847
1848 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1849 {
1850 u32 opts2 = le32_to_cpu(desc->opts2);
1851
1852 if (opts2 & RxVlanTag)
1853 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1854 }
1855
1856 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1857 {
1858 struct rtl8169_private *tp = netdev_priv(dev);
1859 void __iomem *ioaddr = tp->mmio_addr;
1860 u32 status;
1861
1862 cmd->supported =
1863 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1864 cmd->port = PORT_FIBRE;
1865 cmd->transceiver = XCVR_INTERNAL;
1866
1867 status = RTL_R32(TBICSR);
1868 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1869 cmd->autoneg = !!(status & TBINwEnable);
1870
1871 ethtool_cmd_speed_set(cmd, SPEED_1000);
1872 cmd->duplex = DUPLEX_FULL; /* Always set */
1873
1874 return 0;
1875 }
1876
1877 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1878 {
1879 struct rtl8169_private *tp = netdev_priv(dev);
1880
1881 return mii_ethtool_gset(&tp->mii, cmd);
1882 }
1883
1884 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1885 {
1886 struct rtl8169_private *tp = netdev_priv(dev);
1887 int rc;
1888
1889 rtl_lock_work(tp);
1890 rc = tp->get_settings(dev, cmd);
1891 rtl_unlock_work(tp);
1892
1893 return rc;
1894 }
1895
1896 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1897 void *p)
1898 {
1899 struct rtl8169_private *tp = netdev_priv(dev);
1900 u32 __iomem *data = tp->mmio_addr;
1901 u32 *dw = p;
1902 int i;
1903
1904 rtl_lock_work(tp);
1905 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1906 memcpy_fromio(dw++, data++, 4);
1907 rtl_unlock_work(tp);
1908 }
1909
1910 static u32 rtl8169_get_msglevel(struct net_device *dev)
1911 {
1912 struct rtl8169_private *tp = netdev_priv(dev);
1913
1914 return tp->msg_enable;
1915 }
1916
1917 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1918 {
1919 struct rtl8169_private *tp = netdev_priv(dev);
1920
1921 tp->msg_enable = value;
1922 }
1923
1924 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1925 "tx_packets",
1926 "rx_packets",
1927 "tx_errors",
1928 "rx_errors",
1929 "rx_missed",
1930 "align_errors",
1931 "tx_single_collisions",
1932 "tx_multi_collisions",
1933 "unicast",
1934 "broadcast",
1935 "multicast",
1936 "tx_aborted",
1937 "tx_underrun",
1938 };
1939
1940 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1941 {
1942 switch (sset) {
1943 case ETH_SS_STATS:
1944 return ARRAY_SIZE(rtl8169_gstrings);
1945 default:
1946 return -EOPNOTSUPP;
1947 }
1948 }
1949
1950 DECLARE_RTL_COND(rtl_counters_cond)
1951 {
1952 void __iomem *ioaddr = tp->mmio_addr;
1953
1954 return RTL_R32(CounterAddrLow) & CounterDump;
1955 }
1956
1957 static void rtl8169_update_counters(struct net_device *dev)
1958 {
1959 struct rtl8169_private *tp = netdev_priv(dev);
1960 void __iomem *ioaddr = tp->mmio_addr;
1961 struct device *d = &tp->pci_dev->dev;
1962 struct rtl8169_counters *counters;
1963 dma_addr_t paddr;
1964 u32 cmd;
1965
1966 /*
1967 * Some chips are unable to dump tally counters when the receiver
1968 * is disabled.
1969 */
1970 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1971 return;
1972
1973 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1974 if (!counters)
1975 return;
1976
1977 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1978 cmd = (u64)paddr & DMA_BIT_MASK(32);
1979 RTL_W32(CounterAddrLow, cmd);
1980 RTL_W32(CounterAddrLow, cmd | CounterDump);
1981
1982 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1983 memcpy(&tp->counters, counters, sizeof(*counters));
1984
1985 RTL_W32(CounterAddrLow, 0);
1986 RTL_W32(CounterAddrHigh, 0);
1987
1988 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1989 }
1990
1991 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1992 struct ethtool_stats *stats, u64 *data)
1993 {
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995
1996 ASSERT_RTNL();
1997
1998 rtl8169_update_counters(dev);
1999
2000 data[0] = le64_to_cpu(tp->counters.tx_packets);
2001 data[1] = le64_to_cpu(tp->counters.rx_packets);
2002 data[2] = le64_to_cpu(tp->counters.tx_errors);
2003 data[3] = le32_to_cpu(tp->counters.rx_errors);
2004 data[4] = le16_to_cpu(tp->counters.rx_missed);
2005 data[5] = le16_to_cpu(tp->counters.align_errors);
2006 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2007 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2008 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2009 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2010 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2011 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2012 data[12] = le16_to_cpu(tp->counters.tx_underun);
2013 }
2014
2015 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2016 {
2017 switch(stringset) {
2018 case ETH_SS_STATS:
2019 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2020 break;
2021 }
2022 }
2023
2024 static const struct ethtool_ops rtl8169_ethtool_ops = {
2025 .get_drvinfo = rtl8169_get_drvinfo,
2026 .get_regs_len = rtl8169_get_regs_len,
2027 .get_link = ethtool_op_get_link,
2028 .get_settings = rtl8169_get_settings,
2029 .set_settings = rtl8169_set_settings,
2030 .get_msglevel = rtl8169_get_msglevel,
2031 .set_msglevel = rtl8169_set_msglevel,
2032 .get_regs = rtl8169_get_regs,
2033 .get_wol = rtl8169_get_wol,
2034 .set_wol = rtl8169_set_wol,
2035 .get_strings = rtl8169_get_strings,
2036 .get_sset_count = rtl8169_get_sset_count,
2037 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2038 .get_ts_info = ethtool_op_get_ts_info,
2039 };
2040
2041 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2042 struct net_device *dev, u8 default_version)
2043 {
2044 void __iomem *ioaddr = tp->mmio_addr;
2045 /*
2046 * The driver currently handles the 8168Bf and the 8168Be identically
2047 * but they can be identified more specifically through the test below
2048 * if needed:
2049 *
2050 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2051 *
2052 * Same thing for the 8101Eb and the 8101Ec:
2053 *
2054 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2055 */
2056 static const struct rtl_mac_info {
2057 u32 mask;
2058 u32 val;
2059 int mac_version;
2060 } mac_info[] = {
2061 /* 8168G family. */
2062 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2063 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2064 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2065 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2066
2067 /* 8168F family. */
2068 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2069 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2070 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2071
2072 /* 8168E family. */
2073 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2074 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2075 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2076 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2077
2078 /* 8168D family. */
2079 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2080 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2081 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2082
2083 /* 8168DP family. */
2084 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2085 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2086 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2087
2088 /* 8168C family. */
2089 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2090 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2091 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2092 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2093 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2094 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2095 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2096 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2097 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2098
2099 /* 8168B family. */
2100 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2101 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2102 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2103 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2104
2105 /* 8101 family. */
2106 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2107 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2108 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2109 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2110 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2111 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2112 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2113 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2114 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2115 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2116 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2117 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2118 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2119 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2120 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2121 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2122 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2123 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2124 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2125 /* FIXME: where did these entries come from ? -- FR */
2126 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2127 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2128
2129 /* 8110 family. */
2130 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2131 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2132 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2133 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2134 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2135 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2136
2137 /* Catch-all */
2138 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2139 };
2140 const struct rtl_mac_info *p = mac_info;
2141 u32 reg;
2142
2143 reg = RTL_R32(TxConfig);
2144 while ((reg & p->mask) != p->val)
2145 p++;
2146 tp->mac_version = p->mac_version;
2147
2148 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2149 netif_notice(tp, probe, dev,
2150 "unknown MAC, using family default\n");
2151 tp->mac_version = default_version;
2152 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2153 tp->mac_version = tp->mii.supports_gmii ?
2154 RTL_GIGA_MAC_VER_42 :
2155 RTL_GIGA_MAC_VER_43;
2156 }
2157 }
2158
2159 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2160 {
2161 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2162 }
2163
2164 struct phy_reg {
2165 u16 reg;
2166 u16 val;
2167 };
2168
2169 static void rtl_writephy_batch(struct rtl8169_private *tp,
2170 const struct phy_reg *regs, int len)
2171 {
2172 while (len-- > 0) {
2173 rtl_writephy(tp, regs->reg, regs->val);
2174 regs++;
2175 }
2176 }
2177
2178 #define PHY_READ 0x00000000
2179 #define PHY_DATA_OR 0x10000000
2180 #define PHY_DATA_AND 0x20000000
2181 #define PHY_BJMPN 0x30000000
2182 #define PHY_MDIO_CHG 0x40000000
2183 #define PHY_CLEAR_READCOUNT 0x70000000
2184 #define PHY_WRITE 0x80000000
2185 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2186 #define PHY_COMP_EQ_SKIPN 0xa0000000
2187 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2188 #define PHY_WRITE_PREVIOUS 0xc0000000
2189 #define PHY_SKIPN 0xd0000000
2190 #define PHY_DELAY_MS 0xe0000000
2191
2192 struct fw_info {
2193 u32 magic;
2194 char version[RTL_VER_SIZE];
2195 __le32 fw_start;
2196 __le32 fw_len;
2197 u8 chksum;
2198 } __packed;
2199
2200 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2201
2202 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2203 {
2204 const struct firmware *fw = rtl_fw->fw;
2205 struct fw_info *fw_info = (struct fw_info *)fw->data;
2206 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2207 char *version = rtl_fw->version;
2208 bool rc = false;
2209
2210 if (fw->size < FW_OPCODE_SIZE)
2211 goto out;
2212
2213 if (!fw_info->magic) {
2214 size_t i, size, start;
2215 u8 checksum = 0;
2216
2217 if (fw->size < sizeof(*fw_info))
2218 goto out;
2219
2220 for (i = 0; i < fw->size; i++)
2221 checksum += fw->data[i];
2222 if (checksum != 0)
2223 goto out;
2224
2225 start = le32_to_cpu(fw_info->fw_start);
2226 if (start > fw->size)
2227 goto out;
2228
2229 size = le32_to_cpu(fw_info->fw_len);
2230 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2231 goto out;
2232
2233 memcpy(version, fw_info->version, RTL_VER_SIZE);
2234
2235 pa->code = (__le32 *)(fw->data + start);
2236 pa->size = size;
2237 } else {
2238 if (fw->size % FW_OPCODE_SIZE)
2239 goto out;
2240
2241 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2242
2243 pa->code = (__le32 *)fw->data;
2244 pa->size = fw->size / FW_OPCODE_SIZE;
2245 }
2246 version[RTL_VER_SIZE - 1] = 0;
2247
2248 rc = true;
2249 out:
2250 return rc;
2251 }
2252
2253 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2254 struct rtl_fw_phy_action *pa)
2255 {
2256 bool rc = false;
2257 size_t index;
2258
2259 for (index = 0; index < pa->size; index++) {
2260 u32 action = le32_to_cpu(pa->code[index]);
2261 u32 regno = (action & 0x0fff0000) >> 16;
2262
2263 switch(action & 0xf0000000) {
2264 case PHY_READ:
2265 case PHY_DATA_OR:
2266 case PHY_DATA_AND:
2267 case PHY_MDIO_CHG:
2268 case PHY_CLEAR_READCOUNT:
2269 case PHY_WRITE:
2270 case PHY_WRITE_PREVIOUS:
2271 case PHY_DELAY_MS:
2272 break;
2273
2274 case PHY_BJMPN:
2275 if (regno > index) {
2276 netif_err(tp, ifup, tp->dev,
2277 "Out of range of firmware\n");
2278 goto out;
2279 }
2280 break;
2281 case PHY_READCOUNT_EQ_SKIP:
2282 if (index + 2 >= pa->size) {
2283 netif_err(tp, ifup, tp->dev,
2284 "Out of range of firmware\n");
2285 goto out;
2286 }
2287 break;
2288 case PHY_COMP_EQ_SKIPN:
2289 case PHY_COMP_NEQ_SKIPN:
2290 case PHY_SKIPN:
2291 if (index + 1 + regno >= pa->size) {
2292 netif_err(tp, ifup, tp->dev,
2293 "Out of range of firmware\n");
2294 goto out;
2295 }
2296 break;
2297
2298 default:
2299 netif_err(tp, ifup, tp->dev,
2300 "Invalid action 0x%08x\n", action);
2301 goto out;
2302 }
2303 }
2304 rc = true;
2305 out:
2306 return rc;
2307 }
2308
2309 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2310 {
2311 struct net_device *dev = tp->dev;
2312 int rc = -EINVAL;
2313
2314 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2315 netif_err(tp, ifup, dev, "invalid firwmare\n");
2316 goto out;
2317 }
2318
2319 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2320 rc = 0;
2321 out:
2322 return rc;
2323 }
2324
2325 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2326 {
2327 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2328 struct mdio_ops org, *ops = &tp->mdio_ops;
2329 u32 predata, count;
2330 size_t index;
2331
2332 predata = count = 0;
2333 org.write = ops->write;
2334 org.read = ops->read;
2335
2336 for (index = 0; index < pa->size; ) {
2337 u32 action = le32_to_cpu(pa->code[index]);
2338 u32 data = action & 0x0000ffff;
2339 u32 regno = (action & 0x0fff0000) >> 16;
2340
2341 if (!action)
2342 break;
2343
2344 switch(action & 0xf0000000) {
2345 case PHY_READ:
2346 predata = rtl_readphy(tp, regno);
2347 count++;
2348 index++;
2349 break;
2350 case PHY_DATA_OR:
2351 predata |= data;
2352 index++;
2353 break;
2354 case PHY_DATA_AND:
2355 predata &= data;
2356 index++;
2357 break;
2358 case PHY_BJMPN:
2359 index -= regno;
2360 break;
2361 case PHY_MDIO_CHG:
2362 if (data == 0) {
2363 ops->write = org.write;
2364 ops->read = org.read;
2365 } else if (data == 1) {
2366 ops->write = mac_mcu_write;
2367 ops->read = mac_mcu_read;
2368 }
2369
2370 index++;
2371 break;
2372 case PHY_CLEAR_READCOUNT:
2373 count = 0;
2374 index++;
2375 break;
2376 case PHY_WRITE:
2377 rtl_writephy(tp, regno, data);
2378 index++;
2379 break;
2380 case PHY_READCOUNT_EQ_SKIP:
2381 index += (count == data) ? 2 : 1;
2382 break;
2383 case PHY_COMP_EQ_SKIPN:
2384 if (predata == data)
2385 index += regno;
2386 index++;
2387 break;
2388 case PHY_COMP_NEQ_SKIPN:
2389 if (predata != data)
2390 index += regno;
2391 index++;
2392 break;
2393 case PHY_WRITE_PREVIOUS:
2394 rtl_writephy(tp, regno, predata);
2395 index++;
2396 break;
2397 case PHY_SKIPN:
2398 index += regno + 1;
2399 break;
2400 case PHY_DELAY_MS:
2401 mdelay(data);
2402 index++;
2403 break;
2404
2405 default:
2406 BUG();
2407 }
2408 }
2409
2410 ops->write = org.write;
2411 ops->read = org.read;
2412 }
2413
2414 static void rtl_release_firmware(struct rtl8169_private *tp)
2415 {
2416 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2417 release_firmware(tp->rtl_fw->fw);
2418 kfree(tp->rtl_fw);
2419 }
2420 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2421 }
2422
2423 static void rtl_apply_firmware(struct rtl8169_private *tp)
2424 {
2425 struct rtl_fw *rtl_fw = tp->rtl_fw;
2426
2427 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2428 if (!IS_ERR_OR_NULL(rtl_fw))
2429 rtl_phy_write_fw(tp, rtl_fw);
2430 }
2431
2432 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2433 {
2434 if (rtl_readphy(tp, reg) != val)
2435 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2436 else
2437 rtl_apply_firmware(tp);
2438 }
2439
2440 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2441 {
2442 static const struct phy_reg phy_reg_init[] = {
2443 { 0x1f, 0x0001 },
2444 { 0x06, 0x006e },
2445 { 0x08, 0x0708 },
2446 { 0x15, 0x4000 },
2447 { 0x18, 0x65c7 },
2448
2449 { 0x1f, 0x0001 },
2450 { 0x03, 0x00a1 },
2451 { 0x02, 0x0008 },
2452 { 0x01, 0x0120 },
2453 { 0x00, 0x1000 },
2454 { 0x04, 0x0800 },
2455 { 0x04, 0x0000 },
2456
2457 { 0x03, 0xff41 },
2458 { 0x02, 0xdf60 },
2459 { 0x01, 0x0140 },
2460 { 0x00, 0x0077 },
2461 { 0x04, 0x7800 },
2462 { 0x04, 0x7000 },
2463
2464 { 0x03, 0x802f },
2465 { 0x02, 0x4f02 },
2466 { 0x01, 0x0409 },
2467 { 0x00, 0xf0f9 },
2468 { 0x04, 0x9800 },
2469 { 0x04, 0x9000 },
2470
2471 { 0x03, 0xdf01 },
2472 { 0x02, 0xdf20 },
2473 { 0x01, 0xff95 },
2474 { 0x00, 0xba00 },
2475 { 0x04, 0xa800 },
2476 { 0x04, 0xa000 },
2477
2478 { 0x03, 0xff41 },
2479 { 0x02, 0xdf20 },
2480 { 0x01, 0x0140 },
2481 { 0x00, 0x00bb },
2482 { 0x04, 0xb800 },
2483 { 0x04, 0xb000 },
2484
2485 { 0x03, 0xdf41 },
2486 { 0x02, 0xdc60 },
2487 { 0x01, 0x6340 },
2488 { 0x00, 0x007d },
2489 { 0x04, 0xd800 },
2490 { 0x04, 0xd000 },
2491
2492 { 0x03, 0xdf01 },
2493 { 0x02, 0xdf20 },
2494 { 0x01, 0x100a },
2495 { 0x00, 0xa0ff },
2496 { 0x04, 0xf800 },
2497 { 0x04, 0xf000 },
2498
2499 { 0x1f, 0x0000 },
2500 { 0x0b, 0x0000 },
2501 { 0x00, 0x9200 }
2502 };
2503
2504 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2505 }
2506
2507 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2508 {
2509 static const struct phy_reg phy_reg_init[] = {
2510 { 0x1f, 0x0002 },
2511 { 0x01, 0x90d0 },
2512 { 0x1f, 0x0000 }
2513 };
2514
2515 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2516 }
2517
2518 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2519 {
2520 struct pci_dev *pdev = tp->pci_dev;
2521
2522 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2523 (pdev->subsystem_device != 0xe000))
2524 return;
2525
2526 rtl_writephy(tp, 0x1f, 0x0001);
2527 rtl_writephy(tp, 0x10, 0xf01b);
2528 rtl_writephy(tp, 0x1f, 0x0000);
2529 }
2530
2531 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2532 {
2533 static const struct phy_reg phy_reg_init[] = {
2534 { 0x1f, 0x0001 },
2535 { 0x04, 0x0000 },
2536 { 0x03, 0x00a1 },
2537 { 0x02, 0x0008 },
2538 { 0x01, 0x0120 },
2539 { 0x00, 0x1000 },
2540 { 0x04, 0x0800 },
2541 { 0x04, 0x9000 },
2542 { 0x03, 0x802f },
2543 { 0x02, 0x4f02 },
2544 { 0x01, 0x0409 },
2545 { 0x00, 0xf099 },
2546 { 0x04, 0x9800 },
2547 { 0x04, 0xa000 },
2548 { 0x03, 0xdf01 },
2549 { 0x02, 0xdf20 },
2550 { 0x01, 0xff95 },
2551 { 0x00, 0xba00 },
2552 { 0x04, 0xa800 },
2553 { 0x04, 0xf000 },
2554 { 0x03, 0xdf01 },
2555 { 0x02, 0xdf20 },
2556 { 0x01, 0x101a },
2557 { 0x00, 0xa0ff },
2558 { 0x04, 0xf800 },
2559 { 0x04, 0x0000 },
2560 { 0x1f, 0x0000 },
2561
2562 { 0x1f, 0x0001 },
2563 { 0x10, 0xf41b },
2564 { 0x14, 0xfb54 },
2565 { 0x18, 0xf5c7 },
2566 { 0x1f, 0x0000 },
2567
2568 { 0x1f, 0x0001 },
2569 { 0x17, 0x0cc0 },
2570 { 0x1f, 0x0000 }
2571 };
2572
2573 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2574
2575 rtl8169scd_hw_phy_config_quirk(tp);
2576 }
2577
2578 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2579 {
2580 static const struct phy_reg phy_reg_init[] = {
2581 { 0x1f, 0x0001 },
2582 { 0x04, 0x0000 },
2583 { 0x03, 0x00a1 },
2584 { 0x02, 0x0008 },
2585 { 0x01, 0x0120 },
2586 { 0x00, 0x1000 },
2587 { 0x04, 0x0800 },
2588 { 0x04, 0x9000 },
2589 { 0x03, 0x802f },
2590 { 0x02, 0x4f02 },
2591 { 0x01, 0x0409 },
2592 { 0x00, 0xf099 },
2593 { 0x04, 0x9800 },
2594 { 0x04, 0xa000 },
2595 { 0x03, 0xdf01 },
2596 { 0x02, 0xdf20 },
2597 { 0x01, 0xff95 },
2598 { 0x00, 0xba00 },
2599 { 0x04, 0xa800 },
2600 { 0x04, 0xf000 },
2601 { 0x03, 0xdf01 },
2602 { 0x02, 0xdf20 },
2603 { 0x01, 0x101a },
2604 { 0x00, 0xa0ff },
2605 { 0x04, 0xf800 },
2606 { 0x04, 0x0000 },
2607 { 0x1f, 0x0000 },
2608
2609 { 0x1f, 0x0001 },
2610 { 0x0b, 0x8480 },
2611 { 0x1f, 0x0000 },
2612
2613 { 0x1f, 0x0001 },
2614 { 0x18, 0x67c7 },
2615 { 0x04, 0x2000 },
2616 { 0x03, 0x002f },
2617 { 0x02, 0x4360 },
2618 { 0x01, 0x0109 },
2619 { 0x00, 0x3022 },
2620 { 0x04, 0x2800 },
2621 { 0x1f, 0x0000 },
2622
2623 { 0x1f, 0x0001 },
2624 { 0x17, 0x0cc0 },
2625 { 0x1f, 0x0000 }
2626 };
2627
2628 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2629 }
2630
2631 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2632 {
2633 static const struct phy_reg phy_reg_init[] = {
2634 { 0x10, 0xf41b },
2635 { 0x1f, 0x0000 }
2636 };
2637
2638 rtl_writephy(tp, 0x1f, 0x0001);
2639 rtl_patchphy(tp, 0x16, 1 << 0);
2640
2641 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2642 }
2643
2644 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2645 {
2646 static const struct phy_reg phy_reg_init[] = {
2647 { 0x1f, 0x0001 },
2648 { 0x10, 0xf41b },
2649 { 0x1f, 0x0000 }
2650 };
2651
2652 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2653 }
2654
2655 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2656 {
2657 static const struct phy_reg phy_reg_init[] = {
2658 { 0x1f, 0x0000 },
2659 { 0x1d, 0x0f00 },
2660 { 0x1f, 0x0002 },
2661 { 0x0c, 0x1ec8 },
2662 { 0x1f, 0x0000 }
2663 };
2664
2665 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2666 }
2667
2668 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2669 {
2670 static const struct phy_reg phy_reg_init[] = {
2671 { 0x1f, 0x0001 },
2672 { 0x1d, 0x3d98 },
2673 { 0x1f, 0x0000 }
2674 };
2675
2676 rtl_writephy(tp, 0x1f, 0x0000);
2677 rtl_patchphy(tp, 0x14, 1 << 5);
2678 rtl_patchphy(tp, 0x0d, 1 << 5);
2679
2680 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2681 }
2682
2683 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2684 {
2685 static const struct phy_reg phy_reg_init[] = {
2686 { 0x1f, 0x0001 },
2687 { 0x12, 0x2300 },
2688 { 0x1f, 0x0002 },
2689 { 0x00, 0x88d4 },
2690 { 0x01, 0x82b1 },
2691 { 0x03, 0x7002 },
2692 { 0x08, 0x9e30 },
2693 { 0x09, 0x01f0 },
2694 { 0x0a, 0x5500 },
2695 { 0x0c, 0x00c8 },
2696 { 0x1f, 0x0003 },
2697 { 0x12, 0xc096 },
2698 { 0x16, 0x000a },
2699 { 0x1f, 0x0000 },
2700 { 0x1f, 0x0000 },
2701 { 0x09, 0x2000 },
2702 { 0x09, 0x0000 }
2703 };
2704
2705 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2706
2707 rtl_patchphy(tp, 0x14, 1 << 5);
2708 rtl_patchphy(tp, 0x0d, 1 << 5);
2709 rtl_writephy(tp, 0x1f, 0x0000);
2710 }
2711
2712 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2713 {
2714 static const struct phy_reg phy_reg_init[] = {
2715 { 0x1f, 0x0001 },
2716 { 0x12, 0x2300 },
2717 { 0x03, 0x802f },
2718 { 0x02, 0x4f02 },
2719 { 0x01, 0x0409 },
2720 { 0x00, 0xf099 },
2721 { 0x04, 0x9800 },
2722 { 0x04, 0x9000 },
2723 { 0x1d, 0x3d98 },
2724 { 0x1f, 0x0002 },
2725 { 0x0c, 0x7eb8 },
2726 { 0x06, 0x0761 },
2727 { 0x1f, 0x0003 },
2728 { 0x16, 0x0f0a },
2729 { 0x1f, 0x0000 }
2730 };
2731
2732 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2733
2734 rtl_patchphy(tp, 0x16, 1 << 0);
2735 rtl_patchphy(tp, 0x14, 1 << 5);
2736 rtl_patchphy(tp, 0x0d, 1 << 5);
2737 rtl_writephy(tp, 0x1f, 0x0000);
2738 }
2739
2740 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2741 {
2742 static const struct phy_reg phy_reg_init[] = {
2743 { 0x1f, 0x0001 },
2744 { 0x12, 0x2300 },
2745 { 0x1d, 0x3d98 },
2746 { 0x1f, 0x0002 },
2747 { 0x0c, 0x7eb8 },
2748 { 0x06, 0x5461 },
2749 { 0x1f, 0x0003 },
2750 { 0x16, 0x0f0a },
2751 { 0x1f, 0x0000 }
2752 };
2753
2754 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2755
2756 rtl_patchphy(tp, 0x16, 1 << 0);
2757 rtl_patchphy(tp, 0x14, 1 << 5);
2758 rtl_patchphy(tp, 0x0d, 1 << 5);
2759 rtl_writephy(tp, 0x1f, 0x0000);
2760 }
2761
2762 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2763 {
2764 rtl8168c_3_hw_phy_config(tp);
2765 }
2766
2767 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2768 {
2769 static const struct phy_reg phy_reg_init_0[] = {
2770 /* Channel Estimation */
2771 { 0x1f, 0x0001 },
2772 { 0x06, 0x4064 },
2773 { 0x07, 0x2863 },
2774 { 0x08, 0x059c },
2775 { 0x09, 0x26b4 },
2776 { 0x0a, 0x6a19 },
2777 { 0x0b, 0xdcc8 },
2778 { 0x10, 0xf06d },
2779 { 0x14, 0x7f68 },
2780 { 0x18, 0x7fd9 },
2781 { 0x1c, 0xf0ff },
2782 { 0x1d, 0x3d9c },
2783 { 0x1f, 0x0003 },
2784 { 0x12, 0xf49f },
2785 { 0x13, 0x070b },
2786 { 0x1a, 0x05ad },
2787 { 0x14, 0x94c0 },
2788
2789 /*
2790 * Tx Error Issue
2791 * Enhance line driver power
2792 */
2793 { 0x1f, 0x0002 },
2794 { 0x06, 0x5561 },
2795 { 0x1f, 0x0005 },
2796 { 0x05, 0x8332 },
2797 { 0x06, 0x5561 },
2798
2799 /*
2800 * Can not link to 1Gbps with bad cable
2801 * Decrease SNR threshold form 21.07dB to 19.04dB
2802 */
2803 { 0x1f, 0x0001 },
2804 { 0x17, 0x0cc0 },
2805
2806 { 0x1f, 0x0000 },
2807 { 0x0d, 0xf880 }
2808 };
2809
2810 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2811
2812 /*
2813 * Rx Error Issue
2814 * Fine Tune Switching regulator parameter
2815 */
2816 rtl_writephy(tp, 0x1f, 0x0002);
2817 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2818 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2819
2820 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2821 static const struct phy_reg phy_reg_init[] = {
2822 { 0x1f, 0x0002 },
2823 { 0x05, 0x669a },
2824 { 0x1f, 0x0005 },
2825 { 0x05, 0x8330 },
2826 { 0x06, 0x669a },
2827 { 0x1f, 0x0002 }
2828 };
2829 int val;
2830
2831 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2832
2833 val = rtl_readphy(tp, 0x0d);
2834
2835 if ((val & 0x00ff) != 0x006c) {
2836 static const u32 set[] = {
2837 0x0065, 0x0066, 0x0067, 0x0068,
2838 0x0069, 0x006a, 0x006b, 0x006c
2839 };
2840 int i;
2841
2842 rtl_writephy(tp, 0x1f, 0x0002);
2843
2844 val &= 0xff00;
2845 for (i = 0; i < ARRAY_SIZE(set); i++)
2846 rtl_writephy(tp, 0x0d, val | set[i]);
2847 }
2848 } else {
2849 static const struct phy_reg phy_reg_init[] = {
2850 { 0x1f, 0x0002 },
2851 { 0x05, 0x6662 },
2852 { 0x1f, 0x0005 },
2853 { 0x05, 0x8330 },
2854 { 0x06, 0x6662 }
2855 };
2856
2857 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2858 }
2859
2860 /* RSET couple improve */
2861 rtl_writephy(tp, 0x1f, 0x0002);
2862 rtl_patchphy(tp, 0x0d, 0x0300);
2863 rtl_patchphy(tp, 0x0f, 0x0010);
2864
2865 /* Fine tune PLL performance */
2866 rtl_writephy(tp, 0x1f, 0x0002);
2867 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2868 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2869
2870 rtl_writephy(tp, 0x1f, 0x0005);
2871 rtl_writephy(tp, 0x05, 0x001b);
2872
2873 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2874
2875 rtl_writephy(tp, 0x1f, 0x0000);
2876 }
2877
2878 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2879 {
2880 static const struct phy_reg phy_reg_init_0[] = {
2881 /* Channel Estimation */
2882 { 0x1f, 0x0001 },
2883 { 0x06, 0x4064 },
2884 { 0x07, 0x2863 },
2885 { 0x08, 0x059c },
2886 { 0x09, 0x26b4 },
2887 { 0x0a, 0x6a19 },
2888 { 0x0b, 0xdcc8 },
2889 { 0x10, 0xf06d },
2890 { 0x14, 0x7f68 },
2891 { 0x18, 0x7fd9 },
2892 { 0x1c, 0xf0ff },
2893 { 0x1d, 0x3d9c },
2894 { 0x1f, 0x0003 },
2895 { 0x12, 0xf49f },
2896 { 0x13, 0x070b },
2897 { 0x1a, 0x05ad },
2898 { 0x14, 0x94c0 },
2899
2900 /*
2901 * Tx Error Issue
2902 * Enhance line driver power
2903 */
2904 { 0x1f, 0x0002 },
2905 { 0x06, 0x5561 },
2906 { 0x1f, 0x0005 },
2907 { 0x05, 0x8332 },
2908 { 0x06, 0x5561 },
2909
2910 /*
2911 * Can not link to 1Gbps with bad cable
2912 * Decrease SNR threshold form 21.07dB to 19.04dB
2913 */
2914 { 0x1f, 0x0001 },
2915 { 0x17, 0x0cc0 },
2916
2917 { 0x1f, 0x0000 },
2918 { 0x0d, 0xf880 }
2919 };
2920
2921 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2922
2923 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2924 static const struct phy_reg phy_reg_init[] = {
2925 { 0x1f, 0x0002 },
2926 { 0x05, 0x669a },
2927 { 0x1f, 0x0005 },
2928 { 0x05, 0x8330 },
2929 { 0x06, 0x669a },
2930
2931 { 0x1f, 0x0002 }
2932 };
2933 int val;
2934
2935 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2936
2937 val = rtl_readphy(tp, 0x0d);
2938 if ((val & 0x00ff) != 0x006c) {
2939 static const u32 set[] = {
2940 0x0065, 0x0066, 0x0067, 0x0068,
2941 0x0069, 0x006a, 0x006b, 0x006c
2942 };
2943 int i;
2944
2945 rtl_writephy(tp, 0x1f, 0x0002);
2946
2947 val &= 0xff00;
2948 for (i = 0; i < ARRAY_SIZE(set); i++)
2949 rtl_writephy(tp, 0x0d, val | set[i]);
2950 }
2951 } else {
2952 static const struct phy_reg phy_reg_init[] = {
2953 { 0x1f, 0x0002 },
2954 { 0x05, 0x2642 },
2955 { 0x1f, 0x0005 },
2956 { 0x05, 0x8330 },
2957 { 0x06, 0x2642 }
2958 };
2959
2960 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2961 }
2962
2963 /* Fine tune PLL performance */
2964 rtl_writephy(tp, 0x1f, 0x0002);
2965 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2966 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2967
2968 /* Switching regulator Slew rate */
2969 rtl_writephy(tp, 0x1f, 0x0002);
2970 rtl_patchphy(tp, 0x0f, 0x0017);
2971
2972 rtl_writephy(tp, 0x1f, 0x0005);
2973 rtl_writephy(tp, 0x05, 0x001b);
2974
2975 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2976
2977 rtl_writephy(tp, 0x1f, 0x0000);
2978 }
2979
2980 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2981 {
2982 static const struct phy_reg phy_reg_init[] = {
2983 { 0x1f, 0x0002 },
2984 { 0x10, 0x0008 },
2985 { 0x0d, 0x006c },
2986
2987 { 0x1f, 0x0000 },
2988 { 0x0d, 0xf880 },
2989
2990 { 0x1f, 0x0001 },
2991 { 0x17, 0x0cc0 },
2992
2993 { 0x1f, 0x0001 },
2994 { 0x0b, 0xa4d8 },
2995 { 0x09, 0x281c },
2996 { 0x07, 0x2883 },
2997 { 0x0a, 0x6b35 },
2998 { 0x1d, 0x3da4 },
2999 { 0x1c, 0xeffd },
3000 { 0x14, 0x7f52 },
3001 { 0x18, 0x7fc6 },
3002 { 0x08, 0x0601 },
3003 { 0x06, 0x4063 },
3004 { 0x10, 0xf074 },
3005 { 0x1f, 0x0003 },
3006 { 0x13, 0x0789 },
3007 { 0x12, 0xf4bd },
3008 { 0x1a, 0x04fd },
3009 { 0x14, 0x84b0 },
3010 { 0x1f, 0x0000 },
3011 { 0x00, 0x9200 },
3012
3013 { 0x1f, 0x0005 },
3014 { 0x01, 0x0340 },
3015 { 0x1f, 0x0001 },
3016 { 0x04, 0x4000 },
3017 { 0x03, 0x1d21 },
3018 { 0x02, 0x0c32 },
3019 { 0x01, 0x0200 },
3020 { 0x00, 0x5554 },
3021 { 0x04, 0x4800 },
3022 { 0x04, 0x4000 },
3023 { 0x04, 0xf000 },
3024 { 0x03, 0xdf01 },
3025 { 0x02, 0xdf20 },
3026 { 0x01, 0x101a },
3027 { 0x00, 0xa0ff },
3028 { 0x04, 0xf800 },
3029 { 0x04, 0xf000 },
3030 { 0x1f, 0x0000 },
3031
3032 { 0x1f, 0x0007 },
3033 { 0x1e, 0x0023 },
3034 { 0x16, 0x0000 },
3035 { 0x1f, 0x0000 }
3036 };
3037
3038 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3039 }
3040
3041 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3042 {
3043 static const struct phy_reg phy_reg_init[] = {
3044 { 0x1f, 0x0001 },
3045 { 0x17, 0x0cc0 },
3046
3047 { 0x1f, 0x0007 },
3048 { 0x1e, 0x002d },
3049 { 0x18, 0x0040 },
3050 { 0x1f, 0x0000 }
3051 };
3052
3053 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3054 rtl_patchphy(tp, 0x0d, 1 << 5);
3055 }
3056
3057 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3058 {
3059 static const struct phy_reg phy_reg_init[] = {
3060 /* Enable Delay cap */
3061 { 0x1f, 0x0005 },
3062 { 0x05, 0x8b80 },
3063 { 0x06, 0xc896 },
3064 { 0x1f, 0x0000 },
3065
3066 /* Channel estimation fine tune */
3067 { 0x1f, 0x0001 },
3068 { 0x0b, 0x6c20 },
3069 { 0x07, 0x2872 },
3070 { 0x1c, 0xefff },
3071 { 0x1f, 0x0003 },
3072 { 0x14, 0x6420 },
3073 { 0x1f, 0x0000 },
3074
3075 /* Update PFM & 10M TX idle timer */
3076 { 0x1f, 0x0007 },
3077 { 0x1e, 0x002f },
3078 { 0x15, 0x1919 },
3079 { 0x1f, 0x0000 },
3080
3081 { 0x1f, 0x0007 },
3082 { 0x1e, 0x00ac },
3083 { 0x18, 0x0006 },
3084 { 0x1f, 0x0000 }
3085 };
3086
3087 rtl_apply_firmware(tp);
3088
3089 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3090
3091 /* DCO enable for 10M IDLE Power */
3092 rtl_writephy(tp, 0x1f, 0x0007);
3093 rtl_writephy(tp, 0x1e, 0x0023);
3094 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3095 rtl_writephy(tp, 0x1f, 0x0000);
3096
3097 /* For impedance matching */
3098 rtl_writephy(tp, 0x1f, 0x0002);
3099 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3100 rtl_writephy(tp, 0x1f, 0x0000);
3101
3102 /* PHY auto speed down */
3103 rtl_writephy(tp, 0x1f, 0x0007);
3104 rtl_writephy(tp, 0x1e, 0x002d);
3105 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3106 rtl_writephy(tp, 0x1f, 0x0000);
3107 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3108
3109 rtl_writephy(tp, 0x1f, 0x0005);
3110 rtl_writephy(tp, 0x05, 0x8b86);
3111 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3112 rtl_writephy(tp, 0x1f, 0x0000);
3113
3114 rtl_writephy(tp, 0x1f, 0x0005);
3115 rtl_writephy(tp, 0x05, 0x8b85);
3116 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3117 rtl_writephy(tp, 0x1f, 0x0007);
3118 rtl_writephy(tp, 0x1e, 0x0020);
3119 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3120 rtl_writephy(tp, 0x1f, 0x0006);
3121 rtl_writephy(tp, 0x00, 0x5a00);
3122 rtl_writephy(tp, 0x1f, 0x0000);
3123 rtl_writephy(tp, 0x0d, 0x0007);
3124 rtl_writephy(tp, 0x0e, 0x003c);
3125 rtl_writephy(tp, 0x0d, 0x4007);
3126 rtl_writephy(tp, 0x0e, 0x0000);
3127 rtl_writephy(tp, 0x0d, 0x0000);
3128 }
3129
3130 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3131 {
3132 const u16 w[] = {
3133 addr[0] | (addr[1] << 8),
3134 addr[2] | (addr[3] << 8),
3135 addr[4] | (addr[5] << 8)
3136 };
3137 const struct exgmac_reg e[] = {
3138 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3139 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3140 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3141 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3142 };
3143
3144 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3145 }
3146
3147 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3148 {
3149 static const struct phy_reg phy_reg_init[] = {
3150 /* Enable Delay cap */
3151 { 0x1f, 0x0004 },
3152 { 0x1f, 0x0007 },
3153 { 0x1e, 0x00ac },
3154 { 0x18, 0x0006 },
3155 { 0x1f, 0x0002 },
3156 { 0x1f, 0x0000 },
3157 { 0x1f, 0x0000 },
3158
3159 /* Channel estimation fine tune */
3160 { 0x1f, 0x0003 },
3161 { 0x09, 0xa20f },
3162 { 0x1f, 0x0000 },
3163 { 0x1f, 0x0000 },
3164
3165 /* Green Setting */
3166 { 0x1f, 0x0005 },
3167 { 0x05, 0x8b5b },
3168 { 0x06, 0x9222 },
3169 { 0x05, 0x8b6d },
3170 { 0x06, 0x8000 },
3171 { 0x05, 0x8b76 },
3172 { 0x06, 0x8000 },
3173 { 0x1f, 0x0000 }
3174 };
3175
3176 rtl_apply_firmware(tp);
3177
3178 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3179
3180 /* For 4-corner performance improve */
3181 rtl_writephy(tp, 0x1f, 0x0005);
3182 rtl_writephy(tp, 0x05, 0x8b80);
3183 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3184 rtl_writephy(tp, 0x1f, 0x0000);
3185
3186 /* PHY auto speed down */
3187 rtl_writephy(tp, 0x1f, 0x0004);
3188 rtl_writephy(tp, 0x1f, 0x0007);
3189 rtl_writephy(tp, 0x1e, 0x002d);
3190 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3191 rtl_writephy(tp, 0x1f, 0x0002);
3192 rtl_writephy(tp, 0x1f, 0x0000);
3193 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3194
3195 /* improve 10M EEE waveform */
3196 rtl_writephy(tp, 0x1f, 0x0005);
3197 rtl_writephy(tp, 0x05, 0x8b86);
3198 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3199 rtl_writephy(tp, 0x1f, 0x0000);
3200
3201 /* Improve 2-pair detection performance */
3202 rtl_writephy(tp, 0x1f, 0x0005);
3203 rtl_writephy(tp, 0x05, 0x8b85);
3204 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3205 rtl_writephy(tp, 0x1f, 0x0000);
3206
3207 /* EEE setting */
3208 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3209 rtl_writephy(tp, 0x1f, 0x0005);
3210 rtl_writephy(tp, 0x05, 0x8b85);
3211 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3212 rtl_writephy(tp, 0x1f, 0x0004);
3213 rtl_writephy(tp, 0x1f, 0x0007);
3214 rtl_writephy(tp, 0x1e, 0x0020);
3215 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3216 rtl_writephy(tp, 0x1f, 0x0002);
3217 rtl_writephy(tp, 0x1f, 0x0000);
3218 rtl_writephy(tp, 0x0d, 0x0007);
3219 rtl_writephy(tp, 0x0e, 0x003c);
3220 rtl_writephy(tp, 0x0d, 0x4007);
3221 rtl_writephy(tp, 0x0e, 0x0000);
3222 rtl_writephy(tp, 0x0d, 0x0000);
3223
3224 /* Green feature */
3225 rtl_writephy(tp, 0x1f, 0x0003);
3226 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3227 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3228 rtl_writephy(tp, 0x1f, 0x0000);
3229
3230 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3231 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3232 }
3233
3234 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3235 {
3236 /* For 4-corner performance improve */
3237 rtl_writephy(tp, 0x1f, 0x0005);
3238 rtl_writephy(tp, 0x05, 0x8b80);
3239 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3240 rtl_writephy(tp, 0x1f, 0x0000);
3241
3242 /* PHY auto speed down */
3243 rtl_writephy(tp, 0x1f, 0x0007);
3244 rtl_writephy(tp, 0x1e, 0x002d);
3245 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3246 rtl_writephy(tp, 0x1f, 0x0000);
3247 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3248
3249 /* Improve 10M EEE waveform */
3250 rtl_writephy(tp, 0x1f, 0x0005);
3251 rtl_writephy(tp, 0x05, 0x8b86);
3252 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3253 rtl_writephy(tp, 0x1f, 0x0000);
3254 }
3255
3256 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3257 {
3258 static const struct phy_reg phy_reg_init[] = {
3259 /* Channel estimation fine tune */
3260 { 0x1f, 0x0003 },
3261 { 0x09, 0xa20f },
3262 { 0x1f, 0x0000 },
3263
3264 /* Modify green table for giga & fnet */
3265 { 0x1f, 0x0005 },
3266 { 0x05, 0x8b55 },
3267 { 0x06, 0x0000 },
3268 { 0x05, 0x8b5e },
3269 { 0x06, 0x0000 },
3270 { 0x05, 0x8b67 },
3271 { 0x06, 0x0000 },
3272 { 0x05, 0x8b70 },
3273 { 0x06, 0x0000 },
3274 { 0x1f, 0x0000 },
3275 { 0x1f, 0x0007 },
3276 { 0x1e, 0x0078 },
3277 { 0x17, 0x0000 },
3278 { 0x19, 0x00fb },
3279 { 0x1f, 0x0000 },
3280
3281 /* Modify green table for 10M */
3282 { 0x1f, 0x0005 },
3283 { 0x05, 0x8b79 },
3284 { 0x06, 0xaa00 },
3285 { 0x1f, 0x0000 },
3286
3287 /* Disable hiimpedance detection (RTCT) */
3288 { 0x1f, 0x0003 },
3289 { 0x01, 0x328a },
3290 { 0x1f, 0x0000 }
3291 };
3292
3293 rtl_apply_firmware(tp);
3294
3295 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3296
3297 rtl8168f_hw_phy_config(tp);
3298
3299 /* Improve 2-pair detection performance */
3300 rtl_writephy(tp, 0x1f, 0x0005);
3301 rtl_writephy(tp, 0x05, 0x8b85);
3302 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3303 rtl_writephy(tp, 0x1f, 0x0000);
3304 }
3305
3306 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3307 {
3308 rtl_apply_firmware(tp);
3309
3310 rtl8168f_hw_phy_config(tp);
3311 }
3312
3313 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3314 {
3315 static const struct phy_reg phy_reg_init[] = {
3316 /* Channel estimation fine tune */
3317 { 0x1f, 0x0003 },
3318 { 0x09, 0xa20f },
3319 { 0x1f, 0x0000 },
3320
3321 /* Modify green table for giga & fnet */
3322 { 0x1f, 0x0005 },
3323 { 0x05, 0x8b55 },
3324 { 0x06, 0x0000 },
3325 { 0x05, 0x8b5e },
3326 { 0x06, 0x0000 },
3327 { 0x05, 0x8b67 },
3328 { 0x06, 0x0000 },
3329 { 0x05, 0x8b70 },
3330 { 0x06, 0x0000 },
3331 { 0x1f, 0x0000 },
3332 { 0x1f, 0x0007 },
3333 { 0x1e, 0x0078 },
3334 { 0x17, 0x0000 },
3335 { 0x19, 0x00aa },
3336 { 0x1f, 0x0000 },
3337
3338 /* Modify green table for 10M */
3339 { 0x1f, 0x0005 },
3340 { 0x05, 0x8b79 },
3341 { 0x06, 0xaa00 },
3342 { 0x1f, 0x0000 },
3343
3344 /* Disable hiimpedance detection (RTCT) */
3345 { 0x1f, 0x0003 },
3346 { 0x01, 0x328a },
3347 { 0x1f, 0x0000 }
3348 };
3349
3350
3351 rtl_apply_firmware(tp);
3352
3353 rtl8168f_hw_phy_config(tp);
3354
3355 /* Improve 2-pair detection performance */
3356 rtl_writephy(tp, 0x1f, 0x0005);
3357 rtl_writephy(tp, 0x05, 0x8b85);
3358 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3359 rtl_writephy(tp, 0x1f, 0x0000);
3360
3361 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3362
3363 /* Modify green table for giga */
3364 rtl_writephy(tp, 0x1f, 0x0005);
3365 rtl_writephy(tp, 0x05, 0x8b54);
3366 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3367 rtl_writephy(tp, 0x05, 0x8b5d);
3368 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3369 rtl_writephy(tp, 0x05, 0x8a7c);
3370 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3371 rtl_writephy(tp, 0x05, 0x8a7f);
3372 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3373 rtl_writephy(tp, 0x05, 0x8a82);
3374 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3375 rtl_writephy(tp, 0x05, 0x8a85);
3376 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3377 rtl_writephy(tp, 0x05, 0x8a88);
3378 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3379 rtl_writephy(tp, 0x1f, 0x0000);
3380
3381 /* uc same-seed solution */
3382 rtl_writephy(tp, 0x1f, 0x0005);
3383 rtl_writephy(tp, 0x05, 0x8b85);
3384 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3385 rtl_writephy(tp, 0x1f, 0x0000);
3386
3387 /* eee setting */
3388 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3389 rtl_writephy(tp, 0x1f, 0x0005);
3390 rtl_writephy(tp, 0x05, 0x8b85);
3391 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3392 rtl_writephy(tp, 0x1f, 0x0004);
3393 rtl_writephy(tp, 0x1f, 0x0007);
3394 rtl_writephy(tp, 0x1e, 0x0020);
3395 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3396 rtl_writephy(tp, 0x1f, 0x0000);
3397 rtl_writephy(tp, 0x0d, 0x0007);
3398 rtl_writephy(tp, 0x0e, 0x003c);
3399 rtl_writephy(tp, 0x0d, 0x4007);
3400 rtl_writephy(tp, 0x0e, 0x0000);
3401 rtl_writephy(tp, 0x0d, 0x0000);
3402
3403 /* Green feature */
3404 rtl_writephy(tp, 0x1f, 0x0003);
3405 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3406 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3407 rtl_writephy(tp, 0x1f, 0x0000);
3408 }
3409
3410 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3411 {
3412 rtl_apply_firmware(tp);
3413
3414 rtl_writephy(tp, 0x1f, 0x0a46);
3415 if (rtl_readphy(tp, 0x10) & 0x0100) {
3416 rtl_writephy(tp, 0x1f, 0x0bcc);
3417 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3418 } else {
3419 rtl_writephy(tp, 0x1f, 0x0bcc);
3420 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3421 }
3422
3423 rtl_writephy(tp, 0x1f, 0x0a46);
3424 if (rtl_readphy(tp, 0x13) & 0x0100) {
3425 rtl_writephy(tp, 0x1f, 0x0c41);
3426 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3427 } else {
3428 rtl_writephy(tp, 0x1f, 0x0c41);
3429 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3430 }
3431
3432 /* Enable PHY auto speed down */
3433 rtl_writephy(tp, 0x1f, 0x0a44);
3434 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3435
3436 rtl_writephy(tp, 0x1f, 0x0bcc);
3437 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3438 rtl_writephy(tp, 0x1f, 0x0a44);
3439 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3440 rtl_writephy(tp, 0x1f, 0x0a43);
3441 rtl_writephy(tp, 0x13, 0x8084);
3442 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3443 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3444
3445 /* EEE auto-fallback function */
3446 rtl_writephy(tp, 0x1f, 0x0a4b);
3447 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3448
3449 /* Enable UC LPF tune function */
3450 rtl_writephy(tp, 0x1f, 0x0a43);
3451 rtl_writephy(tp, 0x13, 0x8012);
3452 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3453
3454 rtl_writephy(tp, 0x1f, 0x0c42);
3455 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3456
3457 /* Improve SWR Efficiency */
3458 rtl_writephy(tp, 0x1f, 0x0bcd);
3459 rtl_writephy(tp, 0x14, 0x5065);
3460 rtl_writephy(tp, 0x14, 0xd065);
3461 rtl_writephy(tp, 0x1f, 0x0bc8);
3462 rtl_writephy(tp, 0x11, 0x5655);
3463 rtl_writephy(tp, 0x1f, 0x0bcd);
3464 rtl_writephy(tp, 0x14, 0x1065);
3465 rtl_writephy(tp, 0x14, 0x9065);
3466 rtl_writephy(tp, 0x14, 0x1065);
3467
3468 rtl_writephy(tp, 0x1f, 0x0000);
3469 }
3470
3471 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3472 {
3473 rtl_apply_firmware(tp);
3474 }
3475
3476 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3477 {
3478 static const struct phy_reg phy_reg_init[] = {
3479 { 0x1f, 0x0003 },
3480 { 0x08, 0x441d },
3481 { 0x01, 0x9100 },
3482 { 0x1f, 0x0000 }
3483 };
3484
3485 rtl_writephy(tp, 0x1f, 0x0000);
3486 rtl_patchphy(tp, 0x11, 1 << 12);
3487 rtl_patchphy(tp, 0x19, 1 << 13);
3488 rtl_patchphy(tp, 0x10, 1 << 15);
3489
3490 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3491 }
3492
3493 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3494 {
3495 static const struct phy_reg phy_reg_init[] = {
3496 { 0x1f, 0x0005 },
3497 { 0x1a, 0x0000 },
3498 { 0x1f, 0x0000 },
3499
3500 { 0x1f, 0x0004 },
3501 { 0x1c, 0x0000 },
3502 { 0x1f, 0x0000 },
3503
3504 { 0x1f, 0x0001 },
3505 { 0x15, 0x7701 },
3506 { 0x1f, 0x0000 }
3507 };
3508
3509 /* Disable ALDPS before ram code */
3510 rtl_writephy(tp, 0x1f, 0x0000);
3511 rtl_writephy(tp, 0x18, 0x0310);
3512 msleep(100);
3513
3514 rtl_apply_firmware(tp);
3515
3516 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3517 }
3518
3519 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3520 {
3521 /* Disable ALDPS before setting firmware */
3522 rtl_writephy(tp, 0x1f, 0x0000);
3523 rtl_writephy(tp, 0x18, 0x0310);
3524 msleep(20);
3525
3526 rtl_apply_firmware(tp);
3527
3528 /* EEE setting */
3529 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3530 rtl_writephy(tp, 0x1f, 0x0004);
3531 rtl_writephy(tp, 0x10, 0x401f);
3532 rtl_writephy(tp, 0x19, 0x7030);
3533 rtl_writephy(tp, 0x1f, 0x0000);
3534 }
3535
3536 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3537 {
3538 static const struct phy_reg phy_reg_init[] = {
3539 { 0x1f, 0x0004 },
3540 { 0x10, 0xc07f },
3541 { 0x19, 0x7030 },
3542 { 0x1f, 0x0000 }
3543 };
3544
3545 /* Disable ALDPS before ram code */
3546 rtl_writephy(tp, 0x1f, 0x0000);
3547 rtl_writephy(tp, 0x18, 0x0310);
3548 msleep(100);
3549
3550 rtl_apply_firmware(tp);
3551
3552 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3553 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3554
3555 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3556 }
3557
3558 static void rtl_hw_phy_config(struct net_device *dev)
3559 {
3560 struct rtl8169_private *tp = netdev_priv(dev);
3561
3562 rtl8169_print_mac_version(tp);
3563
3564 switch (tp->mac_version) {
3565 case RTL_GIGA_MAC_VER_01:
3566 break;
3567 case RTL_GIGA_MAC_VER_02:
3568 case RTL_GIGA_MAC_VER_03:
3569 rtl8169s_hw_phy_config(tp);
3570 break;
3571 case RTL_GIGA_MAC_VER_04:
3572 rtl8169sb_hw_phy_config(tp);
3573 break;
3574 case RTL_GIGA_MAC_VER_05:
3575 rtl8169scd_hw_phy_config(tp);
3576 break;
3577 case RTL_GIGA_MAC_VER_06:
3578 rtl8169sce_hw_phy_config(tp);
3579 break;
3580 case RTL_GIGA_MAC_VER_07:
3581 case RTL_GIGA_MAC_VER_08:
3582 case RTL_GIGA_MAC_VER_09:
3583 rtl8102e_hw_phy_config(tp);
3584 break;
3585 case RTL_GIGA_MAC_VER_11:
3586 rtl8168bb_hw_phy_config(tp);
3587 break;
3588 case RTL_GIGA_MAC_VER_12:
3589 rtl8168bef_hw_phy_config(tp);
3590 break;
3591 case RTL_GIGA_MAC_VER_17:
3592 rtl8168bef_hw_phy_config(tp);
3593 break;
3594 case RTL_GIGA_MAC_VER_18:
3595 rtl8168cp_1_hw_phy_config(tp);
3596 break;
3597 case RTL_GIGA_MAC_VER_19:
3598 rtl8168c_1_hw_phy_config(tp);
3599 break;
3600 case RTL_GIGA_MAC_VER_20:
3601 rtl8168c_2_hw_phy_config(tp);
3602 break;
3603 case RTL_GIGA_MAC_VER_21:
3604 rtl8168c_3_hw_phy_config(tp);
3605 break;
3606 case RTL_GIGA_MAC_VER_22:
3607 rtl8168c_4_hw_phy_config(tp);
3608 break;
3609 case RTL_GIGA_MAC_VER_23:
3610 case RTL_GIGA_MAC_VER_24:
3611 rtl8168cp_2_hw_phy_config(tp);
3612 break;
3613 case RTL_GIGA_MAC_VER_25:
3614 rtl8168d_1_hw_phy_config(tp);
3615 break;
3616 case RTL_GIGA_MAC_VER_26:
3617 rtl8168d_2_hw_phy_config(tp);
3618 break;
3619 case RTL_GIGA_MAC_VER_27:
3620 rtl8168d_3_hw_phy_config(tp);
3621 break;
3622 case RTL_GIGA_MAC_VER_28:
3623 rtl8168d_4_hw_phy_config(tp);
3624 break;
3625 case RTL_GIGA_MAC_VER_29:
3626 case RTL_GIGA_MAC_VER_30:
3627 rtl8105e_hw_phy_config(tp);
3628 break;
3629 case RTL_GIGA_MAC_VER_31:
3630 /* None. */
3631 break;
3632 case RTL_GIGA_MAC_VER_32:
3633 case RTL_GIGA_MAC_VER_33:
3634 rtl8168e_1_hw_phy_config(tp);
3635 break;
3636 case RTL_GIGA_MAC_VER_34:
3637 rtl8168e_2_hw_phy_config(tp);
3638 break;
3639 case RTL_GIGA_MAC_VER_35:
3640 rtl8168f_1_hw_phy_config(tp);
3641 break;
3642 case RTL_GIGA_MAC_VER_36:
3643 rtl8168f_2_hw_phy_config(tp);
3644 break;
3645
3646 case RTL_GIGA_MAC_VER_37:
3647 rtl8402_hw_phy_config(tp);
3648 break;
3649
3650 case RTL_GIGA_MAC_VER_38:
3651 rtl8411_hw_phy_config(tp);
3652 break;
3653
3654 case RTL_GIGA_MAC_VER_39:
3655 rtl8106e_hw_phy_config(tp);
3656 break;
3657
3658 case RTL_GIGA_MAC_VER_40:
3659 rtl8168g_1_hw_phy_config(tp);
3660 break;
3661 case RTL_GIGA_MAC_VER_42:
3662 case RTL_GIGA_MAC_VER_43:
3663 case RTL_GIGA_MAC_VER_44:
3664 rtl8168g_2_hw_phy_config(tp);
3665 break;
3666
3667 case RTL_GIGA_MAC_VER_41:
3668 default:
3669 break;
3670 }
3671 }
3672
3673 static void rtl_phy_work(struct rtl8169_private *tp)
3674 {
3675 struct timer_list *timer = &tp->timer;
3676 void __iomem *ioaddr = tp->mmio_addr;
3677 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3678
3679 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3680
3681 if (tp->phy_reset_pending(tp)) {
3682 /*
3683 * A busy loop could burn quite a few cycles on nowadays CPU.
3684 * Let's delay the execution of the timer for a few ticks.
3685 */
3686 timeout = HZ/10;
3687 goto out_mod_timer;
3688 }
3689
3690 if (tp->link_ok(ioaddr))
3691 return;
3692
3693 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3694
3695 tp->phy_reset_enable(tp);
3696
3697 out_mod_timer:
3698 mod_timer(timer, jiffies + timeout);
3699 }
3700
3701 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3702 {
3703 if (!test_and_set_bit(flag, tp->wk.flags))
3704 schedule_work(&tp->wk.work);
3705 }
3706
3707 static void rtl8169_phy_timer(unsigned long __opaque)
3708 {
3709 struct net_device *dev = (struct net_device *)__opaque;
3710 struct rtl8169_private *tp = netdev_priv(dev);
3711
3712 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3713 }
3714
3715 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3716 void __iomem *ioaddr)
3717 {
3718 iounmap(ioaddr);
3719 pci_release_regions(pdev);
3720 pci_clear_mwi(pdev);
3721 pci_disable_device(pdev);
3722 free_netdev(dev);
3723 }
3724
3725 DECLARE_RTL_COND(rtl_phy_reset_cond)
3726 {
3727 return tp->phy_reset_pending(tp);
3728 }
3729
3730 static void rtl8169_phy_reset(struct net_device *dev,
3731 struct rtl8169_private *tp)
3732 {
3733 tp->phy_reset_enable(tp);
3734 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3735 }
3736
3737 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3738 {
3739 void __iomem *ioaddr = tp->mmio_addr;
3740
3741 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3742 (RTL_R8(PHYstatus) & TBI_Enable);
3743 }
3744
3745 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3746 {
3747 void __iomem *ioaddr = tp->mmio_addr;
3748
3749 rtl_hw_phy_config(dev);
3750
3751 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3752 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3753 RTL_W8(0x82, 0x01);
3754 }
3755
3756 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3757
3758 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3759 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3760
3761 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3762 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3763 RTL_W8(0x82, 0x01);
3764 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3765 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3766 }
3767
3768 rtl8169_phy_reset(dev, tp);
3769
3770 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3771 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3772 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3773 (tp->mii.supports_gmii ?
3774 ADVERTISED_1000baseT_Half |
3775 ADVERTISED_1000baseT_Full : 0));
3776
3777 if (rtl_tbi_enabled(tp))
3778 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3779 }
3780
3781 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3782 {
3783 void __iomem *ioaddr = tp->mmio_addr;
3784
3785 rtl_lock_work(tp);
3786
3787 RTL_W8(Cfg9346, Cfg9346_Unlock);
3788
3789 RTL_W32(MAC4, addr[4] | addr[5] << 8);
3790 RTL_R32(MAC4);
3791
3792 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3793 RTL_R32(MAC0);
3794
3795 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3796 rtl_rar_exgmac_set(tp, addr);
3797
3798 RTL_W8(Cfg9346, Cfg9346_Lock);
3799
3800 rtl_unlock_work(tp);
3801 }
3802
3803 static int rtl_set_mac_address(struct net_device *dev, void *p)
3804 {
3805 struct rtl8169_private *tp = netdev_priv(dev);
3806 struct sockaddr *addr = p;
3807
3808 if (!is_valid_ether_addr(addr->sa_data))
3809 return -EADDRNOTAVAIL;
3810
3811 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3812
3813 rtl_rar_set(tp, dev->dev_addr);
3814
3815 return 0;
3816 }
3817
3818 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3819 {
3820 struct rtl8169_private *tp = netdev_priv(dev);
3821 struct mii_ioctl_data *data = if_mii(ifr);
3822
3823 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3824 }
3825
3826 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3827 struct mii_ioctl_data *data, int cmd)
3828 {
3829 switch (cmd) {
3830 case SIOCGMIIPHY:
3831 data->phy_id = 32; /* Internal PHY */
3832 return 0;
3833
3834 case SIOCGMIIREG:
3835 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3836 return 0;
3837
3838 case SIOCSMIIREG:
3839 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3840 return 0;
3841 }
3842 return -EOPNOTSUPP;
3843 }
3844
3845 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3846 {
3847 return -EOPNOTSUPP;
3848 }
3849
3850 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3851 {
3852 if (tp->features & RTL_FEATURE_MSI) {
3853 pci_disable_msi(pdev);
3854 tp->features &= ~RTL_FEATURE_MSI;
3855 }
3856 }
3857
3858 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3859 {
3860 struct mdio_ops *ops = &tp->mdio_ops;
3861
3862 switch (tp->mac_version) {
3863 case RTL_GIGA_MAC_VER_27:
3864 ops->write = r8168dp_1_mdio_write;
3865 ops->read = r8168dp_1_mdio_read;
3866 break;
3867 case RTL_GIGA_MAC_VER_28:
3868 case RTL_GIGA_MAC_VER_31:
3869 ops->write = r8168dp_2_mdio_write;
3870 ops->read = r8168dp_2_mdio_read;
3871 break;
3872 case RTL_GIGA_MAC_VER_40:
3873 case RTL_GIGA_MAC_VER_41:
3874 case RTL_GIGA_MAC_VER_42:
3875 case RTL_GIGA_MAC_VER_43:
3876 case RTL_GIGA_MAC_VER_44:
3877 ops->write = r8168g_mdio_write;
3878 ops->read = r8168g_mdio_read;
3879 break;
3880 default:
3881 ops->write = r8169_mdio_write;
3882 ops->read = r8169_mdio_read;
3883 break;
3884 }
3885 }
3886
3887 static void rtl_speed_down(struct rtl8169_private *tp)
3888 {
3889 u32 adv;
3890 int lpa;
3891
3892 rtl_writephy(tp, 0x1f, 0x0000);
3893 lpa = rtl_readphy(tp, MII_LPA);
3894
3895 if (lpa & (LPA_10HALF | LPA_10FULL))
3896 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3897 else if (lpa & (LPA_100HALF | LPA_100FULL))
3898 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3899 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3900 else
3901 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3902 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3903 (tp->mii.supports_gmii ?
3904 ADVERTISED_1000baseT_Half |
3905 ADVERTISED_1000baseT_Full : 0);
3906
3907 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3908 adv);
3909 }
3910
3911 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3912 {
3913 void __iomem *ioaddr = tp->mmio_addr;
3914
3915 switch (tp->mac_version) {
3916 case RTL_GIGA_MAC_VER_25:
3917 case RTL_GIGA_MAC_VER_26:
3918 case RTL_GIGA_MAC_VER_29:
3919 case RTL_GIGA_MAC_VER_30:
3920 case RTL_GIGA_MAC_VER_32:
3921 case RTL_GIGA_MAC_VER_33:
3922 case RTL_GIGA_MAC_VER_34:
3923 case RTL_GIGA_MAC_VER_37:
3924 case RTL_GIGA_MAC_VER_38:
3925 case RTL_GIGA_MAC_VER_39:
3926 case RTL_GIGA_MAC_VER_40:
3927 case RTL_GIGA_MAC_VER_41:
3928 case RTL_GIGA_MAC_VER_42:
3929 case RTL_GIGA_MAC_VER_43:
3930 case RTL_GIGA_MAC_VER_44:
3931 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3932 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3933 break;
3934 default:
3935 break;
3936 }
3937 }
3938
3939 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3940 {
3941 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3942 return false;
3943
3944 rtl_speed_down(tp);
3945 rtl_wol_suspend_quirk(tp);
3946
3947 return true;
3948 }
3949
3950 static void r810x_phy_power_down(struct rtl8169_private *tp)
3951 {
3952 rtl_writephy(tp, 0x1f, 0x0000);
3953 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3954 }
3955
3956 static void r810x_phy_power_up(struct rtl8169_private *tp)
3957 {
3958 rtl_writephy(tp, 0x1f, 0x0000);
3959 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3960 }
3961
3962 static void r810x_pll_power_down(struct rtl8169_private *tp)
3963 {
3964 void __iomem *ioaddr = tp->mmio_addr;
3965
3966 if (rtl_wol_pll_power_down(tp))
3967 return;
3968
3969 r810x_phy_power_down(tp);
3970
3971 switch (tp->mac_version) {
3972 case RTL_GIGA_MAC_VER_07:
3973 case RTL_GIGA_MAC_VER_08:
3974 case RTL_GIGA_MAC_VER_09:
3975 case RTL_GIGA_MAC_VER_10:
3976 case RTL_GIGA_MAC_VER_13:
3977 case RTL_GIGA_MAC_VER_16:
3978 break;
3979 default:
3980 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3981 break;
3982 }
3983 }
3984
3985 static void r810x_pll_power_up(struct rtl8169_private *tp)
3986 {
3987 void __iomem *ioaddr = tp->mmio_addr;
3988
3989 r810x_phy_power_up(tp);
3990
3991 switch (tp->mac_version) {
3992 case RTL_GIGA_MAC_VER_07:
3993 case RTL_GIGA_MAC_VER_08:
3994 case RTL_GIGA_MAC_VER_09:
3995 case RTL_GIGA_MAC_VER_10:
3996 case RTL_GIGA_MAC_VER_13:
3997 case RTL_GIGA_MAC_VER_16:
3998 break;
3999 default:
4000 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4001 break;
4002 }
4003 }
4004
4005 static void r8168_phy_power_up(struct rtl8169_private *tp)
4006 {
4007 rtl_writephy(tp, 0x1f, 0x0000);
4008 switch (tp->mac_version) {
4009 case RTL_GIGA_MAC_VER_11:
4010 case RTL_GIGA_MAC_VER_12:
4011 case RTL_GIGA_MAC_VER_17:
4012 case RTL_GIGA_MAC_VER_18:
4013 case RTL_GIGA_MAC_VER_19:
4014 case RTL_GIGA_MAC_VER_20:
4015 case RTL_GIGA_MAC_VER_21:
4016 case RTL_GIGA_MAC_VER_22:
4017 case RTL_GIGA_MAC_VER_23:
4018 case RTL_GIGA_MAC_VER_24:
4019 case RTL_GIGA_MAC_VER_25:
4020 case RTL_GIGA_MAC_VER_26:
4021 case RTL_GIGA_MAC_VER_27:
4022 case RTL_GIGA_MAC_VER_28:
4023 case RTL_GIGA_MAC_VER_31:
4024 rtl_writephy(tp, 0x0e, 0x0000);
4025 break;
4026 default:
4027 break;
4028 }
4029 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4030 }
4031
4032 static void r8168_phy_power_down(struct rtl8169_private *tp)
4033 {
4034 rtl_writephy(tp, 0x1f, 0x0000);
4035 switch (tp->mac_version) {
4036 case RTL_GIGA_MAC_VER_32:
4037 case RTL_GIGA_MAC_VER_33:
4038 case RTL_GIGA_MAC_VER_40:
4039 case RTL_GIGA_MAC_VER_41:
4040 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4041 break;
4042
4043 case RTL_GIGA_MAC_VER_11:
4044 case RTL_GIGA_MAC_VER_12:
4045 case RTL_GIGA_MAC_VER_17:
4046 case RTL_GIGA_MAC_VER_18:
4047 case RTL_GIGA_MAC_VER_19:
4048 case RTL_GIGA_MAC_VER_20:
4049 case RTL_GIGA_MAC_VER_21:
4050 case RTL_GIGA_MAC_VER_22:
4051 case RTL_GIGA_MAC_VER_23:
4052 case RTL_GIGA_MAC_VER_24:
4053 case RTL_GIGA_MAC_VER_25:
4054 case RTL_GIGA_MAC_VER_26:
4055 case RTL_GIGA_MAC_VER_27:
4056 case RTL_GIGA_MAC_VER_28:
4057 case RTL_GIGA_MAC_VER_31:
4058 rtl_writephy(tp, 0x0e, 0x0200);
4059 default:
4060 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4061 break;
4062 }
4063 }
4064
4065 static void r8168_pll_power_down(struct rtl8169_private *tp)
4066 {
4067 void __iomem *ioaddr = tp->mmio_addr;
4068
4069 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4070 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4071 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4072 r8168dp_check_dash(tp)) {
4073 return;
4074 }
4075
4076 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4077 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4078 (RTL_R16(CPlusCmd) & ASF)) {
4079 return;
4080 }
4081
4082 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4083 tp->mac_version == RTL_GIGA_MAC_VER_33)
4084 rtl_ephy_write(tp, 0x19, 0xff64);
4085
4086 if (rtl_wol_pll_power_down(tp))
4087 return;
4088
4089 r8168_phy_power_down(tp);
4090
4091 switch (tp->mac_version) {
4092 case RTL_GIGA_MAC_VER_25:
4093 case RTL_GIGA_MAC_VER_26:
4094 case RTL_GIGA_MAC_VER_27:
4095 case RTL_GIGA_MAC_VER_28:
4096 case RTL_GIGA_MAC_VER_31:
4097 case RTL_GIGA_MAC_VER_32:
4098 case RTL_GIGA_MAC_VER_33:
4099 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4100 break;
4101 case RTL_GIGA_MAC_VER_40:
4102 case RTL_GIGA_MAC_VER_41:
4103 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4104 0xfc000000, ERIAR_EXGMAC);
4105 break;
4106 }
4107 }
4108
4109 static void r8168_pll_power_up(struct rtl8169_private *tp)
4110 {
4111 void __iomem *ioaddr = tp->mmio_addr;
4112
4113 switch (tp->mac_version) {
4114 case RTL_GIGA_MAC_VER_25:
4115 case RTL_GIGA_MAC_VER_26:
4116 case RTL_GIGA_MAC_VER_27:
4117 case RTL_GIGA_MAC_VER_28:
4118 case RTL_GIGA_MAC_VER_31:
4119 case RTL_GIGA_MAC_VER_32:
4120 case RTL_GIGA_MAC_VER_33:
4121 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4122 break;
4123 case RTL_GIGA_MAC_VER_40:
4124 case RTL_GIGA_MAC_VER_41:
4125 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4126 0x00000000, ERIAR_EXGMAC);
4127 break;
4128 }
4129
4130 r8168_phy_power_up(tp);
4131 }
4132
4133 static void rtl_generic_op(struct rtl8169_private *tp,
4134 void (*op)(struct rtl8169_private *))
4135 {
4136 if (op)
4137 op(tp);
4138 }
4139
4140 static void rtl_pll_power_down(struct rtl8169_private *tp)
4141 {
4142 rtl_generic_op(tp, tp->pll_power_ops.down);
4143 }
4144
4145 static void rtl_pll_power_up(struct rtl8169_private *tp)
4146 {
4147 rtl_generic_op(tp, tp->pll_power_ops.up);
4148 }
4149
4150 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4151 {
4152 struct pll_power_ops *ops = &tp->pll_power_ops;
4153
4154 switch (tp->mac_version) {
4155 case RTL_GIGA_MAC_VER_07:
4156 case RTL_GIGA_MAC_VER_08:
4157 case RTL_GIGA_MAC_VER_09:
4158 case RTL_GIGA_MAC_VER_10:
4159 case RTL_GIGA_MAC_VER_16:
4160 case RTL_GIGA_MAC_VER_29:
4161 case RTL_GIGA_MAC_VER_30:
4162 case RTL_GIGA_MAC_VER_37:
4163 case RTL_GIGA_MAC_VER_39:
4164 case RTL_GIGA_MAC_VER_43:
4165 ops->down = r810x_pll_power_down;
4166 ops->up = r810x_pll_power_up;
4167 break;
4168
4169 case RTL_GIGA_MAC_VER_11:
4170 case RTL_GIGA_MAC_VER_12:
4171 case RTL_GIGA_MAC_VER_17:
4172 case RTL_GIGA_MAC_VER_18:
4173 case RTL_GIGA_MAC_VER_19:
4174 case RTL_GIGA_MAC_VER_20:
4175 case RTL_GIGA_MAC_VER_21:
4176 case RTL_GIGA_MAC_VER_22:
4177 case RTL_GIGA_MAC_VER_23:
4178 case RTL_GIGA_MAC_VER_24:
4179 case RTL_GIGA_MAC_VER_25:
4180 case RTL_GIGA_MAC_VER_26:
4181 case RTL_GIGA_MAC_VER_27:
4182 case RTL_GIGA_MAC_VER_28:
4183 case RTL_GIGA_MAC_VER_31:
4184 case RTL_GIGA_MAC_VER_32:
4185 case RTL_GIGA_MAC_VER_33:
4186 case RTL_GIGA_MAC_VER_34:
4187 case RTL_GIGA_MAC_VER_35:
4188 case RTL_GIGA_MAC_VER_36:
4189 case RTL_GIGA_MAC_VER_38:
4190 case RTL_GIGA_MAC_VER_40:
4191 case RTL_GIGA_MAC_VER_41:
4192 case RTL_GIGA_MAC_VER_42:
4193 case RTL_GIGA_MAC_VER_44:
4194 ops->down = r8168_pll_power_down;
4195 ops->up = r8168_pll_power_up;
4196 break;
4197
4198 default:
4199 ops->down = NULL;
4200 ops->up = NULL;
4201 break;
4202 }
4203 }
4204
4205 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4206 {
4207 void __iomem *ioaddr = tp->mmio_addr;
4208
4209 switch (tp->mac_version) {
4210 case RTL_GIGA_MAC_VER_01:
4211 case RTL_GIGA_MAC_VER_02:
4212 case RTL_GIGA_MAC_VER_03:
4213 case RTL_GIGA_MAC_VER_04:
4214 case RTL_GIGA_MAC_VER_05:
4215 case RTL_GIGA_MAC_VER_06:
4216 case RTL_GIGA_MAC_VER_10:
4217 case RTL_GIGA_MAC_VER_11:
4218 case RTL_GIGA_MAC_VER_12:
4219 case RTL_GIGA_MAC_VER_13:
4220 case RTL_GIGA_MAC_VER_14:
4221 case RTL_GIGA_MAC_VER_15:
4222 case RTL_GIGA_MAC_VER_16:
4223 case RTL_GIGA_MAC_VER_17:
4224 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4225 break;
4226 case RTL_GIGA_MAC_VER_18:
4227 case RTL_GIGA_MAC_VER_19:
4228 case RTL_GIGA_MAC_VER_20:
4229 case RTL_GIGA_MAC_VER_21:
4230 case RTL_GIGA_MAC_VER_22:
4231 case RTL_GIGA_MAC_VER_23:
4232 case RTL_GIGA_MAC_VER_24:
4233 case RTL_GIGA_MAC_VER_34:
4234 case RTL_GIGA_MAC_VER_35:
4235 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4236 break;
4237 case RTL_GIGA_MAC_VER_40:
4238 case RTL_GIGA_MAC_VER_41:
4239 case RTL_GIGA_MAC_VER_42:
4240 case RTL_GIGA_MAC_VER_43:
4241 case RTL_GIGA_MAC_VER_44:
4242 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4243 break;
4244 default:
4245 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4246 break;
4247 }
4248 }
4249
4250 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4251 {
4252 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4253 }
4254
4255 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4256 {
4257 void __iomem *ioaddr = tp->mmio_addr;
4258
4259 RTL_W8(Cfg9346, Cfg9346_Unlock);
4260 rtl_generic_op(tp, tp->jumbo_ops.enable);
4261 RTL_W8(Cfg9346, Cfg9346_Lock);
4262 }
4263
4264 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4265 {
4266 void __iomem *ioaddr = tp->mmio_addr;
4267
4268 RTL_W8(Cfg9346, Cfg9346_Unlock);
4269 rtl_generic_op(tp, tp->jumbo_ops.disable);
4270 RTL_W8(Cfg9346, Cfg9346_Lock);
4271 }
4272
4273 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4274 {
4275 void __iomem *ioaddr = tp->mmio_addr;
4276
4277 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4278 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4279 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4280 }
4281
4282 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4283 {
4284 void __iomem *ioaddr = tp->mmio_addr;
4285
4286 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4287 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4288 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4289 }
4290
4291 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4292 {
4293 void __iomem *ioaddr = tp->mmio_addr;
4294
4295 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4296 }
4297
4298 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4299 {
4300 void __iomem *ioaddr = tp->mmio_addr;
4301
4302 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4303 }
4304
4305 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4306 {
4307 void __iomem *ioaddr = tp->mmio_addr;
4308
4309 RTL_W8(MaxTxPacketSize, 0x3f);
4310 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4311 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4312 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4313 }
4314
4315 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4316 {
4317 void __iomem *ioaddr = tp->mmio_addr;
4318
4319 RTL_W8(MaxTxPacketSize, 0x0c);
4320 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4321 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4322 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4323 }
4324
4325 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4326 {
4327 rtl_tx_performance_tweak(tp->pci_dev,
4328 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4329 }
4330
4331 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4332 {
4333 rtl_tx_performance_tweak(tp->pci_dev,
4334 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4335 }
4336
4337 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4338 {
4339 void __iomem *ioaddr = tp->mmio_addr;
4340
4341 r8168b_0_hw_jumbo_enable(tp);
4342
4343 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4344 }
4345
4346 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4347 {
4348 void __iomem *ioaddr = tp->mmio_addr;
4349
4350 r8168b_0_hw_jumbo_disable(tp);
4351
4352 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4353 }
4354
4355 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4356 {
4357 struct jumbo_ops *ops = &tp->jumbo_ops;
4358
4359 switch (tp->mac_version) {
4360 case RTL_GIGA_MAC_VER_11:
4361 ops->disable = r8168b_0_hw_jumbo_disable;
4362 ops->enable = r8168b_0_hw_jumbo_enable;
4363 break;
4364 case RTL_GIGA_MAC_VER_12:
4365 case RTL_GIGA_MAC_VER_17:
4366 ops->disable = r8168b_1_hw_jumbo_disable;
4367 ops->enable = r8168b_1_hw_jumbo_enable;
4368 break;
4369 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4370 case RTL_GIGA_MAC_VER_19:
4371 case RTL_GIGA_MAC_VER_20:
4372 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4373 case RTL_GIGA_MAC_VER_22:
4374 case RTL_GIGA_MAC_VER_23:
4375 case RTL_GIGA_MAC_VER_24:
4376 case RTL_GIGA_MAC_VER_25:
4377 case RTL_GIGA_MAC_VER_26:
4378 ops->disable = r8168c_hw_jumbo_disable;
4379 ops->enable = r8168c_hw_jumbo_enable;
4380 break;
4381 case RTL_GIGA_MAC_VER_27:
4382 case RTL_GIGA_MAC_VER_28:
4383 ops->disable = r8168dp_hw_jumbo_disable;
4384 ops->enable = r8168dp_hw_jumbo_enable;
4385 break;
4386 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4387 case RTL_GIGA_MAC_VER_32:
4388 case RTL_GIGA_MAC_VER_33:
4389 case RTL_GIGA_MAC_VER_34:
4390 ops->disable = r8168e_hw_jumbo_disable;
4391 ops->enable = r8168e_hw_jumbo_enable;
4392 break;
4393
4394 /*
4395 * No action needed for jumbo frames with 8169.
4396 * No jumbo for 810x at all.
4397 */
4398 case RTL_GIGA_MAC_VER_40:
4399 case RTL_GIGA_MAC_VER_41:
4400 case RTL_GIGA_MAC_VER_42:
4401 case RTL_GIGA_MAC_VER_43:
4402 case RTL_GIGA_MAC_VER_44:
4403 default:
4404 ops->disable = NULL;
4405 ops->enable = NULL;
4406 break;
4407 }
4408 }
4409
4410 DECLARE_RTL_COND(rtl_chipcmd_cond)
4411 {
4412 void __iomem *ioaddr = tp->mmio_addr;
4413
4414 return RTL_R8(ChipCmd) & CmdReset;
4415 }
4416
4417 static void rtl_hw_reset(struct rtl8169_private *tp)
4418 {
4419 void __iomem *ioaddr = tp->mmio_addr;
4420
4421 RTL_W8(ChipCmd, CmdReset);
4422
4423 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4424 }
4425
4426 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4427 {
4428 struct rtl_fw *rtl_fw;
4429 const char *name;
4430 int rc = -ENOMEM;
4431
4432 name = rtl_lookup_firmware_name(tp);
4433 if (!name)
4434 goto out_no_firmware;
4435
4436 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4437 if (!rtl_fw)
4438 goto err_warn;
4439
4440 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4441 if (rc < 0)
4442 goto err_free;
4443
4444 rc = rtl_check_firmware(tp, rtl_fw);
4445 if (rc < 0)
4446 goto err_release_firmware;
4447
4448 tp->rtl_fw = rtl_fw;
4449 out:
4450 return;
4451
4452 err_release_firmware:
4453 release_firmware(rtl_fw->fw);
4454 err_free:
4455 kfree(rtl_fw);
4456 err_warn:
4457 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4458 name, rc);
4459 out_no_firmware:
4460 tp->rtl_fw = NULL;
4461 goto out;
4462 }
4463
4464 static void rtl_request_firmware(struct rtl8169_private *tp)
4465 {
4466 if (IS_ERR(tp->rtl_fw))
4467 rtl_request_uncached_firmware(tp);
4468 }
4469
4470 static void rtl_rx_close(struct rtl8169_private *tp)
4471 {
4472 void __iomem *ioaddr = tp->mmio_addr;
4473
4474 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4475 }
4476
4477 DECLARE_RTL_COND(rtl_npq_cond)
4478 {
4479 void __iomem *ioaddr = tp->mmio_addr;
4480
4481 return RTL_R8(TxPoll) & NPQ;
4482 }
4483
4484 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4485 {
4486 void __iomem *ioaddr = tp->mmio_addr;
4487
4488 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4489 }
4490
4491 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4492 {
4493 void __iomem *ioaddr = tp->mmio_addr;
4494
4495 /* Disable interrupts */
4496 rtl8169_irq_mask_and_ack(tp);
4497
4498 rtl_rx_close(tp);
4499
4500 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4501 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4502 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4503 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4504 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4505 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4506 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4507 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4508 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4509 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4510 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4511 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4512 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4513 tp->mac_version == RTL_GIGA_MAC_VER_38) {
4514 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4515 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4516 } else {
4517 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4518 udelay(100);
4519 }
4520
4521 rtl_hw_reset(tp);
4522 }
4523
4524 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4525 {
4526 void __iomem *ioaddr = tp->mmio_addr;
4527
4528 /* Set DMA burst size and Interframe Gap Time */
4529 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4530 (InterFrameGap << TxInterFrameGapShift));
4531 }
4532
4533 static void rtl_hw_start(struct net_device *dev)
4534 {
4535 struct rtl8169_private *tp = netdev_priv(dev);
4536
4537 tp->hw_start(dev);
4538
4539 rtl_irq_enable_all(tp);
4540 }
4541
4542 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4543 void __iomem *ioaddr)
4544 {
4545 /*
4546 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4547 * register to be written before TxDescAddrLow to work.
4548 * Switching from MMIO to I/O access fixes the issue as well.
4549 */
4550 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4551 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4552 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4553 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4554 }
4555
4556 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4557 {
4558 u16 cmd;
4559
4560 cmd = RTL_R16(CPlusCmd);
4561 RTL_W16(CPlusCmd, cmd);
4562 return cmd;
4563 }
4564
4565 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4566 {
4567 /* Low hurts. Let's disable the filtering. */
4568 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4569 }
4570
4571 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4572 {
4573 static const struct rtl_cfg2_info {
4574 u32 mac_version;
4575 u32 clk;
4576 u32 val;
4577 } cfg2_info [] = {
4578 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4579 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4580 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4581 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4582 };
4583 const struct rtl_cfg2_info *p = cfg2_info;
4584 unsigned int i;
4585 u32 clk;
4586
4587 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4588 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4589 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4590 RTL_W32(0x7c, p->val);
4591 break;
4592 }
4593 }
4594 }
4595
4596 static void rtl_set_rx_mode(struct net_device *dev)
4597 {
4598 struct rtl8169_private *tp = netdev_priv(dev);
4599 void __iomem *ioaddr = tp->mmio_addr;
4600 u32 mc_filter[2]; /* Multicast hash filter */
4601 int rx_mode;
4602 u32 tmp = 0;
4603
4604 if (dev->flags & IFF_PROMISC) {
4605 /* Unconditionally log net taps. */
4606 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4607 rx_mode =
4608 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4609 AcceptAllPhys;
4610 mc_filter[1] = mc_filter[0] = 0xffffffff;
4611 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4612 (dev->flags & IFF_ALLMULTI)) {
4613 /* Too many to filter perfectly -- accept all multicasts. */
4614 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4615 mc_filter[1] = mc_filter[0] = 0xffffffff;
4616 } else {
4617 struct netdev_hw_addr *ha;
4618
4619 rx_mode = AcceptBroadcast | AcceptMyPhys;
4620 mc_filter[1] = mc_filter[0] = 0;
4621 netdev_for_each_mc_addr(ha, dev) {
4622 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4623 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4624 rx_mode |= AcceptMulticast;
4625 }
4626 }
4627
4628 if (dev->features & NETIF_F_RXALL)
4629 rx_mode |= (AcceptErr | AcceptRunt);
4630
4631 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4632
4633 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4634 u32 data = mc_filter[0];
4635
4636 mc_filter[0] = swab32(mc_filter[1]);
4637 mc_filter[1] = swab32(data);
4638 }
4639
4640 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4641 mc_filter[1] = mc_filter[0] = 0xffffffff;
4642
4643 RTL_W32(MAR0 + 4, mc_filter[1]);
4644 RTL_W32(MAR0 + 0, mc_filter[0]);
4645
4646 RTL_W32(RxConfig, tmp);
4647 }
4648
4649 static void rtl_hw_start_8169(struct net_device *dev)
4650 {
4651 struct rtl8169_private *tp = netdev_priv(dev);
4652 void __iomem *ioaddr = tp->mmio_addr;
4653 struct pci_dev *pdev = tp->pci_dev;
4654
4655 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4656 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4657 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4658 }
4659
4660 RTL_W8(Cfg9346, Cfg9346_Unlock);
4661 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4662 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4663 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4664 tp->mac_version == RTL_GIGA_MAC_VER_04)
4665 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4666
4667 rtl_init_rxcfg(tp);
4668
4669 RTL_W8(EarlyTxThres, NoEarlyTx);
4670
4671 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4672
4673 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4674 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4675 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4676 tp->mac_version == RTL_GIGA_MAC_VER_04)
4677 rtl_set_rx_tx_config_registers(tp);
4678
4679 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4680
4681 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4682 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4683 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4684 "Bit-3 and bit-14 MUST be 1\n");
4685 tp->cp_cmd |= (1 << 14);
4686 }
4687
4688 RTL_W16(CPlusCmd, tp->cp_cmd);
4689
4690 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4691
4692 /*
4693 * Undocumented corner. Supposedly:
4694 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4695 */
4696 RTL_W16(IntrMitigate, 0x0000);
4697
4698 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4699
4700 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4701 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4702 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4703 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4704 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4705 rtl_set_rx_tx_config_registers(tp);
4706 }
4707
4708 RTL_W8(Cfg9346, Cfg9346_Lock);
4709
4710 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4711 RTL_R8(IntrMask);
4712
4713 RTL_W32(RxMissed, 0);
4714
4715 rtl_set_rx_mode(dev);
4716
4717 /* no early-rx interrupts */
4718 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4719 }
4720
4721 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4722 {
4723 if (tp->csi_ops.write)
4724 tp->csi_ops.write(tp, addr, value);
4725 }
4726
4727 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4728 {
4729 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4730 }
4731
4732 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4733 {
4734 u32 csi;
4735
4736 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4737 rtl_csi_write(tp, 0x070c, csi | bits);
4738 }
4739
4740 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4741 {
4742 rtl_csi_access_enable(tp, 0x17000000);
4743 }
4744
4745 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4746 {
4747 rtl_csi_access_enable(tp, 0x27000000);
4748 }
4749
4750 DECLARE_RTL_COND(rtl_csiar_cond)
4751 {
4752 void __iomem *ioaddr = tp->mmio_addr;
4753
4754 return RTL_R32(CSIAR) & CSIAR_FLAG;
4755 }
4756
4757 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4758 {
4759 void __iomem *ioaddr = tp->mmio_addr;
4760
4761 RTL_W32(CSIDR, value);
4762 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4763 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4764
4765 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4766 }
4767
4768 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4769 {
4770 void __iomem *ioaddr = tp->mmio_addr;
4771
4772 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4773 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4774
4775 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4776 RTL_R32(CSIDR) : ~0;
4777 }
4778
4779 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4780 {
4781 void __iomem *ioaddr = tp->mmio_addr;
4782
4783 RTL_W32(CSIDR, value);
4784 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4785 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4786 CSIAR_FUNC_NIC);
4787
4788 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4789 }
4790
4791 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4792 {
4793 void __iomem *ioaddr = tp->mmio_addr;
4794
4795 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4796 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4797
4798 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4799 RTL_R32(CSIDR) : ~0;
4800 }
4801
4802 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4803 {
4804 void __iomem *ioaddr = tp->mmio_addr;
4805
4806 RTL_W32(CSIDR, value);
4807 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4808 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4809 CSIAR_FUNC_NIC2);
4810
4811 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4812 }
4813
4814 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4815 {
4816 void __iomem *ioaddr = tp->mmio_addr;
4817
4818 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4819 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4820
4821 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4822 RTL_R32(CSIDR) : ~0;
4823 }
4824
4825 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4826 {
4827 struct csi_ops *ops = &tp->csi_ops;
4828
4829 switch (tp->mac_version) {
4830 case RTL_GIGA_MAC_VER_01:
4831 case RTL_GIGA_MAC_VER_02:
4832 case RTL_GIGA_MAC_VER_03:
4833 case RTL_GIGA_MAC_VER_04:
4834 case RTL_GIGA_MAC_VER_05:
4835 case RTL_GIGA_MAC_VER_06:
4836 case RTL_GIGA_MAC_VER_10:
4837 case RTL_GIGA_MAC_VER_11:
4838 case RTL_GIGA_MAC_VER_12:
4839 case RTL_GIGA_MAC_VER_13:
4840 case RTL_GIGA_MAC_VER_14:
4841 case RTL_GIGA_MAC_VER_15:
4842 case RTL_GIGA_MAC_VER_16:
4843 case RTL_GIGA_MAC_VER_17:
4844 ops->write = NULL;
4845 ops->read = NULL;
4846 break;
4847
4848 case RTL_GIGA_MAC_VER_37:
4849 case RTL_GIGA_MAC_VER_38:
4850 ops->write = r8402_csi_write;
4851 ops->read = r8402_csi_read;
4852 break;
4853
4854 case RTL_GIGA_MAC_VER_44:
4855 ops->write = r8411_csi_write;
4856 ops->read = r8411_csi_read;
4857 break;
4858
4859 default:
4860 ops->write = r8169_csi_write;
4861 ops->read = r8169_csi_read;
4862 break;
4863 }
4864 }
4865
4866 struct ephy_info {
4867 unsigned int offset;
4868 u16 mask;
4869 u16 bits;
4870 };
4871
4872 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4873 int len)
4874 {
4875 u16 w;
4876
4877 while (len-- > 0) {
4878 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4879 rtl_ephy_write(tp, e->offset, w);
4880 e++;
4881 }
4882 }
4883
4884 static void rtl_disable_clock_request(struct pci_dev *pdev)
4885 {
4886 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4887 PCI_EXP_LNKCTL_CLKREQ_EN);
4888 }
4889
4890 static void rtl_enable_clock_request(struct pci_dev *pdev)
4891 {
4892 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4893 PCI_EXP_LNKCTL_CLKREQ_EN);
4894 }
4895
4896 #define R8168_CPCMD_QUIRK_MASK (\
4897 EnableBist | \
4898 Mac_dbgo_oe | \
4899 Force_half_dup | \
4900 Force_rxflow_en | \
4901 Force_txflow_en | \
4902 Cxpl_dbg_sel | \
4903 ASF | \
4904 PktCntrDisable | \
4905 Mac_dbgo_sel)
4906
4907 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4908 {
4909 void __iomem *ioaddr = tp->mmio_addr;
4910 struct pci_dev *pdev = tp->pci_dev;
4911
4912 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4913
4914 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4915
4916 if (tp->dev->mtu <= ETH_DATA_LEN) {
4917 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4918 PCI_EXP_DEVCTL_NOSNOOP_EN);
4919 }
4920 }
4921
4922 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4923 {
4924 void __iomem *ioaddr = tp->mmio_addr;
4925
4926 rtl_hw_start_8168bb(tp);
4927
4928 RTL_W8(MaxTxPacketSize, TxPacketMax);
4929
4930 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4931 }
4932
4933 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4934 {
4935 void __iomem *ioaddr = tp->mmio_addr;
4936 struct pci_dev *pdev = tp->pci_dev;
4937
4938 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4939
4940 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4941
4942 if (tp->dev->mtu <= ETH_DATA_LEN)
4943 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4944
4945 rtl_disable_clock_request(pdev);
4946
4947 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4948 }
4949
4950 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4951 {
4952 static const struct ephy_info e_info_8168cp[] = {
4953 { 0x01, 0, 0x0001 },
4954 { 0x02, 0x0800, 0x1000 },
4955 { 0x03, 0, 0x0042 },
4956 { 0x06, 0x0080, 0x0000 },
4957 { 0x07, 0, 0x2000 }
4958 };
4959
4960 rtl_csi_access_enable_2(tp);
4961
4962 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4963
4964 __rtl_hw_start_8168cp(tp);
4965 }
4966
4967 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4968 {
4969 void __iomem *ioaddr = tp->mmio_addr;
4970 struct pci_dev *pdev = tp->pci_dev;
4971
4972 rtl_csi_access_enable_2(tp);
4973
4974 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4975
4976 if (tp->dev->mtu <= ETH_DATA_LEN)
4977 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4978
4979 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4980 }
4981
4982 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4983 {
4984 void __iomem *ioaddr = tp->mmio_addr;
4985 struct pci_dev *pdev = tp->pci_dev;
4986
4987 rtl_csi_access_enable_2(tp);
4988
4989 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4990
4991 /* Magic. */
4992 RTL_W8(DBG_REG, 0x20);
4993
4994 RTL_W8(MaxTxPacketSize, TxPacketMax);
4995
4996 if (tp->dev->mtu <= ETH_DATA_LEN)
4997 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4998
4999 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5000 }
5001
5002 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5003 {
5004 void __iomem *ioaddr = tp->mmio_addr;
5005 static const struct ephy_info e_info_8168c_1[] = {
5006 { 0x02, 0x0800, 0x1000 },
5007 { 0x03, 0, 0x0002 },
5008 { 0x06, 0x0080, 0x0000 }
5009 };
5010
5011 rtl_csi_access_enable_2(tp);
5012
5013 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5014
5015 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5016
5017 __rtl_hw_start_8168cp(tp);
5018 }
5019
5020 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5021 {
5022 static const struct ephy_info e_info_8168c_2[] = {
5023 { 0x01, 0, 0x0001 },
5024 { 0x03, 0x0400, 0x0220 }
5025 };
5026
5027 rtl_csi_access_enable_2(tp);
5028
5029 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5030
5031 __rtl_hw_start_8168cp(tp);
5032 }
5033
5034 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5035 {
5036 rtl_hw_start_8168c_2(tp);
5037 }
5038
5039 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5040 {
5041 rtl_csi_access_enable_2(tp);
5042
5043 __rtl_hw_start_8168cp(tp);
5044 }
5045
5046 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5047 {
5048 void __iomem *ioaddr = tp->mmio_addr;
5049 struct pci_dev *pdev = tp->pci_dev;
5050
5051 rtl_csi_access_enable_2(tp);
5052
5053 rtl_disable_clock_request(pdev);
5054
5055 RTL_W8(MaxTxPacketSize, TxPacketMax);
5056
5057 if (tp->dev->mtu <= ETH_DATA_LEN)
5058 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5059
5060 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5061 }
5062
5063 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5064 {
5065 void __iomem *ioaddr = tp->mmio_addr;
5066 struct pci_dev *pdev = tp->pci_dev;
5067
5068 rtl_csi_access_enable_1(tp);
5069
5070 if (tp->dev->mtu <= ETH_DATA_LEN)
5071 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5072
5073 RTL_W8(MaxTxPacketSize, TxPacketMax);
5074
5075 rtl_disable_clock_request(pdev);
5076 }
5077
5078 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5079 {
5080 void __iomem *ioaddr = tp->mmio_addr;
5081 struct pci_dev *pdev = tp->pci_dev;
5082 static const struct ephy_info e_info_8168d_4[] = {
5083 { 0x0b, ~0, 0x48 },
5084 { 0x19, 0x20, 0x50 },
5085 { 0x0c, ~0, 0x20 }
5086 };
5087 int i;
5088
5089 rtl_csi_access_enable_1(tp);
5090
5091 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5092
5093 RTL_W8(MaxTxPacketSize, TxPacketMax);
5094
5095 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5096 const struct ephy_info *e = e_info_8168d_4 + i;
5097 u16 w;
5098
5099 w = rtl_ephy_read(tp, e->offset);
5100 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5101 }
5102
5103 rtl_enable_clock_request(pdev);
5104 }
5105
5106 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5107 {
5108 void __iomem *ioaddr = tp->mmio_addr;
5109 struct pci_dev *pdev = tp->pci_dev;
5110 static const struct ephy_info e_info_8168e_1[] = {
5111 { 0x00, 0x0200, 0x0100 },
5112 { 0x00, 0x0000, 0x0004 },
5113 { 0x06, 0x0002, 0x0001 },
5114 { 0x06, 0x0000, 0x0030 },
5115 { 0x07, 0x0000, 0x2000 },
5116 { 0x00, 0x0000, 0x0020 },
5117 { 0x03, 0x5800, 0x2000 },
5118 { 0x03, 0x0000, 0x0001 },
5119 { 0x01, 0x0800, 0x1000 },
5120 { 0x07, 0x0000, 0x4000 },
5121 { 0x1e, 0x0000, 0x2000 },
5122 { 0x19, 0xffff, 0xfe6c },
5123 { 0x0a, 0x0000, 0x0040 }
5124 };
5125
5126 rtl_csi_access_enable_2(tp);
5127
5128 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5129
5130 if (tp->dev->mtu <= ETH_DATA_LEN)
5131 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5132
5133 RTL_W8(MaxTxPacketSize, TxPacketMax);
5134
5135 rtl_disable_clock_request(pdev);
5136
5137 /* Reset tx FIFO pointer */
5138 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5139 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5140
5141 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5142 }
5143
5144 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5145 {
5146 void __iomem *ioaddr = tp->mmio_addr;
5147 struct pci_dev *pdev = tp->pci_dev;
5148 static const struct ephy_info e_info_8168e_2[] = {
5149 { 0x09, 0x0000, 0x0080 },
5150 { 0x19, 0x0000, 0x0224 }
5151 };
5152
5153 rtl_csi_access_enable_1(tp);
5154
5155 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5156
5157 if (tp->dev->mtu <= ETH_DATA_LEN)
5158 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5159
5160 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5161 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5162 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5163 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5164 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5165 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5166 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5167 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5168
5169 RTL_W8(MaxTxPacketSize, EarlySize);
5170
5171 rtl_disable_clock_request(pdev);
5172
5173 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5174 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5175
5176 /* Adjust EEE LED frequency */
5177 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5178
5179 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5180 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5181 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5182 }
5183
5184 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5185 {
5186 void __iomem *ioaddr = tp->mmio_addr;
5187 struct pci_dev *pdev = tp->pci_dev;
5188
5189 rtl_csi_access_enable_2(tp);
5190
5191 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5192
5193 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5194 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5195 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5196 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5197 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5198 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5199 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5200 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5201 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5202 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5203
5204 RTL_W8(MaxTxPacketSize, EarlySize);
5205
5206 rtl_disable_clock_request(pdev);
5207
5208 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5209 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5210 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5211 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5212 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5213 }
5214
5215 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5216 {
5217 void __iomem *ioaddr = tp->mmio_addr;
5218 static const struct ephy_info e_info_8168f_1[] = {
5219 { 0x06, 0x00c0, 0x0020 },
5220 { 0x08, 0x0001, 0x0002 },
5221 { 0x09, 0x0000, 0x0080 },
5222 { 0x19, 0x0000, 0x0224 }
5223 };
5224
5225 rtl_hw_start_8168f(tp);
5226
5227 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5228
5229 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5230
5231 /* Adjust EEE LED frequency */
5232 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5233 }
5234
5235 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5236 {
5237 static const struct ephy_info e_info_8168f_1[] = {
5238 { 0x06, 0x00c0, 0x0020 },
5239 { 0x0f, 0xffff, 0x5200 },
5240 { 0x1e, 0x0000, 0x4000 },
5241 { 0x19, 0x0000, 0x0224 }
5242 };
5243
5244 rtl_hw_start_8168f(tp);
5245
5246 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5247
5248 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5249 }
5250
5251 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5252 {
5253 void __iomem *ioaddr = tp->mmio_addr;
5254 struct pci_dev *pdev = tp->pci_dev;
5255
5256 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5257
5258 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5259 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5260 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5261 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5262
5263 rtl_csi_access_enable_1(tp);
5264
5265 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5266
5267 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5268 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5269 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5270
5271 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5272 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5273 RTL_W8(MaxTxPacketSize, EarlySize);
5274
5275 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5276 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5277
5278 /* Adjust EEE LED frequency */
5279 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5280
5281 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5282 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5283 }
5284
5285 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5286 {
5287 void __iomem *ioaddr = tp->mmio_addr;
5288 static const struct ephy_info e_info_8168g_2[] = {
5289 { 0x00, 0x0000, 0x0008 },
5290 { 0x0c, 0x3df0, 0x0200 },
5291 { 0x19, 0xffff, 0xfc00 },
5292 { 0x1e, 0xffff, 0x20eb }
5293 };
5294
5295 rtl_hw_start_8168g_1(tp);
5296
5297 /* disable aspm and clock request before access ephy */
5298 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5299 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5300 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5301 }
5302
5303 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5304 {
5305 void __iomem *ioaddr = tp->mmio_addr;
5306 static const struct ephy_info e_info_8411_2[] = {
5307 { 0x00, 0x0000, 0x0008 },
5308 { 0x0c, 0x3df0, 0x0200 },
5309 { 0x0f, 0xffff, 0x5200 },
5310 { 0x19, 0x0020, 0x0000 },
5311 { 0x1e, 0x0000, 0x2000 }
5312 };
5313
5314 rtl_hw_start_8168g_1(tp);
5315
5316 /* disable aspm and clock request before access ephy */
5317 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5318 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5319 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5320 }
5321
5322 static void rtl_hw_start_8168(struct net_device *dev)
5323 {
5324 struct rtl8169_private *tp = netdev_priv(dev);
5325 void __iomem *ioaddr = tp->mmio_addr;
5326
5327 RTL_W8(Cfg9346, Cfg9346_Unlock);
5328
5329 RTL_W8(MaxTxPacketSize, TxPacketMax);
5330
5331 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5332
5333 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5334
5335 RTL_W16(CPlusCmd, tp->cp_cmd);
5336
5337 RTL_W16(IntrMitigate, 0x5151);
5338
5339 /* Work around for RxFIFO overflow. */
5340 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5341 tp->event_slow |= RxFIFOOver | PCSTimeout;
5342 tp->event_slow &= ~RxOverflow;
5343 }
5344
5345 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5346
5347 rtl_set_rx_tx_config_registers(tp);
5348
5349 RTL_R8(IntrMask);
5350
5351 switch (tp->mac_version) {
5352 case RTL_GIGA_MAC_VER_11:
5353 rtl_hw_start_8168bb(tp);
5354 break;
5355
5356 case RTL_GIGA_MAC_VER_12:
5357 case RTL_GIGA_MAC_VER_17:
5358 rtl_hw_start_8168bef(tp);
5359 break;
5360
5361 case RTL_GIGA_MAC_VER_18:
5362 rtl_hw_start_8168cp_1(tp);
5363 break;
5364
5365 case RTL_GIGA_MAC_VER_19:
5366 rtl_hw_start_8168c_1(tp);
5367 break;
5368
5369 case RTL_GIGA_MAC_VER_20:
5370 rtl_hw_start_8168c_2(tp);
5371 break;
5372
5373 case RTL_GIGA_MAC_VER_21:
5374 rtl_hw_start_8168c_3(tp);
5375 break;
5376
5377 case RTL_GIGA_MAC_VER_22:
5378 rtl_hw_start_8168c_4(tp);
5379 break;
5380
5381 case RTL_GIGA_MAC_VER_23:
5382 rtl_hw_start_8168cp_2(tp);
5383 break;
5384
5385 case RTL_GIGA_MAC_VER_24:
5386 rtl_hw_start_8168cp_3(tp);
5387 break;
5388
5389 case RTL_GIGA_MAC_VER_25:
5390 case RTL_GIGA_MAC_VER_26:
5391 case RTL_GIGA_MAC_VER_27:
5392 rtl_hw_start_8168d(tp);
5393 break;
5394
5395 case RTL_GIGA_MAC_VER_28:
5396 rtl_hw_start_8168d_4(tp);
5397 break;
5398
5399 case RTL_GIGA_MAC_VER_31:
5400 rtl_hw_start_8168dp(tp);
5401 break;
5402
5403 case RTL_GIGA_MAC_VER_32:
5404 case RTL_GIGA_MAC_VER_33:
5405 rtl_hw_start_8168e_1(tp);
5406 break;
5407 case RTL_GIGA_MAC_VER_34:
5408 rtl_hw_start_8168e_2(tp);
5409 break;
5410
5411 case RTL_GIGA_MAC_VER_35:
5412 case RTL_GIGA_MAC_VER_36:
5413 rtl_hw_start_8168f_1(tp);
5414 break;
5415
5416 case RTL_GIGA_MAC_VER_38:
5417 rtl_hw_start_8411(tp);
5418 break;
5419
5420 case RTL_GIGA_MAC_VER_40:
5421 case RTL_GIGA_MAC_VER_41:
5422 rtl_hw_start_8168g_1(tp);
5423 break;
5424 case RTL_GIGA_MAC_VER_42:
5425 rtl_hw_start_8168g_2(tp);
5426 break;
5427
5428 case RTL_GIGA_MAC_VER_44:
5429 rtl_hw_start_8411_2(tp);
5430 break;
5431
5432 default:
5433 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5434 dev->name, tp->mac_version);
5435 break;
5436 }
5437
5438 RTL_W8(Cfg9346, Cfg9346_Lock);
5439
5440 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5441
5442 rtl_set_rx_mode(dev);
5443
5444 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5445 }
5446
5447 #define R810X_CPCMD_QUIRK_MASK (\
5448 EnableBist | \
5449 Mac_dbgo_oe | \
5450 Force_half_dup | \
5451 Force_rxflow_en | \
5452 Force_txflow_en | \
5453 Cxpl_dbg_sel | \
5454 ASF | \
5455 PktCntrDisable | \
5456 Mac_dbgo_sel)
5457
5458 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5459 {
5460 void __iomem *ioaddr = tp->mmio_addr;
5461 struct pci_dev *pdev = tp->pci_dev;
5462 static const struct ephy_info e_info_8102e_1[] = {
5463 { 0x01, 0, 0x6e65 },
5464 { 0x02, 0, 0x091f },
5465 { 0x03, 0, 0xc2f9 },
5466 { 0x06, 0, 0xafb5 },
5467 { 0x07, 0, 0x0e00 },
5468 { 0x19, 0, 0xec80 },
5469 { 0x01, 0, 0x2e65 },
5470 { 0x01, 0, 0x6e65 }
5471 };
5472 u8 cfg1;
5473
5474 rtl_csi_access_enable_2(tp);
5475
5476 RTL_W8(DBG_REG, FIX_NAK_1);
5477
5478 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5479
5480 RTL_W8(Config1,
5481 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5482 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5483
5484 cfg1 = RTL_R8(Config1);
5485 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5486 RTL_W8(Config1, cfg1 & ~LEDS0);
5487
5488 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5489 }
5490
5491 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5492 {
5493 void __iomem *ioaddr = tp->mmio_addr;
5494 struct pci_dev *pdev = tp->pci_dev;
5495
5496 rtl_csi_access_enable_2(tp);
5497
5498 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5499
5500 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5501 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5502 }
5503
5504 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5505 {
5506 rtl_hw_start_8102e_2(tp);
5507
5508 rtl_ephy_write(tp, 0x03, 0xc2f9);
5509 }
5510
5511 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5512 {
5513 void __iomem *ioaddr = tp->mmio_addr;
5514 static const struct ephy_info e_info_8105e_1[] = {
5515 { 0x07, 0, 0x4000 },
5516 { 0x19, 0, 0x0200 },
5517 { 0x19, 0, 0x0020 },
5518 { 0x1e, 0, 0x2000 },
5519 { 0x03, 0, 0x0001 },
5520 { 0x19, 0, 0x0100 },
5521 { 0x19, 0, 0x0004 },
5522 { 0x0a, 0, 0x0020 }
5523 };
5524
5525 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5526 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5527
5528 /* Disable Early Tally Counter */
5529 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5530
5531 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5532 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5533
5534 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5535 }
5536
5537 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5538 {
5539 rtl_hw_start_8105e_1(tp);
5540 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5541 }
5542
5543 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5544 {
5545 void __iomem *ioaddr = tp->mmio_addr;
5546 static const struct ephy_info e_info_8402[] = {
5547 { 0x19, 0xffff, 0xff64 },
5548 { 0x1e, 0, 0x4000 }
5549 };
5550
5551 rtl_csi_access_enable_2(tp);
5552
5553 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5554 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5555
5556 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5557 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5558
5559 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5560
5561 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5562
5563 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5564 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5565 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5566 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5567 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5568 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5569 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5570 }
5571
5572 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5573 {
5574 void __iomem *ioaddr = tp->mmio_addr;
5575
5576 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5577 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5578
5579 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5580 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5581 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5582 }
5583
5584 static void rtl_hw_start_8101(struct net_device *dev)
5585 {
5586 struct rtl8169_private *tp = netdev_priv(dev);
5587 void __iomem *ioaddr = tp->mmio_addr;
5588 struct pci_dev *pdev = tp->pci_dev;
5589
5590 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5591 tp->event_slow &= ~RxFIFOOver;
5592
5593 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5594 tp->mac_version == RTL_GIGA_MAC_VER_16)
5595 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5596 PCI_EXP_DEVCTL_NOSNOOP_EN);
5597
5598 RTL_W8(Cfg9346, Cfg9346_Unlock);
5599
5600 RTL_W8(MaxTxPacketSize, TxPacketMax);
5601
5602 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5603
5604 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5605 RTL_W16(CPlusCmd, tp->cp_cmd);
5606
5607 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5608
5609 rtl_set_rx_tx_config_registers(tp);
5610
5611 switch (tp->mac_version) {
5612 case RTL_GIGA_MAC_VER_07:
5613 rtl_hw_start_8102e_1(tp);
5614 break;
5615
5616 case RTL_GIGA_MAC_VER_08:
5617 rtl_hw_start_8102e_3(tp);
5618 break;
5619
5620 case RTL_GIGA_MAC_VER_09:
5621 rtl_hw_start_8102e_2(tp);
5622 break;
5623
5624 case RTL_GIGA_MAC_VER_29:
5625 rtl_hw_start_8105e_1(tp);
5626 break;
5627 case RTL_GIGA_MAC_VER_30:
5628 rtl_hw_start_8105e_2(tp);
5629 break;
5630
5631 case RTL_GIGA_MAC_VER_37:
5632 rtl_hw_start_8402(tp);
5633 break;
5634
5635 case RTL_GIGA_MAC_VER_39:
5636 rtl_hw_start_8106(tp);
5637 break;
5638 case RTL_GIGA_MAC_VER_43:
5639 rtl_hw_start_8168g_2(tp);
5640 break;
5641 }
5642
5643 RTL_W8(Cfg9346, Cfg9346_Lock);
5644
5645 RTL_W16(IntrMitigate, 0x0000);
5646
5647 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5648
5649 rtl_set_rx_mode(dev);
5650
5651 RTL_R8(IntrMask);
5652
5653 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5654 }
5655
5656 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5657 {
5658 struct rtl8169_private *tp = netdev_priv(dev);
5659
5660 if (new_mtu < ETH_ZLEN ||
5661 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5662 return -EINVAL;
5663
5664 if (new_mtu > ETH_DATA_LEN)
5665 rtl_hw_jumbo_enable(tp);
5666 else
5667 rtl_hw_jumbo_disable(tp);
5668
5669 dev->mtu = new_mtu;
5670 netdev_update_features(dev);
5671
5672 return 0;
5673 }
5674
5675 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5676 {
5677 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5678 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5679 }
5680
5681 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5682 void **data_buff, struct RxDesc *desc)
5683 {
5684 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5685 DMA_FROM_DEVICE);
5686
5687 kfree(*data_buff);
5688 *data_buff = NULL;
5689 rtl8169_make_unusable_by_asic(desc);
5690 }
5691
5692 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5693 {
5694 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5695
5696 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5697 }
5698
5699 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5700 u32 rx_buf_sz)
5701 {
5702 desc->addr = cpu_to_le64(mapping);
5703 wmb();
5704 rtl8169_mark_to_asic(desc, rx_buf_sz);
5705 }
5706
5707 static inline void *rtl8169_align(void *data)
5708 {
5709 return (void *)ALIGN((long)data, 16);
5710 }
5711
5712 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5713 struct RxDesc *desc)
5714 {
5715 void *data;
5716 dma_addr_t mapping;
5717 struct device *d = &tp->pci_dev->dev;
5718 struct net_device *dev = tp->dev;
5719 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5720
5721 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5722 if (!data)
5723 return NULL;
5724
5725 if (rtl8169_align(data) != data) {
5726 kfree(data);
5727 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5728 if (!data)
5729 return NULL;
5730 }
5731
5732 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5733 DMA_FROM_DEVICE);
5734 if (unlikely(dma_mapping_error(d, mapping))) {
5735 if (net_ratelimit())
5736 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5737 goto err_out;
5738 }
5739
5740 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5741 return data;
5742
5743 err_out:
5744 kfree(data);
5745 return NULL;
5746 }
5747
5748 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5749 {
5750 unsigned int i;
5751
5752 for (i = 0; i < NUM_RX_DESC; i++) {
5753 if (tp->Rx_databuff[i]) {
5754 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5755 tp->RxDescArray + i);
5756 }
5757 }
5758 }
5759
5760 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5761 {
5762 desc->opts1 |= cpu_to_le32(RingEnd);
5763 }
5764
5765 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5766 {
5767 unsigned int i;
5768
5769 for (i = 0; i < NUM_RX_DESC; i++) {
5770 void *data;
5771
5772 if (tp->Rx_databuff[i])
5773 continue;
5774
5775 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5776 if (!data) {
5777 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5778 goto err_out;
5779 }
5780 tp->Rx_databuff[i] = data;
5781 }
5782
5783 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5784 return 0;
5785
5786 err_out:
5787 rtl8169_rx_clear(tp);
5788 return -ENOMEM;
5789 }
5790
5791 static int rtl8169_init_ring(struct net_device *dev)
5792 {
5793 struct rtl8169_private *tp = netdev_priv(dev);
5794
5795 rtl8169_init_ring_indexes(tp);
5796
5797 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5798 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5799
5800 return rtl8169_rx_fill(tp);
5801 }
5802
5803 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5804 struct TxDesc *desc)
5805 {
5806 unsigned int len = tx_skb->len;
5807
5808 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5809
5810 desc->opts1 = 0x00;
5811 desc->opts2 = 0x00;
5812 desc->addr = 0x00;
5813 tx_skb->len = 0;
5814 }
5815
5816 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5817 unsigned int n)
5818 {
5819 unsigned int i;
5820
5821 for (i = 0; i < n; i++) {
5822 unsigned int entry = (start + i) % NUM_TX_DESC;
5823 struct ring_info *tx_skb = tp->tx_skb + entry;
5824 unsigned int len = tx_skb->len;
5825
5826 if (len) {
5827 struct sk_buff *skb = tx_skb->skb;
5828
5829 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5830 tp->TxDescArray + entry);
5831 if (skb) {
5832 tp->dev->stats.tx_dropped++;
5833 dev_kfree_skb(skb);
5834 tx_skb->skb = NULL;
5835 }
5836 }
5837 }
5838 }
5839
5840 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5841 {
5842 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5843 tp->cur_tx = tp->dirty_tx = 0;
5844 }
5845
5846 static void rtl_reset_work(struct rtl8169_private *tp)
5847 {
5848 struct net_device *dev = tp->dev;
5849 int i;
5850
5851 napi_disable(&tp->napi);
5852 netif_stop_queue(dev);
5853 synchronize_sched();
5854
5855 rtl8169_hw_reset(tp);
5856
5857 for (i = 0; i < NUM_RX_DESC; i++)
5858 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5859
5860 rtl8169_tx_clear(tp);
5861 rtl8169_init_ring_indexes(tp);
5862
5863 napi_enable(&tp->napi);
5864 rtl_hw_start(dev);
5865 netif_wake_queue(dev);
5866 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5867 }
5868
5869 static void rtl8169_tx_timeout(struct net_device *dev)
5870 {
5871 struct rtl8169_private *tp = netdev_priv(dev);
5872
5873 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5874 }
5875
5876 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5877 u32 *opts)
5878 {
5879 struct skb_shared_info *info = skb_shinfo(skb);
5880 unsigned int cur_frag, entry;
5881 struct TxDesc * uninitialized_var(txd);
5882 struct device *d = &tp->pci_dev->dev;
5883
5884 entry = tp->cur_tx;
5885 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5886 const skb_frag_t *frag = info->frags + cur_frag;
5887 dma_addr_t mapping;
5888 u32 status, len;
5889 void *addr;
5890
5891 entry = (entry + 1) % NUM_TX_DESC;
5892
5893 txd = tp->TxDescArray + entry;
5894 len = skb_frag_size(frag);
5895 addr = skb_frag_address(frag);
5896 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5897 if (unlikely(dma_mapping_error(d, mapping))) {
5898 if (net_ratelimit())
5899 netif_err(tp, drv, tp->dev,
5900 "Failed to map TX fragments DMA!\n");
5901 goto err_out;
5902 }
5903
5904 /* Anti gcc 2.95.3 bugware (sic) */
5905 status = opts[0] | len |
5906 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5907
5908 txd->opts1 = cpu_to_le32(status);
5909 txd->opts2 = cpu_to_le32(opts[1]);
5910 txd->addr = cpu_to_le64(mapping);
5911
5912 tp->tx_skb[entry].len = len;
5913 }
5914
5915 if (cur_frag) {
5916 tp->tx_skb[entry].skb = skb;
5917 txd->opts1 |= cpu_to_le32(LastFrag);
5918 }
5919
5920 return cur_frag;
5921
5922 err_out:
5923 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5924 return -EIO;
5925 }
5926
5927 static bool rtl_skb_pad(struct sk_buff *skb)
5928 {
5929 if (skb_padto(skb, ETH_ZLEN))
5930 return false;
5931 skb_put(skb, ETH_ZLEN - skb->len);
5932 return true;
5933 }
5934
5935 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5936 {
5937 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5938 }
5939
5940 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5941 struct sk_buff *skb, u32 *opts)
5942 {
5943 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5944 u32 mss = skb_shinfo(skb)->gso_size;
5945 int offset = info->opts_offset;
5946
5947 if (mss) {
5948 opts[0] |= TD_LSO;
5949 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5950 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5951 const struct iphdr *ip = ip_hdr(skb);
5952
5953 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5954 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5955
5956 if (ip->protocol == IPPROTO_TCP)
5957 opts[offset] |= info->checksum.tcp;
5958 else if (ip->protocol == IPPROTO_UDP)
5959 opts[offset] |= info->checksum.udp;
5960 else
5961 WARN_ON_ONCE(1);
5962 } else {
5963 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5964 return rtl_skb_pad(skb);
5965 }
5966 return true;
5967 }
5968
5969 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5970 struct net_device *dev)
5971 {
5972 struct rtl8169_private *tp = netdev_priv(dev);
5973 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5974 struct TxDesc *txd = tp->TxDescArray + entry;
5975 void __iomem *ioaddr = tp->mmio_addr;
5976 struct device *d = &tp->pci_dev->dev;
5977 dma_addr_t mapping;
5978 u32 status, len;
5979 u32 opts[2];
5980 int frags;
5981
5982 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5983 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5984 goto err_stop_0;
5985 }
5986
5987 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5988 goto err_stop_0;
5989
5990 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5991 opts[0] = DescOwn;
5992
5993 if (!rtl8169_tso_csum(tp, skb, opts))
5994 goto err_update_stats;
5995
5996 len = skb_headlen(skb);
5997 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5998 if (unlikely(dma_mapping_error(d, mapping))) {
5999 if (net_ratelimit())
6000 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6001 goto err_dma_0;
6002 }
6003
6004 tp->tx_skb[entry].len = len;
6005 txd->addr = cpu_to_le64(mapping);
6006
6007 frags = rtl8169_xmit_frags(tp, skb, opts);
6008 if (frags < 0)
6009 goto err_dma_1;
6010 else if (frags)
6011 opts[0] |= FirstFrag;
6012 else {
6013 opts[0] |= FirstFrag | LastFrag;
6014 tp->tx_skb[entry].skb = skb;
6015 }
6016
6017 txd->opts2 = cpu_to_le32(opts[1]);
6018
6019 skb_tx_timestamp(skb);
6020
6021 wmb();
6022
6023 /* Anti gcc 2.95.3 bugware (sic) */
6024 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6025 txd->opts1 = cpu_to_le32(status);
6026
6027 tp->cur_tx += frags + 1;
6028
6029 wmb();
6030
6031 RTL_W8(TxPoll, NPQ);
6032
6033 mmiowb();
6034
6035 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6036 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6037 * not miss a ring update when it notices a stopped queue.
6038 */
6039 smp_wmb();
6040 netif_stop_queue(dev);
6041 /* Sync with rtl_tx:
6042 * - publish queue status and cur_tx ring index (write barrier)
6043 * - refresh dirty_tx ring index (read barrier).
6044 * May the current thread have a pessimistic view of the ring
6045 * status and forget to wake up queue, a racing rtl_tx thread
6046 * can't.
6047 */
6048 smp_mb();
6049 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6050 netif_wake_queue(dev);
6051 }
6052
6053 return NETDEV_TX_OK;
6054
6055 err_dma_1:
6056 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6057 err_dma_0:
6058 dev_kfree_skb(skb);
6059 err_update_stats:
6060 dev->stats.tx_dropped++;
6061 return NETDEV_TX_OK;
6062
6063 err_stop_0:
6064 netif_stop_queue(dev);
6065 dev->stats.tx_dropped++;
6066 return NETDEV_TX_BUSY;
6067 }
6068
6069 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6070 {
6071 struct rtl8169_private *tp = netdev_priv(dev);
6072 struct pci_dev *pdev = tp->pci_dev;
6073 u16 pci_status, pci_cmd;
6074
6075 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6076 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6077
6078 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6079 pci_cmd, pci_status);
6080
6081 /*
6082 * The recovery sequence below admits a very elaborated explanation:
6083 * - it seems to work;
6084 * - I did not see what else could be done;
6085 * - it makes iop3xx happy.
6086 *
6087 * Feel free to adjust to your needs.
6088 */
6089 if (pdev->broken_parity_status)
6090 pci_cmd &= ~PCI_COMMAND_PARITY;
6091 else
6092 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6093
6094 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6095
6096 pci_write_config_word(pdev, PCI_STATUS,
6097 pci_status & (PCI_STATUS_DETECTED_PARITY |
6098 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6099 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6100
6101 /* The infamous DAC f*ckup only happens at boot time */
6102 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6103 void __iomem *ioaddr = tp->mmio_addr;
6104
6105 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6106 tp->cp_cmd &= ~PCIDAC;
6107 RTL_W16(CPlusCmd, tp->cp_cmd);
6108 dev->features &= ~NETIF_F_HIGHDMA;
6109 }
6110
6111 rtl8169_hw_reset(tp);
6112
6113 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6114 }
6115
6116 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6117 {
6118 unsigned int dirty_tx, tx_left;
6119
6120 dirty_tx = tp->dirty_tx;
6121 smp_rmb();
6122 tx_left = tp->cur_tx - dirty_tx;
6123
6124 while (tx_left > 0) {
6125 unsigned int entry = dirty_tx % NUM_TX_DESC;
6126 struct ring_info *tx_skb = tp->tx_skb + entry;
6127 u32 status;
6128
6129 rmb();
6130 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6131 if (status & DescOwn)
6132 break;
6133
6134 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6135 tp->TxDescArray + entry);
6136 if (status & LastFrag) {
6137 u64_stats_update_begin(&tp->tx_stats.syncp);
6138 tp->tx_stats.packets++;
6139 tp->tx_stats.bytes += tx_skb->skb->len;
6140 u64_stats_update_end(&tp->tx_stats.syncp);
6141 dev_kfree_skb(tx_skb->skb);
6142 tx_skb->skb = NULL;
6143 }
6144 dirty_tx++;
6145 tx_left--;
6146 }
6147
6148 if (tp->dirty_tx != dirty_tx) {
6149 tp->dirty_tx = dirty_tx;
6150 /* Sync with rtl8169_start_xmit:
6151 * - publish dirty_tx ring index (write barrier)
6152 * - refresh cur_tx ring index and queue status (read barrier)
6153 * May the current thread miss the stopped queue condition,
6154 * a racing xmit thread can only have a right view of the
6155 * ring status.
6156 */
6157 smp_mb();
6158 if (netif_queue_stopped(dev) &&
6159 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6160 netif_wake_queue(dev);
6161 }
6162 /*
6163 * 8168 hack: TxPoll requests are lost when the Tx packets are
6164 * too close. Let's kick an extra TxPoll request when a burst
6165 * of start_xmit activity is detected (if it is not detected,
6166 * it is slow enough). -- FR
6167 */
6168 if (tp->cur_tx != dirty_tx) {
6169 void __iomem *ioaddr = tp->mmio_addr;
6170
6171 RTL_W8(TxPoll, NPQ);
6172 }
6173 }
6174 }
6175
6176 static inline int rtl8169_fragmented_frame(u32 status)
6177 {
6178 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6179 }
6180
6181 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6182 {
6183 u32 status = opts1 & RxProtoMask;
6184
6185 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6186 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6187 skb->ip_summed = CHECKSUM_UNNECESSARY;
6188 else
6189 skb_checksum_none_assert(skb);
6190 }
6191
6192 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6193 struct rtl8169_private *tp,
6194 int pkt_size,
6195 dma_addr_t addr)
6196 {
6197 struct sk_buff *skb;
6198 struct device *d = &tp->pci_dev->dev;
6199
6200 data = rtl8169_align(data);
6201 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6202 prefetch(data);
6203 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6204 if (skb)
6205 memcpy(skb->data, data, pkt_size);
6206 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6207
6208 return skb;
6209 }
6210
6211 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6212 {
6213 unsigned int cur_rx, rx_left;
6214 unsigned int count;
6215
6216 cur_rx = tp->cur_rx;
6217
6218 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6219 unsigned int entry = cur_rx % NUM_RX_DESC;
6220 struct RxDesc *desc = tp->RxDescArray + entry;
6221 u32 status;
6222
6223 rmb();
6224 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6225
6226 if (status & DescOwn)
6227 break;
6228 if (unlikely(status & RxRES)) {
6229 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6230 status);
6231 dev->stats.rx_errors++;
6232 if (status & (RxRWT | RxRUNT))
6233 dev->stats.rx_length_errors++;
6234 if (status & RxCRC)
6235 dev->stats.rx_crc_errors++;
6236 if (status & RxFOVF) {
6237 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6238 dev->stats.rx_fifo_errors++;
6239 }
6240 if ((status & (RxRUNT | RxCRC)) &&
6241 !(status & (RxRWT | RxFOVF)) &&
6242 (dev->features & NETIF_F_RXALL))
6243 goto process_pkt;
6244 } else {
6245 struct sk_buff *skb;
6246 dma_addr_t addr;
6247 int pkt_size;
6248
6249 process_pkt:
6250 addr = le64_to_cpu(desc->addr);
6251 if (likely(!(dev->features & NETIF_F_RXFCS)))
6252 pkt_size = (status & 0x00003fff) - 4;
6253 else
6254 pkt_size = status & 0x00003fff;
6255
6256 /*
6257 * The driver does not support incoming fragmented
6258 * frames. They are seen as a symptom of over-mtu
6259 * sized frames.
6260 */
6261 if (unlikely(rtl8169_fragmented_frame(status))) {
6262 dev->stats.rx_dropped++;
6263 dev->stats.rx_length_errors++;
6264 goto release_descriptor;
6265 }
6266
6267 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6268 tp, pkt_size, addr);
6269 if (!skb) {
6270 dev->stats.rx_dropped++;
6271 goto release_descriptor;
6272 }
6273
6274 rtl8169_rx_csum(skb, status);
6275 skb_put(skb, pkt_size);
6276 skb->protocol = eth_type_trans(skb, dev);
6277
6278 rtl8169_rx_vlan_tag(desc, skb);
6279
6280 napi_gro_receive(&tp->napi, skb);
6281
6282 u64_stats_update_begin(&tp->rx_stats.syncp);
6283 tp->rx_stats.packets++;
6284 tp->rx_stats.bytes += pkt_size;
6285 u64_stats_update_end(&tp->rx_stats.syncp);
6286 }
6287 release_descriptor:
6288 desc->opts2 = 0;
6289 wmb();
6290 rtl8169_mark_to_asic(desc, rx_buf_sz);
6291 }
6292
6293 count = cur_rx - tp->cur_rx;
6294 tp->cur_rx = cur_rx;
6295
6296 return count;
6297 }
6298
6299 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6300 {
6301 struct net_device *dev = dev_instance;
6302 struct rtl8169_private *tp = netdev_priv(dev);
6303 int handled = 0;
6304 u16 status;
6305
6306 status = rtl_get_events(tp);
6307 if (status && status != 0xffff) {
6308 status &= RTL_EVENT_NAPI | tp->event_slow;
6309 if (status) {
6310 handled = 1;
6311
6312 rtl_irq_disable(tp);
6313 napi_schedule(&tp->napi);
6314 }
6315 }
6316 return IRQ_RETVAL(handled);
6317 }
6318
6319 /*
6320 * Workqueue context.
6321 */
6322 static void rtl_slow_event_work(struct rtl8169_private *tp)
6323 {
6324 struct net_device *dev = tp->dev;
6325 u16 status;
6326
6327 status = rtl_get_events(tp) & tp->event_slow;
6328 rtl_ack_events(tp, status);
6329
6330 if (unlikely(status & RxFIFOOver)) {
6331 switch (tp->mac_version) {
6332 /* Work around for rx fifo overflow */
6333 case RTL_GIGA_MAC_VER_11:
6334 netif_stop_queue(dev);
6335 /* XXX - Hack alert. See rtl_task(). */
6336 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6337 default:
6338 break;
6339 }
6340 }
6341
6342 if (unlikely(status & SYSErr))
6343 rtl8169_pcierr_interrupt(dev);
6344
6345 if (status & LinkChg)
6346 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6347
6348 rtl_irq_enable_all(tp);
6349 }
6350
6351 static void rtl_task(struct work_struct *work)
6352 {
6353 static const struct {
6354 int bitnr;
6355 void (*action)(struct rtl8169_private *);
6356 } rtl_work[] = {
6357 /* XXX - keep rtl_slow_event_work() as first element. */
6358 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6359 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6360 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6361 };
6362 struct rtl8169_private *tp =
6363 container_of(work, struct rtl8169_private, wk.work);
6364 struct net_device *dev = tp->dev;
6365 int i;
6366
6367 rtl_lock_work(tp);
6368
6369 if (!netif_running(dev) ||
6370 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6371 goto out_unlock;
6372
6373 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6374 bool pending;
6375
6376 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6377 if (pending)
6378 rtl_work[i].action(tp);
6379 }
6380
6381 out_unlock:
6382 rtl_unlock_work(tp);
6383 }
6384
6385 static int rtl8169_poll(struct napi_struct *napi, int budget)
6386 {
6387 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6388 struct net_device *dev = tp->dev;
6389 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6390 int work_done= 0;
6391 u16 status;
6392
6393 status = rtl_get_events(tp);
6394 rtl_ack_events(tp, status & ~tp->event_slow);
6395
6396 if (status & RTL_EVENT_NAPI_RX)
6397 work_done = rtl_rx(dev, tp, (u32) budget);
6398
6399 if (status & RTL_EVENT_NAPI_TX)
6400 rtl_tx(dev, tp);
6401
6402 if (status & tp->event_slow) {
6403 enable_mask &= ~tp->event_slow;
6404
6405 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6406 }
6407
6408 if (work_done < budget) {
6409 napi_complete(napi);
6410
6411 rtl_irq_enable(tp, enable_mask);
6412 mmiowb();
6413 }
6414
6415 return work_done;
6416 }
6417
6418 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6419 {
6420 struct rtl8169_private *tp = netdev_priv(dev);
6421
6422 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6423 return;
6424
6425 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6426 RTL_W32(RxMissed, 0);
6427 }
6428
6429 static void rtl8169_down(struct net_device *dev)
6430 {
6431 struct rtl8169_private *tp = netdev_priv(dev);
6432 void __iomem *ioaddr = tp->mmio_addr;
6433
6434 del_timer_sync(&tp->timer);
6435
6436 napi_disable(&tp->napi);
6437 netif_stop_queue(dev);
6438
6439 rtl8169_hw_reset(tp);
6440 /*
6441 * At this point device interrupts can not be enabled in any function,
6442 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6443 * and napi is disabled (rtl8169_poll).
6444 */
6445 rtl8169_rx_missed(dev, ioaddr);
6446
6447 /* Give a racing hard_start_xmit a few cycles to complete. */
6448 synchronize_sched();
6449
6450 rtl8169_tx_clear(tp);
6451
6452 rtl8169_rx_clear(tp);
6453
6454 rtl_pll_power_down(tp);
6455 }
6456
6457 static int rtl8169_close(struct net_device *dev)
6458 {
6459 struct rtl8169_private *tp = netdev_priv(dev);
6460 struct pci_dev *pdev = tp->pci_dev;
6461
6462 pm_runtime_get_sync(&pdev->dev);
6463
6464 /* Update counters before going down */
6465 rtl8169_update_counters(dev);
6466
6467 rtl_lock_work(tp);
6468 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6469
6470 rtl8169_down(dev);
6471 rtl_unlock_work(tp);
6472
6473 cancel_work_sync(&tp->wk.work);
6474
6475 free_irq(pdev->irq, dev);
6476
6477 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6478 tp->RxPhyAddr);
6479 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6480 tp->TxPhyAddr);
6481 tp->TxDescArray = NULL;
6482 tp->RxDescArray = NULL;
6483
6484 pm_runtime_put_sync(&pdev->dev);
6485
6486 return 0;
6487 }
6488
6489 #ifdef CONFIG_NET_POLL_CONTROLLER
6490 static void rtl8169_netpoll(struct net_device *dev)
6491 {
6492 struct rtl8169_private *tp = netdev_priv(dev);
6493
6494 rtl8169_interrupt(tp->pci_dev->irq, dev);
6495 }
6496 #endif
6497
6498 static int rtl_open(struct net_device *dev)
6499 {
6500 struct rtl8169_private *tp = netdev_priv(dev);
6501 void __iomem *ioaddr = tp->mmio_addr;
6502 struct pci_dev *pdev = tp->pci_dev;
6503 int retval = -ENOMEM;
6504
6505 pm_runtime_get_sync(&pdev->dev);
6506
6507 /*
6508 * Rx and Tx descriptors needs 256 bytes alignment.
6509 * dma_alloc_coherent provides more.
6510 */
6511 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6512 &tp->TxPhyAddr, GFP_KERNEL);
6513 if (!tp->TxDescArray)
6514 goto err_pm_runtime_put;
6515
6516 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6517 &tp->RxPhyAddr, GFP_KERNEL);
6518 if (!tp->RxDescArray)
6519 goto err_free_tx_0;
6520
6521 retval = rtl8169_init_ring(dev);
6522 if (retval < 0)
6523 goto err_free_rx_1;
6524
6525 INIT_WORK(&tp->wk.work, rtl_task);
6526
6527 smp_mb();
6528
6529 rtl_request_firmware(tp);
6530
6531 retval = request_irq(pdev->irq, rtl8169_interrupt,
6532 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6533 dev->name, dev);
6534 if (retval < 0)
6535 goto err_release_fw_2;
6536
6537 rtl_lock_work(tp);
6538
6539 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6540
6541 napi_enable(&tp->napi);
6542
6543 rtl8169_init_phy(dev, tp);
6544
6545 __rtl8169_set_features(dev, dev->features);
6546
6547 rtl_pll_power_up(tp);
6548
6549 rtl_hw_start(dev);
6550
6551 netif_start_queue(dev);
6552
6553 rtl_unlock_work(tp);
6554
6555 tp->saved_wolopts = 0;
6556 pm_runtime_put_noidle(&pdev->dev);
6557
6558 rtl8169_check_link_status(dev, tp, ioaddr);
6559 out:
6560 return retval;
6561
6562 err_release_fw_2:
6563 rtl_release_firmware(tp);
6564 rtl8169_rx_clear(tp);
6565 err_free_rx_1:
6566 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6567 tp->RxPhyAddr);
6568 tp->RxDescArray = NULL;
6569 err_free_tx_0:
6570 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6571 tp->TxPhyAddr);
6572 tp->TxDescArray = NULL;
6573 err_pm_runtime_put:
6574 pm_runtime_put_noidle(&pdev->dev);
6575 goto out;
6576 }
6577
6578 static struct rtnl_link_stats64 *
6579 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6580 {
6581 struct rtl8169_private *tp = netdev_priv(dev);
6582 void __iomem *ioaddr = tp->mmio_addr;
6583 unsigned int start;
6584
6585 if (netif_running(dev))
6586 rtl8169_rx_missed(dev, ioaddr);
6587
6588 do {
6589 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6590 stats->rx_packets = tp->rx_stats.packets;
6591 stats->rx_bytes = tp->rx_stats.bytes;
6592 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6593
6594
6595 do {
6596 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6597 stats->tx_packets = tp->tx_stats.packets;
6598 stats->tx_bytes = tp->tx_stats.bytes;
6599 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6600
6601 stats->rx_dropped = dev->stats.rx_dropped;
6602 stats->tx_dropped = dev->stats.tx_dropped;
6603 stats->rx_length_errors = dev->stats.rx_length_errors;
6604 stats->rx_errors = dev->stats.rx_errors;
6605 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6606 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6607 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6608
6609 return stats;
6610 }
6611
6612 static void rtl8169_net_suspend(struct net_device *dev)
6613 {
6614 struct rtl8169_private *tp = netdev_priv(dev);
6615
6616 if (!netif_running(dev))
6617 return;
6618
6619 netif_device_detach(dev);
6620 netif_stop_queue(dev);
6621
6622 rtl_lock_work(tp);
6623 napi_disable(&tp->napi);
6624 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6625 rtl_unlock_work(tp);
6626
6627 rtl_pll_power_down(tp);
6628 }
6629
6630 #ifdef CONFIG_PM
6631
6632 static int rtl8169_suspend(struct device *device)
6633 {
6634 struct pci_dev *pdev = to_pci_dev(device);
6635 struct net_device *dev = pci_get_drvdata(pdev);
6636
6637 rtl8169_net_suspend(dev);
6638
6639 return 0;
6640 }
6641
6642 static void __rtl8169_resume(struct net_device *dev)
6643 {
6644 struct rtl8169_private *tp = netdev_priv(dev);
6645
6646 netif_device_attach(dev);
6647
6648 rtl_pll_power_up(tp);
6649
6650 rtl_lock_work(tp);
6651 napi_enable(&tp->napi);
6652 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6653 rtl_unlock_work(tp);
6654
6655 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6656 }
6657
6658 static int rtl8169_resume(struct device *device)
6659 {
6660 struct pci_dev *pdev = to_pci_dev(device);
6661 struct net_device *dev = pci_get_drvdata(pdev);
6662 struct rtl8169_private *tp = netdev_priv(dev);
6663
6664 rtl8169_init_phy(dev, tp);
6665
6666 if (netif_running(dev))
6667 __rtl8169_resume(dev);
6668
6669 return 0;
6670 }
6671
6672 static int rtl8169_runtime_suspend(struct device *device)
6673 {
6674 struct pci_dev *pdev = to_pci_dev(device);
6675 struct net_device *dev = pci_get_drvdata(pdev);
6676 struct rtl8169_private *tp = netdev_priv(dev);
6677
6678 if (!tp->TxDescArray)
6679 return 0;
6680
6681 rtl_lock_work(tp);
6682 tp->saved_wolopts = __rtl8169_get_wol(tp);
6683 __rtl8169_set_wol(tp, WAKE_ANY);
6684 rtl_unlock_work(tp);
6685
6686 rtl8169_net_suspend(dev);
6687
6688 return 0;
6689 }
6690
6691 static int rtl8169_runtime_resume(struct device *device)
6692 {
6693 struct pci_dev *pdev = to_pci_dev(device);
6694 struct net_device *dev = pci_get_drvdata(pdev);
6695 struct rtl8169_private *tp = netdev_priv(dev);
6696
6697 if (!tp->TxDescArray)
6698 return 0;
6699
6700 rtl_lock_work(tp);
6701 __rtl8169_set_wol(tp, tp->saved_wolopts);
6702 tp->saved_wolopts = 0;
6703 rtl_unlock_work(tp);
6704
6705 rtl8169_init_phy(dev, tp);
6706
6707 __rtl8169_resume(dev);
6708
6709 return 0;
6710 }
6711
6712 static int rtl8169_runtime_idle(struct device *device)
6713 {
6714 struct pci_dev *pdev = to_pci_dev(device);
6715 struct net_device *dev = pci_get_drvdata(pdev);
6716 struct rtl8169_private *tp = netdev_priv(dev);
6717
6718 return tp->TxDescArray ? -EBUSY : 0;
6719 }
6720
6721 static const struct dev_pm_ops rtl8169_pm_ops = {
6722 .suspend = rtl8169_suspend,
6723 .resume = rtl8169_resume,
6724 .freeze = rtl8169_suspend,
6725 .thaw = rtl8169_resume,
6726 .poweroff = rtl8169_suspend,
6727 .restore = rtl8169_resume,
6728 .runtime_suspend = rtl8169_runtime_suspend,
6729 .runtime_resume = rtl8169_runtime_resume,
6730 .runtime_idle = rtl8169_runtime_idle,
6731 };
6732
6733 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6734
6735 #else /* !CONFIG_PM */
6736
6737 #define RTL8169_PM_OPS NULL
6738
6739 #endif /* !CONFIG_PM */
6740
6741 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6742 {
6743 void __iomem *ioaddr = tp->mmio_addr;
6744
6745 /* WoL fails with 8168b when the receiver is disabled. */
6746 switch (tp->mac_version) {
6747 case RTL_GIGA_MAC_VER_11:
6748 case RTL_GIGA_MAC_VER_12:
6749 case RTL_GIGA_MAC_VER_17:
6750 pci_clear_master(tp->pci_dev);
6751
6752 RTL_W8(ChipCmd, CmdRxEnb);
6753 /* PCI commit */
6754 RTL_R8(ChipCmd);
6755 break;
6756 default:
6757 break;
6758 }
6759 }
6760
6761 static void rtl_shutdown(struct pci_dev *pdev)
6762 {
6763 struct net_device *dev = pci_get_drvdata(pdev);
6764 struct rtl8169_private *tp = netdev_priv(dev);
6765 struct device *d = &pdev->dev;
6766
6767 pm_runtime_get_sync(d);
6768
6769 rtl8169_net_suspend(dev);
6770
6771 /* Restore original MAC address */
6772 rtl_rar_set(tp, dev->perm_addr);
6773
6774 rtl8169_hw_reset(tp);
6775
6776 if (system_state == SYSTEM_POWER_OFF) {
6777 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6778 rtl_wol_suspend_quirk(tp);
6779 rtl_wol_shutdown_quirk(tp);
6780 }
6781
6782 pci_wake_from_d3(pdev, true);
6783 pci_set_power_state(pdev, PCI_D3hot);
6784 }
6785
6786 pm_runtime_put_noidle(d);
6787 }
6788
6789 static void rtl_remove_one(struct pci_dev *pdev)
6790 {
6791 struct net_device *dev = pci_get_drvdata(pdev);
6792 struct rtl8169_private *tp = netdev_priv(dev);
6793
6794 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6795 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6796 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6797 rtl8168_driver_stop(tp);
6798 }
6799
6800 netif_napi_del(&tp->napi);
6801
6802 unregister_netdev(dev);
6803
6804 rtl_release_firmware(tp);
6805
6806 if (pci_dev_run_wake(pdev))
6807 pm_runtime_get_noresume(&pdev->dev);
6808
6809 /* restore original MAC address */
6810 rtl_rar_set(tp, dev->perm_addr);
6811
6812 rtl_disable_msi(pdev, tp);
6813 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6814 }
6815
6816 static const struct net_device_ops rtl_netdev_ops = {
6817 .ndo_open = rtl_open,
6818 .ndo_stop = rtl8169_close,
6819 .ndo_get_stats64 = rtl8169_get_stats64,
6820 .ndo_start_xmit = rtl8169_start_xmit,
6821 .ndo_tx_timeout = rtl8169_tx_timeout,
6822 .ndo_validate_addr = eth_validate_addr,
6823 .ndo_change_mtu = rtl8169_change_mtu,
6824 .ndo_fix_features = rtl8169_fix_features,
6825 .ndo_set_features = rtl8169_set_features,
6826 .ndo_set_mac_address = rtl_set_mac_address,
6827 .ndo_do_ioctl = rtl8169_ioctl,
6828 .ndo_set_rx_mode = rtl_set_rx_mode,
6829 #ifdef CONFIG_NET_POLL_CONTROLLER
6830 .ndo_poll_controller = rtl8169_netpoll,
6831 #endif
6832
6833 };
6834
6835 static const struct rtl_cfg_info {
6836 void (*hw_start)(struct net_device *);
6837 unsigned int region;
6838 unsigned int align;
6839 u16 event_slow;
6840 unsigned features;
6841 u8 default_ver;
6842 } rtl_cfg_infos [] = {
6843 [RTL_CFG_0] = {
6844 .hw_start = rtl_hw_start_8169,
6845 .region = 1,
6846 .align = 0,
6847 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6848 .features = RTL_FEATURE_GMII,
6849 .default_ver = RTL_GIGA_MAC_VER_01,
6850 },
6851 [RTL_CFG_1] = {
6852 .hw_start = rtl_hw_start_8168,
6853 .region = 2,
6854 .align = 8,
6855 .event_slow = SYSErr | LinkChg | RxOverflow,
6856 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6857 .default_ver = RTL_GIGA_MAC_VER_11,
6858 },
6859 [RTL_CFG_2] = {
6860 .hw_start = rtl_hw_start_8101,
6861 .region = 2,
6862 .align = 8,
6863 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6864 PCSTimeout,
6865 .features = RTL_FEATURE_MSI,
6866 .default_ver = RTL_GIGA_MAC_VER_13,
6867 }
6868 };
6869
6870 /* Cfg9346_Unlock assumed. */
6871 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6872 const struct rtl_cfg_info *cfg)
6873 {
6874 void __iomem *ioaddr = tp->mmio_addr;
6875 unsigned msi = 0;
6876 u8 cfg2;
6877
6878 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6879 if (cfg->features & RTL_FEATURE_MSI) {
6880 if (pci_enable_msi(tp->pci_dev)) {
6881 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6882 } else {
6883 cfg2 |= MSIEnable;
6884 msi = RTL_FEATURE_MSI;
6885 }
6886 }
6887 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6888 RTL_W8(Config2, cfg2);
6889 return msi;
6890 }
6891
6892 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6893 {
6894 void __iomem *ioaddr = tp->mmio_addr;
6895
6896 return RTL_R8(MCU) & LINK_LIST_RDY;
6897 }
6898
6899 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6900 {
6901 void __iomem *ioaddr = tp->mmio_addr;
6902
6903 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6904 }
6905
6906 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6907 {
6908 void __iomem *ioaddr = tp->mmio_addr;
6909 u32 data;
6910
6911 tp->ocp_base = OCP_STD_PHY_BASE;
6912
6913 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6914
6915 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6916 return;
6917
6918 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6919 return;
6920
6921 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6922 msleep(1);
6923 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6924
6925 data = r8168_mac_ocp_read(tp, 0xe8de);
6926 data &= ~(1 << 14);
6927 r8168_mac_ocp_write(tp, 0xe8de, data);
6928
6929 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6930 return;
6931
6932 data = r8168_mac_ocp_read(tp, 0xe8de);
6933 data |= (1 << 15);
6934 r8168_mac_ocp_write(tp, 0xe8de, data);
6935
6936 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6937 return;
6938 }
6939
6940 static void rtl_hw_initialize(struct rtl8169_private *tp)
6941 {
6942 switch (tp->mac_version) {
6943 case RTL_GIGA_MAC_VER_40:
6944 case RTL_GIGA_MAC_VER_41:
6945 case RTL_GIGA_MAC_VER_42:
6946 case RTL_GIGA_MAC_VER_43:
6947 case RTL_GIGA_MAC_VER_44:
6948 rtl_hw_init_8168g(tp);
6949 break;
6950
6951 default:
6952 break;
6953 }
6954 }
6955
6956 static int
6957 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6958 {
6959 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6960 const unsigned int region = cfg->region;
6961 struct rtl8169_private *tp;
6962 struct mii_if_info *mii;
6963 struct net_device *dev;
6964 void __iomem *ioaddr;
6965 int chipset, i;
6966 int rc;
6967
6968 if (netif_msg_drv(&debug)) {
6969 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6970 MODULENAME, RTL8169_VERSION);
6971 }
6972
6973 dev = alloc_etherdev(sizeof (*tp));
6974 if (!dev) {
6975 rc = -ENOMEM;
6976 goto out;
6977 }
6978
6979 SET_NETDEV_DEV(dev, &pdev->dev);
6980 dev->netdev_ops = &rtl_netdev_ops;
6981 tp = netdev_priv(dev);
6982 tp->dev = dev;
6983 tp->pci_dev = pdev;
6984 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6985
6986 mii = &tp->mii;
6987 mii->dev = dev;
6988 mii->mdio_read = rtl_mdio_read;
6989 mii->mdio_write = rtl_mdio_write;
6990 mii->phy_id_mask = 0x1f;
6991 mii->reg_num_mask = 0x1f;
6992 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6993
6994 /* disable ASPM completely as that cause random device stop working
6995 * problems as well as full system hangs for some PCIe devices users */
6996 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6997 PCIE_LINK_STATE_CLKPM);
6998
6999 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7000 rc = pci_enable_device(pdev);
7001 if (rc < 0) {
7002 netif_err(tp, probe, dev, "enable failure\n");
7003 goto err_out_free_dev_1;
7004 }
7005
7006 if (pci_set_mwi(pdev) < 0)
7007 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7008
7009 /* make sure PCI base addr 1 is MMIO */
7010 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7011 netif_err(tp, probe, dev,
7012 "region #%d not an MMIO resource, aborting\n",
7013 region);
7014 rc = -ENODEV;
7015 goto err_out_mwi_2;
7016 }
7017
7018 /* check for weird/broken PCI region reporting */
7019 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7020 netif_err(tp, probe, dev,
7021 "Invalid PCI region size(s), aborting\n");
7022 rc = -ENODEV;
7023 goto err_out_mwi_2;
7024 }
7025
7026 rc = pci_request_regions(pdev, MODULENAME);
7027 if (rc < 0) {
7028 netif_err(tp, probe, dev, "could not request regions\n");
7029 goto err_out_mwi_2;
7030 }
7031
7032 tp->cp_cmd = RxChkSum;
7033
7034 if ((sizeof(dma_addr_t) > 4) &&
7035 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7036 tp->cp_cmd |= PCIDAC;
7037 dev->features |= NETIF_F_HIGHDMA;
7038 } else {
7039 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7040 if (rc < 0) {
7041 netif_err(tp, probe, dev, "DMA configuration failed\n");
7042 goto err_out_free_res_3;
7043 }
7044 }
7045
7046 /* ioremap MMIO region */
7047 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7048 if (!ioaddr) {
7049 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7050 rc = -EIO;
7051 goto err_out_free_res_3;
7052 }
7053 tp->mmio_addr = ioaddr;
7054
7055 if (!pci_is_pcie(pdev))
7056 netif_info(tp, probe, dev, "not PCI Express\n");
7057
7058 /* Identify chip attached to board */
7059 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7060
7061 rtl_init_rxcfg(tp);
7062
7063 rtl_irq_disable(tp);
7064
7065 rtl_hw_initialize(tp);
7066
7067 rtl_hw_reset(tp);
7068
7069 rtl_ack_events(tp, 0xffff);
7070
7071 pci_set_master(pdev);
7072
7073 /*
7074 * Pretend we are using VLANs; This bypasses a nasty bug where
7075 * Interrupts stop flowing on high load on 8110SCd controllers.
7076 */
7077 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7078 tp->cp_cmd |= RxVlan;
7079
7080 rtl_init_mdio_ops(tp);
7081 rtl_init_pll_power_ops(tp);
7082 rtl_init_jumbo_ops(tp);
7083 rtl_init_csi_ops(tp);
7084
7085 rtl8169_print_mac_version(tp);
7086
7087 chipset = tp->mac_version;
7088 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7089
7090 RTL_W8(Cfg9346, Cfg9346_Unlock);
7091 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7092 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7093 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7094 tp->features |= RTL_FEATURE_WOL;
7095 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7096 tp->features |= RTL_FEATURE_WOL;
7097 tp->features |= rtl_try_msi(tp, cfg);
7098 RTL_W8(Cfg9346, Cfg9346_Lock);
7099
7100 if (rtl_tbi_enabled(tp)) {
7101 tp->set_speed = rtl8169_set_speed_tbi;
7102 tp->get_settings = rtl8169_gset_tbi;
7103 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7104 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7105 tp->link_ok = rtl8169_tbi_link_ok;
7106 tp->do_ioctl = rtl_tbi_ioctl;
7107 } else {
7108 tp->set_speed = rtl8169_set_speed_xmii;
7109 tp->get_settings = rtl8169_gset_xmii;
7110 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7111 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7112 tp->link_ok = rtl8169_xmii_link_ok;
7113 tp->do_ioctl = rtl_xmii_ioctl;
7114 }
7115
7116 mutex_init(&tp->wk.mutex);
7117
7118 /* Get MAC address */
7119 for (i = 0; i < ETH_ALEN; i++)
7120 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7121
7122 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7123 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7124
7125 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7126
7127 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7128 * properly for all devices */
7129 dev->features |= NETIF_F_RXCSUM |
7130 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7131
7132 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7133 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7134 NETIF_F_HW_VLAN_CTAG_RX;
7135 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7136 NETIF_F_HIGHDMA;
7137
7138 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7139 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7140 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7141
7142 dev->hw_features |= NETIF_F_RXALL;
7143 dev->hw_features |= NETIF_F_RXFCS;
7144
7145 tp->hw_start = cfg->hw_start;
7146 tp->event_slow = cfg->event_slow;
7147
7148 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7149 ~(RxBOVF | RxFOVF) : ~0;
7150
7151 init_timer(&tp->timer);
7152 tp->timer.data = (unsigned long) dev;
7153 tp->timer.function = rtl8169_phy_timer;
7154
7155 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7156
7157 rc = register_netdev(dev);
7158 if (rc < 0)
7159 goto err_out_msi_4;
7160
7161 pci_set_drvdata(pdev, dev);
7162
7163 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7164 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7165 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7166 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7167 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7168 "tx checksumming: %s]\n",
7169 rtl_chip_infos[chipset].jumbo_max,
7170 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7171 }
7172
7173 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7174 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7175 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7176 rtl8168_driver_start(tp);
7177 }
7178
7179 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7180
7181 if (pci_dev_run_wake(pdev))
7182 pm_runtime_put_noidle(&pdev->dev);
7183
7184 netif_carrier_off(dev);
7185
7186 out:
7187 return rc;
7188
7189 err_out_msi_4:
7190 netif_napi_del(&tp->napi);
7191 rtl_disable_msi(pdev, tp);
7192 iounmap(ioaddr);
7193 err_out_free_res_3:
7194 pci_release_regions(pdev);
7195 err_out_mwi_2:
7196 pci_clear_mwi(pdev);
7197 pci_disable_device(pdev);
7198 err_out_free_dev_1:
7199 free_netdev(dev);
7200 goto out;
7201 }
7202
7203 static struct pci_driver rtl8169_pci_driver = {
7204 .name = MODULENAME,
7205 .id_table = rtl8169_pci_tbl,
7206 .probe = rtl_init_one,
7207 .remove = rtl_remove_one,
7208 .shutdown = rtl_shutdown,
7209 .driver.pm = RTL8169_PM_OPS,
7210 };
7211
7212 module_pci_driver(rtl8169_pci_driver);
Linux with added FPC-III support