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Linux 4.2.1
[linux/fpc-iii.git] / drivers / bus / arm-ccn.c
blob7d9879e166cf4c4346402cb353ef3cd002483740
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2014 ARM Limited
12 */
13
14 #include <linux/ctype.h>
15 #include <linux/hrtimer.h>
16 #include <linux/idr.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define CCN_NUM_XP_PORTS 2
25 #define CCN_NUM_VCS 4
26 #define CCN_NUM_REGIONS 256
27 #define CCN_REGION_SIZE 0x10000
28
29 #define CCN_ALL_OLY_ID 0xff00
30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
34
35 #define CCN_MN_ERRINT_STATUS 0x0008
36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
49
50 #define CCN_DT_ACTIVE_DSM 0x0000
51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
53 #define CCN_DT_CTL 0x0028
54 #define CCN_DT_CTL__DT_EN (1 << 0)
55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
56 #define CCN_DT_PMCCNTR 0x0140
57 #define CCN_DT_PMCCNTRSR 0x0190
58 #define CCN_DT_PMOVSR 0x0198
59 #define CCN_DT_PMOVSR_CLR 0x01a0
60 #define CCN_DT_PMOVSR_CLR__MASK 0x1f
61 #define CCN_DT_PMCR 0x01a8
62 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
63 #define CCN_DT_PMCR__PMU_EN (1 << 0)
64 #define CCN_DT_PMSR 0x01b0
65 #define CCN_DT_PMSR_REQ 0x01b8
66 #define CCN_DT_PMSR_CLR 0x01c0
67
68 #define CCN_HNF_PMU_EVENT_SEL 0x0600
69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
71
72 #define CCN_XP_DT_CONFIG 0x0300
73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
80 #define CCN_XP_DT_INTERFACE_SEL 0x0308
81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
87 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
88 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
89 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
90 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
91 #define CCN_XP_DT_CONTROL 0x0370
92 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
96 #define CCN_XP_PMU_EVENT_SEL 0x0600
97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
99
100 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
103
104 #define CCN_RNI_PMU_EVENT_SEL 0x0600
105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
107
108 #define CCN_TYPE_MN 0x01
109 #define CCN_TYPE_DT 0x02
110 #define CCN_TYPE_HNF 0x04
111 #define CCN_TYPE_HNI 0x05
112 #define CCN_TYPE_XP 0x08
113 #define CCN_TYPE_SBSX 0x0c
114 #define CCN_TYPE_SBAS 0x10
115 #define CCN_TYPE_RNI_1P 0x14
116 #define CCN_TYPE_RNI_2P 0x15
117 #define CCN_TYPE_RNI_3P 0x16
118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
119 #define CCN_TYPE_RND_2P 0x19
120 #define CCN_TYPE_RND_3P 0x1a
121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
122
123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
124
125 #define CCN_NUM_PMU_EVENTS 4
126 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
127 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
128 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
129
130 #define CCN_NUM_PREDEFINED_MASKS 4
131 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
132 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
133 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
134 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
135
136 struct arm_ccn_component {
137 void __iomem *base;
138 u32 type;
139
140 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
141 union {
142 struct {
143 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
144 } xp;
145 };
146 };
147
148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
149 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
150
151 struct arm_ccn_dt {
152 int id;
153 void __iomem *base;
154
155 spinlock_t config_lock;
156
157 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
158 struct {
159 struct arm_ccn_component *source;
160 struct perf_event *event;
161 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
162
163 struct {
164 u64 l, h;
165 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
166
167 struct hrtimer hrtimer;
168
169 cpumask_t cpu;
170 struct notifier_block cpu_nb;
171
172 struct pmu pmu;
173 };
174
175 struct arm_ccn {
176 struct device *dev;
177 void __iomem *base;
178 unsigned int irq;
179
180 unsigned sbas_present:1;
181 unsigned sbsx_present:1;
182
183 int num_nodes;
184 struct arm_ccn_component *node;
185
186 int num_xps;
187 struct arm_ccn_component *xp;
188
189 struct arm_ccn_dt dt;
190 };
191
192
193 static int arm_ccn_node_to_xp(int node)
194 {
195 return node / CCN_NUM_XP_PORTS;
196 }
197
198 static int arm_ccn_node_to_xp_port(int node)
199 {
200 return node % CCN_NUM_XP_PORTS;
201 }
202
203
204 /*
205 * Bit shifts and masks in these defines must be kept in sync with
206 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
207 */
208 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
209 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
210 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
211 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
212 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
213 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
214 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
215 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
216
217 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
218 {
219 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
220 *config |= (node_xp << 0) | (type << 8) | (port << 24);
221 }
222
223 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
224 struct device_attribute *attr, char *buf)
225 {
226 struct dev_ext_attribute *ea = container_of(attr,
227 struct dev_ext_attribute, attr);
228
229 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
230 }
231
232 #define CCN_FORMAT_ATTR(_name, _config) \
233 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
234 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
235 NULL), _config }
236
237 static CCN_FORMAT_ATTR(node, "config:0-7");
238 static CCN_FORMAT_ATTR(xp, "config:0-7");
239 static CCN_FORMAT_ATTR(type, "config:8-15");
240 static CCN_FORMAT_ATTR(event, "config:16-23");
241 static CCN_FORMAT_ATTR(port, "config:24-25");
242 static CCN_FORMAT_ATTR(vc, "config:26-28");
243 static CCN_FORMAT_ATTR(dir, "config:29-29");
244 static CCN_FORMAT_ATTR(mask, "config:30-33");
245 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
246 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
247
248 static struct attribute *arm_ccn_pmu_format_attrs[] = {
249 &arm_ccn_pmu_format_attr_node.attr.attr,
250 &arm_ccn_pmu_format_attr_xp.attr.attr,
251 &arm_ccn_pmu_format_attr_type.attr.attr,
252 &arm_ccn_pmu_format_attr_event.attr.attr,
253 &arm_ccn_pmu_format_attr_port.attr.attr,
254 &arm_ccn_pmu_format_attr_vc.attr.attr,
255 &arm_ccn_pmu_format_attr_dir.attr.attr,
256 &arm_ccn_pmu_format_attr_mask.attr.attr,
257 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
258 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
259 NULL
260 };
261
262 static struct attribute_group arm_ccn_pmu_format_attr_group = {
263 .name = "format",
264 .attrs = arm_ccn_pmu_format_attrs,
265 };
266
267
268 struct arm_ccn_pmu_event {
269 struct device_attribute attr;
270 u32 type;
271 u32 event;
272 int num_ports;
273 int num_vcs;
274 const char *def;
275 int mask;
276 };
277
278 #define CCN_EVENT_ATTR(_name) \
279 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
280
281 /*
282 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
283 * their ports in XP they are connected to. For the sake of usability they are
284 * explicitly defined here (and translated into a relevant watchpoint in
285 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
286 * knowledge of the flit format.
287 */
288
289 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
290 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
291 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
292 .def = _def, .mask = _mask, }
293
294 #define CCN_EVENT_HNI(_name, _def, _mask) { \
295 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
296 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
297 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
298
299 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
300 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
301 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
302 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
303
304 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
305 .type = CCN_TYPE_HNF, .event = _event, }
306
307 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
308 .type = CCN_TYPE_XP, .event = _event, \
309 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
310
311 /*
312 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
313 * on configuration. One of them is picked to represent the whole group,
314 * as they all share the same event types.
315 */
316 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
317 .type = CCN_TYPE_RNI_3P, .event = _event, }
318
319 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
320 .type = CCN_TYPE_SBAS, .event = _event, }
321
322 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
323 .type = CCN_TYPE_CYCLES }
324
325
326 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
327 struct device_attribute *attr, char *buf)
328 {
329 struct arm_ccn_pmu_event *event = container_of(attr,
330 struct arm_ccn_pmu_event, attr);
331 ssize_t res;
332
333 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
334 if (event->event)
335 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
336 event->event);
337 if (event->def)
338 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
339 event->def);
340 if (event->mask)
341 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
342 event->mask);
343
344 /* Arguments required by an event */
345 switch (event->type) {
346 case CCN_TYPE_CYCLES:
347 break;
348 case CCN_TYPE_XP:
349 res += snprintf(buf + res, PAGE_SIZE - res,
350 ",xp=?,port=?,vc=?,dir=?");
351 if (event->event == CCN_EVENT_WATCHPOINT)
352 res += snprintf(buf + res, PAGE_SIZE - res,
353 ",cmp_l=?,cmp_h=?,mask=?");
354 break;
355 default:
356 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
357 break;
358 }
359
360 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
361
362 return res;
363 }
364
365 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
366 struct attribute *attr, int index)
367 {
368 struct device *dev = kobj_to_dev(kobj);
369 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
370 struct device_attribute *dev_attr = container_of(attr,
371 struct device_attribute, attr);
372 struct arm_ccn_pmu_event *event = container_of(dev_attr,
373 struct arm_ccn_pmu_event, attr);
374
375 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
376 return 0;
377 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
378 return 0;
379
380 return attr->mode;
381 }
382
383 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
384 CCN_EVENT_MN(eobarrier, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
385 CCN_EVENT_MN(ecbarrier, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
386 CCN_EVENT_MN(dvmop, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
387 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
388 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
389 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
390 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
391 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
392 CCN_IDX_MASK_ORDER),
393 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
394 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
395 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
396 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
397 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
398 CCN_IDX_MASK_ORDER),
399 CCN_EVENT_HNF(cache_miss, 0x1),
400 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
401 CCN_EVENT_HNF(cache_fill, 0x3),
402 CCN_EVENT_HNF(pocq_retry, 0x4),
403 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
404 CCN_EVENT_HNF(sf_hit, 0x6),
405 CCN_EVENT_HNF(sf_evictions, 0x7),
406 CCN_EVENT_HNF(snoops_sent, 0x8),
407 CCN_EVENT_HNF(snoops_broadcast, 0x9),
408 CCN_EVENT_HNF(l3_eviction, 0xa),
409 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
410 CCN_EVENT_HNF(mc_retries, 0xc),
411 CCN_EVENT_HNF(mc_reqs, 0xd),
412 CCN_EVENT_HNF(qos_hh_retry, 0xe),
413 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
414 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
415 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
416 CCN_EVENT_RNI(rxdat_flits, 0x4),
417 CCN_EVENT_RNI(txdat_flits, 0x5),
418 CCN_EVENT_RNI(txreq_flits, 0x6),
419 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
420 CCN_EVENT_RNI(rrt_full, 0x8),
421 CCN_EVENT_RNI(wrt_full, 0x9),
422 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
423 CCN_EVENT_XP(upload_starvation, 0x1),
424 CCN_EVENT_XP(download_starvation, 0x2),
425 CCN_EVENT_XP(respin, 0x3),
426 CCN_EVENT_XP(valid_flit, 0x4),
427 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
428 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
429 CCN_EVENT_SBAS(rxdat_flits, 0x4),
430 CCN_EVENT_SBAS(txdat_flits, 0x5),
431 CCN_EVENT_SBAS(txreq_flits, 0x6),
432 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
433 CCN_EVENT_SBAS(rrt_full, 0x8),
434 CCN_EVENT_SBAS(wrt_full, 0x9),
435 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
436 CCN_EVENT_CYCLES(cycles),
437 };
438
439 /* Populated in arm_ccn_init() */
440 static struct attribute
441 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
442
443 static struct attribute_group arm_ccn_pmu_events_attr_group = {
444 .name = "events",
445 .is_visible = arm_ccn_pmu_events_is_visible,
446 .attrs = arm_ccn_pmu_events_attrs,
447 };
448
449
450 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
451 {
452 unsigned long i;
453
454 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
455 return NULL;
456 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
457
458 switch (name[1]) {
459 case 'l':
460 return &ccn->dt.cmp_mask[i].l;
461 case 'h':
462 return &ccn->dt.cmp_mask[i].h;
463 default:
464 return NULL;
465 }
466 }
467
468 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
469 struct device_attribute *attr, char *buf)
470 {
471 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
472 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
473
474 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
475 }
476
477 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
478 struct device_attribute *attr, const char *buf, size_t count)
479 {
480 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
481 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
482 int err = -EINVAL;
483
484 if (mask)
485 err = kstrtoull(buf, 0, mask);
486
487 return err ? err : count;
488 }
489
490 #define CCN_CMP_MASK_ATTR(_name) \
491 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
492 __ATTR(_name, S_IRUGO | S_IWUSR, \
493 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
494
495 #define CCN_CMP_MASK_ATTR_RO(_name) \
496 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
497 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
498
499 static CCN_CMP_MASK_ATTR(0l);
500 static CCN_CMP_MASK_ATTR(0h);
501 static CCN_CMP_MASK_ATTR(1l);
502 static CCN_CMP_MASK_ATTR(1h);
503 static CCN_CMP_MASK_ATTR(2l);
504 static CCN_CMP_MASK_ATTR(2h);
505 static CCN_CMP_MASK_ATTR(3l);
506 static CCN_CMP_MASK_ATTR(3h);
507 static CCN_CMP_MASK_ATTR(4l);
508 static CCN_CMP_MASK_ATTR(4h);
509 static CCN_CMP_MASK_ATTR(5l);
510 static CCN_CMP_MASK_ATTR(5h);
511 static CCN_CMP_MASK_ATTR(6l);
512 static CCN_CMP_MASK_ATTR(6h);
513 static CCN_CMP_MASK_ATTR(7l);
514 static CCN_CMP_MASK_ATTR(7h);
515 static CCN_CMP_MASK_ATTR_RO(8l);
516 static CCN_CMP_MASK_ATTR_RO(8h);
517 static CCN_CMP_MASK_ATTR_RO(9l);
518 static CCN_CMP_MASK_ATTR_RO(9h);
519 static CCN_CMP_MASK_ATTR_RO(al);
520 static CCN_CMP_MASK_ATTR_RO(ah);
521 static CCN_CMP_MASK_ATTR_RO(bl);
522 static CCN_CMP_MASK_ATTR_RO(bh);
523
524 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
525 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
526 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
527 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
528 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
529 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
530 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
531 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
532 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
533 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
534 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
535 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
536 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
537 NULL
538 };
539
540 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
541 .name = "cmp_mask",
542 .attrs = arm_ccn_pmu_cmp_mask_attrs,
543 };
544
545 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
546 struct device_attribute *attr, char *buf)
547 {
548 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
549
550 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
551 }
552
553 static struct device_attribute arm_ccn_pmu_cpumask_attr =
554 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
555
556 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
557 &arm_ccn_pmu_cpumask_attr.attr,
558 NULL,
559 };
560
561 static struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
562 .attrs = arm_ccn_pmu_cpumask_attrs,
563 };
564
565 /*
566 * Default poll period is 10ms, which is way over the top anyway,
567 * as in the worst case scenario (an event every cycle), with 1GHz
568 * clocked bus, the smallest, 32 bit counter will overflow in
569 * more than 4s.
570 */
571 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
572 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
573 S_IRUGO | S_IWUSR);
574
575 static ktime_t arm_ccn_pmu_timer_period(void)
576 {
577 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
578 }
579
580
581 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
582 &arm_ccn_pmu_events_attr_group,
583 &arm_ccn_pmu_format_attr_group,
584 &arm_ccn_pmu_cmp_mask_attr_group,
585 &arm_ccn_pmu_cpumask_attr_group,
586 NULL
587 };
588
589
590 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
591 {
592 int bit;
593
594 do {
595 bit = find_first_zero_bit(bitmap, size);
596 if (bit >= size)
597 return -EAGAIN;
598 } while (test_and_set_bit(bit, bitmap));
599
600 return bit;
601 }
602
603 /* All RN-I and RN-D nodes have identical PMUs */
604 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
605 {
606 if (a == b)
607 return 1;
608
609 switch (a) {
610 case CCN_TYPE_RNI_1P:
611 case CCN_TYPE_RNI_2P:
612 case CCN_TYPE_RNI_3P:
613 case CCN_TYPE_RND_1P:
614 case CCN_TYPE_RND_2P:
615 case CCN_TYPE_RND_3P:
616 switch (b) {
617 case CCN_TYPE_RNI_1P:
618 case CCN_TYPE_RNI_2P:
619 case CCN_TYPE_RNI_3P:
620 case CCN_TYPE_RND_1P:
621 case CCN_TYPE_RND_2P:
622 case CCN_TYPE_RND_3P:
623 return 1;
624 }
625 break;
626 }
627
628 return 0;
629 }
630
631 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
632 {
633 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
634 struct hw_perf_event *hw = &event->hw;
635 u32 node_xp, type, event_id;
636 struct arm_ccn_component *source;
637 int bit;
638
639 node_xp = CCN_CONFIG_NODE(event->attr.config);
640 type = CCN_CONFIG_TYPE(event->attr.config);
641 event_id = CCN_CONFIG_EVENT(event->attr.config);
642
643 /* Allocate the cycle counter */
644 if (type == CCN_TYPE_CYCLES) {
645 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
646 ccn->dt.pmu_counters_mask))
647 return -EAGAIN;
648
649 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
650 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
651
652 return 0;
653 }
654
655 /* Allocate an event counter */
656 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
657 CCN_NUM_PMU_EVENT_COUNTERS);
658 if (hw->idx < 0) {
659 dev_dbg(ccn->dev, "No more counters available!\n");
660 return -EAGAIN;
661 }
662
663 if (type == CCN_TYPE_XP)
664 source = &ccn->xp[node_xp];
665 else
666 source = &ccn->node[node_xp];
667 ccn->dt.pmu_counters[hw->idx].source = source;
668
669 /* Allocate an event source or a watchpoint */
670 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
671 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
672 CCN_NUM_XP_WATCHPOINTS);
673 else
674 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
675 CCN_NUM_PMU_EVENTS);
676 if (bit < 0) {
677 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
678 node_xp);
679 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
680 return -EAGAIN;
681 }
682 hw->config_base = bit;
683
684 ccn->dt.pmu_counters[hw->idx].event = event;
685
686 return 0;
687 }
688
689 static void arm_ccn_pmu_event_release(struct perf_event *event)
690 {
691 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
692 struct hw_perf_event *hw = &event->hw;
693
694 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
695 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
696 } else {
697 struct arm_ccn_component *source =
698 ccn->dt.pmu_counters[hw->idx].source;
699
700 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
701 CCN_CONFIG_EVENT(event->attr.config) ==
702 CCN_EVENT_WATCHPOINT)
703 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
704 else
705 clear_bit(hw->config_base, source->pmu_events_mask);
706 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
707 }
708
709 ccn->dt.pmu_counters[hw->idx].source = NULL;
710 ccn->dt.pmu_counters[hw->idx].event = NULL;
711 }
712
713 static int arm_ccn_pmu_event_init(struct perf_event *event)
714 {
715 struct arm_ccn *ccn;
716 struct hw_perf_event *hw = &event->hw;
717 u32 node_xp, type, event_id;
718 int valid;
719 int i;
720 struct perf_event *sibling;
721
722 if (event->attr.type != event->pmu->type)
723 return -ENOENT;
724
725 ccn = pmu_to_arm_ccn(event->pmu);
726
727 if (hw->sample_period) {
728 dev_warn(ccn->dev, "Sampling not supported!\n");
729 return -EOPNOTSUPP;
730 }
731
732 if (has_branch_stack(event) || event->attr.exclude_user ||
733 event->attr.exclude_kernel || event->attr.exclude_hv ||
734 event->attr.exclude_idle) {
735 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
736 return -EOPNOTSUPP;
737 }
738
739 if (event->cpu < 0) {
740 dev_warn(ccn->dev, "Can't provide per-task data!\n");
741 return -EOPNOTSUPP;
742 }
743 /*
744 * Many perf core operations (eg. events rotation) operate on a
745 * single CPU context. This is obvious for CPU PMUs, where one
746 * expects the same sets of events being observed on all CPUs,
747 * but can lead to issues for off-core PMUs, like CCN, where each
748 * event could be theoretically assigned to a different CPU. To
749 * mitigate this, we enforce CPU assignment to one, selected
750 * processor (the one described in the "cpumask" attribute).
751 */
752 event->cpu = cpumask_first(&ccn->dt.cpu);
753
754 node_xp = CCN_CONFIG_NODE(event->attr.config);
755 type = CCN_CONFIG_TYPE(event->attr.config);
756 event_id = CCN_CONFIG_EVENT(event->attr.config);
757
758 /* Validate node/xp vs topology */
759 switch (type) {
760 case CCN_TYPE_XP:
761 if (node_xp >= ccn->num_xps) {
762 dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
763 return -EINVAL;
764 }
765 break;
766 case CCN_TYPE_CYCLES:
767 break;
768 default:
769 if (node_xp >= ccn->num_nodes) {
770 dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
771 return -EINVAL;
772 }
773 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
774 dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
775 type, node_xp);
776 return -EINVAL;
777 }
778 break;
779 }
780
781 /* Validate event ID vs available for the type */
782 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
783 i++) {
784 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
785 u32 port = CCN_CONFIG_PORT(event->attr.config);
786 u32 vc = CCN_CONFIG_VC(event->attr.config);
787
788 if (!arm_ccn_pmu_type_eq(type, e->type))
789 continue;
790 if (event_id != e->event)
791 continue;
792 if (e->num_ports && port >= e->num_ports) {
793 dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
794 port, node_xp);
795 return -EINVAL;
796 }
797 if (e->num_vcs && vc >= e->num_vcs) {
798 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
799 vc, node_xp);
800 return -EINVAL;
801 }
802 valid = 1;
803 }
804 if (!valid) {
805 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
806 event_id, node_xp);
807 return -EINVAL;
808 }
809
810 /* Watchpoint-based event for a node is actually set on XP */
811 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
812 u32 port;
813
814 type = CCN_TYPE_XP;
815 port = arm_ccn_node_to_xp_port(node_xp);
816 node_xp = arm_ccn_node_to_xp(node_xp);
817
818 arm_ccn_pmu_config_set(&event->attr.config,
819 node_xp, type, port);
820 }
821
822 /*
823 * We must NOT create groups containing mixed PMUs, although software
824 * events are acceptable (for example to create a CCN group
825 * periodically read when a hrtimer aka cpu-clock leader triggers).
826 */
827 if (event->group_leader->pmu != event->pmu &&
828 !is_software_event(event->group_leader))
829 return -EINVAL;
830
831 list_for_each_entry(sibling, &event->group_leader->sibling_list,
832 group_entry)
833 if (sibling->pmu != event->pmu &&
834 !is_software_event(sibling))
835 return -EINVAL;
836
837 return 0;
838 }
839
840 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
841 {
842 u64 res;
843
844 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
845 #ifdef readq
846 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
847 #else
848 /* 40 bit counter, can do snapshot and read in two parts */
849 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
850 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
851 ;
852 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
853 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
854 res <<= 32;
855 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
856 #endif
857 } else {
858 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
859 }
860
861 return res;
862 }
863
864 static void arm_ccn_pmu_event_update(struct perf_event *event)
865 {
866 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
867 struct hw_perf_event *hw = &event->hw;
868 u64 prev_count, new_count, mask;
869
870 do {
871 prev_count = local64_read(&hw->prev_count);
872 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
873 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
874
875 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
876
877 local64_add((new_count - prev_count) & mask, &event->count);
878 }
879
880 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
881 {
882 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
883 struct hw_perf_event *hw = &event->hw;
884 struct arm_ccn_component *xp;
885 u32 val, dt_cfg;
886
887 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
888 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
889 else
890 xp = &ccn->xp[arm_ccn_node_to_xp(
891 CCN_CONFIG_NODE(event->attr.config))];
892
893 if (enable)
894 dt_cfg = hw->event_base;
895 else
896 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
897
898 spin_lock(&ccn->dt.config_lock);
899
900 val = readl(xp->base + CCN_XP_DT_CONFIG);
901 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
902 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
903 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
904 writel(val, xp->base + CCN_XP_DT_CONFIG);
905
906 spin_unlock(&ccn->dt.config_lock);
907 }
908
909 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
910 {
911 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
912 struct hw_perf_event *hw = &event->hw;
913
914 local64_set(&event->hw.prev_count,
915 arm_ccn_pmu_read_counter(ccn, hw->idx));
916 hw->state = 0;
917
918 /*
919 * Pin the timer, so that the overflows are handled by the chosen
920 * event->cpu (this is the same one as presented in "cpumask"
921 * attribute).
922 */
923 if (!ccn->irq)
924 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
925 HRTIMER_MODE_REL_PINNED);
926
927 /* Set the DT bus input, engaging the counter */
928 arm_ccn_pmu_xp_dt_config(event, 1);
929 }
930
931 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
932 {
933 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
934 struct hw_perf_event *hw = &event->hw;
935 u64 timeout;
936
937 /* Disable counting, setting the DT bus to pass-through mode */
938 arm_ccn_pmu_xp_dt_config(event, 0);
939
940 if (!ccn->irq)
941 hrtimer_cancel(&ccn->dt.hrtimer);
942
943 /* Let the DT bus drain */
944 timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
945 ccn->num_xps;
946 while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
947 timeout)
948 cpu_relax();
949
950 if (flags & PERF_EF_UPDATE)
951 arm_ccn_pmu_event_update(event);
952
953 hw->state |= PERF_HES_STOPPED;
954 }
955
956 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
957 {
958 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
959 struct hw_perf_event *hw = &event->hw;
960 struct arm_ccn_component *source =
961 ccn->dt.pmu_counters[hw->idx].source;
962 unsigned long wp = hw->config_base;
963 u32 val;
964 u64 cmp_l = event->attr.config1;
965 u64 cmp_h = event->attr.config2;
966 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
967 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
968
969 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
970
971 /* Direction (RX/TX), device (port) & virtual channel */
972 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
973 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
974 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
975 val |= CCN_CONFIG_DIR(event->attr.config) <<
976 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
977 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
978 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
979 val |= CCN_CONFIG_PORT(event->attr.config) <<
980 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
981 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
982 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
983 val |= CCN_CONFIG_VC(event->attr.config) <<
984 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
985 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
986
987 /* Comparison values */
988 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
989 writel((cmp_l >> 32) & 0xefffffff,
990 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
991 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
992 writel((cmp_h >> 32) & 0x0fffffff,
993 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
994
995 /* Mask */
996 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
997 writel((mask_l >> 32) & 0xefffffff,
998 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
999 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
1000 writel((mask_h >> 32) & 0x0fffffff,
1001 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1002 }
1003
1004 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1005 {
1006 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1007 struct hw_perf_event *hw = &event->hw;
1008 struct arm_ccn_component *source =
1009 ccn->dt.pmu_counters[hw->idx].source;
1010 u32 val, id;
1011
1012 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1013
1014 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1015 (CCN_CONFIG_PORT(event->attr.config) << 3) |
1016 (CCN_CONFIG_EVENT(event->attr.config) << 0);
1017
1018 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1019 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1020 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1021 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1022 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1023 }
1024
1025 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1026 {
1027 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1028 struct hw_perf_event *hw = &event->hw;
1029 struct arm_ccn_component *source =
1030 ccn->dt.pmu_counters[hw->idx].source;
1031 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1032 u32 val, port;
1033
1034 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1035 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1036 hw->config_base);
1037
1038 /* These *_event_sel regs should be identical, but let's make sure... */
1039 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1040 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1041 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1042 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1043 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1044 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1045 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1046 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1047 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1048 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1049 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1050 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1051 return;
1052
1053 /* Set the event id for the pre-allocated counter */
1054 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1055 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1056 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1057 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1058 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1059 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1060 }
1061
1062 static void arm_ccn_pmu_event_config(struct perf_event *event)
1063 {
1064 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1065 struct hw_perf_event *hw = &event->hw;
1066 u32 xp, offset, val;
1067
1068 /* Cycle counter requires no setup */
1069 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1070 return;
1071
1072 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1073 xp = CCN_CONFIG_XP(event->attr.config);
1074 else
1075 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1076
1077 spin_lock(&ccn->dt.config_lock);
1078
1079 /* Set the DT bus "distance" register */
1080 offset = (hw->idx / 4) * 4;
1081 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1082 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1083 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1084 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1085 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1086
1087 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1088 if (CCN_CONFIG_EVENT(event->attr.config) ==
1089 CCN_EVENT_WATCHPOINT)
1090 arm_ccn_pmu_xp_watchpoint_config(event);
1091 else
1092 arm_ccn_pmu_xp_event_config(event);
1093 } else {
1094 arm_ccn_pmu_node_event_config(event);
1095 }
1096
1097 spin_unlock(&ccn->dt.config_lock);
1098 }
1099
1100 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1101 {
1102 int err;
1103 struct hw_perf_event *hw = &event->hw;
1104
1105 err = arm_ccn_pmu_event_alloc(event);
1106 if (err)
1107 return err;
1108
1109 arm_ccn_pmu_event_config(event);
1110
1111 hw->state = PERF_HES_STOPPED;
1112
1113 if (flags & PERF_EF_START)
1114 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1115
1116 return 0;
1117 }
1118
1119 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1120 {
1121 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1122
1123 arm_ccn_pmu_event_release(event);
1124 }
1125
1126 static void arm_ccn_pmu_event_read(struct perf_event *event)
1127 {
1128 arm_ccn_pmu_event_update(event);
1129 }
1130
1131 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1132 {
1133 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1134 int idx;
1135
1136 if (!pmovsr)
1137 return IRQ_NONE;
1138
1139 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1140
1141 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1142
1143 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1144 struct perf_event *event = dt->pmu_counters[idx].event;
1145 int overflowed = pmovsr & BIT(idx);
1146
1147 WARN_ON_ONCE(overflowed && !event &&
1148 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1149
1150 if (!event || !overflowed)
1151 continue;
1152
1153 arm_ccn_pmu_event_update(event);
1154 }
1155
1156 return IRQ_HANDLED;
1157 }
1158
1159 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1160 {
1161 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1162 hrtimer);
1163 unsigned long flags;
1164
1165 local_irq_save(flags);
1166 arm_ccn_pmu_overflow_handler(dt);
1167 local_irq_restore(flags);
1168
1169 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1170 return HRTIMER_RESTART;
1171 }
1172
1173
1174 static int arm_ccn_pmu_cpu_notifier(struct notifier_block *nb,
1175 unsigned long action, void *hcpu)
1176 {
1177 struct arm_ccn_dt *dt = container_of(nb, struct arm_ccn_dt, cpu_nb);
1178 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1179 unsigned int cpu = (long)hcpu; /* for (long) see kernel/cpu.c */
1180 unsigned int target;
1181
1182 switch (action & ~CPU_TASKS_FROZEN) {
1183 case CPU_DOWN_PREPARE:
1184 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1185 break;
1186 target = cpumask_any_but(cpu_online_mask, cpu);
1187 if (target < 0)
1188 break;
1189 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1190 cpumask_set_cpu(target, &dt->cpu);
1191 WARN_ON(irq_set_affinity(ccn->irq, &dt->cpu) != 0);
1192 default:
1193 break;
1194 }
1195
1196 return NOTIFY_OK;
1197 }
1198
1199
1200 static DEFINE_IDA(arm_ccn_pmu_ida);
1201
1202 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1203 {
1204 int i;
1205 char *name;
1206 int err;
1207
1208 /* Initialize DT subsystem */
1209 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1210 spin_lock_init(&ccn->dt.config_lock);
1211 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1212 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1213 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1214 ccn->dt.base + CCN_DT_PMCR);
1215 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1216 for (i = 0; i < ccn->num_xps; i++) {
1217 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1218 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1219 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1220 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1221 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1222 CCN_XP_DT_CONTROL__DT_ENABLE,
1223 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1224 }
1225 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1226 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1227 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1228 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1229 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1230 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1231 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1232 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1233
1234 /* Get a convenient /sys/event_source/devices/ name */
1235 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1236 if (ccn->dt.id == 0) {
1237 name = "ccn";
1238 } else {
1239 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1240
1241 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1242 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1243 }
1244
1245 /* Perf driver registration */
1246 ccn->dt.pmu = (struct pmu) {
1247 .attr_groups = arm_ccn_pmu_attr_groups,
1248 .task_ctx_nr = perf_invalid_context,
1249 .event_init = arm_ccn_pmu_event_init,
1250 .add = arm_ccn_pmu_event_add,
1251 .del = arm_ccn_pmu_event_del,
1252 .start = arm_ccn_pmu_event_start,
1253 .stop = arm_ccn_pmu_event_stop,
1254 .read = arm_ccn_pmu_event_read,
1255 };
1256
1257 /* No overflow interrupt? Have to use a timer instead. */
1258 if (!ccn->irq) {
1259 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1260 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1261 HRTIMER_MODE_REL);
1262 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1263 }
1264
1265 /* Pick one CPU which we will use to collect data from CCN... */
1266 cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);
1267
1268 /*
1269 * ... and change the selection when it goes offline. Priority is
1270 * picked to have a chance to migrate events before perf is notified.
1271 */
1272 ccn->dt.cpu_nb.notifier_call = arm_ccn_pmu_cpu_notifier;
1273 ccn->dt.cpu_nb.priority = CPU_PRI_PERF + 1,
1274 err = register_cpu_notifier(&ccn->dt.cpu_nb);
1275 if (err)
1276 goto error_cpu_notifier;
1277
1278 /* Also make sure that the overflow interrupt is handled by this CPU */
1279 if (ccn->irq) {
1280 err = irq_set_affinity(ccn->irq, &ccn->dt.cpu);
1281 if (err) {
1282 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1283 goto error_set_affinity;
1284 }
1285 }
1286
1287 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1288 if (err)
1289 goto error_pmu_register;
1290
1291 return 0;
1292
1293 error_pmu_register:
1294 error_set_affinity:
1295 unregister_cpu_notifier(&ccn->dt.cpu_nb);
1296 error_cpu_notifier:
1297 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1298 for (i = 0; i < ccn->num_xps; i++)
1299 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1300 writel(0, ccn->dt.base + CCN_DT_PMCR);
1301 return err;
1302 }
1303
1304 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1305 {
1306 int i;
1307
1308 irq_set_affinity(ccn->irq, cpu_possible_mask);
1309 unregister_cpu_notifier(&ccn->dt.cpu_nb);
1310 for (i = 0; i < ccn->num_xps; i++)
1311 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1312 writel(0, ccn->dt.base + CCN_DT_PMCR);
1313 perf_pmu_unregister(&ccn->dt.pmu);
1314 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1315 }
1316
1317
1318 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1319 int (*callback)(struct arm_ccn *ccn, int region,
1320 void __iomem *base, u32 type, u32 id))
1321 {
1322 int region;
1323
1324 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1325 u32 val, type, id;
1326 void __iomem *base;
1327 int err;
1328
1329 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1330 4 * (region / 32));
1331 if (!(val & (1 << (region % 32))))
1332 continue;
1333
1334 base = ccn->base + region * CCN_REGION_SIZE;
1335 val = readl(base + CCN_ALL_OLY_ID);
1336 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1337 CCN_ALL_OLY_ID__OLY_ID__MASK;
1338 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1339 CCN_ALL_OLY_ID__NODE_ID__MASK;
1340
1341 err = callback(ccn, region, base, type, id);
1342 if (err)
1343 return err;
1344 }
1345
1346 return 0;
1347 }
1348
1349 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1350 void __iomem *base, u32 type, u32 id)
1351 {
1352
1353 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1354 ccn->num_xps = id + 1;
1355 else if (id >= ccn->num_nodes)
1356 ccn->num_nodes = id + 1;
1357
1358 return 0;
1359 }
1360
1361 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1362 void __iomem *base, u32 type, u32 id)
1363 {
1364 struct arm_ccn_component *component;
1365
1366 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1367
1368 switch (type) {
1369 case CCN_TYPE_MN:
1370 case CCN_TYPE_DT:
1371 return 0;
1372 case CCN_TYPE_XP:
1373 component = &ccn->xp[id];
1374 break;
1375 case CCN_TYPE_SBSX:
1376 ccn->sbsx_present = 1;
1377 component = &ccn->node[id];
1378 break;
1379 case CCN_TYPE_SBAS:
1380 ccn->sbas_present = 1;
1381 /* Fall-through */
1382 default:
1383 component = &ccn->node[id];
1384 break;
1385 }
1386
1387 component->base = base;
1388 component->type = type;
1389
1390 return 0;
1391 }
1392
1393
1394 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1395 const u32 *err_sig_val)
1396 {
1397 /* This should be really handled by firmware... */
1398 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1399 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1400 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1401 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1402 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1403 ccn->base + CCN_MN_ERRINT_STATUS);
1404
1405 return IRQ_HANDLED;
1406 }
1407
1408
1409 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1410 {
1411 irqreturn_t res = IRQ_NONE;
1412 struct arm_ccn *ccn = dev_id;
1413 u32 err_sig_val[6];
1414 u32 err_or;
1415 int i;
1416
1417 /* PMU overflow is a special case */
1418 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1419 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1420 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1421 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1422 }
1423
1424 /* Have to read all err_sig_vals to clear them */
1425 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1426 err_sig_val[i] = readl(ccn->base +
1427 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1428 err_or |= err_sig_val[i];
1429 }
1430 if (err_or)
1431 res |= arm_ccn_error_handler(ccn, err_sig_val);
1432
1433 if (res != IRQ_NONE)
1434 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1435 ccn->base + CCN_MN_ERRINT_STATUS);
1436
1437 return res;
1438 }
1439
1440
1441 static int arm_ccn_probe(struct platform_device *pdev)
1442 {
1443 struct arm_ccn *ccn;
1444 struct resource *res;
1445 unsigned int irq;
1446 int err;
1447
1448 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1449 if (!ccn)
1450 return -ENOMEM;
1451 ccn->dev = &pdev->dev;
1452 platform_set_drvdata(pdev, ccn);
1453
1454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1455 if (!res)
1456 return -EINVAL;
1457
1458 if (!devm_request_mem_region(ccn->dev, res->start,
1459 resource_size(res), pdev->name))
1460 return -EBUSY;
1461
1462 ccn->base = devm_ioremap(ccn->dev, res->start,
1463 resource_size(res));
1464 if (!ccn->base)
1465 return -EFAULT;
1466
1467 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1468 if (!res)
1469 return -EINVAL;
1470 irq = res->start;
1471
1472 /* Check if we can use the interrupt */
1473 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1474 ccn->base + CCN_MN_ERRINT_STATUS);
1475 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1476 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1477 /* Can set 'disable' bits, so can acknowledge interrupts */
1478 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1479 ccn->base + CCN_MN_ERRINT_STATUS);
1480 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
1481 dev_name(ccn->dev), ccn);
1482 if (err)
1483 return err;
1484
1485 ccn->irq = irq;
1486 }
1487
1488
1489 /* Build topology */
1490
1491 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1492 if (err)
1493 return err;
1494
1495 ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1496 GFP_KERNEL);
1497 ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1498 GFP_KERNEL);
1499 if (!ccn->node || !ccn->xp)
1500 return -ENOMEM;
1501
1502 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1503 if (err)
1504 return err;
1505
1506 return arm_ccn_pmu_init(ccn);
1507 }
1508
1509 static int arm_ccn_remove(struct platform_device *pdev)
1510 {
1511 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1512
1513 arm_ccn_pmu_cleanup(ccn);
1514
1515 return 0;
1516 }
1517
1518 static const struct of_device_id arm_ccn_match[] = {
1519 { .compatible = "arm,ccn-504", },
1520 {},
1521 };
1522
1523 static struct platform_driver arm_ccn_driver = {
1524 .driver = {
1525 .name = "arm-ccn",
1526 .of_match_table = arm_ccn_match,
1527 },
1528 .probe = arm_ccn_probe,
1529 .remove = arm_ccn_remove,
1530 };
1531
1532 static int __init arm_ccn_init(void)
1533 {
1534 int i;
1535
1536 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1537 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1538
1539 return platform_driver_register(&arm_ccn_driver);
1540 }
1541
1542 static void __exit arm_ccn_exit(void)
1543 {
1544 platform_driver_unregister(&arm_ccn_driver);
1545 }
1546
1547 module_init(arm_ccn_init);
1548 module_exit(arm_ccn_exit);
1549
1550 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1551 MODULE_LICENSE("GPL");
Linux with added FPC-III support