drivers/dma/ppc4xx/dma.h

   1 /*
   2  * 440SPe's DMA engines support header file
   3  *
   4  * 2006-2009 (C) DENX Software Engineering.
   5  *
   6  * Author: Yuri Tikhonov <yur@emcraft.com>
   7  *
   8  * This file is licensed under the term of  the GNU General Public License
   9  * version 2. The program licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #ifndef _PPC440SPE_DMA_H
  14 #define _PPC440SPE_DMA_H
  15
  16 #include <linux/types.h>
  17
  18 /* Number of elements in the array with statical CDBs */
  19 #define MAX_STAT_DMA_CDBS       16
  20 /* Number of DMA engines available on the contoller */
  21 #define DMA_ENGINES_NUM         2
  22
  23 /* Maximum h/w supported number of destinations */
  24 #define DMA_DEST_MAX_NUM        2
  25
  26 /* FIFO's params */
  27 #define DMA0_FIFO_SIZE          0x1000
  28 #define DMA1_FIFO_SIZE          0x1000
  29 #define DMA_FIFO_ENABLE         (1<<12)
  30
  31 /* DMA Configuration Register. Data Transfer Engine PLB Priority: */
  32 #define DMA_CFG_DXEPR_LP        (0<<26)
  33 #define DMA_CFG_DXEPR_HP        (3<<26)
  34 #define DMA_CFG_DXEPR_HHP       (2<<26)
  35 #define DMA_CFG_DXEPR_HHHP      (1<<26)
  36
  37 /* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
  38 #define DMA_CFG_DFMPP_LP        (0<<23)
  39 #define DMA_CFG_DFMPP_HP        (3<<23)
  40 #define DMA_CFG_DFMPP_HHP       (2<<23)
  41 #define DMA_CFG_DFMPP_HHHP      (1<<23)
  42
  43 /* DMA Configuration Register. Force 64-byte Alignment */
  44 #define DMA_CFG_FALGN           (1 << 19)
  45
  46 /*UIC0:*/
  47 #define D0CPF_INT               (1<<12)
  48 #define D0CSF_INT               (1<<11)
  49 #define D1CPF_INT               (1<<10)
  50 #define D1CSF_INT               (1<<9)
  51 /*UIC1:*/
  52 #define DMAE_INT                (1<<9)
  53
  54 /* I2O IOP Interrupt Mask Register */
  55 #define I2O_IOPIM_P0SNE         (1<<3)
  56 #define I2O_IOPIM_P0EM          (1<<5)
  57 #define I2O_IOPIM_P1SNE         (1<<6)
  58 #define I2O_IOPIM_P1EM          (1<<8)
  59
  60 /* DMA CDB fields */
  61 #define DMA_CDB_MSK             (0xF)
  62 #define DMA_CDB_64B_ADDR        (1<<2)
  63 #define DMA_CDB_NO_INT          (1<<3)
  64 #define DMA_CDB_STATUS_MSK      (0x3)
  65 #define DMA_CDB_ADDR_MSK        (0xFFFFFFF0)
  66
  67 /* DMA CDB OpCodes */
  68 #define DMA_CDB_OPC_NO_OP       (0x00)
  69 #define DMA_CDB_OPC_MV_SG1_SG2  (0x01)
  70 #define DMA_CDB_OPC_MULTICAST   (0x05)
  71 #define DMA_CDB_OPC_DFILL128    (0x24)
  72 #define DMA_CDB_OPC_DCHECK128   (0x23)
  73
  74 #define DMA_CUED_XOR_BASE       (0x10000000)
  75 #define DMA_CUED_XOR_HB         (0x00000008)
  76
  77 #ifdef CONFIG_440SP
  78 #define DMA_CUED_MULT1_OFF      0
  79 #define DMA_CUED_MULT2_OFF      8
  80 #define DMA_CUED_MULT3_OFF      16
  81 #define DMA_CUED_REGION_OFF     24
  82 #define DMA_CUED_XOR_WIN_MSK    (0xFC000000)
  83 #else
  84 #define DMA_CUED_MULT1_OFF      2
  85 #define DMA_CUED_MULT2_OFF      10
  86 #define DMA_CUED_MULT3_OFF      18
  87 #define DMA_CUED_REGION_OFF     26
  88 #define DMA_CUED_XOR_WIN_MSK    (0xF0000000)
  89 #endif
  90
  91 #define DMA_CUED_REGION_MSK     0x3
  92 #define DMA_RXOR123             0x0
  93 #define DMA_RXOR124             0x1
  94 #define DMA_RXOR125             0x2
  95 #define DMA_RXOR12              0x3
  96
  97 /* S/G addresses */
  98 #define DMA_CDB_SG_SRC          1
  99 #define DMA_CDB_SG_DST1         2
 100 #define DMA_CDB_SG_DST2         3
 101
 102 /*
 103  * DMAx engines Command Descriptor Block Type
 104  */
 105 struct dma_cdb {
 106         /*
 107          * Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
 108          */
 109         u8      pad0[2];        /* reserved */
 110         u8      attr;           /* attributes */
 111         u8      opc;            /* opcode */
 112         u32     sg1u;           /* upper SG1 address */
 113         u32     sg1l;           /* lower SG1 address */
 114         u32     cnt;            /* SG count, 3B used */
 115         u32     sg2u;           /* upper SG2 address */
 116         u32     sg2l;           /* lower SG2 address */
 117         u32     sg3u;           /* upper SG3 address */
 118         u32     sg3l;           /* lower SG3 address */
 119 };
 120
 121 /*
 122  * DMAx hardware registers (p.515 in 440SPe UM 1.22)
 123  */
 124 struct dma_regs {
 125         u32     cpfpl;
 126         u32     cpfph;
 127         u32     csfpl;
 128         u32     csfph;
 129         u32     dsts;
 130         u32     cfg;
 131         u8      pad0[0x8];
 132         u16     cpfhp;
 133         u16     cpftp;
 134         u16     csfhp;
 135         u16     csftp;
 136         u8      pad1[0x8];
 137         u32     acpl;
 138         u32     acph;
 139         u32     s1bpl;
 140         u32     s1bph;
 141         u32     s2bpl;
 142         u32     s2bph;
 143         u32     s3bpl;
 144         u32     s3bph;
 145         u8      pad2[0x10];
 146         u32     earl;
 147         u32     earh;
 148         u8      pad3[0x8];
 149         u32     seat;
 150         u32     sead;
 151         u32     op;
 152         u32     fsiz;
 153 };
 154
 155 /*
 156  * I2O hardware registers (p.528 in 440SPe UM 1.22)
 157  */
 158 struct i2o_regs {
 159         u32     ists;
 160         u32     iseat;
 161         u32     isead;
 162         u8      pad0[0x14];
 163         u32     idbel;
 164         u8      pad1[0xc];
 165         u32     ihis;
 166         u32     ihim;
 167         u8      pad2[0x8];
 168         u32     ihiq;
 169         u32     ihoq;
 170         u8      pad3[0x8];
 171         u32     iopis;
 172         u32     iopim;
 173         u32     iopiq;
 174         u8      iopoq;
 175         u8      pad4[3];
 176         u16     iiflh;
 177         u16     iiflt;
 178         u16     iiplh;
 179         u16     iiplt;
 180         u16     ioflh;
 181         u16     ioflt;
 182         u16     ioplh;
 183         u16     ioplt;
 184         u32     iidc;
 185         u32     ictl;
 186         u32     ifcpp;
 187         u8      pad5[0x4];
 188         u16     mfac0;
 189         u16     mfac1;
 190         u16     mfac2;
 191         u16     mfac3;
 192         u16     mfac4;
 193         u16     mfac5;
 194         u16     mfac6;
 195         u16     mfac7;
 196         u16     ifcfh;
 197         u16     ifcht;
 198         u8      pad6[0x4];
 199         u32     iifmc;
 200         u32     iodb;
 201         u32     iodbc;
 202         u32     ifbal;
 203         u32     ifbah;
 204         u32     ifsiz;
 205         u32     ispd0;
 206         u32     ispd1;
 207         u32     ispd2;
 208         u32     ispd3;
 209         u32     ihipl;
 210         u32     ihiph;
 211         u32     ihopl;
 212         u32     ihoph;
 213         u32     iiipl;
 214         u32     iiiph;
 215         u32     iiopl;
 216         u32     iioph;
 217         u32     ifcpl;
 218         u32     ifcph;
 219         u8      pad7[0x8];
 220         u32     iopt;
 221 };
 222
 223 #endif /* _PPC440SPE_DMA_H */