drivers/gpio/gpio-em.c

   1 /*
   2  * Emma Mobile GPIO Support - GIO
   3  *
   4  *  Copyright (C) 2012 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/bitops.h>
  29 #include <linux/err.h>
  30 #include <linux/gpio.h>
  31 #include <linux/slab.h>
  32 #include <linux/module.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/platform_data/gpio-em.h>
  35
  36 struct em_gio_priv {
  37         void __iomem *base0;
  38         void __iomem *base1;
  39         spinlock_t sense_lock;
  40         struct platform_device *pdev;
  41         struct gpio_chip gpio_chip;
  42         struct irq_chip irq_chip;
  43         struct irq_domain *irq_domain;
  44 };
  45
  46 #define GIO_E1 0x00
  47 #define GIO_E0 0x04
  48 #define GIO_EM 0x04
  49 #define GIO_OL 0x08
  50 #define GIO_OH 0x0c
  51 #define GIO_I 0x10
  52 #define GIO_IIA 0x14
  53 #define GIO_IEN 0x18
  54 #define GIO_IDS 0x1c
  55 #define GIO_IIM 0x1c
  56 #define GIO_RAW 0x20
  57 #define GIO_MST 0x24
  58 #define GIO_IIR 0x28
  59
  60 #define GIO_IDT0 0x40
  61 #define GIO_IDT1 0x44
  62 #define GIO_IDT2 0x48
  63 #define GIO_IDT3 0x4c
  64 #define GIO_RAWBL 0x50
  65 #define GIO_RAWBH 0x54
  66 #define GIO_IRBL 0x58
  67 #define GIO_IRBH 0x5c
  68
  69 #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
  70
  71 static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
  72 {
  73         if (offs < GIO_IDT0)
  74                 return ioread32(p->base0 + offs);
  75         else
  76                 return ioread32(p->base1 + (offs - GIO_IDT0));
  77 }
  78
  79 static inline void em_gio_write(struct em_gio_priv *p, int offs,
  80                                 unsigned long value)
  81 {
  82         if (offs < GIO_IDT0)
  83                 iowrite32(value, p->base0 + offs);
  84         else
  85                 iowrite32(value, p->base1 + (offs - GIO_IDT0));
  86 }
  87
  88 static void em_gio_irq_disable(struct irq_data *d)
  89 {
  90         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  91
  92         em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
  93 }
  94
  95 static void em_gio_irq_enable(struct irq_data *d)
  96 {
  97         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  98
  99         em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
 100 }
 101
 102 static int em_gio_irq_reqres(struct irq_data *d)
 103 {
 104         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 105
 106         if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
 107                 dev_err(p->gpio_chip.dev,
 108                         "unable to lock HW IRQ %lu for IRQ\n",
 109                         irqd_to_hwirq(d));
 110                 return -EINVAL;
 111         }
 112         return 0;
 113 }
 114
 115 static void em_gio_irq_relres(struct irq_data *d)
 116 {
 117         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 118
 119         gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
 120 }
 121
 122
 123 #define GIO_ASYNC(x) (x + 8)
 124
 125 static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
 126         [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
 127         [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
 128         [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
 129         [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
 130         [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
 131 };
 132
 133 static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
 134 {
 135         unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
 136         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 137         unsigned int reg, offset, shift;
 138         unsigned long flags;
 139         unsigned long tmp;
 140
 141         if (!value)
 142                 return -EINVAL;
 143
 144         offset = irqd_to_hwirq(d);
 145
 146         pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
 147
 148         /* 8 x 4 bit fields in 4 IDT registers */
 149         reg = GIO_IDT(offset >> 3);
 150         shift = (offset & 0x07) << 4;
 151
 152         spin_lock_irqsave(&p->sense_lock, flags);
 153
 154         /* disable the interrupt in IIA */
 155         tmp = em_gio_read(p, GIO_IIA);
 156         tmp &= ~BIT(offset);
 157         em_gio_write(p, GIO_IIA, tmp);
 158
 159         /* change the sense setting in IDT */
 160         tmp = em_gio_read(p, reg);
 161         tmp &= ~(0xf << shift);
 162         tmp |= value << shift;
 163         em_gio_write(p, reg, tmp);
 164
 165         /* clear pending interrupts */
 166         em_gio_write(p, GIO_IIR, BIT(offset));
 167
 168         /* enable the interrupt in IIA */
 169         tmp = em_gio_read(p, GIO_IIA);
 170         tmp |= BIT(offset);
 171         em_gio_write(p, GIO_IIA, tmp);
 172
 173         spin_unlock_irqrestore(&p->sense_lock, flags);
 174
 175         return 0;
 176 }
 177
 178 static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
 179 {
 180         struct em_gio_priv *p = dev_id;
 181         unsigned long pending;
 182         unsigned int offset, irqs_handled = 0;
 183
 184         while ((pending = em_gio_read(p, GIO_MST))) {
 185                 offset = __ffs(pending);
 186                 em_gio_write(p, GIO_IIR, BIT(offset));
 187                 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
 188                 irqs_handled++;
 189         }
 190
 191         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 192 }
 193
 194 static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
 195 {
 196         return container_of(chip, struct em_gio_priv, gpio_chip);
 197 }
 198
 199 static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
 200 {
 201         em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
 202         return 0;
 203 }
 204
 205 static int em_gio_get(struct gpio_chip *chip, unsigned offset)
 206 {
 207         return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
 208 }
 209
 210 static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
 211                          unsigned shift, int value)
 212 {
 213         /* upper 16 bits contains mask and lower 16 actual value */
 214         em_gio_write(gpio_to_priv(chip), reg,
 215                      (BIT(shift + 16)) | (value << shift));
 216 }
 217
 218 static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
 219 {
 220         /* output is split into two registers */
 221         if (offset < 16)
 222                 __em_gio_set(chip, GIO_OL, offset, value);
 223         else
 224                 __em_gio_set(chip, GIO_OH, offset - 16, value);
 225 }
 226
 227 static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
 228                                    int value)
 229 {
 230         /* write GPIO value to output before selecting output mode of pin */
 231         em_gio_set(chip, offset, value);
 232         em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
 233         return 0;
 234 }
 235
 236 static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
 237 {
 238         return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
 239 }
 240
 241 static int em_gio_request(struct gpio_chip *chip, unsigned offset)
 242 {
 243         return pinctrl_request_gpio(chip->base + offset);
 244 }
 245
 246 static void em_gio_free(struct gpio_chip *chip, unsigned offset)
 247 {
 248         pinctrl_free_gpio(chip->base + offset);
 249
 250         /* Set the GPIO as an input to ensure that the next GPIO request won't
 251         * drive the GPIO pin as an output.
 252         */
 253         em_gio_direction_input(chip, offset);
 254 }
 255
 256 static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
 257                                  irq_hw_number_t hwirq)
 258 {
 259         struct em_gio_priv *p = h->host_data;
 260
 261         pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
 262
 263         irq_set_chip_data(irq, h->host_data);
 264         irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
 265         set_irq_flags(irq, IRQF_VALID); /* kill me now */
 266         return 0;
 267 }
 268
 269 static const struct irq_domain_ops em_gio_irq_domain_ops = {
 270         .map    = em_gio_irq_domain_map,
 271         .xlate  = irq_domain_xlate_twocell,
 272 };
 273
 274 static int em_gio_probe(struct platform_device *pdev)
 275 {
 276         struct gpio_em_config pdata_dt;
 277         struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
 278         struct em_gio_priv *p;
 279         struct resource *io[2], *irq[2];
 280         struct gpio_chip *gpio_chip;
 281         struct irq_chip *irq_chip;
 282         const char *name = dev_name(&pdev->dev);
 283         int ret;
 284
 285         p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 286         if (!p) {
 287                 ret = -ENOMEM;
 288                 goto err0;
 289         }
 290
 291         p->pdev = pdev;
 292         platform_set_drvdata(pdev, p);
 293         spin_lock_init(&p->sense_lock);
 294
 295         io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 296         io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 297         irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 298         irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 299
 300         if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
 301                 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
 302                 ret = -EINVAL;
 303                 goto err0;
 304         }
 305
 306         p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
 307                                         resource_size(io[0]));
 308         if (!p->base0) {
 309                 dev_err(&pdev->dev, "failed to remap low I/O memory\n");
 310                 ret = -ENXIO;
 311                 goto err0;
 312         }
 313
 314         p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
 315                                    resource_size(io[1]));
 316         if (!p->base1) {
 317                 dev_err(&pdev->dev, "failed to remap high I/O memory\n");
 318                 ret = -ENXIO;
 319                 goto err0;
 320         }
 321
 322         if (!pdata) {
 323                 memset(&pdata_dt, 0, sizeof(pdata_dt));
 324                 pdata = &pdata_dt;
 325
 326                 if (of_property_read_u32(pdev->dev.of_node, "ngpios",
 327                                          &pdata->number_of_pins)) {
 328                         dev_err(&pdev->dev, "Missing ngpios OF property\n");
 329                         ret = -EINVAL;
 330                         goto err0;
 331                 }
 332
 333                 pdata->gpio_base = -1;
 334         }
 335
 336         gpio_chip = &p->gpio_chip;
 337         gpio_chip->of_node = pdev->dev.of_node;
 338         gpio_chip->direction_input = em_gio_direction_input;
 339         gpio_chip->get = em_gio_get;
 340         gpio_chip->direction_output = em_gio_direction_output;
 341         gpio_chip->set = em_gio_set;
 342         gpio_chip->to_irq = em_gio_to_irq;
 343         gpio_chip->request = em_gio_request;
 344         gpio_chip->free = em_gio_free;
 345         gpio_chip->label = name;
 346         gpio_chip->dev = &pdev->dev;
 347         gpio_chip->owner = THIS_MODULE;
 348         gpio_chip->base = pdata->gpio_base;
 349         gpio_chip->ngpio = pdata->number_of_pins;
 350
 351         irq_chip = &p->irq_chip;
 352         irq_chip->name = name;
 353         irq_chip->irq_mask = em_gio_irq_disable;
 354         irq_chip->irq_unmask = em_gio_irq_enable;
 355         irq_chip->irq_set_type = em_gio_irq_set_type;
 356         irq_chip->irq_request_resources = em_gio_irq_reqres;
 357         irq_chip->irq_release_resources = em_gio_irq_relres;
 358         irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
 359
 360         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 361                                               pdata->number_of_pins,
 362                                               pdata->irq_base,
 363                                               &em_gio_irq_domain_ops, p);
 364         if (!p->irq_domain) {
 365                 ret = -ENXIO;
 366                 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 367                 goto err0;
 368         }
 369
 370         if (devm_request_irq(&pdev->dev, irq[0]->start,
 371                              em_gio_irq_handler, 0, name, p)) {
 372                 dev_err(&pdev->dev, "failed to request low IRQ\n");
 373                 ret = -ENOENT;
 374                 goto err1;
 375         }
 376
 377         if (devm_request_irq(&pdev->dev, irq[1]->start,
 378                              em_gio_irq_handler, 0, name, p)) {
 379                 dev_err(&pdev->dev, "failed to request high IRQ\n");
 380                 ret = -ENOENT;
 381                 goto err1;
 382         }
 383
 384         ret = gpiochip_add(gpio_chip);
 385         if (ret) {
 386                 dev_err(&pdev->dev, "failed to add GPIO controller\n");
 387                 goto err1;
 388         }
 389
 390         if (pdata->pctl_name) {
 391                 ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
 392                                              gpio_chip->base, gpio_chip->ngpio);
 393                 if (ret < 0)
 394                         dev_warn(&pdev->dev, "failed to add pin range\n");
 395         }
 396         return 0;
 397
 398 err1:
 399         irq_domain_remove(p->irq_domain);
 400 err0:
 401         return ret;
 402 }
 403
 404 static int em_gio_remove(struct platform_device *pdev)
 405 {
 406         struct em_gio_priv *p = platform_get_drvdata(pdev);
 407
 408         gpiochip_remove(&p->gpio_chip);
 409
 410         irq_domain_remove(p->irq_domain);
 411         return 0;
 412 }
 413
 414 static const struct of_device_id em_gio_dt_ids[] = {
 415         { .compatible = "renesas,em-gio", },
 416         {},
 417 };
 418 MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
 419
 420 static struct platform_driver em_gio_device_driver = {
 421         .probe          = em_gio_probe,
 422         .remove         = em_gio_remove,
 423         .driver         = {
 424                 .name   = "em_gio",
 425                 .of_match_table = em_gio_dt_ids,
 426         }
 427 };
 428
 429 static int __init em_gio_init(void)
 430 {
 431         return platform_driver_register(&em_gio_device_driver);
 432 }
 433 postcore_initcall(em_gio_init);
 434
 435 static void __exit em_gio_exit(void)
 436 {
 437         platform_driver_unregister(&em_gio_device_driver);
 438 }
 439 module_exit(em_gio_exit);
 440
 441 MODULE_AUTHOR("Magnus Damm");
 442 MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
 443 MODULE_LICENSE("GPL v2");