drivers/gpio/gpio-generic.c

   1 /*
   2  * Generic driver for memory-mapped GPIO controllers.
   3  *
   4  * Copyright 2008 MontaVista Software, Inc.
   5  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
  13  * ...``                                                         ```````..
  14  * ..The simplest form of a GPIO controller that the driver supports is``
  15  *  `.just a single "data" register, where GPIO state can be read and/or `
  16  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
  17  *        `````````
  18                                     ___
  19 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
  20 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
  21 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
  22                                                  `....trivial..'~`.```.```
  23  *                                                    ```````
  24  *  .```````~~~~`..`.``.``.
  25  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
  26  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
  27  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
  28  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
  29  *     ``.`.``...```                  ```.. output pins are also supported.`
  30  *                        ^^             `````.`````````.,``~``~``~~``````
  31  *                                                   .                  ^^
  32  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
  33  * .. The expectation is that in at least some cases .    ,-~~~-,
  34  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
  35  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
  36  *  ..````````......```````````                             \o_
  37  *                                                           |
  38  *                              ^^                          / \
  39  *
  40  *           ...`````~~`.....``.`..........``````.`.``.```........``.
  41  *            `  8, 16, 32 and 64 bits registers are supported, and``.
  42  *            . the number of GPIOs is determined by the width of   ~
  43  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
  44  *               `.......````.```
  45  */
  46
  47 #include <linux/init.h>
  48 #include <linux/err.h>
  49 #include <linux/bug.h>
  50 #include <linux/kernel.h>
  51 #include <linux/module.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/compiler.h>
  54 #include <linux/types.h>
  55 #include <linux/errno.h>
  56 #include <linux/log2.h>
  57 #include <linux/ioport.h>
  58 #include <linux/io.h>
  59 #include <linux/gpio.h>
  60 #include <linux/slab.h>
  61 #include <linux/platform_device.h>
  62 #include <linux/mod_devicetable.h>
  63 #include <linux/basic_mmio_gpio.h>
  64
  65 static void bgpio_write8(void __iomem *reg, unsigned long data)
  66 {
  67         writeb(data, reg);
  68 }
  69
  70 static unsigned long bgpio_read8(void __iomem *reg)
  71 {
  72         return readb(reg);
  73 }
  74
  75 static void bgpio_write16(void __iomem *reg, unsigned long data)
  76 {
  77         writew(data, reg);
  78 }
  79
  80 static unsigned long bgpio_read16(void __iomem *reg)
  81 {
  82         return readw(reg);
  83 }
  84
  85 static void bgpio_write32(void __iomem *reg, unsigned long data)
  86 {
  87         writel(data, reg);
  88 }
  89
  90 static unsigned long bgpio_read32(void __iomem *reg)
  91 {
  92         return readl(reg);
  93 }
  94
  95 #if BITS_PER_LONG >= 64
  96 static void bgpio_write64(void __iomem *reg, unsigned long data)
  97 {
  98         writeq(data, reg);
  99 }
 100
 101 static unsigned long bgpio_read64(void __iomem *reg)
 102 {
 103         return readq(reg);
 104 }
 105 #endif /* BITS_PER_LONG >= 64 */
 106
 107 static void bgpio_write16be(void __iomem *reg, unsigned long data)
 108 {
 109         iowrite16be(data, reg);
 110 }
 111
 112 static unsigned long bgpio_read16be(void __iomem *reg)
 113 {
 114         return ioread16be(reg);
 115 }
 116
 117 static void bgpio_write32be(void __iomem *reg, unsigned long data)
 118 {
 119         iowrite32be(data, reg);
 120 }
 121
 122 static unsigned long bgpio_read32be(void __iomem *reg)
 123 {
 124         return ioread32be(reg);
 125 }
 126
 127 static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
 128 {
 129         return 1 << pin;
 130 }
 131
 132 static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
 133                                        unsigned int pin)
 134 {
 135         return 1 << (bgc->bits - 1 - pin);
 136 }
 137
 138 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
 139 {
 140         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 141         unsigned long pinmask = bgc->pin2mask(bgc, gpio);
 142
 143         if (bgc->dir & pinmask)
 144                 return bgc->read_reg(bgc->reg_set) & pinmask;
 145         else
 146                 return bgc->read_reg(bgc->reg_dat) & pinmask;
 147 }
 148
 149 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
 150 {
 151         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 152
 153         return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
 154 }
 155
 156 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 157 {
 158         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 159         unsigned long mask = bgc->pin2mask(bgc, gpio);
 160         unsigned long flags;
 161
 162         spin_lock_irqsave(&bgc->lock, flags);
 163
 164         if (val)
 165                 bgc->data |= mask;
 166         else
 167                 bgc->data &= ~mask;
 168
 169         bgc->write_reg(bgc->reg_dat, bgc->data);
 170
 171         spin_unlock_irqrestore(&bgc->lock, flags);
 172 }
 173
 174 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
 175                                  int val)
 176 {
 177         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 178         unsigned long mask = bgc->pin2mask(bgc, gpio);
 179
 180         if (val)
 181                 bgc->write_reg(bgc->reg_set, mask);
 182         else
 183                 bgc->write_reg(bgc->reg_clr, mask);
 184 }
 185
 186 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
 187 {
 188         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 189         unsigned long mask = bgc->pin2mask(bgc, gpio);
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&bgc->lock, flags);
 193
 194         if (val)
 195                 bgc->data |= mask;
 196         else
 197                 bgc->data &= ~mask;
 198
 199         bgc->write_reg(bgc->reg_set, bgc->data);
 200
 201         spin_unlock_irqrestore(&bgc->lock, flags);
 202 }
 203
 204 static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
 205                                      unsigned long *mask, unsigned long *bits,
 206                                      unsigned long *set_mask,
 207                                      unsigned long *clear_mask)
 208 {
 209         int i;
 210
 211         *set_mask = 0;
 212         *clear_mask = 0;
 213
 214         for (i = 0; i < bgc->bits; i++) {
 215                 if (*mask == 0)
 216                         break;
 217                 if (__test_and_clear_bit(i, mask)) {
 218                         if (test_bit(i, bits))
 219                                 *set_mask |= bgc->pin2mask(bgc, i);
 220                         else
 221                                 *clear_mask |= bgc->pin2mask(bgc, i);
 222                 }
 223         }
 224 }
 225
 226 static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
 227                                           unsigned long *mask,
 228                                           unsigned long *bits,
 229                                           void __iomem *reg)
 230 {
 231         unsigned long flags;
 232         unsigned long set_mask, clear_mask;
 233
 234         spin_lock_irqsave(&bgc->lock, flags);
 235
 236         bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
 237
 238         bgc->data |= set_mask;
 239         bgc->data &= ~clear_mask;
 240
 241         bgc->write_reg(reg, bgc->data);
 242
 243         spin_unlock_irqrestore(&bgc->lock, flags);
 244 }
 245
 246 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 247                                unsigned long *bits)
 248 {
 249         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 250
 251         bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
 252 }
 253
 254 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
 255                                    unsigned long *bits)
 256 {
 257         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 258
 259         bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
 260 }
 261
 262 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
 263                                           unsigned long *mask,
 264                                           unsigned long *bits)
 265 {
 266         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 267         unsigned long set_mask, clear_mask;
 268
 269         bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
 270
 271         if (set_mask)
 272                 bgc->write_reg(bgc->reg_set, set_mask);
 273         if (clear_mask)
 274                 bgc->write_reg(bgc->reg_clr, clear_mask);
 275 }
 276
 277 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
 278 {
 279         return 0;
 280 }
 281
 282 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
 283                                 int val)
 284 {
 285         gc->set(gc, gpio, val);
 286
 287         return 0;
 288 }
 289
 290 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 291 {
 292         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 293         unsigned long flags;
 294
 295         spin_lock_irqsave(&bgc->lock, flags);
 296
 297         bgc->dir &= ~bgc->pin2mask(bgc, gpio);
 298         bgc->write_reg(bgc->reg_dir, bgc->dir);
 299
 300         spin_unlock_irqrestore(&bgc->lock, flags);
 301
 302         return 0;
 303 }
 304
 305 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 306 {
 307         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 308         unsigned long flags;
 309
 310         gc->set(gc, gpio, val);
 311
 312         spin_lock_irqsave(&bgc->lock, flags);
 313
 314         bgc->dir |= bgc->pin2mask(bgc, gpio);
 315         bgc->write_reg(bgc->reg_dir, bgc->dir);
 316
 317         spin_unlock_irqrestore(&bgc->lock, flags);
 318
 319         return 0;
 320 }
 321
 322 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
 323 {
 324         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 325         unsigned long flags;
 326
 327         spin_lock_irqsave(&bgc->lock, flags);
 328
 329         bgc->dir |= bgc->pin2mask(bgc, gpio);
 330         bgc->write_reg(bgc->reg_dir, bgc->dir);
 331
 332         spin_unlock_irqrestore(&bgc->lock, flags);
 333
 334         return 0;
 335 }
 336
 337 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
 338 {
 339         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 340         unsigned long flags;
 341
 342         gc->set(gc, gpio, val);
 343
 344         spin_lock_irqsave(&bgc->lock, flags);
 345
 346         bgc->dir &= ~bgc->pin2mask(bgc, gpio);
 347         bgc->write_reg(bgc->reg_dir, bgc->dir);
 348
 349         spin_unlock_irqrestore(&bgc->lock, flags);
 350
 351         return 0;
 352 }
 353
 354 static int bgpio_setup_accessors(struct device *dev,
 355                                  struct bgpio_chip *bgc,
 356                                  bool bit_be,
 357                                  bool byte_be)
 358 {
 359
 360         switch (bgc->bits) {
 361         case 8:
 362                 bgc->read_reg   = bgpio_read8;
 363                 bgc->write_reg  = bgpio_write8;
 364                 break;
 365         case 16:
 366                 if (byte_be) {
 367                         bgc->read_reg   = bgpio_read16be;
 368                         bgc->write_reg  = bgpio_write16be;
 369                 } else {
 370                         bgc->read_reg   = bgpio_read16;
 371                         bgc->write_reg  = bgpio_write16;
 372                 }
 373                 break;
 374         case 32:
 375                 if (byte_be) {
 376                         bgc->read_reg   = bgpio_read32be;
 377                         bgc->write_reg  = bgpio_write32be;
 378                 } else {
 379                         bgc->read_reg   = bgpio_read32;
 380                         bgc->write_reg  = bgpio_write32;
 381                 }
 382                 break;
 383 #if BITS_PER_LONG >= 64
 384         case 64:
 385                 if (byte_be) {
 386                         dev_err(dev,
 387                                 "64 bit big endian byte order unsupported\n");
 388                         return -EINVAL;
 389                 } else {
 390                         bgc->read_reg   = bgpio_read64;
 391                         bgc->write_reg  = bgpio_write64;
 392                 }
 393                 break;
 394 #endif /* BITS_PER_LONG >= 64 */
 395         default:
 396                 dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
 397                 return -EINVAL;
 398         }
 399
 400         bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
 401
 402         return 0;
 403 }
 404
 405 /*
 406  * Create the device and allocate the resources.  For setting GPIO's there are
 407  * three supported configurations:
 408  *
 409  *      - single input/output register resource (named "dat").
 410  *      - set/clear pair (named "set" and "clr").
 411  *      - single output register resource and single input resource ("set" and
 412  *      dat").
 413  *
 414  * For the single output register, this drives a 1 by setting a bit and a zero
 415  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 416  * in the set register and clears it by setting a bit in the clear register.
 417  * The configuration is detected by which resources are present.
 418  *
 419  * For setting the GPIO direction, there are three supported configurations:
 420  *
 421  *      - simple bidirection GPIO that requires no configuration.
 422  *      - an output direction register (named "dirout") where a 1 bit
 423  *      indicates the GPIO is an output.
 424  *      - an input direction register (named "dirin") where a 1 bit indicates
 425  *      the GPIO is an input.
 426  */
 427 static int bgpio_setup_io(struct bgpio_chip *bgc,
 428                           void __iomem *dat,
 429                           void __iomem *set,
 430                           void __iomem *clr,
 431                           unsigned long flags)
 432 {
 433
 434         bgc->reg_dat = dat;
 435         if (!bgc->reg_dat)
 436                 return -EINVAL;
 437
 438         if (set && clr) {
 439                 bgc->reg_set = set;
 440                 bgc->reg_clr = clr;
 441                 bgc->gc.set = bgpio_set_with_clear;
 442                 bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
 443         } else if (set && !clr) {
 444                 bgc->reg_set = set;
 445                 bgc->gc.set = bgpio_set_set;
 446                 bgc->gc.set_multiple = bgpio_set_multiple_set;
 447         } else {
 448                 bgc->gc.set = bgpio_set;
 449                 bgc->gc.set_multiple = bgpio_set_multiple;
 450         }
 451
 452         if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
 453             (flags & BGPIOF_READ_OUTPUT_REG_SET))
 454                 bgc->gc.get = bgpio_get_set;
 455         else
 456                 bgc->gc.get = bgpio_get;
 457
 458         return 0;
 459 }
 460
 461 static int bgpio_setup_direction(struct bgpio_chip *bgc,
 462                                  void __iomem *dirout,
 463                                  void __iomem *dirin)
 464 {
 465         if (dirout && dirin) {
 466                 return -EINVAL;
 467         } else if (dirout) {
 468                 bgc->reg_dir = dirout;
 469                 bgc->gc.direction_output = bgpio_dir_out;
 470                 bgc->gc.direction_input = bgpio_dir_in;
 471         } else if (dirin) {
 472                 bgc->reg_dir = dirin;
 473                 bgc->gc.direction_output = bgpio_dir_out_inv;
 474                 bgc->gc.direction_input = bgpio_dir_in_inv;
 475         } else {
 476                 bgc->gc.direction_output = bgpio_simple_dir_out;
 477                 bgc->gc.direction_input = bgpio_simple_dir_in;
 478         }
 479
 480         return 0;
 481 }
 482
 483 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
 484 {
 485         if (gpio_pin < chip->ngpio)
 486                 return 0;
 487
 488         return -EINVAL;
 489 }
 490
 491 int bgpio_remove(struct bgpio_chip *bgc)
 492 {
 493         gpiochip_remove(&bgc->gc);
 494         return 0;
 495 }
 496 EXPORT_SYMBOL_GPL(bgpio_remove);
 497
 498 int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
 499                unsigned long sz, void __iomem *dat, void __iomem *set,
 500                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
 501                unsigned long flags)
 502 {
 503         int ret;
 504
 505         if (!is_power_of_2(sz))
 506                 return -EINVAL;
 507
 508         bgc->bits = sz * 8;
 509         if (bgc->bits > BITS_PER_LONG)
 510                 return -EINVAL;
 511
 512         spin_lock_init(&bgc->lock);
 513         bgc->gc.dev = dev;
 514         bgc->gc.label = dev_name(dev);
 515         bgc->gc.base = -1;
 516         bgc->gc.ngpio = bgc->bits;
 517         bgc->gc.request = bgpio_request;
 518
 519         ret = bgpio_setup_io(bgc, dat, set, clr, flags);
 520         if (ret)
 521                 return ret;
 522
 523         ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
 524                                     flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 525         if (ret)
 526                 return ret;
 527
 528         ret = bgpio_setup_direction(bgc, dirout, dirin);
 529         if (ret)
 530                 return ret;
 531
 532         bgc->data = bgc->read_reg(bgc->reg_dat);
 533         if (bgc->gc.set == bgpio_set_set &&
 534                         !(flags & BGPIOF_UNREADABLE_REG_SET))
 535                 bgc->data = bgc->read_reg(bgc->reg_set);
 536         if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
 537                 bgc->dir = bgc->read_reg(bgc->reg_dir);
 538
 539         return ret;
 540 }
 541 EXPORT_SYMBOL_GPL(bgpio_init);
 542
 543 #ifdef CONFIG_GPIO_GENERIC_PLATFORM
 544
 545 static void __iomem *bgpio_map(struct platform_device *pdev,
 546                                const char *name,
 547                                resource_size_t sane_sz,
 548                                int *err)
 549 {
 550         struct device *dev = &pdev->dev;
 551         struct resource *r;
 552         resource_size_t start;
 553         resource_size_t sz;
 554         void __iomem *ret;
 555
 556         *err = 0;
 557
 558         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 559         if (!r)
 560                 return NULL;
 561
 562         sz = resource_size(r);
 563         if (sz != sane_sz) {
 564                 *err = -EINVAL;
 565                 return NULL;
 566         }
 567
 568         start = r->start;
 569         if (!devm_request_mem_region(dev, start, sz, r->name)) {
 570                 *err = -EBUSY;
 571                 return NULL;
 572         }
 573
 574         ret = devm_ioremap(dev, start, sz);
 575         if (!ret) {
 576                 *err = -ENOMEM;
 577                 return NULL;
 578         }
 579
 580         return ret;
 581 }
 582
 583 static int bgpio_pdev_probe(struct platform_device *pdev)
 584 {
 585         struct device *dev = &pdev->dev;
 586         struct resource *r;
 587         void __iomem *dat;
 588         void __iomem *set;
 589         void __iomem *clr;
 590         void __iomem *dirout;
 591         void __iomem *dirin;
 592         unsigned long sz;
 593         unsigned long flags = pdev->id_entry->driver_data;
 594         int err;
 595         struct bgpio_chip *bgc;
 596         struct bgpio_pdata *pdata = dev_get_platdata(dev);
 597
 598         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
 599         if (!r)
 600                 return -EINVAL;
 601
 602         sz = resource_size(r);
 603
 604         dat = bgpio_map(pdev, "dat", sz, &err);
 605         if (!dat)
 606                 return err ? err : -EINVAL;
 607
 608         set = bgpio_map(pdev, "set", sz, &err);
 609         if (err)
 610                 return err;
 611
 612         clr = bgpio_map(pdev, "clr", sz, &err);
 613         if (err)
 614                 return err;
 615
 616         dirout = bgpio_map(pdev, "dirout", sz, &err);
 617         if (err)
 618                 return err;
 619
 620         dirin = bgpio_map(pdev, "dirin", sz, &err);
 621         if (err)
 622                 return err;
 623
 624         bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
 625         if (!bgc)
 626                 return -ENOMEM;
 627
 628         err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
 629         if (err)
 630                 return err;
 631
 632         if (pdata) {
 633                 if (pdata->label)
 634                         bgc->gc.label = pdata->label;
 635                 bgc->gc.base = pdata->base;
 636                 if (pdata->ngpio > 0)
 637                         bgc->gc.ngpio = pdata->ngpio;
 638         }
 639
 640         platform_set_drvdata(pdev, bgc);
 641
 642         return gpiochip_add(&bgc->gc);
 643 }
 644
 645 static int bgpio_pdev_remove(struct platform_device *pdev)
 646 {
 647         struct bgpio_chip *bgc = platform_get_drvdata(pdev);
 648
 649         return bgpio_remove(bgc);
 650 }
 651
 652 static const struct platform_device_id bgpio_id_table[] = {
 653         {
 654                 .name           = "basic-mmio-gpio",
 655                 .driver_data    = 0,
 656         }, {
 657                 .name           = "basic-mmio-gpio-be",
 658                 .driver_data    = BGPIOF_BIG_ENDIAN,
 659         },
 660         { }
 661 };
 662 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
 663
 664 static struct platform_driver bgpio_driver = {
 665         .driver = {
 666                 .name = "basic-mmio-gpio",
 667         },
 668         .id_table = bgpio_id_table,
 669         .probe = bgpio_pdev_probe,
 670         .remove = bgpio_pdev_remove,
 671 };
 672
 673 module_platform_driver(bgpio_driver);
 674
 675 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
 676
 677 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
 678 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
 679 MODULE_LICENSE("GPL");