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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpio / gpio-lynxpoint.c
blob153af464c7a780e7ef57c8ba15e3e7d7b5307ede
1 /*
2 * GPIO controller driver for Intel Lynxpoint PCH chipset>
3 * Copyright (c) 2012, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/gpio.h>
29 #include <linux/slab.h>
30 #include <linux/acpi.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/io.h>
34
35 /* LynxPoint chipset has support for 94 gpio pins */
36
37 #define LP_NUM_GPIO 94
38
39 /* Bitmapped register offsets */
40 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
41 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
42 #define LP_INT_STAT 0x80
43 #define LP_INT_ENABLE 0x90
44
45 /* Each pin has two 32 bit config registers, starting at 0x100 */
46 #define LP_CONFIG1 0x100
47 #define LP_CONFIG2 0x104
48
49 /* LP_CONFIG1 reg bits */
50 #define OUT_LVL_BIT BIT(31)
51 #define IN_LVL_BIT BIT(30)
52 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
53 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
54 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */
55 #define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
56
57 /* LP_CONFIG2 reg bits */
58 #define GPINDIS_BIT BIT(2) /* disable input sensing */
59 #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
60
61 struct lp_gpio {
62 struct gpio_chip chip;
63 struct platform_device *pdev;
64 spinlock_t lock;
65 unsigned long reg_base;
66 };
67
68 /*
69 * Lynxpoint gpios are controlled through both bitmapped registers and
70 * per gpio specific registers. The bitmapped registers are in chunks of
71 * 3 x 32bit registers to cover all 94 gpios
72 *
73 * per gpio specific registers consist of two 32bit registers per gpio
74 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
75 * 188 config registers.
76 *
77 * A simplified view of the register layout look like this:
78 *
79 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
80 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
81 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
82 * ...
83 * LP_INT_ENABLE[31:0] ...
84 * LP_INT_ENABLE[63:31] ...
85 * LP_INT_ENABLE[94:64] ...
86 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
87 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
88 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
89 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
90 * LP2_CONFIG1 (gpio 2) ...
91 * LP2_CONFIG2 (gpio 2) ...
92 * ...
93 * LP94_CONFIG1 (gpio 94) ...
94 * LP94_CONFIG2 (gpio 94) ...
95 */
96
97 static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
98 int reg)
99 {
100 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
101 int reg_offset;
102
103 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
104 /* per gpio specific config registers */
105 reg_offset = offset * 8;
106 else
107 /* bitmapped registers */
108 reg_offset = (offset / 32) * 4;
109
110 return lg->reg_base + reg + reg_offset;
111 }
112
113 static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
114 {
115 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
116 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
117 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
118 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
119
120 pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
121
122 /* Fail if BIOS reserved pin for ACPI use */
123 if (!(inl(acpi_use) & BIT(offset % 32))) {
124 dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
125 return -EBUSY;
126 }
127 /* Fail if pin is in alternate function mode (not GPIO mode) */
128 if (!(inl(reg) & USE_SEL_BIT))
129 return -ENODEV;
130
131 /* enable input sensing */
132 outl(inl(conf2) & ~GPINDIS_BIT, conf2);
133
134
135 return 0;
136 }
137
138 static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
139 {
140 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
141 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
142
143 /* disable input sensing */
144 outl(inl(conf2) | GPINDIS_BIT, conf2);
145
146 pm_runtime_put(&lg->pdev->dev);
147 }
148
149 static int lp_irq_type(struct irq_data *d, unsigned type)
150 {
151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
152 struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
153 u32 hwirq = irqd_to_hwirq(d);
154 unsigned long flags;
155 u32 value;
156 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
157
158 if (hwirq >= lg->chip.ngpio)
159 return -EINVAL;
160
161 spin_lock_irqsave(&lg->lock, flags);
162 value = inl(reg);
163
164 /* set both TRIG_SEL and INV bits to 0 for rising edge */
165 if (type & IRQ_TYPE_EDGE_RISING)
166 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
167
168 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
169 if (type & IRQ_TYPE_EDGE_FALLING)
170 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
171
172 /* TRIG_SEL bit 1, INV bit 0 for level low */
173 if (type & IRQ_TYPE_LEVEL_LOW)
174 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
175
176 /* TRIG_SEL bit 1, INV bit 1 for level high */
177 if (type & IRQ_TYPE_LEVEL_HIGH)
178 value |= TRIG_SEL_BIT | INT_INV_BIT;
179
180 outl(value, reg);
181 spin_unlock_irqrestore(&lg->lock, flags);
182
183 return 0;
184 }
185
186 static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
187 {
188 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
189 return !!(inl(reg) & IN_LVL_BIT);
190 }
191
192 static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
193 {
194 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
195 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
196 unsigned long flags;
197
198 spin_lock_irqsave(&lg->lock, flags);
199
200 if (value)
201 outl(inl(reg) | OUT_LVL_BIT, reg);
202 else
203 outl(inl(reg) & ~OUT_LVL_BIT, reg);
204
205 spin_unlock_irqrestore(&lg->lock, flags);
206 }
207
208 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
209 {
210 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
211 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
212 unsigned long flags;
213
214 spin_lock_irqsave(&lg->lock, flags);
215 outl(inl(reg) | DIR_BIT, reg);
216 spin_unlock_irqrestore(&lg->lock, flags);
217
218 return 0;
219 }
220
221 static int lp_gpio_direction_output(struct gpio_chip *chip,
222 unsigned offset, int value)
223 {
224 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
225 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
226 unsigned long flags;
227
228 lp_gpio_set(chip, offset, value);
229
230 spin_lock_irqsave(&lg->lock, flags);
231 outl(inl(reg) & ~DIR_BIT, reg);
232 spin_unlock_irqrestore(&lg->lock, flags);
233
234 return 0;
235 }
236
237 static void lp_gpio_irq_handler(unsigned hwirq, struct irq_desc *desc)
238 {
239 struct irq_data *data = irq_desc_get_irq_data(desc);
240 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
241 struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
242 struct irq_chip *chip = irq_data_get_irq_chip(data);
243 u32 base, pin, mask;
244 unsigned long reg, ena, pending;
245
246 /* check from GPIO controller which pin triggered the interrupt */
247 for (base = 0; base < lg->chip.ngpio; base += 32) {
248 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
249 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
250
251 while ((pending = (inl(reg) & inl(ena)))) {
252 unsigned irq;
253
254 pin = __ffs(pending);
255 mask = BIT(pin);
256 /* Clear before handling so we don't lose an edge */
257 outl(mask, reg);
258 irq = irq_find_mapping(lg->chip.irqdomain, base + pin);
259 generic_handle_irq(irq);
260 }
261 }
262 chip->irq_eoi(data);
263 }
264
265 static void lp_irq_unmask(struct irq_data *d)
266 {
267 }
268
269 static void lp_irq_mask(struct irq_data *d)
270 {
271 }
272
273 static void lp_irq_enable(struct irq_data *d)
274 {
275 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
276 struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
277 u32 hwirq = irqd_to_hwirq(d);
278 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
279 unsigned long flags;
280
281 spin_lock_irqsave(&lg->lock, flags);
282 outl(inl(reg) | BIT(hwirq % 32), reg);
283 spin_unlock_irqrestore(&lg->lock, flags);
284 }
285
286 static void lp_irq_disable(struct irq_data *d)
287 {
288 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
289 struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
290 u32 hwirq = irqd_to_hwirq(d);
291 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
292 unsigned long flags;
293
294 spin_lock_irqsave(&lg->lock, flags);
295 outl(inl(reg) & ~BIT(hwirq % 32), reg);
296 spin_unlock_irqrestore(&lg->lock, flags);
297 }
298
299 static struct irq_chip lp_irqchip = {
300 .name = "LP-GPIO",
301 .irq_mask = lp_irq_mask,
302 .irq_unmask = lp_irq_unmask,
303 .irq_enable = lp_irq_enable,
304 .irq_disable = lp_irq_disable,
305 .irq_set_type = lp_irq_type,
306 .flags = IRQCHIP_SKIP_SET_WAKE,
307 };
308
309 static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
310 {
311 unsigned long reg;
312 unsigned base;
313
314 for (base = 0; base < lg->chip.ngpio; base += 32) {
315 /* disable gpio pin interrupts */
316 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
317 outl(0, reg);
318 /* Clear interrupt status register */
319 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
320 outl(0xffffffff, reg);
321 }
322 }
323
324 static int lp_gpio_probe(struct platform_device *pdev)
325 {
326 struct lp_gpio *lg;
327 struct gpio_chip *gc;
328 struct resource *io_rc, *irq_rc;
329 struct device *dev = &pdev->dev;
330 unsigned long reg_len;
331 int ret = -ENODEV;
332
333 lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
334 if (!lg)
335 return -ENOMEM;
336
337 lg->pdev = pdev;
338 platform_set_drvdata(pdev, lg);
339
340 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
341 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
342
343 if (!io_rc) {
344 dev_err(dev, "missing IO resources\n");
345 return -EINVAL;
346 }
347
348 lg->reg_base = io_rc->start;
349 reg_len = resource_size(io_rc);
350
351 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
352 dev_err(dev, "failed requesting IO region 0x%x\n",
353 (unsigned int)lg->reg_base);
354 return -EBUSY;
355 }
356
357 spin_lock_init(&lg->lock);
358
359 gc = &lg->chip;
360 gc->label = dev_name(dev);
361 gc->owner = THIS_MODULE;
362 gc->request = lp_gpio_request;
363 gc->free = lp_gpio_free;
364 gc->direction_input = lp_gpio_direction_input;
365 gc->direction_output = lp_gpio_direction_output;
366 gc->get = lp_gpio_get;
367 gc->set = lp_gpio_set;
368 gc->base = -1;
369 gc->ngpio = LP_NUM_GPIO;
370 gc->can_sleep = false;
371 gc->dev = dev;
372
373 ret = gpiochip_add(gc);
374 if (ret) {
375 dev_err(dev, "failed adding lp-gpio chip\n");
376 return ret;
377 }
378
379 /* set up interrupts */
380 if (irq_rc && irq_rc->start) {
381 lp_gpio_irq_init_hw(lg);
382 ret = gpiochip_irqchip_add(gc, &lp_irqchip, 0,
383 handle_simple_irq, IRQ_TYPE_NONE);
384 if (ret) {
385 dev_err(dev, "failed to add irqchip\n");
386 gpiochip_remove(gc);
387 return ret;
388 }
389
390 gpiochip_set_chained_irqchip(gc, &lp_irqchip,
391 (unsigned)irq_rc->start,
392 lp_gpio_irq_handler);
393 }
394
395 pm_runtime_enable(dev);
396
397 return 0;
398 }
399
400 static int lp_gpio_runtime_suspend(struct device *dev)
401 {
402 return 0;
403 }
404
405 static int lp_gpio_runtime_resume(struct device *dev)
406 {
407 return 0;
408 }
409
410 static int lp_gpio_resume(struct device *dev)
411 {
412 struct platform_device *pdev = to_platform_device(dev);
413 struct lp_gpio *lg = platform_get_drvdata(pdev);
414 unsigned long reg;
415 int i;
416
417 /* on some hardware suspend clears input sensing, re-enable it here */
418 for (i = 0; i < lg->chip.ngpio; i++) {
419 if (gpiochip_is_requested(&lg->chip, i) != NULL) {
420 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
421 outl(inl(reg) & ~GPINDIS_BIT, reg);
422 }
423 }
424 return 0;
425 }
426
427 static const struct dev_pm_ops lp_gpio_pm_ops = {
428 .runtime_suspend = lp_gpio_runtime_suspend,
429 .runtime_resume = lp_gpio_runtime_resume,
430 .resume = lp_gpio_resume,
431 };
432
433 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
434 { "INT33C7", 0 },
435 { "INT3437", 0 },
436 { }
437 };
438 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
439
440 static int lp_gpio_remove(struct platform_device *pdev)
441 {
442 struct lp_gpio *lg = platform_get_drvdata(pdev);
443 pm_runtime_disable(&pdev->dev);
444 gpiochip_remove(&lg->chip);
445 return 0;
446 }
447
448 static struct platform_driver lp_gpio_driver = {
449 .probe = lp_gpio_probe,
450 .remove = lp_gpio_remove,
451 .driver = {
452 .name = "lp_gpio",
453 .pm = &lp_gpio_pm_ops,
454 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
455 },
456 };
457
458 static int __init lp_gpio_init(void)
459 {
460 return platform_driver_register(&lp_gpio_driver);
461 }
462
463 static void __exit lp_gpio_exit(void)
464 {
465 platform_driver_unregister(&lp_gpio_driver);
466 }
467
468 subsys_initcall(lp_gpio_init);
469 module_exit(lp_gpio_exit);
470
471 MODULE_AUTHOR("Mathias Nyman (Intel)");
472 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
473 MODULE_LICENSE("GPL");
474 MODULE_ALIAS("platform:lp_gpio");
Linux with added FPC-III support