drivers/gpio/gpio-mxc.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/gpio.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/slab.h>
  32 #include <linux/basic_mmio_gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/module.h>
  36 #include <asm-generic/bug.h>
  37
  38 enum mxc_gpio_hwtype {
  39         IMX1_GPIO,      /* runs on i.mx1 */
  40         IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
  41         IMX31_GPIO,     /* runs on i.mx31 */
  42         IMX35_GPIO,     /* runs on all other i.mx */
  43 };
  44
  45 /* device type dependent stuff */
  46 struct mxc_gpio_hwdata {
  47         unsigned dr_reg;
  48         unsigned gdir_reg;
  49         unsigned psr_reg;
  50         unsigned icr1_reg;
  51         unsigned icr2_reg;
  52         unsigned imr_reg;
  53         unsigned isr_reg;
  54         int edge_sel_reg;
  55         unsigned low_level;
  56         unsigned high_level;
  57         unsigned rise_edge;
  58         unsigned fall_edge;
  59 };
  60
  61 struct mxc_gpio_port {
  62         struct list_head node;
  63         void __iomem *base;
  64         int irq;
  65         int irq_high;
  66         struct irq_domain *domain;
  67         struct bgpio_chip bgc;
  68         u32 both_edges;
  69 };
  70
  71 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  72         .dr_reg         = 0x1c,
  73         .gdir_reg       = 0x00,
  74         .psr_reg        = 0x24,
  75         .icr1_reg       = 0x28,
  76         .icr2_reg       = 0x2c,
  77         .imr_reg        = 0x30,
  78         .isr_reg        = 0x34,
  79         .edge_sel_reg   = -EINVAL,
  80         .low_level      = 0x03,
  81         .high_level     = 0x02,
  82         .rise_edge      = 0x00,
  83         .fall_edge      = 0x01,
  84 };
  85
  86 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  87         .dr_reg         = 0x00,
  88         .gdir_reg       = 0x04,
  89         .psr_reg        = 0x08,
  90         .icr1_reg       = 0x0c,
  91         .icr2_reg       = 0x10,
  92         .imr_reg        = 0x14,
  93         .isr_reg        = 0x18,
  94         .edge_sel_reg   = -EINVAL,
  95         .low_level      = 0x00,
  96         .high_level     = 0x01,
  97         .rise_edge      = 0x02,
  98         .fall_edge      = 0x03,
  99 };
 100
 101 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
 102         .dr_reg         = 0x00,
 103         .gdir_reg       = 0x04,
 104         .psr_reg        = 0x08,
 105         .icr1_reg       = 0x0c,
 106         .icr2_reg       = 0x10,
 107         .imr_reg        = 0x14,
 108         .isr_reg        = 0x18,
 109         .edge_sel_reg   = 0x1c,
 110         .low_level      = 0x00,
 111         .high_level     = 0x01,
 112         .rise_edge      = 0x02,
 113         .fall_edge      = 0x03,
 114 };
 115
 116 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
 117 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
 118
 119 #define GPIO_DR                 (mxc_gpio_hwdata->dr_reg)
 120 #define GPIO_GDIR               (mxc_gpio_hwdata->gdir_reg)
 121 #define GPIO_PSR                (mxc_gpio_hwdata->psr_reg)
 122 #define GPIO_ICR1               (mxc_gpio_hwdata->icr1_reg)
 123 #define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 124 #define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 125 #define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
 126 #define GPIO_EDGE_SEL           (mxc_gpio_hwdata->edge_sel_reg)
 127
 128 #define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 129 #define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 130 #define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 131 #define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
 132 #define GPIO_INT_BOTH_EDGES     0x4
 133
 134 static const struct platform_device_id mxc_gpio_devtype[] = {
 135         {
 136                 .name = "imx1-gpio",
 137                 .driver_data = IMX1_GPIO,
 138         }, {
 139                 .name = "imx21-gpio",
 140                 .driver_data = IMX21_GPIO,
 141         }, {
 142                 .name = "imx31-gpio",
 143                 .driver_data = IMX31_GPIO,
 144         }, {
 145                 .name = "imx35-gpio",
 146                 .driver_data = IMX35_GPIO,
 147         }, {
 148                 /* sentinel */
 149         }
 150 };
 151
 152 static const struct of_device_id mxc_gpio_dt_ids[] = {
 153         { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
 154         { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
 155         { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
 156         { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
 157         { /* sentinel */ }
 158 };
 159
 160 /*
 161  * MX2 has one interrupt *for all* gpio ports. The list is used
 162  * to save the references to all ports, so that mx2_gpio_irq_handler
 163  * can walk through all interrupt status registers.
 164  */
 165 static LIST_HEAD(mxc_gpio_ports);
 166
 167 /* Note: This driver assumes 32 GPIOs are handled in one register */
 168
 169 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 170 {
 171         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 172         struct mxc_gpio_port *port = gc->private;
 173         u32 bit, val;
 174         u32 gpio_idx = d->hwirq;
 175         u32 gpio = port->bgc.gc.base + gpio_idx;
 176         int edge;
 177         void __iomem *reg = port->base;
 178
 179         port->both_edges &= ~(1 << gpio_idx);
 180         switch (type) {
 181         case IRQ_TYPE_EDGE_RISING:
 182                 edge = GPIO_INT_RISE_EDGE;
 183                 break;
 184         case IRQ_TYPE_EDGE_FALLING:
 185                 edge = GPIO_INT_FALL_EDGE;
 186                 break;
 187         case IRQ_TYPE_EDGE_BOTH:
 188                 if (GPIO_EDGE_SEL >= 0) {
 189                         edge = GPIO_INT_BOTH_EDGES;
 190                 } else {
 191                         val = gpio_get_value(gpio);
 192                         if (val) {
 193                                 edge = GPIO_INT_LOW_LEV;
 194                                 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 195                         } else {
 196                                 edge = GPIO_INT_HIGH_LEV;
 197                                 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 198                         }
 199                         port->both_edges |= 1 << gpio_idx;
 200                 }
 201                 break;
 202         case IRQ_TYPE_LEVEL_LOW:
 203                 edge = GPIO_INT_LOW_LEV;
 204                 break;
 205         case IRQ_TYPE_LEVEL_HIGH:
 206                 edge = GPIO_INT_HIGH_LEV;
 207                 break;
 208         default:
 209                 return -EINVAL;
 210         }
 211
 212         if (GPIO_EDGE_SEL >= 0) {
 213                 val = readl(port->base + GPIO_EDGE_SEL);
 214                 if (edge == GPIO_INT_BOTH_EDGES)
 215                         writel(val | (1 << gpio_idx),
 216                                 port->base + GPIO_EDGE_SEL);
 217                 else
 218                         writel(val & ~(1 << gpio_idx),
 219                                 port->base + GPIO_EDGE_SEL);
 220         }
 221
 222         if (edge != GPIO_INT_BOTH_EDGES) {
 223                 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
 224                 bit = gpio_idx & 0xf;
 225                 val = readl(reg) & ~(0x3 << (bit << 1));
 226                 writel(val | (edge << (bit << 1)), reg);
 227         }
 228
 229         writel(1 << gpio_idx, port->base + GPIO_ISR);
 230
 231         return 0;
 232 }
 233
 234 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 235 {
 236         void __iomem *reg = port->base;
 237         u32 bit, val;
 238         int edge;
 239
 240         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 241         bit = gpio & 0xf;
 242         val = readl(reg);
 243         edge = (val >> (bit << 1)) & 3;
 244         val &= ~(0x3 << (bit << 1));
 245         if (edge == GPIO_INT_HIGH_LEV) {
 246                 edge = GPIO_INT_LOW_LEV;
 247                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 248         } else if (edge == GPIO_INT_LOW_LEV) {
 249                 edge = GPIO_INT_HIGH_LEV;
 250                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 251         } else {
 252                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 253                        gpio, edge);
 254                 return;
 255         }
 256         writel(val | (edge << (bit << 1)), reg);
 257 }
 258
 259 /* handle 32 interrupts in one status register */
 260 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 261 {
 262         while (irq_stat != 0) {
 263                 int irqoffset = fls(irq_stat) - 1;
 264
 265                 if (port->both_edges & (1 << irqoffset))
 266                         mxc_flip_edge(port, irqoffset);
 267
 268                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 269
 270                 irq_stat &= ~(1 << irqoffset);
 271         }
 272 }
 273
 274 /* MX1 and MX3 has one interrupt *per* gpio port */
 275 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 276 {
 277         u32 irq_stat;
 278         struct mxc_gpio_port *port = irq_get_handler_data(irq);
 279         struct irq_chip *chip = irq_get_chip(irq);
 280
 281         chained_irq_enter(chip, desc);
 282
 283         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 284
 285         mxc_gpio_irq_handler(port, irq_stat);
 286
 287         chained_irq_exit(chip, desc);
 288 }
 289
 290 /* MX2 has one interrupt *for all* gpio ports */
 291 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 292 {
 293         u32 irq_msk, irq_stat;
 294         struct mxc_gpio_port *port;
 295         struct irq_chip *chip = irq_get_chip(irq);
 296
 297         chained_irq_enter(chip, desc);
 298
 299         /* walk through all interrupt status registers */
 300         list_for_each_entry(port, &mxc_gpio_ports, node) {
 301                 irq_msk = readl(port->base + GPIO_IMR);
 302                 if (!irq_msk)
 303                         continue;
 304
 305                 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 306                 if (irq_stat)
 307                         mxc_gpio_irq_handler(port, irq_stat);
 308         }
 309         chained_irq_exit(chip, desc);
 310 }
 311
 312 /*
 313  * Set interrupt number "irq" in the GPIO as a wake-up source.
 314  * While system is running, all registered GPIO interrupts need to have
 315  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 316  * need to have wake-up enabled.
 317  * @param  irq          interrupt source number
 318  * @param  enable       enable as wake-up if equal to non-zero
 319  * @return       This function returns 0 on success.
 320  */
 321 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 322 {
 323         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 324         struct mxc_gpio_port *port = gc->private;
 325         u32 gpio_idx = d->hwirq;
 326
 327         if (enable) {
 328                 if (port->irq_high && (gpio_idx >= 16))
 329                         enable_irq_wake(port->irq_high);
 330                 else
 331                         enable_irq_wake(port->irq);
 332         } else {
 333                 if (port->irq_high && (gpio_idx >= 16))
 334                         disable_irq_wake(port->irq_high);
 335                 else
 336                         disable_irq_wake(port->irq);
 337         }
 338
 339         return 0;
 340 }
 341
 342 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
 343 {
 344         struct irq_chip_generic *gc;
 345         struct irq_chip_type *ct;
 346
 347         gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
 348                                     port->base, handle_level_irq);
 349         gc->private = port;
 350
 351         ct = gc->chip_types;
 352         ct->chip.irq_ack = irq_gc_ack_set_bit;
 353         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 354         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 355         ct->chip.irq_set_type = gpio_set_irq_type;
 356         ct->chip.irq_set_wake = gpio_set_wake_irq;
 357         ct->regs.ack = GPIO_ISR;
 358         ct->regs.mask = GPIO_IMR;
 359
 360         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 361                                IRQ_NOREQUEST, 0);
 362 }
 363
 364 static void mxc_gpio_get_hw(struct platform_device *pdev)
 365 {
 366         const struct of_device_id *of_id =
 367                         of_match_device(mxc_gpio_dt_ids, &pdev->dev);
 368         enum mxc_gpio_hwtype hwtype;
 369
 370         if (of_id)
 371                 pdev->id_entry = of_id->data;
 372         hwtype = pdev->id_entry->driver_data;
 373
 374         if (mxc_gpio_hwtype) {
 375                 /*
 376                  * The driver works with a reasonable presupposition,
 377                  * that is all gpio ports must be the same type when
 378                  * running on one soc.
 379                  */
 380                 BUG_ON(mxc_gpio_hwtype != hwtype);
 381                 return;
 382         }
 383
 384         if (hwtype == IMX35_GPIO)
 385                 mxc_gpio_hwdata = &imx35_gpio_hwdata;
 386         else if (hwtype == IMX31_GPIO)
 387                 mxc_gpio_hwdata = &imx31_gpio_hwdata;
 388         else
 389                 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
 390
 391         mxc_gpio_hwtype = hwtype;
 392 }
 393
 394 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 395 {
 396         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 397         struct mxc_gpio_port *port =
 398                 container_of(bgc, struct mxc_gpio_port, bgc);
 399
 400         return irq_find_mapping(port->domain, offset);
 401 }
 402
 403 static int mxc_gpio_probe(struct platform_device *pdev)
 404 {
 405         struct device_node *np = pdev->dev.of_node;
 406         struct mxc_gpio_port *port;
 407         struct resource *iores;
 408         int irq_base;
 409         int err;
 410
 411         mxc_gpio_get_hw(pdev);
 412
 413         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 414         if (!port)
 415                 return -ENOMEM;
 416
 417         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 418         port->base = devm_ioremap_resource(&pdev->dev, iores);
 419         if (IS_ERR(port->base))
 420                 return PTR_ERR(port->base);
 421
 422         port->irq_high = platform_get_irq(pdev, 1);
 423         port->irq = platform_get_irq(pdev, 0);
 424         if (port->irq < 0)
 425                 return port->irq;
 426
 427         /* disable the interrupt and clear the status */
 428         writel(0, port->base + GPIO_IMR);
 429         writel(~0, port->base + GPIO_ISR);
 430
 431         if (mxc_gpio_hwtype == IMX21_GPIO) {
 432                 /*
 433                  * Setup one handler for all GPIO interrupts. Actually setting
 434                  * the handler is needed only once, but doing it for every port
 435                  * is more robust and easier.
 436                  */
 437                 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
 438         } else {
 439                 /* setup one handler for each entry */
 440                 irq_set_chained_handler_and_data(port->irq,
 441                                                  mx3_gpio_irq_handler, port);
 442                 if (port->irq_high > 0)
 443                         /* setup handler for GPIO 16 to 31 */
 444                         irq_set_chained_handler_and_data(port->irq_high,
 445                                                          mx3_gpio_irq_handler,
 446                                                          port);
 447         }
 448
 449         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 450                          port->base + GPIO_PSR,
 451                          port->base + GPIO_DR, NULL,
 452                          port->base + GPIO_GDIR, NULL,
 453                          BGPIOF_READ_OUTPUT_REG_SET);
 454         if (err)
 455                 goto out_bgio;
 456
 457         port->bgc.gc.to_irq = mxc_gpio_to_irq;
 458         port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
 459                                              pdev->id * 32;
 460
 461         err = gpiochip_add(&port->bgc.gc);
 462         if (err)
 463                 goto out_bgpio_remove;
 464
 465         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 466         if (irq_base < 0) {
 467                 err = irq_base;
 468                 goto out_gpiochip_remove;
 469         }
 470
 471         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 472                                              &irq_domain_simple_ops, NULL);
 473         if (!port->domain) {
 474                 err = -ENODEV;
 475                 goto out_irqdesc_free;
 476         }
 477
 478         /* gpio-mxc can be a generic irq chip */
 479         mxc_gpio_init_gc(port, irq_base);
 480
 481         list_add_tail(&port->node, &mxc_gpio_ports);
 482
 483         return 0;
 484
 485 out_irqdesc_free:
 486         irq_free_descs(irq_base, 32);
 487 out_gpiochip_remove:
 488         gpiochip_remove(&port->bgc.gc);
 489 out_bgpio_remove:
 490         bgpio_remove(&port->bgc);
 491 out_bgio:
 492         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 493         return err;
 494 }
 495
 496 static struct platform_driver mxc_gpio_driver = {
 497         .driver         = {
 498                 .name   = "gpio-mxc",
 499                 .of_match_table = mxc_gpio_dt_ids,
 500         },
 501         .probe          = mxc_gpio_probe,
 502         .id_table       = mxc_gpio_devtype,
 503 };
 504
 505 static int __init gpio_mxc_init(void)
 506 {
 507         return platform_driver_register(&mxc_gpio_driver);
 508 }
 509 postcore_initcall(gpio_mxc_init);
 510
 511 MODULE_AUTHOR("Freescale Semiconductor, "
 512               "Daniel Mack <danielncaiaq.de>, "
 513               "Juergen Beisert <kernel@pengutronix.de>");
 514 MODULE_DESCRIPTION("Freescale MXC GPIO");
 515 MODULE_LICENSE("GPL");