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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpio / gpio-omap.c
blob61a731ff9a076fccd0c9b2bdc15d3ca10ce5e21c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30
31 #define OFF_MODE 1
32
33 static LIST_HEAD(omap_gpio_list);
34
35 struct gpio_regs {
36 u32 irqenable1;
37 u32 irqenable2;
38 u32 wake_en;
39 u32 ctrl;
40 u32 oe;
41 u32 leveldetect0;
42 u32 leveldetect1;
43 u32 risingdetect;
44 u32 fallingdetect;
45 u32 dataout;
46 u32 debounce;
47 u32 debounce_en;
48 };
49
50 struct gpio_bank {
51 struct list_head node;
52 void __iomem *base;
53 u16 irq;
54 u32 non_wakeup_gpios;
55 u32 enabled_non_wakeup_gpios;
56 struct gpio_regs context;
57 u32 saved_datain;
58 u32 level_mask;
59 u32 toggle_mask;
60 spinlock_t lock;
61 struct gpio_chip chip;
62 struct clk *dbck;
63 u32 mod_usage;
64 u32 irq_usage;
65 u32 dbck_enable_mask;
66 bool dbck_enabled;
67 struct device *dev;
68 bool is_mpuio;
69 bool dbck_flag;
70 bool loses_context;
71 bool context_valid;
72 int stride;
73 u32 width;
74 int context_loss_count;
75 int power_mode;
76 bool workaround_enabled;
77
78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
79 int (*get_context_loss_count)(struct device *dev);
80
81 struct omap_gpio_reg_offs *regs;
82 };
83
84 #define GPIO_MOD_CTRL_BIT BIT(0)
85
86 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
87 #define LINE_USED(line, offset) (line & (BIT(offset)))
88
89 static void omap_gpio_unmask_irq(struct irq_data *d);
90
91 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
92 {
93 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
94 return container_of(chip, struct gpio_bank, chip);
95 }
96
97 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
98 int is_input)
99 {
100 void __iomem *reg = bank->base;
101 u32 l;
102
103 reg += bank->regs->direction;
104 l = readl_relaxed(reg);
105 if (is_input)
106 l |= BIT(gpio);
107 else
108 l &= ~(BIT(gpio));
109 writel_relaxed(l, reg);
110 bank->context.oe = l;
111 }
112
113
114 /* set data out value using dedicate set/clear register */
115 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
116 int enable)
117 {
118 void __iomem *reg = bank->base;
119 u32 l = BIT(offset);
120
121 if (enable) {
122 reg += bank->regs->set_dataout;
123 bank->context.dataout |= l;
124 } else {
125 reg += bank->regs->clr_dataout;
126 bank->context.dataout &= ~l;
127 }
128
129 writel_relaxed(l, reg);
130 }
131
132 /* set data out value using mask register */
133 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
134 int enable)
135 {
136 void __iomem *reg = bank->base + bank->regs->dataout;
137 u32 gpio_bit = BIT(offset);
138 u32 l;
139
140 l = readl_relaxed(reg);
141 if (enable)
142 l |= gpio_bit;
143 else
144 l &= ~gpio_bit;
145 writel_relaxed(l, reg);
146 bank->context.dataout = l;
147 }
148
149 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
150 {
151 void __iomem *reg = bank->base + bank->regs->datain;
152
153 return (readl_relaxed(reg) & (BIT(offset))) != 0;
154 }
155
156 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
157 {
158 void __iomem *reg = bank->base + bank->regs->dataout;
159
160 return (readl_relaxed(reg) & (BIT(offset))) != 0;
161 }
162
163 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
164 {
165 int l = readl_relaxed(base + reg);
166
167 if (set)
168 l |= mask;
169 else
170 l &= ~mask;
171
172 writel_relaxed(l, base + reg);
173 }
174
175 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
176 {
177 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
178 clk_prepare_enable(bank->dbck);
179 bank->dbck_enabled = true;
180
181 writel_relaxed(bank->dbck_enable_mask,
182 bank->base + bank->regs->debounce_en);
183 }
184 }
185
186 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
187 {
188 if (bank->dbck_enable_mask && bank->dbck_enabled) {
189 /*
190 * Disable debounce before cutting it's clock. If debounce is
191 * enabled but the clock is not, GPIO module seems to be unable
192 * to detect events and generate interrupts at least on OMAP3.
193 */
194 writel_relaxed(0, bank->base + bank->regs->debounce_en);
195
196 clk_disable_unprepare(bank->dbck);
197 bank->dbck_enabled = false;
198 }
199 }
200
201 /**
202 * omap2_set_gpio_debounce - low level gpio debounce time
203 * @bank: the gpio bank we're acting upon
204 * @offset: the gpio number on this @bank
205 * @debounce: debounce time to use
206 *
207 * OMAP's debounce time is in 31us steps so we need
208 * to convert and round up to the closest unit.
209 */
210 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
211 unsigned debounce)
212 {
213 void __iomem *reg;
214 u32 val;
215 u32 l;
216
217 if (!bank->dbck_flag)
218 return;
219
220 if (debounce < 32)
221 debounce = 0x01;
222 else if (debounce > 7936)
223 debounce = 0xff;
224 else
225 debounce = (debounce / 0x1f) - 1;
226
227 l = BIT(offset);
228
229 clk_prepare_enable(bank->dbck);
230 reg = bank->base + bank->regs->debounce;
231 writel_relaxed(debounce, reg);
232
233 reg = bank->base + bank->regs->debounce_en;
234 val = readl_relaxed(reg);
235
236 if (debounce)
237 val |= l;
238 else
239 val &= ~l;
240 bank->dbck_enable_mask = val;
241
242 writel_relaxed(val, reg);
243 clk_disable_unprepare(bank->dbck);
244 /*
245 * Enable debounce clock per module.
246 * This call is mandatory because in omap_gpio_request() when
247 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
248 * runtime callbck fails to turn on dbck because dbck_enable_mask
249 * used within _gpio_dbck_enable() is still not initialized at
250 * that point. Therefore we have to enable dbck here.
251 */
252 omap_gpio_dbck_enable(bank);
253 if (bank->dbck_enable_mask) {
254 bank->context.debounce = debounce;
255 bank->context.debounce_en = val;
256 }
257 }
258
259 /**
260 * omap_clear_gpio_debounce - clear debounce settings for a gpio
261 * @bank: the gpio bank we're acting upon
262 * @offset: the gpio number on this @bank
263 *
264 * If a gpio is using debounce, then clear the debounce enable bit and if
265 * this is the only gpio in this bank using debounce, then clear the debounce
266 * time too. The debounce clock will also be disabled when calling this function
267 * if this is the only gpio in the bank using debounce.
268 */
269 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
270 {
271 u32 gpio_bit = BIT(offset);
272
273 if (!bank->dbck_flag)
274 return;
275
276 if (!(bank->dbck_enable_mask & gpio_bit))
277 return;
278
279 bank->dbck_enable_mask &= ~gpio_bit;
280 bank->context.debounce_en &= ~gpio_bit;
281 writel_relaxed(bank->context.debounce_en,
282 bank->base + bank->regs->debounce_en);
283
284 if (!bank->dbck_enable_mask) {
285 bank->context.debounce = 0;
286 writel_relaxed(bank->context.debounce, bank->base +
287 bank->regs->debounce);
288 clk_disable_unprepare(bank->dbck);
289 bank->dbck_enabled = false;
290 }
291 }
292
293 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
294 unsigned trigger)
295 {
296 void __iomem *base = bank->base;
297 u32 gpio_bit = BIT(gpio);
298
299 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
300 trigger & IRQ_TYPE_LEVEL_LOW);
301 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
302 trigger & IRQ_TYPE_LEVEL_HIGH);
303 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
304 trigger & IRQ_TYPE_EDGE_RISING);
305 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
306 trigger & IRQ_TYPE_EDGE_FALLING);
307
308 bank->context.leveldetect0 =
309 readl_relaxed(bank->base + bank->regs->leveldetect0);
310 bank->context.leveldetect1 =
311 readl_relaxed(bank->base + bank->regs->leveldetect1);
312 bank->context.risingdetect =
313 readl_relaxed(bank->base + bank->regs->risingdetect);
314 bank->context.fallingdetect =
315 readl_relaxed(bank->base + bank->regs->fallingdetect);
316
317 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
318 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
319 bank->context.wake_en =
320 readl_relaxed(bank->base + bank->regs->wkup_en);
321 }
322
323 /* This part needs to be executed always for OMAP{34xx, 44xx} */
324 if (!bank->regs->irqctrl) {
325 /* On omap24xx proceed only when valid GPIO bit is set */
326 if (bank->non_wakeup_gpios) {
327 if (!(bank->non_wakeup_gpios & gpio_bit))
328 goto exit;
329 }
330
331 /*
332 * Log the edge gpio and manually trigger the IRQ
333 * after resume if the input level changes
334 * to avoid irq lost during PER RET/OFF mode
335 * Applies for omap2 non-wakeup gpio and all omap3 gpios
336 */
337 if (trigger & IRQ_TYPE_EDGE_BOTH)
338 bank->enabled_non_wakeup_gpios |= gpio_bit;
339 else
340 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
341 }
342
343 exit:
344 bank->level_mask =
345 readl_relaxed(bank->base + bank->regs->leveldetect0) |
346 readl_relaxed(bank->base + bank->regs->leveldetect1);
347 }
348
349 #ifdef CONFIG_ARCH_OMAP1
350 /*
351 * This only applies to chips that can't do both rising and falling edge
352 * detection at once. For all other chips, this function is a noop.
353 */
354 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
355 {
356 void __iomem *reg = bank->base;
357 u32 l = 0;
358
359 if (!bank->regs->irqctrl)
360 return;
361
362 reg += bank->regs->irqctrl;
363
364 l = readl_relaxed(reg);
365 if ((l >> gpio) & 1)
366 l &= ~(BIT(gpio));
367 else
368 l |= BIT(gpio);
369
370 writel_relaxed(l, reg);
371 }
372 #else
373 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
374 #endif
375
376 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
377 unsigned trigger)
378 {
379 void __iomem *reg = bank->base;
380 void __iomem *base = bank->base;
381 u32 l = 0;
382
383 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
384 omap_set_gpio_trigger(bank, gpio, trigger);
385 } else if (bank->regs->irqctrl) {
386 reg += bank->regs->irqctrl;
387
388 l = readl_relaxed(reg);
389 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
390 bank->toggle_mask |= BIT(gpio);
391 if (trigger & IRQ_TYPE_EDGE_RISING)
392 l |= BIT(gpio);
393 else if (trigger & IRQ_TYPE_EDGE_FALLING)
394 l &= ~(BIT(gpio));
395 else
396 return -EINVAL;
397
398 writel_relaxed(l, reg);
399 } else if (bank->regs->edgectrl1) {
400 if (gpio & 0x08)
401 reg += bank->regs->edgectrl2;
402 else
403 reg += bank->regs->edgectrl1;
404
405 gpio &= 0x07;
406 l = readl_relaxed(reg);
407 l &= ~(3 << (gpio << 1));
408 if (trigger & IRQ_TYPE_EDGE_RISING)
409 l |= 2 << (gpio << 1);
410 if (trigger & IRQ_TYPE_EDGE_FALLING)
411 l |= BIT(gpio << 1);
412
413 /* Enable wake-up during idle for dynamic tick */
414 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
415 bank->context.wake_en =
416 readl_relaxed(bank->base + bank->regs->wkup_en);
417 writel_relaxed(l, reg);
418 }
419 return 0;
420 }
421
422 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
423 {
424 if (bank->regs->pinctrl) {
425 void __iomem *reg = bank->base + bank->regs->pinctrl;
426
427 /* Claim the pin for MPU */
428 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
429 }
430
431 if (bank->regs->ctrl && !BANK_USED(bank)) {
432 void __iomem *reg = bank->base + bank->regs->ctrl;
433 u32 ctrl;
434
435 ctrl = readl_relaxed(reg);
436 /* Module is enabled, clocks are not gated */
437 ctrl &= ~GPIO_MOD_CTRL_BIT;
438 writel_relaxed(ctrl, reg);
439 bank->context.ctrl = ctrl;
440 }
441 }
442
443 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
444 {
445 void __iomem *base = bank->base;
446
447 if (bank->regs->wkup_en &&
448 !LINE_USED(bank->mod_usage, offset) &&
449 !LINE_USED(bank->irq_usage, offset)) {
450 /* Disable wake-up during idle for dynamic tick */
451 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
452 bank->context.wake_en =
453 readl_relaxed(bank->base + bank->regs->wkup_en);
454 }
455
456 if (bank->regs->ctrl && !BANK_USED(bank)) {
457 void __iomem *reg = bank->base + bank->regs->ctrl;
458 u32 ctrl;
459
460 ctrl = readl_relaxed(reg);
461 /* Module is disabled, clocks are gated */
462 ctrl |= GPIO_MOD_CTRL_BIT;
463 writel_relaxed(ctrl, reg);
464 bank->context.ctrl = ctrl;
465 }
466 }
467
468 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
469 {
470 void __iomem *reg = bank->base + bank->regs->direction;
471
472 return readl_relaxed(reg) & BIT(offset);
473 }
474
475 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
476 {
477 if (!LINE_USED(bank->mod_usage, offset)) {
478 omap_enable_gpio_module(bank, offset);
479 omap_set_gpio_direction(bank, offset, 1);
480 }
481 bank->irq_usage |= BIT(offset);
482 }
483
484 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
485 {
486 struct gpio_bank *bank = omap_irq_data_get_bank(d);
487 int retval;
488 unsigned long flags;
489 unsigned offset = d->hwirq;
490
491 if (type & ~IRQ_TYPE_SENSE_MASK)
492 return -EINVAL;
493
494 if (!bank->regs->leveldetect0 &&
495 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
496 return -EINVAL;
497
498 if (!BANK_USED(bank))
499 pm_runtime_get_sync(bank->dev);
500
501 spin_lock_irqsave(&bank->lock, flags);
502 retval = omap_set_gpio_triggering(bank, offset, type);
503 if (retval) {
504 spin_unlock_irqrestore(&bank->lock, flags);
505 goto error;
506 }
507 omap_gpio_init_irq(bank, offset);
508 if (!omap_gpio_is_input(bank, offset)) {
509 spin_unlock_irqrestore(&bank->lock, flags);
510 retval = -EINVAL;
511 goto error;
512 }
513 spin_unlock_irqrestore(&bank->lock, flags);
514
515 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
516 __irq_set_handler_locked(d->irq, handle_level_irq);
517 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
518 __irq_set_handler_locked(d->irq, handle_edge_irq);
519
520 return 0;
521
522 error:
523 if (!BANK_USED(bank))
524 pm_runtime_put(bank->dev);
525 return retval;
526 }
527
528 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
529 {
530 void __iomem *reg = bank->base;
531
532 reg += bank->regs->irqstatus;
533 writel_relaxed(gpio_mask, reg);
534
535 /* Workaround for clearing DSP GPIO interrupts to allow retention */
536 if (bank->regs->irqstatus2) {
537 reg = bank->base + bank->regs->irqstatus2;
538 writel_relaxed(gpio_mask, reg);
539 }
540
541 /* Flush posted write for the irq status to avoid spurious interrupts */
542 readl_relaxed(reg);
543 }
544
545 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
546 unsigned offset)
547 {
548 omap_clear_gpio_irqbank(bank, BIT(offset));
549 }
550
551 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
552 {
553 void __iomem *reg = bank->base;
554 u32 l;
555 u32 mask = (BIT(bank->width)) - 1;
556
557 reg += bank->regs->irqenable;
558 l = readl_relaxed(reg);
559 if (bank->regs->irqenable_inv)
560 l = ~l;
561 l &= mask;
562 return l;
563 }
564
565 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
566 {
567 void __iomem *reg = bank->base;
568 u32 l;
569
570 if (bank->regs->set_irqenable) {
571 reg += bank->regs->set_irqenable;
572 l = gpio_mask;
573 bank->context.irqenable1 |= gpio_mask;
574 } else {
575 reg += bank->regs->irqenable;
576 l = readl_relaxed(reg);
577 if (bank->regs->irqenable_inv)
578 l &= ~gpio_mask;
579 else
580 l |= gpio_mask;
581 bank->context.irqenable1 = l;
582 }
583
584 writel_relaxed(l, reg);
585 }
586
587 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
588 {
589 void __iomem *reg = bank->base;
590 u32 l;
591
592 if (bank->regs->clr_irqenable) {
593 reg += bank->regs->clr_irqenable;
594 l = gpio_mask;
595 bank->context.irqenable1 &= ~gpio_mask;
596 } else {
597 reg += bank->regs->irqenable;
598 l = readl_relaxed(reg);
599 if (bank->regs->irqenable_inv)
600 l |= gpio_mask;
601 else
602 l &= ~gpio_mask;
603 bank->context.irqenable1 = l;
604 }
605
606 writel_relaxed(l, reg);
607 }
608
609 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
610 unsigned offset, int enable)
611 {
612 if (enable)
613 omap_enable_gpio_irqbank(bank, BIT(offset));
614 else
615 omap_disable_gpio_irqbank(bank, BIT(offset));
616 }
617
618 /*
619 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
620 * 1510 does not seem to have a wake-up register. If JTAG is connected
621 * to the target, system will wake up always on GPIO events. While
622 * system is running all registered GPIO interrupts need to have wake-up
623 * enabled. When system is suspended, only selected GPIO interrupts need
624 * to have wake-up enabled.
625 */
626 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
627 int enable)
628 {
629 u32 gpio_bit = BIT(offset);
630 unsigned long flags;
631
632 if (bank->non_wakeup_gpios & gpio_bit) {
633 dev_err(bank->dev,
634 "Unable to modify wakeup on non-wakeup GPIO%d\n",
635 offset);
636 return -EINVAL;
637 }
638
639 spin_lock_irqsave(&bank->lock, flags);
640 if (enable)
641 bank->context.wake_en |= gpio_bit;
642 else
643 bank->context.wake_en &= ~gpio_bit;
644
645 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
646 spin_unlock_irqrestore(&bank->lock, flags);
647
648 return 0;
649 }
650
651 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
652 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
653 {
654 struct gpio_bank *bank = omap_irq_data_get_bank(d);
655 unsigned offset = d->hwirq;
656
657 return omap_set_gpio_wakeup(bank, offset, enable);
658 }
659
660 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
661 {
662 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
663 unsigned long flags;
664
665 /*
666 * If this is the first gpio_request for the bank,
667 * enable the bank module.
668 */
669 if (!BANK_USED(bank))
670 pm_runtime_get_sync(bank->dev);
671
672 spin_lock_irqsave(&bank->lock, flags);
673 omap_enable_gpio_module(bank, offset);
674 bank->mod_usage |= BIT(offset);
675 spin_unlock_irqrestore(&bank->lock, flags);
676
677 return 0;
678 }
679
680 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
681 {
682 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
683 unsigned long flags;
684
685 spin_lock_irqsave(&bank->lock, flags);
686 bank->mod_usage &= ~(BIT(offset));
687 if (!LINE_USED(bank->irq_usage, offset)) {
688 omap_set_gpio_direction(bank, offset, 1);
689 omap_clear_gpio_debounce(bank, offset);
690 }
691 omap_disable_gpio_module(bank, offset);
692 spin_unlock_irqrestore(&bank->lock, flags);
693
694 /*
695 * If this is the last gpio to be freed in the bank,
696 * disable the bank module.
697 */
698 if (!BANK_USED(bank))
699 pm_runtime_put(bank->dev);
700 }
701
702 /*
703 * We need to unmask the GPIO bank interrupt as soon as possible to
704 * avoid missing GPIO interrupts for other lines in the bank.
705 * Then we need to mask-read-clear-unmask the triggered GPIO lines
706 * in the bank to avoid missing nested interrupts for a GPIO line.
707 * If we wait to unmask individual GPIO lines in the bank after the
708 * line's interrupt handler has been run, we may miss some nested
709 * interrupts.
710 */
711 static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
712 {
713 void __iomem *isr_reg = NULL;
714 u32 isr;
715 unsigned int bit;
716 struct gpio_bank *bank;
717 int unmasked = 0;
718 struct irq_chip *irqchip = irq_desc_get_chip(desc);
719 struct gpio_chip *chip = irq_get_handler_data(irq);
720
721 chained_irq_enter(irqchip, desc);
722
723 bank = container_of(chip, struct gpio_bank, chip);
724 isr_reg = bank->base + bank->regs->irqstatus;
725 pm_runtime_get_sync(bank->dev);
726
727 if (WARN_ON(!isr_reg))
728 goto exit;
729
730 while (1) {
731 u32 isr_saved, level_mask = 0;
732 u32 enabled;
733
734 enabled = omap_get_gpio_irqbank_mask(bank);
735 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
736
737 if (bank->level_mask)
738 level_mask = bank->level_mask & enabled;
739
740 /* clear edge sensitive interrupts before handler(s) are
741 called so that we don't miss any interrupt occurred while
742 executing them */
743 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
744 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
745 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
746
747 /* if there is only edge sensitive GPIO pin interrupts
748 configured, we could unmask GPIO bank interrupt immediately */
749 if (!level_mask && !unmasked) {
750 unmasked = 1;
751 chained_irq_exit(irqchip, desc);
752 }
753
754 if (!isr)
755 break;
756
757 while (isr) {
758 bit = __ffs(isr);
759 isr &= ~(BIT(bit));
760
761 /*
762 * Some chips can't respond to both rising and falling
763 * at the same time. If this irq was requested with
764 * both flags, we need to flip the ICR data for the IRQ
765 * to respond to the IRQ for the opposite direction.
766 * This will be indicated in the bank toggle_mask.
767 */
768 if (bank->toggle_mask & (BIT(bit)))
769 omap_toggle_gpio_edge_triggering(bank, bit);
770
771 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
772 bit));
773 }
774 }
775 /* if bank has any level sensitive GPIO pin interrupt
776 configured, we must unmask the bank interrupt only after
777 handler(s) are executed in order to avoid spurious bank
778 interrupt */
779 exit:
780 if (!unmasked)
781 chained_irq_exit(irqchip, desc);
782 pm_runtime_put(bank->dev);
783 }
784
785 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
786 {
787 struct gpio_bank *bank = omap_irq_data_get_bank(d);
788 unsigned long flags;
789 unsigned offset = d->hwirq;
790
791 if (!BANK_USED(bank))
792 pm_runtime_get_sync(bank->dev);
793
794 spin_lock_irqsave(&bank->lock, flags);
795
796 if (!LINE_USED(bank->mod_usage, offset))
797 omap_set_gpio_direction(bank, offset, 1);
798 else if (!omap_gpio_is_input(bank, offset))
799 goto err;
800 omap_enable_gpio_module(bank, offset);
801 bank->irq_usage |= BIT(offset);
802
803 spin_unlock_irqrestore(&bank->lock, flags);
804 omap_gpio_unmask_irq(d);
805
806 return 0;
807 err:
808 spin_unlock_irqrestore(&bank->lock, flags);
809 if (!BANK_USED(bank))
810 pm_runtime_put(bank->dev);
811 return -EINVAL;
812 }
813
814 static void omap_gpio_irq_shutdown(struct irq_data *d)
815 {
816 struct gpio_bank *bank = omap_irq_data_get_bank(d);
817 unsigned long flags;
818 unsigned offset = d->hwirq;
819
820 spin_lock_irqsave(&bank->lock, flags);
821 bank->irq_usage &= ~(BIT(offset));
822 omap_set_gpio_irqenable(bank, offset, 0);
823 omap_clear_gpio_irqstatus(bank, offset);
824 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
825 if (!LINE_USED(bank->mod_usage, offset))
826 omap_clear_gpio_debounce(bank, offset);
827 omap_disable_gpio_module(bank, offset);
828 spin_unlock_irqrestore(&bank->lock, flags);
829
830 /*
831 * If this is the last IRQ to be freed in the bank,
832 * disable the bank module.
833 */
834 if (!BANK_USED(bank))
835 pm_runtime_put(bank->dev);
836 }
837
838 static void omap_gpio_ack_irq(struct irq_data *d)
839 {
840 struct gpio_bank *bank = omap_irq_data_get_bank(d);
841 unsigned offset = d->hwirq;
842
843 omap_clear_gpio_irqstatus(bank, offset);
844 }
845
846 static void omap_gpio_mask_irq(struct irq_data *d)
847 {
848 struct gpio_bank *bank = omap_irq_data_get_bank(d);
849 unsigned offset = d->hwirq;
850 unsigned long flags;
851
852 spin_lock_irqsave(&bank->lock, flags);
853 omap_set_gpio_irqenable(bank, offset, 0);
854 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
855 spin_unlock_irqrestore(&bank->lock, flags);
856 }
857
858 static void omap_gpio_unmask_irq(struct irq_data *d)
859 {
860 struct gpio_bank *bank = omap_irq_data_get_bank(d);
861 unsigned offset = d->hwirq;
862 u32 trigger = irqd_get_trigger_type(d);
863 unsigned long flags;
864
865 spin_lock_irqsave(&bank->lock, flags);
866 if (trigger)
867 omap_set_gpio_triggering(bank, offset, trigger);
868
869 /* For level-triggered GPIOs, the clearing must be done after
870 * the HW source is cleared, thus after the handler has run */
871 if (bank->level_mask & BIT(offset)) {
872 omap_set_gpio_irqenable(bank, offset, 0);
873 omap_clear_gpio_irqstatus(bank, offset);
874 }
875
876 omap_set_gpio_irqenable(bank, offset, 1);
877 spin_unlock_irqrestore(&bank->lock, flags);
878 }
879
880 /*---------------------------------------------------------------------*/
881
882 static int omap_mpuio_suspend_noirq(struct device *dev)
883 {
884 struct platform_device *pdev = to_platform_device(dev);
885 struct gpio_bank *bank = platform_get_drvdata(pdev);
886 void __iomem *mask_reg = bank->base +
887 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
888 unsigned long flags;
889
890 spin_lock_irqsave(&bank->lock, flags);
891 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
892 spin_unlock_irqrestore(&bank->lock, flags);
893
894 return 0;
895 }
896
897 static int omap_mpuio_resume_noirq(struct device *dev)
898 {
899 struct platform_device *pdev = to_platform_device(dev);
900 struct gpio_bank *bank = platform_get_drvdata(pdev);
901 void __iomem *mask_reg = bank->base +
902 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
903 unsigned long flags;
904
905 spin_lock_irqsave(&bank->lock, flags);
906 writel_relaxed(bank->context.wake_en, mask_reg);
907 spin_unlock_irqrestore(&bank->lock, flags);
908
909 return 0;
910 }
911
912 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
913 .suspend_noirq = omap_mpuio_suspend_noirq,
914 .resume_noirq = omap_mpuio_resume_noirq,
915 };
916
917 /* use platform_driver for this. */
918 static struct platform_driver omap_mpuio_driver = {
919 .driver = {
920 .name = "mpuio",
921 .pm = &omap_mpuio_dev_pm_ops,
922 },
923 };
924
925 static struct platform_device omap_mpuio_device = {
926 .name = "mpuio",
927 .id = -1,
928 .dev = {
929 .driver = &omap_mpuio_driver.driver,
930 }
931 /* could list the /proc/iomem resources */
932 };
933
934 static inline void omap_mpuio_init(struct gpio_bank *bank)
935 {
936 platform_set_drvdata(&omap_mpuio_device, bank);
937
938 if (platform_driver_register(&omap_mpuio_driver) == 0)
939 (void) platform_device_register(&omap_mpuio_device);
940 }
941
942 /*---------------------------------------------------------------------*/
943
944 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
945 {
946 struct gpio_bank *bank;
947 unsigned long flags;
948 void __iomem *reg;
949 int dir;
950
951 bank = container_of(chip, struct gpio_bank, chip);
952 reg = bank->base + bank->regs->direction;
953 spin_lock_irqsave(&bank->lock, flags);
954 dir = !!(readl_relaxed(reg) & BIT(offset));
955 spin_unlock_irqrestore(&bank->lock, flags);
956 return dir;
957 }
958
959 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
960 {
961 struct gpio_bank *bank;
962 unsigned long flags;
963
964 bank = container_of(chip, struct gpio_bank, chip);
965 spin_lock_irqsave(&bank->lock, flags);
966 omap_set_gpio_direction(bank, offset, 1);
967 spin_unlock_irqrestore(&bank->lock, flags);
968 return 0;
969 }
970
971 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
972 {
973 struct gpio_bank *bank;
974
975 bank = container_of(chip, struct gpio_bank, chip);
976
977 if (omap_gpio_is_input(bank, offset))
978 return omap_get_gpio_datain(bank, offset);
979 else
980 return omap_get_gpio_dataout(bank, offset);
981 }
982
983 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
984 {
985 struct gpio_bank *bank;
986 unsigned long flags;
987
988 bank = container_of(chip, struct gpio_bank, chip);
989 spin_lock_irqsave(&bank->lock, flags);
990 bank->set_dataout(bank, offset, value);
991 omap_set_gpio_direction(bank, offset, 0);
992 spin_unlock_irqrestore(&bank->lock, flags);
993 return 0;
994 }
995
996 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
997 unsigned debounce)
998 {
999 struct gpio_bank *bank;
1000 unsigned long flags;
1001
1002 bank = container_of(chip, struct gpio_bank, chip);
1003
1004 spin_lock_irqsave(&bank->lock, flags);
1005 omap2_set_gpio_debounce(bank, offset, debounce);
1006 spin_unlock_irqrestore(&bank->lock, flags);
1007
1008 return 0;
1009 }
1010
1011 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1012 {
1013 struct gpio_bank *bank;
1014 unsigned long flags;
1015
1016 bank = container_of(chip, struct gpio_bank, chip);
1017 spin_lock_irqsave(&bank->lock, flags);
1018 bank->set_dataout(bank, offset, value);
1019 spin_unlock_irqrestore(&bank->lock, flags);
1020 }
1021
1022 /*---------------------------------------------------------------------*/
1023
1024 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1025 {
1026 static bool called;
1027 u32 rev;
1028
1029 if (called || bank->regs->revision == USHRT_MAX)
1030 return;
1031
1032 rev = readw_relaxed(bank->base + bank->regs->revision);
1033 pr_info("OMAP GPIO hardware version %d.%d\n",
1034 (rev >> 4) & 0x0f, rev & 0x0f);
1035
1036 called = true;
1037 }
1038
1039 static void omap_gpio_mod_init(struct gpio_bank *bank)
1040 {
1041 void __iomem *base = bank->base;
1042 u32 l = 0xffffffff;
1043
1044 if (bank->width == 16)
1045 l = 0xffff;
1046
1047 if (bank->is_mpuio) {
1048 writel_relaxed(l, bank->base + bank->regs->irqenable);
1049 return;
1050 }
1051
1052 omap_gpio_rmw(base, bank->regs->irqenable, l,
1053 bank->regs->irqenable_inv);
1054 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1055 !bank->regs->irqenable_inv);
1056 if (bank->regs->debounce_en)
1057 writel_relaxed(0, base + bank->regs->debounce_en);
1058
1059 /* Save OE default value (0xffffffff) in the context */
1060 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1061 /* Initialize interface clk ungated, module enabled */
1062 if (bank->regs->ctrl)
1063 writel_relaxed(0, base + bank->regs->ctrl);
1064
1065 bank->dbck = clk_get(bank->dev, "dbclk");
1066 if (IS_ERR(bank->dbck))
1067 dev_err(bank->dev, "Could not get gpio dbck\n");
1068 }
1069
1070 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1071 {
1072 static int gpio;
1073 int irq_base = 0;
1074 int ret;
1075
1076 /*
1077 * REVISIT eventually switch from OMAP-specific gpio structs
1078 * over to the generic ones
1079 */
1080 bank->chip.request = omap_gpio_request;
1081 bank->chip.free = omap_gpio_free;
1082 bank->chip.get_direction = omap_gpio_get_direction;
1083 bank->chip.direction_input = omap_gpio_input;
1084 bank->chip.get = omap_gpio_get;
1085 bank->chip.direction_output = omap_gpio_output;
1086 bank->chip.set_debounce = omap_gpio_debounce;
1087 bank->chip.set = omap_gpio_set;
1088 if (bank->is_mpuio) {
1089 bank->chip.label = "mpuio";
1090 if (bank->regs->wkup_en)
1091 bank->chip.dev = &omap_mpuio_device.dev;
1092 bank->chip.base = OMAP_MPUIO(0);
1093 } else {
1094 bank->chip.label = "gpio";
1095 bank->chip.base = gpio;
1096 gpio += bank->width;
1097 }
1098 bank->chip.ngpio = bank->width;
1099
1100 ret = gpiochip_add(&bank->chip);
1101 if (ret) {
1102 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1103 return ret;
1104 }
1105
1106 #ifdef CONFIG_ARCH_OMAP1
1107 /*
1108 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1109 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1110 */
1111 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1112 if (irq_base < 0) {
1113 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1114 return -ENODEV;
1115 }
1116 #endif
1117
1118 /* MPUIO is a bit different, reading IRQ status clears it */
1119 if (bank->is_mpuio) {
1120 irqc->irq_ack = dummy_irq_chip.irq_ack;
1121 irqc->irq_mask = irq_gc_mask_set_bit;
1122 irqc->irq_unmask = irq_gc_mask_clr_bit;
1123 if (!bank->regs->wkup_en)
1124 irqc->irq_set_wake = NULL;
1125 }
1126
1127 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1128 irq_base, omap_gpio_irq_handler,
1129 IRQ_TYPE_NONE);
1130
1131 if (ret) {
1132 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1133 gpiochip_remove(&bank->chip);
1134 return -ENODEV;
1135 }
1136
1137 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1138 bank->irq, omap_gpio_irq_handler);
1139
1140 return 0;
1141 }
1142
1143 static const struct of_device_id omap_gpio_match[];
1144
1145 static int omap_gpio_probe(struct platform_device *pdev)
1146 {
1147 struct device *dev = &pdev->dev;
1148 struct device_node *node = dev->of_node;
1149 const struct of_device_id *match;
1150 const struct omap_gpio_platform_data *pdata;
1151 struct resource *res;
1152 struct gpio_bank *bank;
1153 struct irq_chip *irqc;
1154 int ret;
1155
1156 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1157
1158 pdata = match ? match->data : dev_get_platdata(dev);
1159 if (!pdata)
1160 return -EINVAL;
1161
1162 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1163 if (!bank) {
1164 dev_err(dev, "Memory alloc failed\n");
1165 return -ENOMEM;
1166 }
1167
1168 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1169 if (!irqc)
1170 return -ENOMEM;
1171
1172 irqc->irq_startup = omap_gpio_irq_startup,
1173 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1174 irqc->irq_ack = omap_gpio_ack_irq,
1175 irqc->irq_mask = omap_gpio_mask_irq,
1176 irqc->irq_unmask = omap_gpio_unmask_irq,
1177 irqc->irq_set_type = omap_gpio_irq_type,
1178 irqc->irq_set_wake = omap_gpio_wake_enable,
1179 irqc->name = dev_name(&pdev->dev);
1180
1181 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1182 if (unlikely(!res)) {
1183 dev_err(dev, "Invalid IRQ resource\n");
1184 return -ENODEV;
1185 }
1186
1187 bank->irq = res->start;
1188 bank->dev = dev;
1189 bank->chip.dev = dev;
1190 bank->chip.owner = THIS_MODULE;
1191 bank->dbck_flag = pdata->dbck_flag;
1192 bank->stride = pdata->bank_stride;
1193 bank->width = pdata->bank_width;
1194 bank->is_mpuio = pdata->is_mpuio;
1195 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1196 bank->regs = pdata->regs;
1197 #ifdef CONFIG_OF_GPIO
1198 bank->chip.of_node = of_node_get(node);
1199 #endif
1200 if (node) {
1201 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1202 bank->loses_context = true;
1203 } else {
1204 bank->loses_context = pdata->loses_context;
1205
1206 if (bank->loses_context)
1207 bank->get_context_loss_count =
1208 pdata->get_context_loss_count;
1209 }
1210
1211 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1212 bank->set_dataout = omap_set_gpio_dataout_reg;
1213 else
1214 bank->set_dataout = omap_set_gpio_dataout_mask;
1215
1216 spin_lock_init(&bank->lock);
1217
1218 /* Static mapping, never released */
1219 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 bank->base = devm_ioremap_resource(dev, res);
1221 if (IS_ERR(bank->base)) {
1222 irq_domain_remove(bank->chip.irqdomain);
1223 return PTR_ERR(bank->base);
1224 }
1225
1226 platform_set_drvdata(pdev, bank);
1227
1228 pm_runtime_enable(bank->dev);
1229 pm_runtime_irq_safe(bank->dev);
1230 pm_runtime_get_sync(bank->dev);
1231
1232 if (bank->is_mpuio)
1233 omap_mpuio_init(bank);
1234
1235 omap_gpio_mod_init(bank);
1236
1237 ret = omap_gpio_chip_init(bank, irqc);
1238 if (ret)
1239 return ret;
1240
1241 omap_gpio_show_rev(bank);
1242
1243 pm_runtime_put(bank->dev);
1244
1245 list_add_tail(&bank->node, &omap_gpio_list);
1246
1247 return 0;
1248 }
1249
1250 static int omap_gpio_remove(struct platform_device *pdev)
1251 {
1252 struct gpio_bank *bank = platform_get_drvdata(pdev);
1253
1254 list_del(&bank->node);
1255 gpiochip_remove(&bank->chip);
1256 pm_runtime_disable(bank->dev);
1257
1258 return 0;
1259 }
1260
1261 #ifdef CONFIG_ARCH_OMAP2PLUS
1262
1263 #if defined(CONFIG_PM)
1264 static void omap_gpio_restore_context(struct gpio_bank *bank);
1265
1266 static int omap_gpio_runtime_suspend(struct device *dev)
1267 {
1268 struct platform_device *pdev = to_platform_device(dev);
1269 struct gpio_bank *bank = platform_get_drvdata(pdev);
1270 u32 l1 = 0, l2 = 0;
1271 unsigned long flags;
1272 u32 wake_low, wake_hi;
1273
1274 spin_lock_irqsave(&bank->lock, flags);
1275
1276 /*
1277 * Only edges can generate a wakeup event to the PRCM.
1278 *
1279 * Therefore, ensure any wake-up capable GPIOs have
1280 * edge-detection enabled before going idle to ensure a wakeup
1281 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1282 * NDA TRM 25.5.3.1)
1283 *
1284 * The normal values will be restored upon ->runtime_resume()
1285 * by writing back the values saved in bank->context.
1286 */
1287 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1288 if (wake_low)
1289 writel_relaxed(wake_low | bank->context.fallingdetect,
1290 bank->base + bank->regs->fallingdetect);
1291 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1292 if (wake_hi)
1293 writel_relaxed(wake_hi | bank->context.risingdetect,
1294 bank->base + bank->regs->risingdetect);
1295
1296 if (!bank->enabled_non_wakeup_gpios)
1297 goto update_gpio_context_count;
1298
1299 if (bank->power_mode != OFF_MODE) {
1300 bank->power_mode = 0;
1301 goto update_gpio_context_count;
1302 }
1303 /*
1304 * If going to OFF, remove triggering for all
1305 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1306 * generated. See OMAP2420 Errata item 1.101.
1307 */
1308 bank->saved_datain = readl_relaxed(bank->base +
1309 bank->regs->datain);
1310 l1 = bank->context.fallingdetect;
1311 l2 = bank->context.risingdetect;
1312
1313 l1 &= ~bank->enabled_non_wakeup_gpios;
1314 l2 &= ~bank->enabled_non_wakeup_gpios;
1315
1316 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1317 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1318
1319 bank->workaround_enabled = true;
1320
1321 update_gpio_context_count:
1322 if (bank->get_context_loss_count)
1323 bank->context_loss_count =
1324 bank->get_context_loss_count(bank->dev);
1325
1326 omap_gpio_dbck_disable(bank);
1327 spin_unlock_irqrestore(&bank->lock, flags);
1328
1329 return 0;
1330 }
1331
1332 static void omap_gpio_init_context(struct gpio_bank *p);
1333
1334 static int omap_gpio_runtime_resume(struct device *dev)
1335 {
1336 struct platform_device *pdev = to_platform_device(dev);
1337 struct gpio_bank *bank = platform_get_drvdata(pdev);
1338 u32 l = 0, gen, gen0, gen1;
1339 unsigned long flags;
1340 int c;
1341
1342 spin_lock_irqsave(&bank->lock, flags);
1343
1344 /*
1345 * On the first resume during the probe, the context has not
1346 * been initialised and so initialise it now. Also initialise
1347 * the context loss count.
1348 */
1349 if (bank->loses_context && !bank->context_valid) {
1350 omap_gpio_init_context(bank);
1351
1352 if (bank->get_context_loss_count)
1353 bank->context_loss_count =
1354 bank->get_context_loss_count(bank->dev);
1355 }
1356
1357 omap_gpio_dbck_enable(bank);
1358
1359 /*
1360 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1361 * GPIOs were set to edge trigger also in order to be able to
1362 * generate a PRCM wakeup. Here we restore the
1363 * pre-runtime_suspend() values for edge triggering.
1364 */
1365 writel_relaxed(bank->context.fallingdetect,
1366 bank->base + bank->regs->fallingdetect);
1367 writel_relaxed(bank->context.risingdetect,
1368 bank->base + bank->regs->risingdetect);
1369
1370 if (bank->loses_context) {
1371 if (!bank->get_context_loss_count) {
1372 omap_gpio_restore_context(bank);
1373 } else {
1374 c = bank->get_context_loss_count(bank->dev);
1375 if (c != bank->context_loss_count) {
1376 omap_gpio_restore_context(bank);
1377 } else {
1378 spin_unlock_irqrestore(&bank->lock, flags);
1379 return 0;
1380 }
1381 }
1382 }
1383
1384 if (!bank->workaround_enabled) {
1385 spin_unlock_irqrestore(&bank->lock, flags);
1386 return 0;
1387 }
1388
1389 l = readl_relaxed(bank->base + bank->regs->datain);
1390
1391 /*
1392 * Check if any of the non-wakeup interrupt GPIOs have changed
1393 * state. If so, generate an IRQ by software. This is
1394 * horribly racy, but it's the best we can do to work around
1395 * this silicon bug.
1396 */
1397 l ^= bank->saved_datain;
1398 l &= bank->enabled_non_wakeup_gpios;
1399
1400 /*
1401 * No need to generate IRQs for the rising edge for gpio IRQs
1402 * configured with falling edge only; and vice versa.
1403 */
1404 gen0 = l & bank->context.fallingdetect;
1405 gen0 &= bank->saved_datain;
1406
1407 gen1 = l & bank->context.risingdetect;
1408 gen1 &= ~(bank->saved_datain);
1409
1410 /* FIXME: Consider GPIO IRQs with level detections properly! */
1411 gen = l & (~(bank->context.fallingdetect) &
1412 ~(bank->context.risingdetect));
1413 /* Consider all GPIO IRQs needed to be updated */
1414 gen |= gen0 | gen1;
1415
1416 if (gen) {
1417 u32 old0, old1;
1418
1419 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1420 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1421
1422 if (!bank->regs->irqstatus_raw0) {
1423 writel_relaxed(old0 | gen, bank->base +
1424 bank->regs->leveldetect0);
1425 writel_relaxed(old1 | gen, bank->base +
1426 bank->regs->leveldetect1);
1427 }
1428
1429 if (bank->regs->irqstatus_raw0) {
1430 writel_relaxed(old0 | l, bank->base +
1431 bank->regs->leveldetect0);
1432 writel_relaxed(old1 | l, bank->base +
1433 bank->regs->leveldetect1);
1434 }
1435 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1436 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1437 }
1438
1439 bank->workaround_enabled = false;
1440 spin_unlock_irqrestore(&bank->lock, flags);
1441
1442 return 0;
1443 }
1444 #endif /* CONFIG_PM */
1445
1446 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1447 void omap2_gpio_prepare_for_idle(int pwr_mode)
1448 {
1449 struct gpio_bank *bank;
1450
1451 list_for_each_entry(bank, &omap_gpio_list, node) {
1452 if (!BANK_USED(bank) || !bank->loses_context)
1453 continue;
1454
1455 bank->power_mode = pwr_mode;
1456
1457 pm_runtime_put_sync_suspend(bank->dev);
1458 }
1459 }
1460
1461 void omap2_gpio_resume_after_idle(void)
1462 {
1463 struct gpio_bank *bank;
1464
1465 list_for_each_entry(bank, &omap_gpio_list, node) {
1466 if (!BANK_USED(bank) || !bank->loses_context)
1467 continue;
1468
1469 pm_runtime_get_sync(bank->dev);
1470 }
1471 }
1472 #endif
1473
1474 #if defined(CONFIG_PM)
1475 static void omap_gpio_init_context(struct gpio_bank *p)
1476 {
1477 struct omap_gpio_reg_offs *regs = p->regs;
1478 void __iomem *base = p->base;
1479
1480 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1481 p->context.oe = readl_relaxed(base + regs->direction);
1482 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1483 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1484 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1485 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1486 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1487 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1488 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1489
1490 if (regs->set_dataout && p->regs->clr_dataout)
1491 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1492 else
1493 p->context.dataout = readl_relaxed(base + regs->dataout);
1494
1495 p->context_valid = true;
1496 }
1497
1498 static void omap_gpio_restore_context(struct gpio_bank *bank)
1499 {
1500 writel_relaxed(bank->context.wake_en,
1501 bank->base + bank->regs->wkup_en);
1502 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1503 writel_relaxed(bank->context.leveldetect0,
1504 bank->base + bank->regs->leveldetect0);
1505 writel_relaxed(bank->context.leveldetect1,
1506 bank->base + bank->regs->leveldetect1);
1507 writel_relaxed(bank->context.risingdetect,
1508 bank->base + bank->regs->risingdetect);
1509 writel_relaxed(bank->context.fallingdetect,
1510 bank->base + bank->regs->fallingdetect);
1511 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1512 writel_relaxed(bank->context.dataout,
1513 bank->base + bank->regs->set_dataout);
1514 else
1515 writel_relaxed(bank->context.dataout,
1516 bank->base + bank->regs->dataout);
1517 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1518
1519 if (bank->dbck_enable_mask) {
1520 writel_relaxed(bank->context.debounce, bank->base +
1521 bank->regs->debounce);
1522 writel_relaxed(bank->context.debounce_en,
1523 bank->base + bank->regs->debounce_en);
1524 }
1525
1526 writel_relaxed(bank->context.irqenable1,
1527 bank->base + bank->regs->irqenable);
1528 writel_relaxed(bank->context.irqenable2,
1529 bank->base + bank->regs->irqenable2);
1530 }
1531 #endif /* CONFIG_PM */
1532 #else
1533 #define omap_gpio_runtime_suspend NULL
1534 #define omap_gpio_runtime_resume NULL
1535 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1536 #endif
1537
1538 static const struct dev_pm_ops gpio_pm_ops = {
1539 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1540 NULL)
1541 };
1542
1543 #if defined(CONFIG_OF)
1544 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1545 .revision = OMAP24XX_GPIO_REVISION,
1546 .direction = OMAP24XX_GPIO_OE,
1547 .datain = OMAP24XX_GPIO_DATAIN,
1548 .dataout = OMAP24XX_GPIO_DATAOUT,
1549 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1550 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1551 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1552 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1553 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1554 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1555 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1556 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1557 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1558 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1559 .ctrl = OMAP24XX_GPIO_CTRL,
1560 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1561 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1562 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1563 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1564 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1565 };
1566
1567 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1568 .revision = OMAP4_GPIO_REVISION,
1569 .direction = OMAP4_GPIO_OE,
1570 .datain = OMAP4_GPIO_DATAIN,
1571 .dataout = OMAP4_GPIO_DATAOUT,
1572 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1573 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1574 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1575 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1576 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1577 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1578 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1579 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1580 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1581 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1582 .ctrl = OMAP4_GPIO_CTRL,
1583 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1584 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1585 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1586 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1587 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1588 };
1589
1590 static const struct omap_gpio_platform_data omap2_pdata = {
1591 .regs = &omap2_gpio_regs,
1592 .bank_width = 32,
1593 .dbck_flag = false,
1594 };
1595
1596 static const struct omap_gpio_platform_data omap3_pdata = {
1597 .regs = &omap2_gpio_regs,
1598 .bank_width = 32,
1599 .dbck_flag = true,
1600 };
1601
1602 static const struct omap_gpio_platform_data omap4_pdata = {
1603 .regs = &omap4_gpio_regs,
1604 .bank_width = 32,
1605 .dbck_flag = true,
1606 };
1607
1608 static const struct of_device_id omap_gpio_match[] = {
1609 {
1610 .compatible = "ti,omap4-gpio",
1611 .data = &omap4_pdata,
1612 },
1613 {
1614 .compatible = "ti,omap3-gpio",
1615 .data = &omap3_pdata,
1616 },
1617 {
1618 .compatible = "ti,omap2-gpio",
1619 .data = &omap2_pdata,
1620 },
1621 { },
1622 };
1623 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1624 #endif
1625
1626 static struct platform_driver omap_gpio_driver = {
1627 .probe = omap_gpio_probe,
1628 .remove = omap_gpio_remove,
1629 .driver = {
1630 .name = "omap_gpio",
1631 .pm = &gpio_pm_ops,
1632 .of_match_table = of_match_ptr(omap_gpio_match),
1633 },
1634 };
1635
1636 /*
1637 * gpio driver register needs to be done before
1638 * machine_init functions access gpio APIs.
1639 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1640 */
1641 static int __init omap_gpio_drv_reg(void)
1642 {
1643 return platform_driver_register(&omap_gpio_driver);
1644 }
1645 postcore_initcall(omap_gpio_drv_reg);
1646
1647 static void __exit omap_gpio_exit(void)
1648 {
1649 platform_driver_unregister(&omap_gpio_driver);
1650 }
1651 module_exit(omap_gpio_exit);
1652
1653 MODULE_DESCRIPTION("omap gpio driver");
1654 MODULE_ALIAS("platform:gpio-omap");
1655 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support