drivers/gpio/gpio-rcar.c

   1 /*
   2  * Renesas R-Car GPIO Support
   3  *
   4  *  Copyright (C) 2014 Renesas Electronics Corporation
   5  *  Copyright (C) 2013 Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/gpio.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/ioport.h>
  24 #include <linux/irq.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/platform_data/gpio-rcar.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33
  34 struct gpio_rcar_priv {
  35         void __iomem *base;
  36         spinlock_t lock;
  37         struct gpio_rcar_config config;
  38         struct platform_device *pdev;
  39         struct gpio_chip gpio_chip;
  40         struct irq_chip irq_chip;
  41         unsigned int irq_parent;
  42         struct clk *clk;
  43 };
  44
  45 #define IOINTSEL 0x00   /* General IO/Interrupt Switching Register */
  46 #define INOUTSEL 0x04   /* General Input/Output Switching Register */
  47 #define OUTDT 0x08      /* General Output Register */
  48 #define INDT 0x0c       /* General Input Register */
  49 #define INTDT 0x10      /* Interrupt Display Register */
  50 #define INTCLR 0x14     /* Interrupt Clear Register */
  51 #define INTMSK 0x18     /* Interrupt Mask Register */
  52 #define MSKCLR 0x1c     /* Interrupt Mask Clear Register */
  53 #define POSNEG 0x20     /* Positive/Negative Logic Select Register */
  54 #define EDGLEVEL 0x24   /* Edge/level Select Register */
  55 #define FILONOFF 0x28   /* Chattering Prevention On/Off Register */
  56 #define BOTHEDGE 0x4c   /* One Edge/Both Edge Select Register */
  57
  58 #define RCAR_MAX_GPIO_PER_BANK          32
  59
  60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  61 {
  62         return ioread32(p->base + offs);
  63 }
  64
  65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  66                                    u32 value)
  67 {
  68         iowrite32(value, p->base + offs);
  69 }
  70
  71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  72                                  int bit, bool value)
  73 {
  74         u32 tmp = gpio_rcar_read(p, offs);
  75
  76         if (value)
  77                 tmp |= BIT(bit);
  78         else
  79                 tmp &= ~BIT(bit);
  80
  81         gpio_rcar_write(p, offs, tmp);
  82 }
  83
  84 static void gpio_rcar_irq_disable(struct irq_data *d)
  85 {
  86         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  87         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
  88                                                 gpio_chip);
  89
  90         gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  91 }
  92
  93 static void gpio_rcar_irq_enable(struct irq_data *d)
  94 {
  95         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  96         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
  97                                                 gpio_chip);
  98
  99         gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
 100 }
 101
 102 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 103                                                   unsigned int hwirq,
 104                                                   bool active_high_rising_edge,
 105                                                   bool level_trigger,
 106                                                   bool both)
 107 {
 108         unsigned long flags;
 109
 110         /* follow steps in the GPIO documentation for
 111          * "Setting Edge-Sensitive Interrupt Input Mode" and
 112          * "Setting Level-Sensitive Interrupt Input Mode"
 113          */
 114
 115         spin_lock_irqsave(&p->lock, flags);
 116
 117         /* Configure postive or negative logic in POSNEG */
 118         gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 119
 120         /* Configure edge or level trigger in EDGLEVEL */
 121         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 122
 123         /* Select one edge or both edges in BOTHEDGE */
 124         if (p->config.has_both_edge_trigger)
 125                 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 126
 127         /* Select "Interrupt Input Mode" in IOINTSEL */
 128         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 129
 130         /* Write INTCLR in case of edge trigger */
 131         if (!level_trigger)
 132                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
 133
 134         spin_unlock_irqrestore(&p->lock, flags);
 135 }
 136
 137 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 138 {
 139         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 140         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
 141                                                 gpio_chip);
 142         unsigned int hwirq = irqd_to_hwirq(d);
 143
 144         dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
 145
 146         switch (type & IRQ_TYPE_SENSE_MASK) {
 147         case IRQ_TYPE_LEVEL_HIGH:
 148                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 149                                                       false);
 150                 break;
 151         case IRQ_TYPE_LEVEL_LOW:
 152                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 153                                                       false);
 154                 break;
 155         case IRQ_TYPE_EDGE_RISING:
 156                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 157                                                       false);
 158                 break;
 159         case IRQ_TYPE_EDGE_FALLING:
 160                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 161                                                       false);
 162                 break;
 163         case IRQ_TYPE_EDGE_BOTH:
 164                 if (!p->config.has_both_edge_trigger)
 165                         return -EINVAL;
 166                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 167                                                       true);
 168                 break;
 169         default:
 170                 return -EINVAL;
 171         }
 172         return 0;
 173 }
 174
 175 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
 176 {
 177         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 178         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
 179                                                 gpio_chip);
 180         int error;
 181
 182         if (p->irq_parent) {
 183                 error = irq_set_irq_wake(p->irq_parent, on);
 184                 if (error) {
 185                         dev_dbg(&p->pdev->dev,
 186                                 "irq %u doesn't support irq_set_wake\n",
 187                                 p->irq_parent);
 188                         p->irq_parent = 0;
 189                 }
 190         }
 191
 192         if (!p->clk)
 193                 return 0;
 194
 195         if (on)
 196                 clk_enable(p->clk);
 197         else
 198                 clk_disable(p->clk);
 199
 200         return 0;
 201 }
 202
 203 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 204 {
 205         struct gpio_rcar_priv *p = dev_id;
 206         u32 pending;
 207         unsigned int offset, irqs_handled = 0;
 208
 209         while ((pending = gpio_rcar_read(p, INTDT) &
 210                           gpio_rcar_read(p, INTMSK))) {
 211                 offset = __ffs(pending);
 212                 gpio_rcar_write(p, INTCLR, BIT(offset));
 213                 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
 214                                                     offset));
 215                 irqs_handled++;
 216         }
 217
 218         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 219 }
 220
 221 static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
 222 {
 223         return container_of(chip, struct gpio_rcar_priv, gpio_chip);
 224 }
 225
 226 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 227                                                        unsigned int gpio,
 228                                                        bool output)
 229 {
 230         struct gpio_rcar_priv *p = gpio_to_priv(chip);
 231         unsigned long flags;
 232
 233         /* follow steps in the GPIO documentation for
 234          * "Setting General Output Mode" and
 235          * "Setting General Input Mode"
 236          */
 237
 238         spin_lock_irqsave(&p->lock, flags);
 239
 240         /* Configure postive logic in POSNEG */
 241         gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 242
 243         /* Select "General Input/Output Mode" in IOINTSEL */
 244         gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 245
 246         /* Select Input Mode or Output Mode in INOUTSEL */
 247         gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 248
 249         spin_unlock_irqrestore(&p->lock, flags);
 250 }
 251
 252 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 253 {
 254         return pinctrl_request_gpio(chip->base + offset);
 255 }
 256
 257 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 258 {
 259         pinctrl_free_gpio(chip->base + offset);
 260
 261         /* Set the GPIO as an input to ensure that the next GPIO request won't
 262          * drive the GPIO pin as an output.
 263          */
 264         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 265 }
 266
 267 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 268 {
 269         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 270         return 0;
 271 }
 272
 273 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 274 {
 275         u32 bit = BIT(offset);
 276
 277         /* testing on r8a7790 shows that INDT does not show correct pin state
 278          * when configured as output, so use OUTDT in case of output pins */
 279         if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
 280                 return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
 281         else
 282                 return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
 283 }
 284
 285 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 286 {
 287         struct gpio_rcar_priv *p = gpio_to_priv(chip);
 288         unsigned long flags;
 289
 290         spin_lock_irqsave(&p->lock, flags);
 291         gpio_rcar_modify_bit(p, OUTDT, offset, value);
 292         spin_unlock_irqrestore(&p->lock, flags);
 293 }
 294
 295 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 296                                       int value)
 297 {
 298         /* write GPIO value to output before selecting output mode of pin */
 299         gpio_rcar_set(chip, offset, value);
 300         gpio_rcar_config_general_input_output_mode(chip, offset, true);
 301         return 0;
 302 }
 303
 304 struct gpio_rcar_info {
 305         bool has_both_edge_trigger;
 306 };
 307
 308 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
 309         .has_both_edge_trigger = false,
 310 };
 311
 312 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
 313         .has_both_edge_trigger = true,
 314 };
 315
 316 static const struct of_device_id gpio_rcar_of_table[] = {
 317         {
 318                 .compatible = "renesas,gpio-r8a7790",
 319                 .data = &gpio_rcar_info_gen2,
 320         }, {
 321                 .compatible = "renesas,gpio-r8a7791",
 322                 .data = &gpio_rcar_info_gen2,
 323         }, {
 324                 .compatible = "renesas,gpio-r8a7793",
 325                 .data = &gpio_rcar_info_gen2,
 326         }, {
 327                 .compatible = "renesas,gpio-r8a7794",
 328                 .data = &gpio_rcar_info_gen2,
 329         }, {
 330                 .compatible = "renesas,gpio-rcar",
 331                 .data = &gpio_rcar_info_gen1,
 332         }, {
 333                 /* Terminator */
 334         },
 335 };
 336
 337 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 338
 339 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
 340 {
 341         struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
 342         struct device_node *np = p->pdev->dev.of_node;
 343         struct of_phandle_args args;
 344         int ret;
 345
 346         if (pdata) {
 347                 p->config = *pdata;
 348         } else if (IS_ENABLED(CONFIG_OF) && np) {
 349                 const struct of_device_id *match;
 350                 const struct gpio_rcar_info *info;
 351
 352                 match = of_match_node(gpio_rcar_of_table, np);
 353                 if (!match)
 354                         return -EINVAL;
 355
 356                 info = match->data;
 357
 358                 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
 359                                                        &args);
 360                 p->config.number_of_pins = ret == 0 ? args.args[2]
 361                                          : RCAR_MAX_GPIO_PER_BANK;
 362                 p->config.gpio_base = -1;
 363                 p->config.has_both_edge_trigger = info->has_both_edge_trigger;
 364         }
 365
 366         if (p->config.number_of_pins == 0 ||
 367             p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
 368                 dev_warn(&p->pdev->dev,
 369                          "Invalid number of gpio lines %u, using %u\n",
 370                          p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
 371                 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int gpio_rcar_probe(struct platform_device *pdev)
 378 {
 379         struct gpio_rcar_priv *p;
 380         struct resource *io, *irq;
 381         struct gpio_chip *gpio_chip;
 382         struct irq_chip *irq_chip;
 383         struct device *dev = &pdev->dev;
 384         const char *name = dev_name(dev);
 385         int ret;
 386
 387         p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 388         if (!p)
 389                 return -ENOMEM;
 390
 391         p->pdev = pdev;
 392         spin_lock_init(&p->lock);
 393
 394         /* Get device configuration from DT node or platform data. */
 395         ret = gpio_rcar_parse_pdata(p);
 396         if (ret < 0)
 397                 return ret;
 398
 399         platform_set_drvdata(pdev, p);
 400
 401         p->clk = devm_clk_get(dev, NULL);
 402         if (IS_ERR(p->clk)) {
 403                 dev_warn(dev, "unable to get clock\n");
 404                 p->clk = NULL;
 405         }
 406
 407         pm_runtime_enable(dev);
 408         pm_runtime_get_sync(dev);
 409
 410         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 411         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 412
 413         if (!io || !irq) {
 414                 dev_err(dev, "missing IRQ or IOMEM\n");
 415                 ret = -EINVAL;
 416                 goto err0;
 417         }
 418
 419         p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
 420         if (!p->base) {
 421                 dev_err(dev, "failed to remap I/O memory\n");
 422                 ret = -ENXIO;
 423                 goto err0;
 424         }
 425
 426         gpio_chip = &p->gpio_chip;
 427         gpio_chip->request = gpio_rcar_request;
 428         gpio_chip->free = gpio_rcar_free;
 429         gpio_chip->direction_input = gpio_rcar_direction_input;
 430         gpio_chip->get = gpio_rcar_get;
 431         gpio_chip->direction_output = gpio_rcar_direction_output;
 432         gpio_chip->set = gpio_rcar_set;
 433         gpio_chip->label = name;
 434         gpio_chip->dev = dev;
 435         gpio_chip->owner = THIS_MODULE;
 436         gpio_chip->base = p->config.gpio_base;
 437         gpio_chip->ngpio = p->config.number_of_pins;
 438
 439         irq_chip = &p->irq_chip;
 440         irq_chip->name = name;
 441         irq_chip->irq_mask = gpio_rcar_irq_disable;
 442         irq_chip->irq_unmask = gpio_rcar_irq_enable;
 443         irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 444         irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
 445         irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
 446
 447         ret = gpiochip_add(gpio_chip);
 448         if (ret) {
 449                 dev_err(dev, "failed to add GPIO controller\n");
 450                 goto err0;
 451         }
 452
 453         ret = gpiochip_irqchip_add(gpio_chip, irq_chip, p->config.irq_base,
 454                                    handle_level_irq, IRQ_TYPE_NONE);
 455         if (ret) {
 456                 dev_err(dev, "cannot add irqchip\n");
 457                 goto err1;
 458         }
 459
 460         p->irq_parent = irq->start;
 461         if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
 462                              IRQF_SHARED, name, p)) {
 463                 dev_err(dev, "failed to request IRQ\n");
 464                 ret = -ENOENT;
 465                 goto err1;
 466         }
 467
 468         dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
 469
 470         /* warn in case of mismatch if irq base is specified */
 471         if (p->config.irq_base) {
 472                 ret = irq_find_mapping(gpio_chip->irqdomain, 0);
 473                 if (p->config.irq_base != ret)
 474                         dev_warn(dev, "irq base mismatch (%u/%u)\n",
 475                                  p->config.irq_base, ret);
 476         }
 477
 478         if (p->config.pctl_name) {
 479                 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
 480                                              gpio_chip->base, gpio_chip->ngpio);
 481                 if (ret < 0)
 482                         dev_warn(dev, "failed to add pin range\n");
 483         }
 484
 485         return 0;
 486
 487 err1:
 488         gpiochip_remove(gpio_chip);
 489 err0:
 490         pm_runtime_put(dev);
 491         pm_runtime_disable(dev);
 492         return ret;
 493 }
 494
 495 static int gpio_rcar_remove(struct platform_device *pdev)
 496 {
 497         struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 498
 499         gpiochip_remove(&p->gpio_chip);
 500
 501         pm_runtime_put(&pdev->dev);
 502         pm_runtime_disable(&pdev->dev);
 503         return 0;
 504 }
 505
 506 static struct platform_driver gpio_rcar_device_driver = {
 507         .probe          = gpio_rcar_probe,
 508         .remove         = gpio_rcar_remove,
 509         .driver         = {
 510                 .name   = "gpio_rcar",
 511                 .of_match_table = of_match_ptr(gpio_rcar_of_table),
 512         }
 513 };
 514
 515 module_platform_driver(gpio_rcar_device_driver);
 516
 517 MODULE_AUTHOR("Magnus Damm");
 518 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 519 MODULE_LICENSE("GPL v2");