drivers/gpio/gpio-zynq.c

   1 /*
   2  * Xilinx Zynq GPIO device driver
   3  *
   4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it under
   7  * the terms of the GNU General Public License as published by the Free Software
   8  * Foundation; either version 2 of the License, or (at your option) any later
   9  * version.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/of.h>
  22
  23 #define DRIVER_NAME "zynq-gpio"
  24
  25 /* Maximum banks */
  26 #define ZYNQ_GPIO_MAX_BANK      4
  27 #define ZYNQMP_GPIO_MAX_BANK    6
  28
  29 #define ZYNQ_GPIO_BANK0_NGPIO   32
  30 #define ZYNQ_GPIO_BANK1_NGPIO   22
  31 #define ZYNQ_GPIO_BANK2_NGPIO   32
  32 #define ZYNQ_GPIO_BANK3_NGPIO   32
  33
  34 #define ZYNQMP_GPIO_BANK0_NGPIO 26
  35 #define ZYNQMP_GPIO_BANK1_NGPIO 26
  36 #define ZYNQMP_GPIO_BANK2_NGPIO 26
  37 #define ZYNQMP_GPIO_BANK3_NGPIO 32
  38 #define ZYNQMP_GPIO_BANK4_NGPIO 32
  39 #define ZYNQMP_GPIO_BANK5_NGPIO 32
  40
  41 #define ZYNQ_GPIO_NR_GPIOS      118
  42 #define ZYNQMP_GPIO_NR_GPIOS    174
  43
  44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str)    0
  45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str)    (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
  46                                         ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
  47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str)    (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
  48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str)    (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
  49                                         ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
  50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str)    (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
  51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str)    (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
  52                                         ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
  53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str)    (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
  54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str)    (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
  55                                         ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
  56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str)    (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
  57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str)    (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
  58                                         ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
  59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str)    (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
  60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str)    (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
  61                                         ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
  62
  63
  64 /* Register offsets for the GPIO device */
  65 /* LSW Mask & Data -WO */
  66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  67 /* MSW Mask & Data -WO */
  68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  69 /* Data Register-RW */
  70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))
  71 /* Direction mode reg-RW */
  72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK)     (0x204 + (0x40 * BANK))
  73 /* Output enable reg-RW */
  74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))
  75 /* Interrupt mask reg-RO */
  76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))
  77 /* Interrupt enable reg-WO */
  78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))
  79 /* Interrupt disable reg-WO */
  80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))
  81 /* Interrupt status reg-RO */
  82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))
  83 /* Interrupt type reg-RW */
  84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))
  85 /* Interrupt polarity reg-RW */
  86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))
  87 /* Interrupt on any, reg-RW */
  88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))
  89
  90 /* Disable all interrupts mask */
  91 #define ZYNQ_GPIO_IXR_DISABLE_ALL       0xFFFFFFFF
  92
  93 /* Mid pin number of a bank */
  94 #define ZYNQ_GPIO_MID_PIN_NUM 16
  95
  96 /* GPIO upper 16 bit mask */
  97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  98
  99 /**
 100  * struct zynq_gpio - gpio device private data structure
 101  * @chip:       instance of the gpio_chip
 102  * @base_addr:  base address of the GPIO device
 103  * @clk:        clock resource for this controller
 104  * @irq:        interrupt for the GPIO device
 105  * @p_data:     pointer to platform data
 106  */
 107 struct zynq_gpio {
 108         struct gpio_chip chip;
 109         void __iomem *base_addr;
 110         struct clk *clk;
 111         int irq;
 112         const struct zynq_platform_data *p_data;
 113 };
 114
 115 /**
 116  * struct zynq_platform_data -  zynq gpio platform data structure
 117  * @label:      string to store in gpio->label
 118  * @ngpio:      max number of gpio pins
 119  * @max_bank:   maximum number of gpio banks
 120  * @bank_min:   this array represents bank's min pin
 121  * @bank_max:   this array represents bank's max pin
 122 */
 123 struct zynq_platform_data {
 124         const char *label;
 125         u16 ngpio;
 126         int max_bank;
 127         int bank_min[ZYNQMP_GPIO_MAX_BANK];
 128         int bank_max[ZYNQMP_GPIO_MAX_BANK];
 129 };
 130
 131 static struct irq_chip zynq_gpio_level_irqchip;
 132 static struct irq_chip zynq_gpio_edge_irqchip;
 133 /**
 134  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
 135  * for a given pin in the GPIO device
 136  * @pin_num:    gpio pin number within the device
 137  * @bank_num:   an output parameter used to return the bank number of the gpio
 138  *              pin
 139  * @bank_pin_num: an output parameter used to return pin number within a bank
 140  *                for the given gpio pin
 141  *
 142  * Returns the bank number and pin offset within the bank.
 143  */
 144 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 145                                           unsigned int *bank_num,
 146                                           unsigned int *bank_pin_num,
 147                                           struct zynq_gpio *gpio)
 148 {
 149         int bank;
 150
 151         for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
 152                 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
 153                         (pin_num <= gpio->p_data->bank_max[bank])) {
 154                                 *bank_num = bank;
 155                                 *bank_pin_num = pin_num -
 156                                                 gpio->p_data->bank_min[bank];
 157                                 return;
 158                 }
 159         }
 160
 161         /* default */
 162         WARN(true, "invalid GPIO pin number: %u", pin_num);
 163         *bank_num = 0;
 164         *bank_pin_num = 0;
 165 }
 166
 167 /**
 168  * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
 169  * @chip:       gpio_chip instance to be worked on
 170  * @pin:        gpio pin number within the device
 171  *
 172  * This function reads the state of the specified pin of the GPIO device.
 173  *
 174  * Return: 0 if the pin is low, 1 if pin is high.
 175  */
 176 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
 177 {
 178         u32 data;
 179         unsigned int bank_num, bank_pin_num;
 180         struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
 181
 182         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 183
 184         data = readl_relaxed(gpio->base_addr +
 185                              ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
 186
 187         return (data >> bank_pin_num) & 1;
 188 }
 189
 190 /**
 191  * zynq_gpio_set_value - Modify the state of the pin with specified value
 192  * @chip:       gpio_chip instance to be worked on
 193  * @pin:        gpio pin number within the device
 194  * @state:      value used to modify the state of the specified pin
 195  *
 196  * This function calculates the register offset (i.e to lower 16 bits or
 197  * upper 16 bits) based on the given pin number and sets the state of a
 198  * gpio pin to the specified value. The state is either 0 or non-zero.
 199  */
 200 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
 201                                 int state)
 202 {
 203         unsigned int reg_offset, bank_num, bank_pin_num;
 204         struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
 205
 206         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 207
 208         if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
 209                 /* only 16 data bits in bit maskable reg */
 210                 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
 211                 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
 212         } else {
 213                 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
 214         }
 215
 216         /*
 217          * get the 32 bit value to be written to the mask/data register where
 218          * the upper 16 bits is the mask and lower 16 bits is the data
 219          */
 220         state = !!state;
 221         state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
 222                 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 223
 224         writel_relaxed(state, gpio->base_addr + reg_offset);
 225 }
 226
 227 /**
 228  * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
 229  * @chip:       gpio_chip instance to be worked on
 230  * @pin:        gpio pin number within the device
 231  *
 232  * This function uses the read-modify-write sequence to set the direction of
 233  * the gpio pin as input.
 234  *
 235  * Return: 0 always
 236  */
 237 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
 238 {
 239         u32 reg;
 240         unsigned int bank_num, bank_pin_num;
 241         struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
 242
 243         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 244
 245         /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
 246         if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
 247                 return -EINVAL;
 248
 249         /* clear the bit in direction mode reg to set the pin as input */
 250         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 251         reg &= ~BIT(bank_pin_num);
 252         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 253
 254         return 0;
 255 }
 256
 257 /**
 258  * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
 259  * @chip:       gpio_chip instance to be worked on
 260  * @pin:        gpio pin number within the device
 261  * @state:      value to be written to specified pin
 262  *
 263  * This function sets the direction of specified GPIO pin as output, configures
 264  * the Output Enable register for the pin and uses zynq_gpio_set to set
 265  * the state of the pin to the value specified.
 266  *
 267  * Return: 0 always
 268  */
 269 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
 270                              int state)
 271 {
 272         u32 reg;
 273         unsigned int bank_num, bank_pin_num;
 274         struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
 275
 276         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 277
 278         /* set the GPIO pin as output */
 279         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 280         reg |= BIT(bank_pin_num);
 281         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 282
 283         /* configure the output enable reg for the pin */
 284         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 285         reg |= BIT(bank_pin_num);
 286         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 287
 288         /* set the state of the pin */
 289         zynq_gpio_set_value(chip, pin, state);
 290         return 0;
 291 }
 292
 293 /**
 294  * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
 295  * @irq_data:   per irq and chip data passed down to chip functions
 296  *
 297  * This function calculates gpio pin number from irq number and sets the
 298  * bit in the Interrupt Disable register of the corresponding bank to disable
 299  * interrupts for that pin.
 300  */
 301 static void zynq_gpio_irq_mask(struct irq_data *irq_data)
 302 {
 303         unsigned int device_pin_num, bank_num, bank_pin_num;
 304         struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
 305
 306         device_pin_num = irq_data->hwirq;
 307         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 308         writel_relaxed(BIT(bank_pin_num),
 309                        gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 310 }
 311
 312 /**
 313  * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
 314  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 315  *              to enable
 316  *
 317  * This function calculates the gpio pin number from irq number and sets the
 318  * bit in the Interrupt Enable register of the corresponding bank to enable
 319  * interrupts for that pin.
 320  */
 321 static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
 322 {
 323         unsigned int device_pin_num, bank_num, bank_pin_num;
 324         struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
 325
 326         device_pin_num = irq_data->hwirq;
 327         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 328         writel_relaxed(BIT(bank_pin_num),
 329                        gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
 330 }
 331
 332 /**
 333  * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
 334  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 335  *              to ack
 336  *
 337  * This function calculates gpio pin number from irq number and sets the bit
 338  * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
 339  */
 340 static void zynq_gpio_irq_ack(struct irq_data *irq_data)
 341 {
 342         unsigned int device_pin_num, bank_num, bank_pin_num;
 343         struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
 344
 345         device_pin_num = irq_data->hwirq;
 346         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 347         writel_relaxed(BIT(bank_pin_num),
 348                        gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 349 }
 350
 351 /**
 352  * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
 353  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 354  *              to enable
 355  *
 356  * Clears the INTSTS bit and unmasks the given interrupt.
 357  */
 358 static void zynq_gpio_irq_enable(struct irq_data *irq_data)
 359 {
 360         /*
 361          * The Zynq GPIO controller does not disable interrupt detection when
 362          * the interrupt is masked and only disables the propagation of the
 363          * interrupt. This means when the controller detects an interrupt
 364          * condition while the interrupt is logically disabled it will propagate
 365          * that interrupt event once the interrupt is enabled. This will cause
 366          * the interrupt consumer to see spurious interrupts to prevent this
 367          * first make sure that the interrupt is not asserted and then enable
 368          * it.
 369          */
 370         zynq_gpio_irq_ack(irq_data);
 371         zynq_gpio_irq_unmask(irq_data);
 372 }
 373
 374 /**
 375  * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
 376  * @irq_data:   irq data containing irq number of gpio pin
 377  * @type:       interrupt type that is to be set for the gpio pin
 378  *
 379  * This function gets the gpio pin number and its bank from the gpio pin number
 380  * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
 381  *
 382  * Return: 0, negative error otherwise.
 383  * TYPE-EDGE_RISING,  INT_TYPE - 1, INT_POLARITY - 1,  INT_ANY - 0;
 384  * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0,  INT_ANY - 0;
 385  * TYPE-EDGE_BOTH,    INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
 386  * TYPE-LEVEL_HIGH,   INT_TYPE - 0, INT_POLARITY - 1,  INT_ANY - NA;
 387  * TYPE-LEVEL_LOW,    INT_TYPE - 0, INT_POLARITY - 0,  INT_ANY - NA
 388  */
 389 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
 390 {
 391         u32 int_type, int_pol, int_any;
 392         unsigned int device_pin_num, bank_num, bank_pin_num;
 393         struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
 394
 395         device_pin_num = irq_data->hwirq;
 396         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 397
 398         int_type = readl_relaxed(gpio->base_addr +
 399                                  ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 400         int_pol = readl_relaxed(gpio->base_addr +
 401                                 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 402         int_any = readl_relaxed(gpio->base_addr +
 403                                 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 404
 405         /*
 406          * based on the type requested, configure the INT_TYPE, INT_POLARITY
 407          * and INT_ANY registers
 408          */
 409         switch (type) {
 410         case IRQ_TYPE_EDGE_RISING:
 411                 int_type |= BIT(bank_pin_num);
 412                 int_pol |= BIT(bank_pin_num);
 413                 int_any &= ~BIT(bank_pin_num);
 414                 break;
 415         case IRQ_TYPE_EDGE_FALLING:
 416                 int_type |= BIT(bank_pin_num);
 417                 int_pol &= ~BIT(bank_pin_num);
 418                 int_any &= ~BIT(bank_pin_num);
 419                 break;
 420         case IRQ_TYPE_EDGE_BOTH:
 421                 int_type |= BIT(bank_pin_num);
 422                 int_any |= BIT(bank_pin_num);
 423                 break;
 424         case IRQ_TYPE_LEVEL_HIGH:
 425                 int_type &= ~BIT(bank_pin_num);
 426                 int_pol |= BIT(bank_pin_num);
 427                 break;
 428         case IRQ_TYPE_LEVEL_LOW:
 429                 int_type &= ~BIT(bank_pin_num);
 430                 int_pol &= ~BIT(bank_pin_num);
 431                 break;
 432         default:
 433                 return -EINVAL;
 434         }
 435
 436         writel_relaxed(int_type,
 437                        gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 438         writel_relaxed(int_pol,
 439                        gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 440         writel_relaxed(int_any,
 441                        gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 442
 443         if (type & IRQ_TYPE_LEVEL_MASK) {
 444                 __irq_set_chip_handler_name_locked(irq_data->irq,
 445                         &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
 446         } else {
 447                 __irq_set_chip_handler_name_locked(irq_data->irq,
 448                         &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
 455 {
 456         struct zynq_gpio *gpio = irq_data_get_irq_chip_data(data);
 457
 458         irq_set_irq_wake(gpio->irq, on);
 459
 460         return 0;
 461 }
 462
 463 /* irq chip descriptor */
 464 static struct irq_chip zynq_gpio_level_irqchip = {
 465         .name           = DRIVER_NAME,
 466         .irq_enable     = zynq_gpio_irq_enable,
 467         .irq_eoi        = zynq_gpio_irq_ack,
 468         .irq_mask       = zynq_gpio_irq_mask,
 469         .irq_unmask     = zynq_gpio_irq_unmask,
 470         .irq_set_type   = zynq_gpio_set_irq_type,
 471         .irq_set_wake   = zynq_gpio_set_wake,
 472         .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
 473                           IRQCHIP_MASK_ON_SUSPEND,
 474 };
 475
 476 static struct irq_chip zynq_gpio_edge_irqchip = {
 477         .name           = DRIVER_NAME,
 478         .irq_enable     = zynq_gpio_irq_enable,
 479         .irq_ack        = zynq_gpio_irq_ack,
 480         .irq_mask       = zynq_gpio_irq_mask,
 481         .irq_unmask     = zynq_gpio_irq_unmask,
 482         .irq_set_type   = zynq_gpio_set_irq_type,
 483         .irq_set_wake   = zynq_gpio_set_wake,
 484         .flags          = IRQCHIP_MASK_ON_SUSPEND,
 485 };
 486
 487 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
 488                                       unsigned int bank_num,
 489                                       unsigned long pending)
 490 {
 491         unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
 492         struct irq_domain *irqdomain = gpio->chip.irqdomain;
 493         int offset;
 494
 495         if (!pending)
 496                 return;
 497
 498         for_each_set_bit(offset, &pending, 32) {
 499                 unsigned int gpio_irq;
 500
 501                 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
 502                 generic_handle_irq(gpio_irq);
 503         }
 504 }
 505
 506 /**
 507  * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
 508  * @irq:        irq number of the gpio bank where interrupt has occurred
 509  * @desc:       irq descriptor instance of the 'irq'
 510  *
 511  * This function reads the Interrupt Status Register of each bank to get the
 512  * gpio pin number which has triggered an interrupt. It then acks the triggered
 513  * interrupt and calls the pin specific handler set by the higher layer
 514  * application for that pin.
 515  * Note: A bug is reported if no handler is set for the gpio pin.
 516  */
 517 static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
 518 {
 519         u32 int_sts, int_enb;
 520         unsigned int bank_num;
 521         struct zynq_gpio *gpio = irq_get_handler_data(irq);
 522         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 523
 524         chained_irq_enter(irqchip, desc);
 525
 526         for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
 527                 int_sts = readl_relaxed(gpio->base_addr +
 528                                         ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 529                 int_enb = readl_relaxed(gpio->base_addr +
 530                                         ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
 531                 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
 532         }
 533
 534         chained_irq_exit(irqchip, desc);
 535 }
 536
 537 static int __maybe_unused zynq_gpio_suspend(struct device *dev)
 538 {
 539         struct platform_device *pdev = to_platform_device(dev);
 540         int irq = platform_get_irq(pdev, 0);
 541         struct irq_data *data = irq_get_irq_data(irq);
 542
 543         if (!irqd_is_wakeup_set(data))
 544                 return pm_runtime_force_suspend(dev);
 545
 546         return 0;
 547 }
 548
 549 static int __maybe_unused zynq_gpio_resume(struct device *dev)
 550 {
 551         struct platform_device *pdev = to_platform_device(dev);
 552         int irq = platform_get_irq(pdev, 0);
 553         struct irq_data *data = irq_get_irq_data(irq);
 554
 555         if (!irqd_is_wakeup_set(data))
 556                 return pm_runtime_force_resume(dev);
 557
 558         return 0;
 559 }
 560
 561 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
 562 {
 563         struct platform_device *pdev = to_platform_device(dev);
 564         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 565
 566         clk_disable_unprepare(gpio->clk);
 567
 568         return 0;
 569 }
 570
 571 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
 572 {
 573         struct platform_device *pdev = to_platform_device(dev);
 574         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 575
 576         return clk_prepare_enable(gpio->clk);
 577 }
 578
 579 static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
 580 {
 581         int ret;
 582
 583         ret = pm_runtime_get_sync(chip->dev);
 584
 585         /*
 586          * If the device is already active pm_runtime_get() will return 1 on
 587          * success, but gpio_request still needs to return 0.
 588          */
 589         return ret < 0 ? ret : 0;
 590 }
 591
 592 static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
 593 {
 594         pm_runtime_put(chip->dev);
 595 }
 596
 597 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
 598         SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
 599         SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
 600                         zynq_gpio_runtime_resume, NULL)
 601 };
 602
 603 static const struct zynq_platform_data zynqmp_gpio_def = {
 604         .label = "zynqmp_gpio",
 605         .ngpio = ZYNQMP_GPIO_NR_GPIOS,
 606         .max_bank = ZYNQMP_GPIO_MAX_BANK,
 607         .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
 608         .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
 609         .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
 610         .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
 611         .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
 612         .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
 613         .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
 614         .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
 615         .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
 616         .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
 617         .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
 618         .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
 619 };
 620
 621 static const struct zynq_platform_data zynq_gpio_def = {
 622         .label = "zynq_gpio",
 623         .ngpio = ZYNQ_GPIO_NR_GPIOS,
 624         .max_bank = ZYNQ_GPIO_MAX_BANK,
 625         .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
 626         .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
 627         .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
 628         .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
 629         .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
 630         .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
 631         .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
 632         .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
 633 };
 634
 635 static const struct of_device_id zynq_gpio_of_match[] = {
 636         { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
 637         { .compatible = "xlnx,zynqmp-gpio-1.0",
 638                                         .data = (void *)&zynqmp_gpio_def },
 639         { /* end of table */ }
 640 };
 641 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
 642
 643 /**
 644  * zynq_gpio_probe - Initialization method for a zynq_gpio device
 645  * @pdev:       platform device instance
 646  *
 647  * This function allocates memory resources for the gpio device and registers
 648  * all the banks of the device. It will also set up interrupts for the gpio
 649  * pins.
 650  * Note: Interrupts are disabled for all the banks during initialization.
 651  *
 652  * Return: 0 on success, negative error otherwise.
 653  */
 654 static int zynq_gpio_probe(struct platform_device *pdev)
 655 {
 656         int ret, bank_num;
 657         struct zynq_gpio *gpio;
 658         struct gpio_chip *chip;
 659         struct resource *res;
 660         const struct of_device_id *match;
 661
 662         gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 663         if (!gpio)
 664                 return -ENOMEM;
 665
 666         match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
 667         if (!match) {
 668                 dev_err(&pdev->dev, "of_match_node() failed\n");
 669                 return -EINVAL;
 670         }
 671         gpio->p_data = match->data;
 672         platform_set_drvdata(pdev, gpio);
 673
 674         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 675         gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
 676         if (IS_ERR(gpio->base_addr))
 677                 return PTR_ERR(gpio->base_addr);
 678
 679         gpio->irq = platform_get_irq(pdev, 0);
 680         if (gpio->irq < 0) {
 681                 dev_err(&pdev->dev, "invalid IRQ\n");
 682                 return gpio->irq;
 683         }
 684
 685         /* configure the gpio chip */
 686         chip = &gpio->chip;
 687         chip->label = gpio->p_data->label;
 688         chip->owner = THIS_MODULE;
 689         chip->dev = &pdev->dev;
 690         chip->get = zynq_gpio_get_value;
 691         chip->set = zynq_gpio_set_value;
 692         chip->request = zynq_gpio_request;
 693         chip->free = zynq_gpio_free;
 694         chip->direction_input = zynq_gpio_dir_in;
 695         chip->direction_output = zynq_gpio_dir_out;
 696         chip->base = -1;
 697         chip->ngpio = gpio->p_data->ngpio;
 698
 699         /* Enable GPIO clock */
 700         gpio->clk = devm_clk_get(&pdev->dev, NULL);
 701         if (IS_ERR(gpio->clk)) {
 702                 dev_err(&pdev->dev, "input clock not found.\n");
 703                 return PTR_ERR(gpio->clk);
 704         }
 705         ret = clk_prepare_enable(gpio->clk);
 706         if (ret) {
 707                 dev_err(&pdev->dev, "Unable to enable clock.\n");
 708                 return ret;
 709         }
 710
 711         /* report a bug if gpio chip registration fails */
 712         ret = gpiochip_add(chip);
 713         if (ret) {
 714                 dev_err(&pdev->dev, "Failed to add gpio chip\n");
 715                 goto err_disable_clk;
 716         }
 717
 718         /* disable interrupts for all banks */
 719         for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
 720                 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
 721                                ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 722
 723         ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
 724                                    handle_level_irq, IRQ_TYPE_NONE);
 725         if (ret) {
 726                 dev_err(&pdev->dev, "Failed to add irq chip\n");
 727                 goto err_rm_gpiochip;
 728         }
 729
 730         gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
 731                                      zynq_gpio_irqhandler);
 732
 733         pm_runtime_set_active(&pdev->dev);
 734         pm_runtime_enable(&pdev->dev);
 735
 736         return 0;
 737
 738 err_rm_gpiochip:
 739         gpiochip_remove(chip);
 740 err_disable_clk:
 741         clk_disable_unprepare(gpio->clk);
 742
 743         return ret;
 744 }
 745
 746 /**
 747  * zynq_gpio_remove - Driver removal function
 748  * @pdev:       platform device instance
 749  *
 750  * Return: 0 always
 751  */
 752 static int zynq_gpio_remove(struct platform_device *pdev)
 753 {
 754         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 755
 756         pm_runtime_get_sync(&pdev->dev);
 757         gpiochip_remove(&gpio->chip);
 758         clk_disable_unprepare(gpio->clk);
 759         device_set_wakeup_capable(&pdev->dev, 0);
 760         pm_runtime_disable(&pdev->dev);
 761         return 0;
 762 }
 763
 764 static struct platform_driver zynq_gpio_driver = {
 765         .driver = {
 766                 .name = DRIVER_NAME,
 767                 .pm = &zynq_gpio_dev_pm_ops,
 768                 .of_match_table = zynq_gpio_of_match,
 769         },
 770         .probe = zynq_gpio_probe,
 771         .remove = zynq_gpio_remove,
 772 };
 773
 774 /**
 775  * zynq_gpio_init - Initial driver registration call
 776  *
 777  * Return: value from platform_driver_register
 778  */
 779 static int __init zynq_gpio_init(void)
 780 {
 781         return platform_driver_register(&zynq_gpio_driver);
 782 }
 783 postcore_initcall(zynq_gpio_init);
 784
 785 MODULE_AUTHOR("Xilinx Inc.");
 786 MODULE_DESCRIPTION("Zynq GPIO driver");
 787 MODULE_LICENSE("GPL");