Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_irq.h
blob8299795f2b2ddda031effc51652129ebefa02022
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __AMDGPU_IRQ_H__
25 #define __AMDGPU_IRQ_H__
27 #include "amdgpu_ih.h"
29 #define AMDGPU_MAX_IRQ_SRC_ID 0x100
31 struct amdgpu_device;
32 struct amdgpu_iv_entry;
34 enum amdgpu_interrupt_state {
35 AMDGPU_IRQ_STATE_DISABLE,
36 AMDGPU_IRQ_STATE_ENABLE,
39 struct amdgpu_irq_src {
40 unsigned num_types;
41 atomic_t *enabled_types;
42 const struct amdgpu_irq_src_funcs *funcs;
45 /* provided by interrupt generating IP blocks */
46 struct amdgpu_irq_src_funcs {
47 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
48 unsigned type, enum amdgpu_interrupt_state state);
50 int (*process)(struct amdgpu_device *adev,
51 struct amdgpu_irq_src *source,
52 struct amdgpu_iv_entry *entry);
55 struct amdgpu_irq {
56 bool installed;
57 spinlock_t lock;
58 /* interrupt sources */
59 struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID];
61 /* status, etc. */
62 bool msi_enabled; /* msi enabled */
64 /* interrupt ring */
65 struct amdgpu_ih_ring ih;
66 const struct amdgpu_ih_funcs *ih_funcs;
69 void amdgpu_irq_preinstall(struct drm_device *dev);
70 int amdgpu_irq_postinstall(struct drm_device *dev);
71 void amdgpu_irq_uninstall(struct drm_device *dev);
72 irqreturn_t amdgpu_irq_handler(int irq, void *arg);
74 int amdgpu_irq_init(struct amdgpu_device *adev);
75 void amdgpu_irq_fini(struct amdgpu_device *adev);
76 int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
77 struct amdgpu_irq_src *source);
78 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
79 struct amdgpu_iv_entry *entry);
80 int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
81 unsigned type);
82 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
83 unsigned type);
84 bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
85 struct amdgpu_irq_src *src,
86 unsigned type);
87 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
88 unsigned type);
89 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
90 unsigned type);
92 #endif