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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_uvd.c
blob2abc661845b68d73a36d95ea1443eac225eb4fca
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT_MS 1000
44
45 /* Firmware Names */
46 #ifdef CONFIG_DRM_AMDGPU_CIK
47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
52 #endif
53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
55
56 /**
57 * amdgpu_uvd_cs_ctx - Command submission parser context
58 *
59 * Used for emulating virtual memory support on UVD 4.2.
60 */
61 struct amdgpu_uvd_cs_ctx {
62 struct amdgpu_cs_parser *parser;
63 unsigned reg, count;
64 unsigned data0, data1;
65 unsigned idx;
66 unsigned ib_idx;
67
68 /* does the IB has a msg command */
69 bool has_msg_cmd;
70
71 /* minimum buffer sizes */
72 unsigned *buf_sizes;
73 };
74
75 #ifdef CONFIG_DRM_AMDGPU_CIK
76 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
77 MODULE_FIRMWARE(FIRMWARE_KABINI);
78 MODULE_FIRMWARE(FIRMWARE_KAVERI);
79 MODULE_FIRMWARE(FIRMWARE_HAWAII);
80 MODULE_FIRMWARE(FIRMWARE_MULLINS);
81 #endif
82 MODULE_FIRMWARE(FIRMWARE_TONGA);
83 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
84
85 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
86 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
87
88 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
89 {
90 unsigned long bo_size;
91 const char *fw_name;
92 const struct common_firmware_header *hdr;
93 unsigned version_major, version_minor, family_id;
94 int i, r;
95
96 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
97
98 switch (adev->asic_type) {
99 #ifdef CONFIG_DRM_AMDGPU_CIK
100 case CHIP_BONAIRE:
101 fw_name = FIRMWARE_BONAIRE;
102 break;
103 case CHIP_KABINI:
104 fw_name = FIRMWARE_KABINI;
105 break;
106 case CHIP_KAVERI:
107 fw_name = FIRMWARE_KAVERI;
108 break;
109 case CHIP_HAWAII:
110 fw_name = FIRMWARE_HAWAII;
111 break;
112 case CHIP_MULLINS:
113 fw_name = FIRMWARE_MULLINS;
114 break;
115 #endif
116 case CHIP_TONGA:
117 fw_name = FIRMWARE_TONGA;
118 break;
119 case CHIP_CARRIZO:
120 fw_name = FIRMWARE_CARRIZO;
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
127 if (r) {
128 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
129 fw_name);
130 return r;
131 }
132
133 r = amdgpu_ucode_validate(adev->uvd.fw);
134 if (r) {
135 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
136 fw_name);
137 release_firmware(adev->uvd.fw);
138 adev->uvd.fw = NULL;
139 return r;
140 }
141
142 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
143 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
144 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
145 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
146 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
147 version_major, version_minor, family_id);
148
149 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
150 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
151 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
152 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo);
153 if (r) {
154 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
155 return r;
156 }
157
158 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
159 if (r) {
160 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
161 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
162 return r;
163 }
164
165 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
166 &adev->uvd.gpu_addr);
167 if (r) {
168 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
169 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
170 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
171 return r;
172 }
173
174 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
175 if (r) {
176 dev_err(adev->dev, "(%d) UVD map failed\n", r);
177 return r;
178 }
179
180 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
181
182 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
183 atomic_set(&adev->uvd.handles[i], 0);
184 adev->uvd.filp[i] = NULL;
185 }
186
187 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
188 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
189 adev->uvd.address_64_bit = true;
190
191 return 0;
192 }
193
194 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
195 {
196 int r;
197
198 if (adev->uvd.vcpu_bo == NULL)
199 return 0;
200
201 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
202 if (!r) {
203 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
204 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
205 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
206 }
207
208 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
209
210 amdgpu_ring_fini(&adev->uvd.ring);
211
212 release_firmware(adev->uvd.fw);
213
214 return 0;
215 }
216
217 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
218 {
219 unsigned size;
220 void *ptr;
221 const struct common_firmware_header *hdr;
222 int i;
223
224 if (adev->uvd.vcpu_bo == NULL)
225 return 0;
226
227 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
228 if (atomic_read(&adev->uvd.handles[i]))
229 break;
230
231 if (i == AMDGPU_MAX_UVD_HANDLES)
232 return 0;
233
234 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
235
236 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
237 size -= le32_to_cpu(hdr->ucode_size_bytes);
238
239 ptr = adev->uvd.cpu_addr;
240 ptr += le32_to_cpu(hdr->ucode_size_bytes);
241
242 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
243 memcpy(adev->uvd.saved_bo, ptr, size);
244
245 return 0;
246 }
247
248 int amdgpu_uvd_resume(struct amdgpu_device *adev)
249 {
250 unsigned size;
251 void *ptr;
252 const struct common_firmware_header *hdr;
253 unsigned offset;
254
255 if (adev->uvd.vcpu_bo == NULL)
256 return -EINVAL;
257
258 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
259 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
260 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
261 (adev->uvd.fw->size) - offset);
262
263 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
264 size -= le32_to_cpu(hdr->ucode_size_bytes);
265 ptr = adev->uvd.cpu_addr;
266 ptr += le32_to_cpu(hdr->ucode_size_bytes);
267
268 if (adev->uvd.saved_bo != NULL) {
269 memcpy(ptr, adev->uvd.saved_bo, size);
270 kfree(adev->uvd.saved_bo);
271 adev->uvd.saved_bo = NULL;
272 } else
273 memset(ptr, 0, size);
274
275 return 0;
276 }
277
278 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
279 {
280 struct amdgpu_ring *ring = &adev->uvd.ring;
281 int i, r;
282
283 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
284 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
285 if (handle != 0 && adev->uvd.filp[i] == filp) {
286 struct amdgpu_fence *fence;
287
288 amdgpu_uvd_note_usage(adev);
289
290 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
291 if (r) {
292 DRM_ERROR("Error destroying UVD (%d)!\n", r);
293 continue;
294 }
295
296 amdgpu_fence_wait(fence, false);
297 amdgpu_fence_unref(&fence);
298
299 adev->uvd.filp[i] = NULL;
300 atomic_set(&adev->uvd.handles[i], 0);
301 }
302 }
303 }
304
305 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
306 {
307 int i;
308 for (i = 0; i < rbo->placement.num_placement; ++i) {
309 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
310 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
311 }
312 }
313
314 /**
315 * amdgpu_uvd_cs_pass1 - first parsing round
316 *
317 * @ctx: UVD parser context
318 *
319 * Make sure UVD message and feedback buffers are in VRAM and
320 * nobody is violating an 256MB boundary.
321 */
322 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
323 {
324 struct amdgpu_bo_va_mapping *mapping;
325 struct amdgpu_bo *bo;
326 uint32_t cmd, lo, hi;
327 uint64_t addr;
328 int r = 0;
329
330 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
331 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
332 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
333
334 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
335 if (mapping == NULL) {
336 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
337 return -EINVAL;
338 }
339
340 if (!ctx->parser->adev->uvd.address_64_bit) {
341 /* check if it's a message or feedback command */
342 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
343 if (cmd == 0x0 || cmd == 0x3) {
344 /* yes, force it into VRAM */
345 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
346 amdgpu_ttm_placement_from_domain(bo, domain);
347 }
348 amdgpu_uvd_force_into_uvd_segment(bo);
349
350 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
351 }
352
353 return r;
354 }
355
356 /**
357 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
358 *
359 * @msg: pointer to message structure
360 * @buf_sizes: returned buffer sizes
361 *
362 * Peek into the decode message and calculate the necessary buffer sizes.
363 */
364 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
365 {
366 unsigned stream_type = msg[4];
367 unsigned width = msg[6];
368 unsigned height = msg[7];
369 unsigned dpb_size = msg[9];
370 unsigned pitch = msg[28];
371 unsigned level = msg[57];
372
373 unsigned width_in_mb = width / 16;
374 unsigned height_in_mb = ALIGN(height / 16, 2);
375 unsigned fs_in_mb = width_in_mb * height_in_mb;
376
377 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
378 unsigned min_ctx_size = 0;
379
380 image_size = width * height;
381 image_size += image_size / 2;
382 image_size = ALIGN(image_size, 1024);
383
384 switch (stream_type) {
385 case 0: /* H264 */
386 case 7: /* H264 Perf */
387 switch(level) {
388 case 30:
389 num_dpb_buffer = 8100 / fs_in_mb;
390 break;
391 case 31:
392 num_dpb_buffer = 18000 / fs_in_mb;
393 break;
394 case 32:
395 num_dpb_buffer = 20480 / fs_in_mb;
396 break;
397 case 41:
398 num_dpb_buffer = 32768 / fs_in_mb;
399 break;
400 case 42:
401 num_dpb_buffer = 34816 / fs_in_mb;
402 break;
403 case 50:
404 num_dpb_buffer = 110400 / fs_in_mb;
405 break;
406 case 51:
407 num_dpb_buffer = 184320 / fs_in_mb;
408 break;
409 default:
410 num_dpb_buffer = 184320 / fs_in_mb;
411 break;
412 }
413 num_dpb_buffer++;
414 if (num_dpb_buffer > 17)
415 num_dpb_buffer = 17;
416
417 /* reference picture buffer */
418 min_dpb_size = image_size * num_dpb_buffer;
419
420 /* macroblock context buffer */
421 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
422
423 /* IT surface buffer */
424 min_dpb_size += width_in_mb * height_in_mb * 32;
425 break;
426
427 case 1: /* VC1 */
428
429 /* reference picture buffer */
430 min_dpb_size = image_size * 3;
431
432 /* CONTEXT_BUFFER */
433 min_dpb_size += width_in_mb * height_in_mb * 128;
434
435 /* IT surface buffer */
436 min_dpb_size += width_in_mb * 64;
437
438 /* DB surface buffer */
439 min_dpb_size += width_in_mb * 128;
440
441 /* BP */
442 tmp = max(width_in_mb, height_in_mb);
443 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
444 break;
445
446 case 3: /* MPEG2 */
447
448 /* reference picture buffer */
449 min_dpb_size = image_size * 3;
450 break;
451
452 case 4: /* MPEG4 */
453
454 /* reference picture buffer */
455 min_dpb_size = image_size * 3;
456
457 /* CM */
458 min_dpb_size += width_in_mb * height_in_mb * 64;
459
460 /* IT surface buffer */
461 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
462 break;
463
464 case 16: /* H265 */
465 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
466 image_size = ALIGN(image_size, 256);
467
468 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
469 min_dpb_size = image_size * num_dpb_buffer;
470 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
471 * 16 * num_dpb_buffer + 52 * 1024;
472 break;
473
474 default:
475 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
476 return -EINVAL;
477 }
478
479 if (width > pitch) {
480 DRM_ERROR("Invalid UVD decoding target pitch!\n");
481 return -EINVAL;
482 }
483
484 if (dpb_size < min_dpb_size) {
485 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
486 dpb_size, min_dpb_size);
487 return -EINVAL;
488 }
489
490 buf_sizes[0x1] = dpb_size;
491 buf_sizes[0x2] = image_size;
492 buf_sizes[0x4] = min_ctx_size;
493 return 0;
494 }
495
496 /**
497 * amdgpu_uvd_cs_msg - handle UVD message
498 *
499 * @ctx: UVD parser context
500 * @bo: buffer object containing the message
501 * @offset: offset into the buffer object
502 *
503 * Peek into the UVD message and extract the session id.
504 * Make sure that we don't open up to many sessions.
505 */
506 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
507 struct amdgpu_bo *bo, unsigned offset)
508 {
509 struct amdgpu_device *adev = ctx->parser->adev;
510 int32_t *msg, msg_type, handle;
511 struct fence *f;
512 void *ptr;
513
514 int i, r;
515
516 if (offset & 0x3F) {
517 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
518 return -EINVAL;
519 }
520
521 f = reservation_object_get_excl(bo->tbo.resv);
522 if (f) {
523 r = amdgpu_fence_wait((struct amdgpu_fence *)f, false);
524 if (r) {
525 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
526 return r;
527 }
528 }
529
530 r = amdgpu_bo_kmap(bo, &ptr);
531 if (r) {
532 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
533 return r;
534 }
535
536 msg = ptr + offset;
537
538 msg_type = msg[1];
539 handle = msg[2];
540
541 if (handle == 0) {
542 DRM_ERROR("Invalid UVD handle!\n");
543 return -EINVAL;
544 }
545
546 if (msg_type == 1) {
547 /* it's a decode msg, calc buffer sizes */
548 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
549 amdgpu_bo_kunmap(bo);
550 if (r)
551 return r;
552
553 } else if (msg_type == 2) {
554 /* it's a destroy msg, free the handle */
555 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
556 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
557 amdgpu_bo_kunmap(bo);
558 return 0;
559 } else {
560 /* it's a create msg */
561 amdgpu_bo_kunmap(bo);
562
563 if (msg_type != 0) {
564 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
565 return -EINVAL;
566 }
567
568 /* it's a create msg, no special handling needed */
569 }
570
571 /* create or decode, validate the handle */
572 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
573 if (atomic_read(&adev->uvd.handles[i]) == handle)
574 return 0;
575 }
576
577 /* handle not found try to alloc a new one */
578 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
579 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
580 adev->uvd.filp[i] = ctx->parser->filp;
581 return 0;
582 }
583 }
584
585 DRM_ERROR("No more free UVD handles!\n");
586 return -EINVAL;
587 }
588
589 /**
590 * amdgpu_uvd_cs_pass2 - second parsing round
591 *
592 * @ctx: UVD parser context
593 *
594 * Patch buffer addresses, make sure buffer sizes are correct.
595 */
596 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
597 {
598 struct amdgpu_bo_va_mapping *mapping;
599 struct amdgpu_bo *bo;
600 struct amdgpu_ib *ib;
601 uint32_t cmd, lo, hi;
602 uint64_t start, end;
603 uint64_t addr;
604 int r;
605
606 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
607 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
608 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
609
610 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
611 if (mapping == NULL)
612 return -EINVAL;
613
614 start = amdgpu_bo_gpu_offset(bo);
615
616 end = (mapping->it.last + 1 - mapping->it.start);
617 end = end * AMDGPU_GPU_PAGE_SIZE + start;
618
619 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
620 start += addr;
621
622 ib = &ctx->parser->ibs[ctx->ib_idx];
623 ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
624 ib->ptr[ctx->data1] = start >> 32;
625
626 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
627 if (cmd < 0x4) {
628 if ((end - start) < ctx->buf_sizes[cmd]) {
629 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
630 (unsigned)(end - start),
631 ctx->buf_sizes[cmd]);
632 return -EINVAL;
633 }
634
635 } else if (cmd == 0x206) {
636 if ((end - start) < ctx->buf_sizes[4]) {
637 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
638 (unsigned)(end - start),
639 ctx->buf_sizes[4]);
640 return -EINVAL;
641 }
642 } else if ((cmd != 0x100) && (cmd != 0x204)) {
643 DRM_ERROR("invalid UVD command %X!\n", cmd);
644 return -EINVAL;
645 }
646
647 if (!ctx->parser->adev->uvd.address_64_bit) {
648 if ((start >> 28) != ((end - 1) >> 28)) {
649 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
650 start, end);
651 return -EINVAL;
652 }
653
654 if ((cmd == 0 || cmd == 0x3) &&
655 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
656 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
657 start, end);
658 return -EINVAL;
659 }
660 }
661
662 if (cmd == 0) {
663 ctx->has_msg_cmd = true;
664 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
665 if (r)
666 return r;
667 } else if (!ctx->has_msg_cmd) {
668 DRM_ERROR("Message needed before other commands are send!\n");
669 return -EINVAL;
670 }
671
672 return 0;
673 }
674
675 /**
676 * amdgpu_uvd_cs_reg - parse register writes
677 *
678 * @ctx: UVD parser context
679 * @cb: callback function
680 *
681 * Parse the register writes, call cb on each complete command.
682 */
683 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
684 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
685 {
686 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
687 int i, r;
688
689 ctx->idx++;
690 for (i = 0; i <= ctx->count; ++i) {
691 unsigned reg = ctx->reg + i;
692
693 if (ctx->idx >= ib->length_dw) {
694 DRM_ERROR("Register command after end of CS!\n");
695 return -EINVAL;
696 }
697
698 switch (reg) {
699 case mmUVD_GPCOM_VCPU_DATA0:
700 ctx->data0 = ctx->idx;
701 break;
702 case mmUVD_GPCOM_VCPU_DATA1:
703 ctx->data1 = ctx->idx;
704 break;
705 case mmUVD_GPCOM_VCPU_CMD:
706 r = cb(ctx);
707 if (r)
708 return r;
709 break;
710 case mmUVD_ENGINE_CNTL:
711 break;
712 default:
713 DRM_ERROR("Invalid reg 0x%X!\n", reg);
714 return -EINVAL;
715 }
716 ctx->idx++;
717 }
718 return 0;
719 }
720
721 /**
722 * amdgpu_uvd_cs_packets - parse UVD packets
723 *
724 * @ctx: UVD parser context
725 * @cb: callback function
726 *
727 * Parse the command stream packets.
728 */
729 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
730 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
731 {
732 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
733 int r;
734
735 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
736 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
737 unsigned type = CP_PACKET_GET_TYPE(cmd);
738 switch (type) {
739 case PACKET_TYPE0:
740 ctx->reg = CP_PACKET0_GET_REG(cmd);
741 ctx->count = CP_PACKET_GET_COUNT(cmd);
742 r = amdgpu_uvd_cs_reg(ctx, cb);
743 if (r)
744 return r;
745 break;
746 case PACKET_TYPE2:
747 ++ctx->idx;
748 break;
749 default:
750 DRM_ERROR("Unknown packet type %d !\n", type);
751 return -EINVAL;
752 }
753 }
754 return 0;
755 }
756
757 /**
758 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
759 *
760 * @parser: Command submission parser context
761 *
762 * Parse the command stream, patch in addresses as necessary.
763 */
764 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
765 {
766 struct amdgpu_uvd_cs_ctx ctx = {};
767 unsigned buf_sizes[] = {
768 [0x00000000] = 2048,
769 [0x00000001] = 0xFFFFFFFF,
770 [0x00000002] = 0xFFFFFFFF,
771 [0x00000003] = 2048,
772 [0x00000004] = 0xFFFFFFFF,
773 };
774 struct amdgpu_ib *ib = &parser->ibs[ib_idx];
775 int r;
776
777 if (ib->length_dw % 16) {
778 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
779 ib->length_dw);
780 return -EINVAL;
781 }
782
783 ctx.parser = parser;
784 ctx.buf_sizes = buf_sizes;
785 ctx.ib_idx = ib_idx;
786
787 /* first round, make sure the buffers are actually in the UVD segment */
788 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
789 if (r)
790 return r;
791
792 /* second round, patch buffer addresses into the command stream */
793 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
794 if (r)
795 return r;
796
797 if (!ctx.has_msg_cmd) {
798 DRM_ERROR("UVD-IBs need a msg command!\n");
799 return -EINVAL;
800 }
801
802 amdgpu_uvd_note_usage(ctx.parser->adev);
803
804 return 0;
805 }
806
807 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
808 struct amdgpu_bo *bo,
809 struct amdgpu_fence **fence)
810 {
811 struct ttm_validate_buffer tv;
812 struct ww_acquire_ctx ticket;
813 struct list_head head;
814 struct amdgpu_ib ib;
815 uint64_t addr;
816 int i, r;
817
818 memset(&tv, 0, sizeof(tv));
819 tv.bo = &bo->tbo;
820
821 INIT_LIST_HEAD(&head);
822 list_add(&tv.head, &head);
823
824 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
825 if (r)
826 return r;
827
828 if (!bo->adev->uvd.address_64_bit) {
829 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
830 amdgpu_uvd_force_into_uvd_segment(bo);
831 }
832
833 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
834 if (r)
835 goto err;
836
837 r = amdgpu_ib_get(ring, NULL, 64, &ib);
838 if (r)
839 goto err;
840
841 addr = amdgpu_bo_gpu_offset(bo);
842 ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
843 ib.ptr[1] = addr;
844 ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
845 ib.ptr[3] = addr >> 32;
846 ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
847 ib.ptr[5] = 0;
848 for (i = 6; i < 16; ++i)
849 ib.ptr[i] = PACKET2(0);
850 ib.length_dw = 16;
851
852 r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
853 if (r)
854 goto err;
855 ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base);
856
857 if (fence)
858 *fence = amdgpu_fence_ref(ib.fence);
859
860 amdgpu_ib_free(ring->adev, &ib);
861 amdgpu_bo_unref(&bo);
862 return 0;
863
864 err:
865 ttm_eu_backoff_reservation(&ticket, &head);
866 return r;
867 }
868
869 /* multiple fence commands without any stream commands in between can
870 crash the vcpu so just try to emmit a dummy create/destroy msg to
871 avoid this */
872 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
873 struct amdgpu_fence **fence)
874 {
875 struct amdgpu_device *adev = ring->adev;
876 struct amdgpu_bo *bo;
877 uint32_t *msg;
878 int r, i;
879
880 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
881 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
882 if (r)
883 return r;
884
885 r = amdgpu_bo_reserve(bo, false);
886 if (r) {
887 amdgpu_bo_unref(&bo);
888 return r;
889 }
890
891 r = amdgpu_bo_kmap(bo, (void **)&msg);
892 if (r) {
893 amdgpu_bo_unreserve(bo);
894 amdgpu_bo_unref(&bo);
895 return r;
896 }
897
898 /* stitch together an UVD create msg */
899 msg[0] = cpu_to_le32(0x00000de4);
900 msg[1] = cpu_to_le32(0x00000000);
901 msg[2] = cpu_to_le32(handle);
902 msg[3] = cpu_to_le32(0x00000000);
903 msg[4] = cpu_to_le32(0x00000000);
904 msg[5] = cpu_to_le32(0x00000000);
905 msg[6] = cpu_to_le32(0x00000000);
906 msg[7] = cpu_to_le32(0x00000780);
907 msg[8] = cpu_to_le32(0x00000440);
908 msg[9] = cpu_to_le32(0x00000000);
909 msg[10] = cpu_to_le32(0x01b37000);
910 for (i = 11; i < 1024; ++i)
911 msg[i] = cpu_to_le32(0x0);
912
913 amdgpu_bo_kunmap(bo);
914 amdgpu_bo_unreserve(bo);
915
916 return amdgpu_uvd_send_msg(ring, bo, fence);
917 }
918
919 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
920 struct amdgpu_fence **fence)
921 {
922 struct amdgpu_device *adev = ring->adev;
923 struct amdgpu_bo *bo;
924 uint32_t *msg;
925 int r, i;
926
927 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
928 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
929 if (r)
930 return r;
931
932 r = amdgpu_bo_reserve(bo, false);
933 if (r) {
934 amdgpu_bo_unref(&bo);
935 return r;
936 }
937
938 r = amdgpu_bo_kmap(bo, (void **)&msg);
939 if (r) {
940 amdgpu_bo_unreserve(bo);
941 amdgpu_bo_unref(&bo);
942 return r;
943 }
944
945 /* stitch together an UVD destroy msg */
946 msg[0] = cpu_to_le32(0x00000de4);
947 msg[1] = cpu_to_le32(0x00000002);
948 msg[2] = cpu_to_le32(handle);
949 msg[3] = cpu_to_le32(0x00000000);
950 for (i = 4; i < 1024; ++i)
951 msg[i] = cpu_to_le32(0x0);
952
953 amdgpu_bo_kunmap(bo);
954 amdgpu_bo_unreserve(bo);
955
956 return amdgpu_uvd_send_msg(ring, bo, fence);
957 }
958
959 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
960 {
961 struct amdgpu_device *adev =
962 container_of(work, struct amdgpu_device, uvd.idle_work.work);
963 unsigned i, fences, handles = 0;
964
965 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
966
967 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
968 if (atomic_read(&adev->uvd.handles[i]))
969 ++handles;
970
971 if (fences == 0 && handles == 0) {
972 if (adev->pm.dpm_enabled) {
973 amdgpu_dpm_enable_uvd(adev, false);
974 } else {
975 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
976 }
977 } else {
978 schedule_delayed_work(&adev->uvd.idle_work,
979 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
980 }
981 }
982
983 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
984 {
985 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
986 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
987 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
988
989 if (set_clocks) {
990 if (adev->pm.dpm_enabled) {
991 amdgpu_dpm_enable_uvd(adev, true);
992 } else {
993 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
994 }
995 }
996 }
Linux with added FPC-III support