2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_ih.h"
28 #include "oss/oss_3_0_1_d.h"
29 #include "oss/oss_3_0_1_sh_mask.h"
31 #include "bif/bif_5_1_d.h"
32 #include "bif/bif_5_1_sh_mask.h"
36 * Starting with r6xx, interrupts are handled via a ring buffer.
37 * Ring buffers are areas of GPU accessible memory that the GPU
38 * writes interrupt vectors into and the host reads vectors out of.
39 * There is a rptr (read pointer) that determines where the
40 * host is currently reading, and a wptr (write pointer)
41 * which determines where the GPU has written. When the
42 * pointers are equal, the ring is idle. When the GPU
43 * writes vectors to the ring buffer, it increments the
44 * wptr. When there is an interrupt, the host then starts
45 * fetching commands and processing them until the pointers are
46 * equal again at which point it updates the rptr.
49 static void cz_ih_set_interrupt_funcs(struct amdgpu_device
*adev
);
52 * cz_ih_enable_interrupts - Enable the interrupt ring buffer
54 * @adev: amdgpu_device pointer
56 * Enable the interrupt ring buffer (VI).
58 static void cz_ih_enable_interrupts(struct amdgpu_device
*adev
)
60 u32 ih_cntl
= RREG32(mmIH_CNTL
);
61 u32 ih_rb_cntl
= RREG32(mmIH_RB_CNTL
);
63 ih_cntl
= REG_SET_FIELD(ih_cntl
, IH_CNTL
, ENABLE_INTR
, 1);
64 ih_rb_cntl
= REG_SET_FIELD(ih_rb_cntl
, IH_RB_CNTL
, RB_ENABLE
, 1);
65 WREG32(mmIH_CNTL
, ih_cntl
);
66 WREG32(mmIH_RB_CNTL
, ih_rb_cntl
);
67 adev
->irq
.ih
.enabled
= true;
71 * cz_ih_disable_interrupts - Disable the interrupt ring buffer
73 * @adev: amdgpu_device pointer
75 * Disable the interrupt ring buffer (VI).
77 static void cz_ih_disable_interrupts(struct amdgpu_device
*adev
)
79 u32 ih_rb_cntl
= RREG32(mmIH_RB_CNTL
);
80 u32 ih_cntl
= RREG32(mmIH_CNTL
);
82 ih_rb_cntl
= REG_SET_FIELD(ih_rb_cntl
, IH_RB_CNTL
, RB_ENABLE
, 0);
83 ih_cntl
= REG_SET_FIELD(ih_cntl
, IH_CNTL
, ENABLE_INTR
, 0);
84 WREG32(mmIH_RB_CNTL
, ih_rb_cntl
);
85 WREG32(mmIH_CNTL
, ih_cntl
);
86 /* set rptr, wptr to 0 */
87 WREG32(mmIH_RB_RPTR
, 0);
88 WREG32(mmIH_RB_WPTR
, 0);
89 adev
->irq
.ih
.enabled
= false;
90 adev
->irq
.ih
.rptr
= 0;
94 * cz_ih_irq_init - init and enable the interrupt ring
96 * @adev: amdgpu_device pointer
98 * Allocate a ring buffer for the interrupt controller,
99 * enable the RLC, disable interrupts, enable the IH
100 * ring buffer and enable it (VI).
101 * Called at device load and reume.
102 * Returns 0 for success, errors for failure.
104 static int cz_ih_irq_init(struct amdgpu_device
*adev
)
108 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
112 cz_ih_disable_interrupts(adev
);
114 /* setup interrupt control */
115 WREG32(mmINTERRUPT_CNTL2
, adev
->dummy_page
.addr
>> 8);
116 interrupt_cntl
= RREG32(mmINTERRUPT_CNTL
);
117 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
118 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
120 interrupt_cntl
= REG_SET_FIELD(interrupt_cntl
, INTERRUPT_CNTL
, IH_DUMMY_RD_OVERRIDE
, 0);
121 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
122 interrupt_cntl
= REG_SET_FIELD(interrupt_cntl
, INTERRUPT_CNTL
, IH_REQ_NONSNOOP_EN
, 0);
123 WREG32(mmINTERRUPT_CNTL
, interrupt_cntl
);
125 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
126 WREG32(mmIH_RB_BASE
, adev
->irq
.ih
.gpu_addr
>> 8);
128 rb_bufsz
= order_base_2(adev
->irq
.ih
.ring_size
/ 4);
129 ih_rb_cntl
= REG_SET_FIELD(0, IH_RB_CNTL
, WPTR_OVERFLOW_ENABLE
, 1);
130 ih_rb_cntl
= REG_SET_FIELD(ih_rb_cntl
, IH_RB_CNTL
, WPTR_OVERFLOW_CLEAR
, 1);
131 ih_rb_cntl
= REG_SET_FIELD(ih_rb_cntl
, IH_RB_CNTL
, RB_SIZE
, rb_bufsz
);
133 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
134 ih_rb_cntl
= REG_SET_FIELD(ih_rb_cntl
, IH_RB_CNTL
, WPTR_WRITEBACK_ENABLE
, 1);
136 /* set the writeback address whether it's enabled or not */
137 wptr_off
= adev
->wb
.gpu_addr
+ (adev
->irq
.ih
.wptr_offs
* 4);
138 WREG32(mmIH_RB_WPTR_ADDR_LO
, lower_32_bits(wptr_off
));
139 WREG32(mmIH_RB_WPTR_ADDR_HI
, upper_32_bits(wptr_off
) & 0xFF);
141 WREG32(mmIH_RB_CNTL
, ih_rb_cntl
);
143 /* set rptr, wptr to 0 */
144 WREG32(mmIH_RB_RPTR
, 0);
145 WREG32(mmIH_RB_WPTR
, 0);
147 /* Default settings for IH_CNTL (disabled at first) */
148 ih_cntl
= RREG32(mmIH_CNTL
);
149 ih_cntl
= REG_SET_FIELD(ih_cntl
, IH_CNTL
, MC_VMID
, 0);
151 if (adev
->irq
.msi_enabled
)
152 ih_cntl
= REG_SET_FIELD(ih_cntl
, IH_CNTL
, RPTR_REARM
, 1);
153 WREG32(mmIH_CNTL
, ih_cntl
);
155 pci_set_master(adev
->pdev
);
157 /* enable interrupts */
158 cz_ih_enable_interrupts(adev
);
164 * cz_ih_irq_disable - disable interrupts
166 * @adev: amdgpu_device pointer
168 * Disable interrupts on the hw (VI).
170 static void cz_ih_irq_disable(struct amdgpu_device
*adev
)
172 cz_ih_disable_interrupts(adev
);
174 /* Wait and acknowledge irq */
179 * cz_ih_get_wptr - get the IH ring buffer wptr
181 * @adev: amdgpu_device pointer
183 * Get the IH ring buffer wptr from either the register
184 * or the writeback memory buffer (VI). Also check for
185 * ring buffer overflow and deal with it.
186 * Used by cz_irq_process(VI).
187 * Returns the value of the wptr.
189 static u32
cz_ih_get_wptr(struct amdgpu_device
*adev
)
193 wptr
= le32_to_cpu(adev
->wb
.wb
[adev
->irq
.ih
.wptr_offs
]);
195 if (REG_GET_FIELD(wptr
, IH_RB_WPTR
, RB_OVERFLOW
)) {
196 wptr
= REG_SET_FIELD(wptr
, IH_RB_WPTR
, RB_OVERFLOW
, 0);
197 /* When a ring buffer overflow happen start parsing interrupt
198 * from the last not overwritten vector (wptr + 16). Hopefully
199 * this should allow us to catchup.
201 dev_warn(adev
->dev
, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
202 wptr
, adev
->irq
.ih
.rptr
, (wptr
+ 16) & adev
->irq
.ih
.ptr_mask
);
203 adev
->irq
.ih
.rptr
= (wptr
+ 16) & adev
->irq
.ih
.ptr_mask
;
204 tmp
= RREG32(mmIH_RB_CNTL
);
205 tmp
= REG_SET_FIELD(tmp
, IH_RB_CNTL
, WPTR_OVERFLOW_CLEAR
, 1);
206 WREG32(mmIH_RB_CNTL
, tmp
);
208 return (wptr
& adev
->irq
.ih
.ptr_mask
);
212 * cz_ih_decode_iv - decode an interrupt vector
214 * @adev: amdgpu_device pointer
216 * Decodes the interrupt vector at the current rptr
217 * position and also advance the position.
219 static void cz_ih_decode_iv(struct amdgpu_device
*adev
,
220 struct amdgpu_iv_entry
*entry
)
222 /* wptr/rptr are in bytes! */
223 u32 ring_index
= adev
->irq
.ih
.rptr
>> 2;
226 dw
[0] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 0]);
227 dw
[1] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 1]);
228 dw
[2] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 2]);
229 dw
[3] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 3]);
231 entry
->src_id
= dw
[0] & 0xff;
232 entry
->src_data
= dw
[1] & 0xfffffff;
233 entry
->ring_id
= dw
[2] & 0xff;
234 entry
->vm_id
= (dw
[2] >> 8) & 0xff;
235 entry
->pas_id
= (dw
[2] >> 16) & 0xffff;
237 /* wptr/rptr are in bytes! */
238 adev
->irq
.ih
.rptr
+= 16;
242 * cz_ih_set_rptr - set the IH ring buffer rptr
244 * @adev: amdgpu_device pointer
246 * Set the IH ring buffer rptr.
248 static void cz_ih_set_rptr(struct amdgpu_device
*adev
)
250 WREG32(mmIH_RB_RPTR
, adev
->irq
.ih
.rptr
);
253 static int cz_ih_early_init(void *handle
)
255 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
257 cz_ih_set_interrupt_funcs(adev
);
261 static int cz_ih_sw_init(void *handle
)
264 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
266 r
= amdgpu_ih_ring_init(adev
, 64 * 1024, false);
270 r
= amdgpu_irq_init(adev
);
275 static int cz_ih_sw_fini(void *handle
)
277 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
279 amdgpu_irq_fini(adev
);
280 amdgpu_ih_ring_fini(adev
);
285 static int cz_ih_hw_init(void *handle
)
288 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
290 r
= cz_ih_irq_init(adev
);
297 static int cz_ih_hw_fini(void *handle
)
299 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
301 cz_ih_irq_disable(adev
);
306 static int cz_ih_suspend(void *handle
)
308 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
310 return cz_ih_hw_fini(adev
);
313 static int cz_ih_resume(void *handle
)
315 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
317 return cz_ih_hw_init(adev
);
320 static bool cz_ih_is_idle(void *handle
)
322 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
323 u32 tmp
= RREG32(mmSRBM_STATUS
);
325 if (REG_GET_FIELD(tmp
, SRBM_STATUS
, IH_BUSY
))
331 static int cz_ih_wait_for_idle(void *handle
)
335 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
337 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
339 tmp
= RREG32(mmSRBM_STATUS
);
340 if (!REG_GET_FIELD(tmp
, SRBM_STATUS
, IH_BUSY
))
347 static void cz_ih_print_status(void *handle
)
349 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
351 dev_info(adev
->dev
, "CZ IH registers\n");
352 dev_info(adev
->dev
, " SRBM_STATUS=0x%08X\n",
353 RREG32(mmSRBM_STATUS
));
354 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
355 RREG32(mmSRBM_STATUS2
));
356 dev_info(adev
->dev
, " INTERRUPT_CNTL=0x%08X\n",
357 RREG32(mmINTERRUPT_CNTL
));
358 dev_info(adev
->dev
, " INTERRUPT_CNTL2=0x%08X\n",
359 RREG32(mmINTERRUPT_CNTL2
));
360 dev_info(adev
->dev
, " IH_CNTL=0x%08X\n",
362 dev_info(adev
->dev
, " IH_RB_CNTL=0x%08X\n",
363 RREG32(mmIH_RB_CNTL
));
364 dev_info(adev
->dev
, " IH_RB_BASE=0x%08X\n",
365 RREG32(mmIH_RB_BASE
));
366 dev_info(adev
->dev
, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
367 RREG32(mmIH_RB_WPTR_ADDR_LO
));
368 dev_info(adev
->dev
, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
369 RREG32(mmIH_RB_WPTR_ADDR_HI
));
370 dev_info(adev
->dev
, " IH_RB_RPTR=0x%08X\n",
371 RREG32(mmIH_RB_RPTR
));
372 dev_info(adev
->dev
, " IH_RB_WPTR=0x%08X\n",
373 RREG32(mmIH_RB_WPTR
));
376 static int cz_ih_soft_reset(void *handle
)
378 u32 srbm_soft_reset
= 0;
379 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
380 u32 tmp
= RREG32(mmSRBM_STATUS
);
382 if (tmp
& SRBM_STATUS__IH_BUSY_MASK
)
383 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
,
386 if (srbm_soft_reset
) {
387 cz_ih_print_status((void *)adev
);
389 tmp
= RREG32(mmSRBM_SOFT_RESET
);
390 tmp
|= srbm_soft_reset
;
391 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
392 WREG32(mmSRBM_SOFT_RESET
, tmp
);
393 tmp
= RREG32(mmSRBM_SOFT_RESET
);
397 tmp
&= ~srbm_soft_reset
;
398 WREG32(mmSRBM_SOFT_RESET
, tmp
);
399 tmp
= RREG32(mmSRBM_SOFT_RESET
);
401 /* Wait a little for things to settle down */
404 cz_ih_print_status((void *)adev
);
410 static int cz_ih_set_clockgating_state(void *handle
,
411 enum amd_clockgating_state state
)
417 static int cz_ih_set_powergating_state(void *handle
,
418 enum amd_powergating_state state
)
424 const struct amd_ip_funcs cz_ih_ip_funcs
= {
425 .early_init
= cz_ih_early_init
,
427 .sw_init
= cz_ih_sw_init
,
428 .sw_fini
= cz_ih_sw_fini
,
429 .hw_init
= cz_ih_hw_init
,
430 .hw_fini
= cz_ih_hw_fini
,
431 .suspend
= cz_ih_suspend
,
432 .resume
= cz_ih_resume
,
433 .is_idle
= cz_ih_is_idle
,
434 .wait_for_idle
= cz_ih_wait_for_idle
,
435 .soft_reset
= cz_ih_soft_reset
,
436 .print_status
= cz_ih_print_status
,
437 .set_clockgating_state
= cz_ih_set_clockgating_state
,
438 .set_powergating_state
= cz_ih_set_powergating_state
,
441 static const struct amdgpu_ih_funcs cz_ih_funcs
= {
442 .get_wptr
= cz_ih_get_wptr
,
443 .decode_iv
= cz_ih_decode_iv
,
444 .set_rptr
= cz_ih_set_rptr
447 static void cz_ih_set_interrupt_funcs(struct amdgpu_device
*adev
)
449 if (adev
->irq
.ih_funcs
== NULL
)
450 adev
->irq
.ih_funcs
= &cz_ih_funcs
;