drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34
  35 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  36 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  37 static int uvd_v6_0_start(struct amdgpu_device *adev);
  38 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  39
  40 /**
  41  * uvd_v6_0_ring_get_rptr - get read pointer
  42  *
  43  * @ring: amdgpu_ring pointer
  44  *
  45  * Returns the current hardware read pointer
  46  */
  47 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  48 {
  49         struct amdgpu_device *adev = ring->adev;
  50
  51         return RREG32(mmUVD_RBC_RB_RPTR);
  52 }
  53
  54 /**
  55  * uvd_v6_0_ring_get_wptr - get write pointer
  56  *
  57  * @ring: amdgpu_ring pointer
  58  *
  59  * Returns the current hardware write pointer
  60  */
  61 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
  62 {
  63         struct amdgpu_device *adev = ring->adev;
  64
  65         return RREG32(mmUVD_RBC_RB_WPTR);
  66 }
  67
  68 /**
  69  * uvd_v6_0_ring_set_wptr - set write pointer
  70  *
  71  * @ring: amdgpu_ring pointer
  72  *
  73  * Commits the write pointer to the hardware
  74  */
  75 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
  76 {
  77         struct amdgpu_device *adev = ring->adev;
  78
  79         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  80 }
  81
  82 static int uvd_v6_0_early_init(void *handle)
  83 {
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         uvd_v6_0_set_ring_funcs(adev);
  87         uvd_v6_0_set_irq_funcs(adev);
  88
  89         return 0;
  90 }
  91
  92 static int uvd_v6_0_sw_init(void *handle)
  93 {
  94         struct amdgpu_ring *ring;
  95         int r;
  96         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  97
  98         /* UVD TRAP */
  99         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 100         if (r)
 101                 return r;
 102
 103         r = amdgpu_uvd_sw_init(adev);
 104         if (r)
 105                 return r;
 106
 107         r = amdgpu_uvd_resume(adev);
 108         if (r)
 109                 return r;
 110
 111         ring = &adev->uvd.ring;
 112         sprintf(ring->name, "uvd");
 113         r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
 114                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 115
 116         return r;
 117 }
 118
 119 static int uvd_v6_0_sw_fini(void *handle)
 120 {
 121         int r;
 122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 123
 124         r = amdgpu_uvd_suspend(adev);
 125         if (r)
 126                 return r;
 127
 128         r = amdgpu_uvd_sw_fini(adev);
 129         if (r)
 130                 return r;
 131
 132         return r;
 133 }
 134
 135 /**
 136  * uvd_v6_0_hw_init - start and test UVD block
 137  *
 138  * @adev: amdgpu_device pointer
 139  *
 140  * Initialize the hardware, boot up the VCPU and do some testing
 141  */
 142 static int uvd_v6_0_hw_init(void *handle)
 143 {
 144         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 145         struct amdgpu_ring *ring = &adev->uvd.ring;
 146         uint32_t tmp;
 147         int r;
 148
 149         r = uvd_v6_0_start(adev);
 150         if (r)
 151                 goto done;
 152
 153         ring->ready = true;
 154         r = amdgpu_ring_test_ring(ring);
 155         if (r) {
 156                 ring->ready = false;
 157                 goto done;
 158         }
 159
 160         r = amdgpu_ring_lock(ring, 10);
 161         if (r) {
 162                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 163                 goto done;
 164         }
 165
 166         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 167         amdgpu_ring_write(ring, tmp);
 168         amdgpu_ring_write(ring, 0xFFFFF);
 169
 170         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 171         amdgpu_ring_write(ring, tmp);
 172         amdgpu_ring_write(ring, 0xFFFFF);
 173
 174         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 175         amdgpu_ring_write(ring, tmp);
 176         amdgpu_ring_write(ring, 0xFFFFF);
 177
 178         /* Clear timeout status bits */
 179         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 180         amdgpu_ring_write(ring, 0x8);
 181
 182         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 183         amdgpu_ring_write(ring, 3);
 184
 185         amdgpu_ring_unlock_commit(ring);
 186
 187 done:
 188         if (!r)
 189                 DRM_INFO("UVD initialized successfully.\n");
 190
 191         return r;
 192 }
 193
 194 /**
 195  * uvd_v6_0_hw_fini - stop the hardware block
 196  *
 197  * @adev: amdgpu_device pointer
 198  *
 199  * Stop the UVD block, mark ring as not ready any more
 200  */
 201 static int uvd_v6_0_hw_fini(void *handle)
 202 {
 203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 204         struct amdgpu_ring *ring = &adev->uvd.ring;
 205
 206         uvd_v6_0_stop(adev);
 207         ring->ready = false;
 208
 209         return 0;
 210 }
 211
 212 static int uvd_v6_0_suspend(void *handle)
 213 {
 214         int r;
 215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 216
 217         r = uvd_v6_0_hw_fini(adev);
 218         if (r)
 219                 return r;
 220
 221         r = amdgpu_uvd_suspend(adev);
 222         if (r)
 223                 return r;
 224
 225         return r;
 226 }
 227
 228 static int uvd_v6_0_resume(void *handle)
 229 {
 230         int r;
 231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 232
 233         r = amdgpu_uvd_resume(adev);
 234         if (r)
 235                 return r;
 236
 237         r = uvd_v6_0_hw_init(adev);
 238         if (r)
 239                 return r;
 240
 241         return r;
 242 }
 243
 244 /**
 245  * uvd_v6_0_mc_resume - memory controller programming
 246  *
 247  * @adev: amdgpu_device pointer
 248  *
 249  * Let the UVD memory controller know it's offsets
 250  */
 251 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 252 {
 253         uint64_t offset;
 254         uint32_t size;
 255
 256         /* programm memory controller bits 0-27 */
 257         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 258                         lower_32_bits(adev->uvd.gpu_addr));
 259         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 260                         upper_32_bits(adev->uvd.gpu_addr));
 261
 262         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 263         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 264         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 265         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 266
 267         offset += size;
 268         size = AMDGPU_UVD_STACK_SIZE;
 269         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 270         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 271
 272         offset += size;
 273         size = AMDGPU_UVD_HEAP_SIZE;
 274         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 275         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 276 }
 277
 278 /**
 279  * uvd_v6_0_start - start UVD block
 280  *
 281  * @adev: amdgpu_device pointer
 282  *
 283  * Setup and start the UVD block
 284  */
 285 static int uvd_v6_0_start(struct amdgpu_device *adev)
 286 {
 287         struct amdgpu_ring *ring = &adev->uvd.ring;
 288         uint32_t rb_bufsz, tmp;
 289         uint32_t lmi_swap_cntl;
 290         uint32_t mp_swap_cntl;
 291         int i, j, r;
 292
 293         /*disable DPG */
 294         WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
 295
 296         /* disable byte swapping */
 297         lmi_swap_cntl = 0;
 298         mp_swap_cntl = 0;
 299
 300         uvd_v6_0_mc_resume(adev);
 301
 302         /* disable clock gating */
 303         WREG32(mmUVD_CGC_GATE, 0);
 304
 305         /* disable interupt */
 306         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 307
 308         /* stall UMC and register bus before resetting VCPU */
 309         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 310         mdelay(1);
 311
 312         /* put LMI, VCPU, RBC etc... into reset */
 313         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 314                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 315                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 316                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 317                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 318         mdelay(5);
 319
 320         /* take UVD block out of reset */
 321         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 322         mdelay(5);
 323
 324         /* initialize UVD memory controller */
 325         WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 326                              (1 << 21) | (1 << 9) | (1 << 20));
 327
 328 #ifdef __BIG_ENDIAN
 329         /* swap (8 in 32) RB and IB */
 330         lmi_swap_cntl = 0xa;
 331         mp_swap_cntl = 0;
 332 #endif
 333         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 334         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 335
 336         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 337         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 338         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 339         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 340         WREG32(mmUVD_MPC_SET_ALU, 0);
 341         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 342
 343         /* take all subblocks out of reset, except VCPU */
 344         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 345         mdelay(5);
 346
 347         /* enable VCPU clock */
 348         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 349
 350         /* enable UMC */
 351         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 352
 353         /* boot up the VCPU */
 354         WREG32(mmUVD_SOFT_RESET, 0);
 355         mdelay(10);
 356
 357         for (i = 0; i < 10; ++i) {
 358                 uint32_t status;
 359
 360                 for (j = 0; j < 100; ++j) {
 361                         status = RREG32(mmUVD_STATUS);
 362                         if (status & 2)
 363                                 break;
 364                         mdelay(10);
 365                 }
 366                 r = 0;
 367                 if (status & 2)
 368                         break;
 369
 370                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 371                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 372                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 373                 mdelay(10);
 374                 WREG32_P(mmUVD_SOFT_RESET, 0,
 375                          ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 376                 mdelay(10);
 377                 r = -1;
 378         }
 379
 380         if (r) {
 381                 DRM_ERROR("UVD not responding, giving up!!!\n");
 382                 return r;
 383         }
 384         /* enable master interrupt */
 385         WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
 386
 387         /* clear the bit 4 of UVD_STATUS */
 388         WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
 389
 390         rb_bufsz = order_base_2(ring->ring_size);
 391         tmp = 0;
 392         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 393         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 394         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 395         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 396         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 397         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 398         /* force RBC into idle state */
 399         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 400
 401         /* set the write pointer delay */
 402         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 403
 404         /* set the wb address */
 405         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 406
 407         /* programm the RB_BASE for ring buffer */
 408         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 409                         lower_32_bits(ring->gpu_addr));
 410         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 411                         upper_32_bits(ring->gpu_addr));
 412
 413         /* Initialize the ring buffer's read and write pointers */
 414         WREG32(mmUVD_RBC_RB_RPTR, 0);
 415
 416         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 417         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 418
 419         WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 420
 421         return 0;
 422 }
 423
 424 /**
 425  * uvd_v6_0_stop - stop UVD block
 426  *
 427  * @adev: amdgpu_device pointer
 428  *
 429  * stop the UVD block
 430  */
 431 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 432 {
 433         /* force RBC into idle state */
 434         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 435
 436         /* Stall UMC and register bus before resetting VCPU */
 437         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 438         mdelay(1);
 439
 440         /* put VCPU into reset */
 441         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 442         mdelay(5);
 443
 444         /* disable VCPU clock */
 445         WREG32(mmUVD_VCPU_CNTL, 0x0);
 446
 447         /* Unstall UMC and register bus */
 448         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 449 }
 450
 451 /**
 452  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 453  *
 454  * @ring: amdgpu_ring pointer
 455  * @fence: fence to emit
 456  *
 457  * Write a fence and a trap command to the ring.
 458  */
 459 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 460                                      unsigned flags)
 461 {
 462         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 463
 464         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 465         amdgpu_ring_write(ring, seq);
 466         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 467         amdgpu_ring_write(ring, addr & 0xffffffff);
 468         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 469         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 470         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 471         amdgpu_ring_write(ring, 0);
 472
 473         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 474         amdgpu_ring_write(ring, 0);
 475         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 476         amdgpu_ring_write(ring, 0);
 477         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 478         amdgpu_ring_write(ring, 2);
 479 }
 480
 481 /**
 482  * uvd_v6_0_ring_emit_semaphore - emit semaphore command
 483  *
 484  * @ring: amdgpu_ring pointer
 485  * @semaphore: semaphore to emit commands for
 486  * @emit_wait: true if we should emit a wait command
 487  *
 488  * Emit a semaphore command (either wait or signal) to the UVD ring.
 489  */
 490 static bool uvd_v6_0_ring_emit_semaphore(struct amdgpu_ring *ring,
 491                                          struct amdgpu_semaphore *semaphore,
 492                                          bool emit_wait)
 493 {
 494         uint64_t addr = semaphore->gpu_addr;
 495
 496         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
 497         amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
 498
 499         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
 500         amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
 501
 502         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
 503         amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
 504
 505         return true;
 506 }
 507
 508 /**
 509  * uvd_v6_0_ring_test_ring - register write test
 510  *
 511  * @ring: amdgpu_ring pointer
 512  *
 513  * Test if we can successfully write to the context register
 514  */
 515 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 516 {
 517         struct amdgpu_device *adev = ring->adev;
 518         uint32_t tmp = 0;
 519         unsigned i;
 520         int r;
 521
 522         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 523         r = amdgpu_ring_lock(ring, 3);
 524         if (r) {
 525                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 526                           ring->idx, r);
 527                 return r;
 528         }
 529         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 530         amdgpu_ring_write(ring, 0xDEADBEEF);
 531         amdgpu_ring_unlock_commit(ring);
 532         for (i = 0; i < adev->usec_timeout; i++) {
 533                 tmp = RREG32(mmUVD_CONTEXT_ID);
 534                 if (tmp == 0xDEADBEEF)
 535                         break;
 536                 DRM_UDELAY(1);
 537         }
 538
 539         if (i < adev->usec_timeout) {
 540                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 541                          ring->idx, i);
 542         } else {
 543                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 544                           ring->idx, tmp);
 545                 r = -EINVAL;
 546         }
 547         return r;
 548 }
 549
 550 /**
 551  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 552  *
 553  * @ring: amdgpu_ring pointer
 554  * @ib: indirect buffer to execute
 555  *
 556  * Write ring commands to execute the indirect buffer
 557  */
 558 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 559                                   struct amdgpu_ib *ib)
 560 {
 561         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 562         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 563         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 564         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 565         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 566         amdgpu_ring_write(ring, ib->length_dw);
 567 }
 568
 569 /**
 570  * uvd_v6_0_ring_test_ib - test ib execution
 571  *
 572  * @ring: amdgpu_ring pointer
 573  *
 574  * Test if we can successfully execute an IB
 575  */
 576 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring)
 577 {
 578         struct amdgpu_fence *fence = NULL;
 579         int r;
 580
 581         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
 582         if (r) {
 583                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 584                 goto error;
 585         }
 586
 587         r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
 588         if (r) {
 589                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 590                 goto error;
 591         }
 592
 593         r = amdgpu_fence_wait(fence, false);
 594         if (r) {
 595                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 596                 goto error;
 597         }
 598         DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
 599 error:
 600         amdgpu_fence_unref(&fence);
 601         return r;
 602 }
 603
 604 static bool uvd_v6_0_is_idle(void *handle)
 605 {
 606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 607
 608         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 609 }
 610
 611 static int uvd_v6_0_wait_for_idle(void *handle)
 612 {
 613         unsigned i;
 614         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 615
 616         for (i = 0; i < adev->usec_timeout; i++) {
 617                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 618                         return 0;
 619         }
 620         return -ETIMEDOUT;
 621 }
 622
 623 static int uvd_v6_0_soft_reset(void *handle)
 624 {
 625         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 626
 627         uvd_v6_0_stop(adev);
 628
 629         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 630                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 631         mdelay(5);
 632
 633         return uvd_v6_0_start(adev);
 634 }
 635
 636 static void uvd_v6_0_print_status(void *handle)
 637 {
 638         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 639         dev_info(adev->dev, "UVD 6.0 registers\n");
 640         dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
 641                  RREG32(mmUVD_SEMA_ADDR_LOW));
 642         dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
 643                  RREG32(mmUVD_SEMA_ADDR_HIGH));
 644         dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
 645                  RREG32(mmUVD_SEMA_CMD));
 646         dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
 647                  RREG32(mmUVD_GPCOM_VCPU_CMD));
 648         dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
 649                  RREG32(mmUVD_GPCOM_VCPU_DATA0));
 650         dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
 651                  RREG32(mmUVD_GPCOM_VCPU_DATA1));
 652         dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
 653                  RREG32(mmUVD_ENGINE_CNTL));
 654         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
 655                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
 656         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
 657                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
 658         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
 659                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
 660         dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
 661                  RREG32(mmUVD_SEMA_CNTL));
 662         dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
 663                  RREG32(mmUVD_LMI_EXT40_ADDR));
 664         dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
 665                  RREG32(mmUVD_CTX_INDEX));
 666         dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
 667                  RREG32(mmUVD_CTX_DATA));
 668         dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
 669                  RREG32(mmUVD_CGC_GATE));
 670         dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
 671                  RREG32(mmUVD_CGC_CTRL));
 672         dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
 673                  RREG32(mmUVD_LMI_CTRL2));
 674         dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
 675                  RREG32(mmUVD_MASTINT_EN));
 676         dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
 677                  RREG32(mmUVD_LMI_ADDR_EXT));
 678         dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
 679                  RREG32(mmUVD_LMI_CTRL));
 680         dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
 681                  RREG32(mmUVD_LMI_SWAP_CNTL));
 682         dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
 683                  RREG32(mmUVD_MP_SWAP_CNTL));
 684         dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
 685                  RREG32(mmUVD_MPC_SET_MUXA0));
 686         dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
 687                  RREG32(mmUVD_MPC_SET_MUXA1));
 688         dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
 689                  RREG32(mmUVD_MPC_SET_MUXB0));
 690         dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
 691                  RREG32(mmUVD_MPC_SET_MUXB1));
 692         dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
 693                  RREG32(mmUVD_MPC_SET_MUX));
 694         dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
 695                  RREG32(mmUVD_MPC_SET_ALU));
 696         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
 697                  RREG32(mmUVD_VCPU_CACHE_OFFSET0));
 698         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
 699                  RREG32(mmUVD_VCPU_CACHE_SIZE0));
 700         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
 701                  RREG32(mmUVD_VCPU_CACHE_OFFSET1));
 702         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
 703                  RREG32(mmUVD_VCPU_CACHE_SIZE1));
 704         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
 705                  RREG32(mmUVD_VCPU_CACHE_OFFSET2));
 706         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
 707                  RREG32(mmUVD_VCPU_CACHE_SIZE2));
 708         dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
 709                  RREG32(mmUVD_VCPU_CNTL));
 710         dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
 711                  RREG32(mmUVD_SOFT_RESET));
 712         dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
 713                  RREG32(mmUVD_RBC_IB_SIZE));
 714         dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
 715                  RREG32(mmUVD_RBC_RB_RPTR));
 716         dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
 717                  RREG32(mmUVD_RBC_RB_WPTR));
 718         dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
 719                  RREG32(mmUVD_RBC_RB_WPTR_CNTL));
 720         dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
 721                  RREG32(mmUVD_RBC_RB_CNTL));
 722         dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
 723                  RREG32(mmUVD_STATUS));
 724         dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
 725                  RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
 726         dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
 727                  RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
 728         dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
 729                  RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
 730         dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
 731                  RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
 732         dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
 733                  RREG32(mmUVD_CONTEXT_ID));
 734 }
 735
 736 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 737                                         struct amdgpu_irq_src *source,
 738                                         unsigned type,
 739                                         enum amdgpu_interrupt_state state)
 740 {
 741         // TODO
 742         return 0;
 743 }
 744
 745 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 746                                       struct amdgpu_irq_src *source,
 747                                       struct amdgpu_iv_entry *entry)
 748 {
 749         DRM_DEBUG("IH: UVD TRAP\n");
 750         amdgpu_fence_process(&adev->uvd.ring);
 751         return 0;
 752 }
 753
 754 static int uvd_v6_0_set_clockgating_state(void *handle,
 755                                           enum amd_clockgating_state state)
 756 {
 757         return 0;
 758 }
 759
 760 static int uvd_v6_0_set_powergating_state(void *handle,
 761                                           enum amd_powergating_state state)
 762 {
 763         /* This doesn't actually powergate the UVD block.
 764          * That's done in the dpm code via the SMC.  This
 765          * just re-inits the block as necessary.  The actual
 766          * gating still happens in the dpm code.  We should
 767          * revisit this when there is a cleaner line between
 768          * the smc and the hw blocks
 769          */
 770         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 771
 772         if (state == AMD_PG_STATE_GATE) {
 773                 uvd_v6_0_stop(adev);
 774                 return 0;
 775         } else {
 776                 return uvd_v6_0_start(adev);
 777         }
 778 }
 779
 780 const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 781         .early_init = uvd_v6_0_early_init,
 782         .late_init = NULL,
 783         .sw_init = uvd_v6_0_sw_init,
 784         .sw_fini = uvd_v6_0_sw_fini,
 785         .hw_init = uvd_v6_0_hw_init,
 786         .hw_fini = uvd_v6_0_hw_fini,
 787         .suspend = uvd_v6_0_suspend,
 788         .resume = uvd_v6_0_resume,
 789         .is_idle = uvd_v6_0_is_idle,
 790         .wait_for_idle = uvd_v6_0_wait_for_idle,
 791         .soft_reset = uvd_v6_0_soft_reset,
 792         .print_status = uvd_v6_0_print_status,
 793         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
 794         .set_powergating_state = uvd_v6_0_set_powergating_state,
 795 };
 796
 797 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
 798         .get_rptr = uvd_v6_0_ring_get_rptr,
 799         .get_wptr = uvd_v6_0_ring_get_wptr,
 800         .set_wptr = uvd_v6_0_ring_set_wptr,
 801         .parse_cs = amdgpu_uvd_ring_parse_cs,
 802         .emit_ib = uvd_v6_0_ring_emit_ib,
 803         .emit_fence = uvd_v6_0_ring_emit_fence,
 804         .emit_semaphore = uvd_v6_0_ring_emit_semaphore,
 805         .test_ring = uvd_v6_0_ring_test_ring,
 806         .test_ib = uvd_v6_0_ring_test_ib,
 807         .is_lockup = amdgpu_ring_test_lockup,
 808 };
 809
 810 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
 811 {
 812         adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs;
 813 }
 814
 815 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
 816         .set = uvd_v6_0_set_interrupt_state,
 817         .process = uvd_v6_0_process_interrupt,
 818 };
 819
 820 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
 821 {
 822         adev->uvd.irq.num_types = 1;
 823         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
 824 }