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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / armada / armada_crtc.c
blob01ffe9bffe38a9e93d49a811a4803f49866a0861
1 /*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
21
22 struct armada_frame_work {
23 struct drm_pending_vblank_event *event;
24 struct armada_regs regs[4];
25 struct drm_framebuffer *old_fb;
26 };
27
28 enum csc_mode {
29 CSC_AUTO = 0,
30 CSC_YUV_CCIR601 = 1,
31 CSC_YUV_CCIR709 = 2,
32 CSC_RGB_COMPUTER = 1,
33 CSC_RGB_STUDIO = 2,
34 };
35
36 /*
37 * A note about interlacing. Let's consider HDMI 1920x1080i.
38 * The timing parameters we have from X are:
39 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
40 * 1920 2448 2492 2640 1080 1084 1094 1125
41 * Which get translated to:
42 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
43 * 1920 2448 2492 2640 540 542 547 562
44 *
45 * This is how it is defined by CEA-861-D - line and pixel numbers are
46 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
47 * line: 2640. The odd frame, the first active line is at line 21, and
48 * the even frame, the first active line is 584.
49 *
50 * LN: 560 561 562 563 567 568 569
51 * DE: ~~~|____________________________//__________________________
52 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
53 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
54 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
55 *
56 * LN: 1123 1124 1125 1 5 6 7
57 * DE: ~~~|____________________________//__________________________
58 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
59 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
60 * 23 blanking lines
61 *
62 * The Armada LCD Controller line and pixel numbers are, like X timings,
63 * referenced to the top left of the active frame.
64 *
65 * So, translating these to our LCD controller:
66 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
67 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
68 * Note: Vsync front porch remains constant!
69 *
70 * if (odd_frame) {
71 * vtotal = mode->crtc_vtotal + 1;
72 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
73 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
74 * } else {
75 * vtotal = mode->crtc_vtotal;
76 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
77 * vhorizpos = mode->crtc_hsync_start;
78 * }
79 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
80 *
81 * So, we need to reprogram these registers on each vsync event:
82 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
83 *
84 * Note: we do not use the frame done interrupts because these appear
85 * to happen too early, and lead to jitter on the display (presumably
86 * they occur at the end of the last active line, before the vsync back
87 * porch, which we're reprogramming.)
88 */
89
90 void
91 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
92 {
93 while (regs->offset != ~0) {
94 void __iomem *reg = dcrtc->base + regs->offset;
95 uint32_t val;
96
97 val = regs->mask;
98 if (val != 0)
99 val &= readl_relaxed(reg);
100 writel_relaxed(val | regs->val, reg);
101 ++regs;
102 }
103 }
104
105 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
106
107 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
108 {
109 uint32_t dumb_ctrl;
110
111 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
112
113 if (!dpms_blanked(dcrtc->dpms))
114 dumb_ctrl |= CFG_DUMB_ENA;
115
116 /*
117 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
118 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
119 * force LCD_D[23:0] to output blank color, overriding the GPIO or
120 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
121 */
122 if (dpms_blanked(dcrtc->dpms) &&
123 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
124 dumb_ctrl &= ~DUMB_MASK;
125 dumb_ctrl |= DUMB_BLANK;
126 }
127
128 /*
129 * The documentation doesn't indicate what the normal state of
130 * the sync signals are. Sebastian Hesselbart kindly probed
131 * these signals on his board to determine their state.
132 *
133 * The non-inverted state of the sync signals is active high.
134 * Setting these bits makes the appropriate signal active low.
135 */
136 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
137 dumb_ctrl |= CFG_INV_CSYNC;
138 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
139 dumb_ctrl |= CFG_INV_HSYNC;
140 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
141 dumb_ctrl |= CFG_INV_VSYNC;
142
143 if (dcrtc->dumb_ctrl != dumb_ctrl) {
144 dcrtc->dumb_ctrl = dumb_ctrl;
145 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
146 }
147 }
148
149 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
150 int x, int y, struct armada_regs *regs, bool interlaced)
151 {
152 struct armada_gem_object *obj = drm_fb_obj(fb);
153 unsigned pitch = fb->pitches[0];
154 unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
155 uint32_t addr_odd, addr_even;
156 unsigned i = 0;
157
158 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
159 pitch, x, y, fb->bits_per_pixel);
160
161 addr_odd = addr_even = obj->dev_addr + offset;
162
163 if (interlaced) {
164 addr_even += pitch;
165 pitch *= 2;
166 }
167
168 /* write offset, base, and pitch */
169 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
170 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
171 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
172
173 return i;
174 }
175
176 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
177 struct armada_frame_work *work)
178 {
179 struct drm_device *dev = dcrtc->crtc.dev;
180 unsigned long flags;
181 int ret;
182
183 ret = drm_vblank_get(dev, dcrtc->num);
184 if (ret) {
185 DRM_ERROR("failed to acquire vblank counter\n");
186 return ret;
187 }
188
189 spin_lock_irqsave(&dev->event_lock, flags);
190 if (!dcrtc->frame_work)
191 dcrtc->frame_work = work;
192 else
193 ret = -EBUSY;
194 spin_unlock_irqrestore(&dev->event_lock, flags);
195
196 if (ret)
197 drm_vblank_put(dev, dcrtc->num);
198
199 return ret;
200 }
201
202 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
203 {
204 struct drm_device *dev = dcrtc->crtc.dev;
205 struct armada_frame_work *work = dcrtc->frame_work;
206
207 dcrtc->frame_work = NULL;
208
209 armada_drm_crtc_update_regs(dcrtc, work->regs);
210
211 if (work->event)
212 drm_send_vblank_event(dev, dcrtc->num, work->event);
213
214 drm_vblank_put(dev, dcrtc->num);
215
216 /* Finally, queue the process-half of the cleanup. */
217 __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
218 kfree(work);
219 }
220
221 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
222 struct drm_framebuffer *fb, bool force)
223 {
224 struct armada_frame_work *work;
225
226 if (!fb)
227 return;
228
229 if (force) {
230 /* Display is disabled, so just drop the old fb */
231 drm_framebuffer_unreference(fb);
232 return;
233 }
234
235 work = kmalloc(sizeof(*work), GFP_KERNEL);
236 if (work) {
237 int i = 0;
238 work->event = NULL;
239 work->old_fb = fb;
240 armada_reg_queue_end(work->regs, i);
241
242 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
243 return;
244
245 kfree(work);
246 }
247
248 /*
249 * Oops - just drop the reference immediately and hope for
250 * the best. The worst that will happen is the buffer gets
251 * reused before it has finished being displayed.
252 */
253 drm_framebuffer_unreference(fb);
254 }
255
256 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
257 {
258 struct drm_device *dev = dcrtc->crtc.dev;
259
260 /*
261 * Tell the DRM core that vblank IRQs aren't going to happen for
262 * a while. This cleans up any pending vblank events for us.
263 */
264 drm_crtc_vblank_off(&dcrtc->crtc);
265
266 /* Handle any pending flip event. */
267 spin_lock_irq(&dev->event_lock);
268 if (dcrtc->frame_work)
269 armada_drm_crtc_complete_frame_work(dcrtc);
270 spin_unlock_irq(&dev->event_lock);
271 }
272
273 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
274 int idx)
275 {
276 }
277
278 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
279 int idx)
280 {
281 }
282
283 /* The mode_config.mutex will be held for this call */
284 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
285 {
286 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
287
288 if (dcrtc->dpms != dpms) {
289 dcrtc->dpms = dpms;
290 armada_drm_crtc_update(dcrtc);
291 if (dpms_blanked(dpms))
292 armada_drm_vblank_off(dcrtc);
293 else
294 drm_crtc_vblank_on(&dcrtc->crtc);
295 }
296 }
297
298 /*
299 * Prepare for a mode set. Turn off overlay to ensure that we don't end
300 * up with the overlay size being bigger than the active screen size.
301 * We rely upon X refreshing this state after the mode set has completed.
302 *
303 * The mode_config.mutex will be held for this call
304 */
305 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
306 {
307 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
308 struct drm_plane *plane;
309
310 /*
311 * If we have an overlay plane associated with this CRTC, disable
312 * it before the modeset to avoid its coordinates being outside
313 * the new mode parameters. DRM doesn't provide help with this.
314 */
315 plane = dcrtc->plane;
316 if (plane) {
317 struct drm_framebuffer *fb = plane->fb;
318
319 plane->funcs->disable_plane(plane);
320 plane->fb = NULL;
321 plane->crtc = NULL;
322 drm_framebuffer_unreference(fb);
323 }
324 }
325
326 /* The mode_config.mutex will be held for this call */
327 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
328 {
329 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
330
331 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
332 dcrtc->dpms = DRM_MODE_DPMS_ON;
333 armada_drm_crtc_update(dcrtc);
334 }
335 }
336
337 /* The mode_config.mutex will be held for this call */
338 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
339 const struct drm_display_mode *mode, struct drm_display_mode *adj)
340 {
341 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
342 int ret;
343
344 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
345 if (!dcrtc->variant->has_spu_adv_reg &&
346 adj->flags & DRM_MODE_FLAG_INTERLACE)
347 return false;
348
349 /* Check whether the display mode is possible */
350 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
351 if (ret)
352 return false;
353
354 return true;
355 }
356
357 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
358 {
359 struct armada_vbl_event *e, *n;
360 void __iomem *base = dcrtc->base;
361
362 if (stat & DMA_FF_UNDERFLOW)
363 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
364 if (stat & GRA_FF_UNDERFLOW)
365 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
366
367 if (stat & VSYNC_IRQ)
368 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
369
370 spin_lock(&dcrtc->irq_lock);
371
372 list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
373 list_del_init(&e->node);
374 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
375 e->fn(dcrtc, e->data);
376 }
377
378 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
379 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
380 uint32_t val;
381
382 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
383 writel_relaxed(dcrtc->v[i].spu_v_h_total,
384 base + LCD_SPUT_V_H_TOTAL);
385
386 val = readl_relaxed(base + LCD_SPU_ADV_REG);
387 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
388 val |= dcrtc->v[i].spu_adv_reg;
389 writel_relaxed(val, base + LCD_SPU_ADV_REG);
390 }
391
392 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
393 writel_relaxed(dcrtc->cursor_hw_pos,
394 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
395 writel_relaxed(dcrtc->cursor_hw_sz,
396 base + LCD_SPU_HWC_HPXL_VLN);
397 armada_updatel(CFG_HWC_ENA,
398 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
399 base + LCD_SPU_DMA_CTRL0);
400 dcrtc->cursor_update = false;
401 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
402 }
403
404 spin_unlock(&dcrtc->irq_lock);
405
406 if (stat & GRA_FRAME_IRQ) {
407 struct drm_device *dev = dcrtc->crtc.dev;
408
409 spin_lock(&dev->event_lock);
410 if (dcrtc->frame_work)
411 armada_drm_crtc_complete_frame_work(dcrtc);
412 spin_unlock(&dev->event_lock);
413
414 wake_up(&dcrtc->frame_wait);
415 }
416 }
417
418 static irqreturn_t armada_drm_irq(int irq, void *arg)
419 {
420 struct armada_crtc *dcrtc = arg;
421 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
422
423 /*
424 * This is rediculous - rather than writing bits to clear, we
425 * have to set the actual status register value. This is racy.
426 */
427 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
428
429 /* Mask out those interrupts we haven't enabled */
430 v = stat & dcrtc->irq_ena;
431
432 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
433 armada_drm_crtc_irq(dcrtc, stat);
434 return IRQ_HANDLED;
435 }
436 return IRQ_NONE;
437 }
438
439 /* These are locked by dev->vbl_lock */
440 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
441 {
442 if (dcrtc->irq_ena & mask) {
443 dcrtc->irq_ena &= ~mask;
444 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
445 }
446 }
447
448 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
449 {
450 if ((dcrtc->irq_ena & mask) != mask) {
451 dcrtc->irq_ena |= mask;
452 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
453 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
454 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
455 }
456 }
457
458 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
459 {
460 struct drm_display_mode *adj = &dcrtc->crtc.mode;
461 uint32_t val = 0;
462
463 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
464 val |= CFG_CSC_YUV_CCIR709;
465 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
466 val |= CFG_CSC_RGB_STUDIO;
467
468 /*
469 * In auto mode, set the colorimetry, based upon the HDMI spec.
470 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
471 * ITU601. It may be more appropriate to set this depending on
472 * the source - but what if the graphic frame is YUV and the
473 * video frame is RGB?
474 */
475 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
476 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
477 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
478 if (dcrtc->csc_yuv_mode == CSC_AUTO)
479 val |= CFG_CSC_YUV_CCIR709;
480 }
481
482 /*
483 * We assume we're connected to a TV-like device, so the YUV->RGB
484 * conversion should produce a limited range. We should set this
485 * depending on the connectors attached to this CRTC, and what
486 * kind of device they report being connected.
487 */
488 if (dcrtc->csc_rgb_mode == CSC_AUTO)
489 val |= CFG_CSC_RGB_STUDIO;
490
491 return val;
492 }
493
494 /* The mode_config.mutex will be held for this call */
495 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
496 struct drm_display_mode *mode, struct drm_display_mode *adj,
497 int x, int y, struct drm_framebuffer *old_fb)
498 {
499 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
500 struct armada_regs regs[17];
501 uint32_t lm, rm, tm, bm, val, sclk;
502 unsigned long flags;
503 unsigned i;
504 bool interlaced;
505
506 drm_framebuffer_reference(crtc->primary->fb);
507
508 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
509
510 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
511 x, y, regs, interlaced);
512
513 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
514 lm = adj->crtc_htotal - adj->crtc_hsync_end;
515 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
516 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
517
518 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
519 adj->crtc_hdisplay,
520 adj->crtc_hsync_start,
521 adj->crtc_hsync_end,
522 adj->crtc_htotal, lm, rm);
523 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
524 adj->crtc_vdisplay,
525 adj->crtc_vsync_start,
526 adj->crtc_vsync_end,
527 adj->crtc_vtotal, tm, bm);
528
529 /* Wait for pending flips to complete */
530 wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
531
532 drm_crtc_vblank_off(crtc);
533
534 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
535 if (val != dcrtc->dumb_ctrl) {
536 dcrtc->dumb_ctrl = val;
537 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
538 }
539
540 /* Now compute the divider for real */
541 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
542
543 /* Ensure graphic fifo is enabled */
544 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
545 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
546
547 if (interlaced ^ dcrtc->interlaced) {
548 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
549 drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
550 else
551 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
552 dcrtc->interlaced = interlaced;
553 }
554
555 spin_lock_irqsave(&dcrtc->irq_lock, flags);
556
557 /* Even interlaced/progressive frame */
558 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
559 adj->crtc_htotal;
560 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
561 val = adj->crtc_hsync_start;
562 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
563 dcrtc->variant->spu_adv_reg;
564
565 if (interlaced) {
566 /* Odd interlaced frame */
567 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
568 (1 << 16);
569 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
570 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
571 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
572 dcrtc->variant->spu_adv_reg;
573 } else {
574 dcrtc->v[0] = dcrtc->v[1];
575 }
576
577 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
578
579 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
580 armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
581 armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
582 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
583 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
584 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
585 LCD_SPUT_V_H_TOTAL);
586
587 if (dcrtc->variant->has_spu_adv_reg) {
588 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
589 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
590 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
591 }
592
593 val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
594 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
595 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
596
597 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
598 val |= CFG_PALETTE_ENA;
599
600 if (interlaced)
601 val |= CFG_GRA_FTOGGLE;
602
603 armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
604 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
605 CFG_SWAPYU | CFG_YUV2RGB) |
606 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
607 LCD_SPU_DMA_CTRL0);
608
609 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
610 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
611
612 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
613 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
614 armada_reg_queue_end(regs, i);
615
616 armada_drm_crtc_update_regs(dcrtc, regs);
617 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
618
619 armada_drm_crtc_update(dcrtc);
620
621 drm_crtc_vblank_on(crtc);
622 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
623
624 return 0;
625 }
626
627 /* The mode_config.mutex will be held for this call */
628 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
629 struct drm_framebuffer *old_fb)
630 {
631 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
632 struct armada_regs regs[4];
633 unsigned i;
634
635 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
636 dcrtc->interlaced);
637 armada_reg_queue_end(regs, i);
638
639 /* Wait for pending flips to complete */
640 wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
641
642 /* Take a reference to the new fb as we're using it */
643 drm_framebuffer_reference(crtc->primary->fb);
644
645 /* Update the base in the CRTC */
646 armada_drm_crtc_update_regs(dcrtc, regs);
647
648 /* Drop our previously held reference */
649 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
650
651 return 0;
652 }
653
654 /* The mode_config.mutex will be held for this call */
655 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
656 {
657 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
658
659 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
660 armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
661
662 /* Power down most RAMs and FIFOs */
663 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
664 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
665 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
666 }
667
668 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
669 .dpms = armada_drm_crtc_dpms,
670 .prepare = armada_drm_crtc_prepare,
671 .commit = armada_drm_crtc_commit,
672 .mode_fixup = armada_drm_crtc_mode_fixup,
673 .mode_set = armada_drm_crtc_mode_set,
674 .mode_set_base = armada_drm_crtc_mode_set_base,
675 .disable = armada_drm_crtc_disable,
676 };
677
678 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
679 unsigned stride, unsigned width, unsigned height)
680 {
681 uint32_t addr;
682 unsigned y;
683
684 addr = SRAM_HWC32_RAM1;
685 for (y = 0; y < height; y++) {
686 uint32_t *p = &pix[y * stride];
687 unsigned x;
688
689 for (x = 0; x < width; x++, p++) {
690 uint32_t val = *p;
691
692 val = (val & 0xff00ff00) |
693 (val & 0x000000ff) << 16 |
694 (val & 0x00ff0000) >> 16;
695
696 writel_relaxed(val,
697 base + LCD_SPU_SRAM_WRDAT);
698 writel_relaxed(addr | SRAM_WRITE,
699 base + LCD_SPU_SRAM_CTRL);
700 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
701 addr += 1;
702 if ((addr & 0x00ff) == 0)
703 addr += 0xf00;
704 if ((addr & 0x30ff) == 0)
705 addr = SRAM_HWC32_RAM2;
706 }
707 }
708 }
709
710 static void armada_drm_crtc_cursor_tran(void __iomem *base)
711 {
712 unsigned addr;
713
714 for (addr = 0; addr < 256; addr++) {
715 /* write the default value */
716 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
717 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
718 base + LCD_SPU_SRAM_CTRL);
719 }
720 }
721
722 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
723 {
724 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
725 uint32_t yoff, yscr, h = dcrtc->cursor_h;
726 uint32_t para1;
727
728 /*
729 * Calculate the visible width and height of the cursor,
730 * screen position, and the position in the cursor bitmap.
731 */
732 if (dcrtc->cursor_x < 0) {
733 xoff = -dcrtc->cursor_x;
734 xscr = 0;
735 w -= min(xoff, w);
736 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
737 xoff = 0;
738 xscr = dcrtc->cursor_x;
739 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
740 } else {
741 xoff = 0;
742 xscr = dcrtc->cursor_x;
743 }
744
745 if (dcrtc->cursor_y < 0) {
746 yoff = -dcrtc->cursor_y;
747 yscr = 0;
748 h -= min(yoff, h);
749 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
750 yoff = 0;
751 yscr = dcrtc->cursor_y;
752 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
753 } else {
754 yoff = 0;
755 yscr = dcrtc->cursor_y;
756 }
757
758 /* On interlaced modes, the vertical cursor size must be halved */
759 s = dcrtc->cursor_w;
760 if (dcrtc->interlaced) {
761 s *= 2;
762 yscr /= 2;
763 h /= 2;
764 }
765
766 if (!dcrtc->cursor_obj || !h || !w) {
767 spin_lock_irq(&dcrtc->irq_lock);
768 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
769 dcrtc->cursor_update = false;
770 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
771 spin_unlock_irq(&dcrtc->irq_lock);
772 return 0;
773 }
774
775 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
776 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
777 dcrtc->base + LCD_SPU_SRAM_PARA1);
778
779 /*
780 * Initialize the transparency if the SRAM was powered down.
781 * We must also reload the cursor data as well.
782 */
783 if (!(para1 & CFG_CSB_256x32)) {
784 armada_drm_crtc_cursor_tran(dcrtc->base);
785 reload = true;
786 }
787
788 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
789 spin_lock_irq(&dcrtc->irq_lock);
790 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
791 dcrtc->cursor_update = false;
792 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
793 spin_unlock_irq(&dcrtc->irq_lock);
794 reload = true;
795 }
796 if (reload) {
797 struct armada_gem_object *obj = dcrtc->cursor_obj;
798 uint32_t *pix;
799 /* Set the top-left corner of the cursor image */
800 pix = obj->addr;
801 pix += yoff * s + xoff;
802 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
803 }
804
805 /* Reload the cursor position, size and enable in the IRQ handler */
806 spin_lock_irq(&dcrtc->irq_lock);
807 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
808 dcrtc->cursor_hw_sz = h << 16 | w;
809 dcrtc->cursor_update = true;
810 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
811 spin_unlock_irq(&dcrtc->irq_lock);
812
813 return 0;
814 }
815
816 static void cursor_update(void *data)
817 {
818 armada_drm_crtc_cursor_update(data, true);
819 }
820
821 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
822 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
823 {
824 struct drm_device *dev = crtc->dev;
825 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
826 struct armada_gem_object *obj = NULL;
827 int ret;
828
829 /* If no cursor support, replicate drm's return value */
830 if (!dcrtc->variant->has_spu_adv_reg)
831 return -ENXIO;
832
833 if (handle && w > 0 && h > 0) {
834 /* maximum size is 64x32 or 32x64 */
835 if (w > 64 || h > 64 || (w > 32 && h > 32))
836 return -ENOMEM;
837
838 obj = armada_gem_object_lookup(dev, file, handle);
839 if (!obj)
840 return -ENOENT;
841
842 /* Must be a kernel-mapped object */
843 if (!obj->addr) {
844 drm_gem_object_unreference_unlocked(&obj->obj);
845 return -EINVAL;
846 }
847
848 if (obj->obj.size < w * h * 4) {
849 DRM_ERROR("buffer is too small\n");
850 drm_gem_object_unreference_unlocked(&obj->obj);
851 return -ENOMEM;
852 }
853 }
854
855 mutex_lock(&dev->struct_mutex);
856 if (dcrtc->cursor_obj) {
857 dcrtc->cursor_obj->update = NULL;
858 dcrtc->cursor_obj->update_data = NULL;
859 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
860 }
861 dcrtc->cursor_obj = obj;
862 dcrtc->cursor_w = w;
863 dcrtc->cursor_h = h;
864 ret = armada_drm_crtc_cursor_update(dcrtc, true);
865 if (obj) {
866 obj->update_data = dcrtc;
867 obj->update = cursor_update;
868 }
869 mutex_unlock(&dev->struct_mutex);
870
871 return ret;
872 }
873
874 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
875 {
876 struct drm_device *dev = crtc->dev;
877 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
878 int ret;
879
880 /* If no cursor support, replicate drm's return value */
881 if (!dcrtc->variant->has_spu_adv_reg)
882 return -EFAULT;
883
884 mutex_lock(&dev->struct_mutex);
885 dcrtc->cursor_x = x;
886 dcrtc->cursor_y = y;
887 ret = armada_drm_crtc_cursor_update(dcrtc, false);
888 mutex_unlock(&dev->struct_mutex);
889
890 return ret;
891 }
892
893 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
894 {
895 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
896 struct armada_private *priv = crtc->dev->dev_private;
897
898 if (dcrtc->cursor_obj)
899 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
900
901 priv->dcrtc[dcrtc->num] = NULL;
902 drm_crtc_cleanup(&dcrtc->crtc);
903
904 if (!IS_ERR(dcrtc->clk))
905 clk_disable_unprepare(dcrtc->clk);
906
907 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
908
909 of_node_put(dcrtc->crtc.port);
910
911 kfree(dcrtc);
912 }
913
914 /*
915 * The mode_config lock is held here, to prevent races between this
916 * and a mode_set.
917 */
918 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
919 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
920 {
921 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
922 struct armada_frame_work *work;
923 struct drm_device *dev = crtc->dev;
924 unsigned long flags;
925 unsigned i;
926 int ret;
927
928 /* We don't support changing the pixel format */
929 if (fb->pixel_format != crtc->primary->fb->pixel_format)
930 return -EINVAL;
931
932 work = kmalloc(sizeof(*work), GFP_KERNEL);
933 if (!work)
934 return -ENOMEM;
935
936 work->event = event;
937 work->old_fb = dcrtc->crtc.primary->fb;
938
939 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
940 dcrtc->interlaced);
941 armada_reg_queue_end(work->regs, i);
942
943 /*
944 * Ensure that we hold a reference on the new framebuffer.
945 * This has to match the behaviour in mode_set.
946 */
947 drm_framebuffer_reference(fb);
948
949 ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
950 if (ret) {
951 /* Undo our reference above */
952 drm_framebuffer_unreference(fb);
953 kfree(work);
954 return ret;
955 }
956
957 /*
958 * Don't take a reference on the new framebuffer;
959 * drm_mode_page_flip_ioctl() has already grabbed a reference and
960 * will _not_ drop that reference on successful return from this
961 * function. Simply mark this new framebuffer as the current one.
962 */
963 dcrtc->crtc.primary->fb = fb;
964
965 /*
966 * Finally, if the display is blanked, we won't receive an
967 * interrupt, so complete it now.
968 */
969 if (dpms_blanked(dcrtc->dpms)) {
970 spin_lock_irqsave(&dev->event_lock, flags);
971 if (dcrtc->frame_work)
972 armada_drm_crtc_complete_frame_work(dcrtc);
973 spin_unlock_irqrestore(&dev->event_lock, flags);
974 }
975
976 return 0;
977 }
978
979 static int
980 armada_drm_crtc_set_property(struct drm_crtc *crtc,
981 struct drm_property *property, uint64_t val)
982 {
983 struct armada_private *priv = crtc->dev->dev_private;
984 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
985 bool update_csc = false;
986
987 if (property == priv->csc_yuv_prop) {
988 dcrtc->csc_yuv_mode = val;
989 update_csc = true;
990 } else if (property == priv->csc_rgb_prop) {
991 dcrtc->csc_rgb_mode = val;
992 update_csc = true;
993 }
994
995 if (update_csc) {
996 uint32_t val;
997
998 val = dcrtc->spu_iopad_ctrl |
999 armada_drm_crtc_calculate_csc(dcrtc);
1000 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static struct drm_crtc_funcs armada_crtc_funcs = {
1007 .cursor_set = armada_drm_crtc_cursor_set,
1008 .cursor_move = armada_drm_crtc_cursor_move,
1009 .destroy = armada_drm_crtc_destroy,
1010 .set_config = drm_crtc_helper_set_config,
1011 .page_flip = armada_drm_crtc_page_flip,
1012 .set_property = armada_drm_crtc_set_property,
1013 };
1014
1015 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1016 { CSC_AUTO, "Auto" },
1017 { CSC_YUV_CCIR601, "CCIR601" },
1018 { CSC_YUV_CCIR709, "CCIR709" },
1019 };
1020
1021 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1022 { CSC_AUTO, "Auto" },
1023 { CSC_RGB_COMPUTER, "Computer system" },
1024 { CSC_RGB_STUDIO, "Studio" },
1025 };
1026
1027 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1028 {
1029 struct armada_private *priv = dev->dev_private;
1030
1031 if (priv->csc_yuv_prop)
1032 return 0;
1033
1034 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1035 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1036 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1037 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1038 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1039 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1040
1041 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1042 return -ENOMEM;
1043
1044 return 0;
1045 }
1046
1047 int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1048 struct resource *res, int irq, const struct armada_variant *variant,
1049 struct device_node *port)
1050 {
1051 struct armada_private *priv = drm->dev_private;
1052 struct armada_crtc *dcrtc;
1053 void __iomem *base;
1054 int ret;
1055
1056 ret = armada_drm_crtc_create_properties(drm);
1057 if (ret)
1058 return ret;
1059
1060 base = devm_ioremap_resource(dev, res);
1061 if (IS_ERR(base))
1062 return PTR_ERR(base);
1063
1064 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1065 if (!dcrtc) {
1066 DRM_ERROR("failed to allocate Armada crtc\n");
1067 return -ENOMEM;
1068 }
1069
1070 if (dev != drm->dev)
1071 dev_set_drvdata(dev, dcrtc);
1072
1073 dcrtc->variant = variant;
1074 dcrtc->base = base;
1075 dcrtc->num = drm->mode_config.num_crtc;
1076 dcrtc->clk = ERR_PTR(-EINVAL);
1077 dcrtc->csc_yuv_mode = CSC_AUTO;
1078 dcrtc->csc_rgb_mode = CSC_AUTO;
1079 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1080 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1081 spin_lock_init(&dcrtc->irq_lock);
1082 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1083 INIT_LIST_HEAD(&dcrtc->vbl_list);
1084 init_waitqueue_head(&dcrtc->frame_wait);
1085
1086 /* Initialize some registers which we don't otherwise set */
1087 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1088 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1089 writel_relaxed(dcrtc->spu_iopad_ctrl,
1090 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1091 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1092 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1093 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1094 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1095 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1096 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1097 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1098 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1099
1100 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1101 dcrtc);
1102 if (ret < 0) {
1103 kfree(dcrtc);
1104 return ret;
1105 }
1106
1107 if (dcrtc->variant->init) {
1108 ret = dcrtc->variant->init(dcrtc, dev);
1109 if (ret) {
1110 kfree(dcrtc);
1111 return ret;
1112 }
1113 }
1114
1115 /* Ensure AXI pipeline is enabled */
1116 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1117
1118 priv->dcrtc[dcrtc->num] = dcrtc;
1119
1120 dcrtc->crtc.port = port;
1121 drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs);
1122 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1123
1124 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1125 dcrtc->csc_yuv_mode);
1126 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1127 dcrtc->csc_rgb_mode);
1128
1129 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1130 }
1131
1132 static int
1133 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1134 {
1135 struct platform_device *pdev = to_platform_device(dev);
1136 struct drm_device *drm = data;
1137 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1138 int irq = platform_get_irq(pdev, 0);
1139 const struct armada_variant *variant;
1140 struct device_node *port = NULL;
1141
1142 if (irq < 0)
1143 return irq;
1144
1145 if (!dev->of_node) {
1146 const struct platform_device_id *id;
1147
1148 id = platform_get_device_id(pdev);
1149 if (!id)
1150 return -ENXIO;
1151
1152 variant = (const struct armada_variant *)id->driver_data;
1153 } else {
1154 const struct of_device_id *match;
1155 struct device_node *np, *parent = dev->of_node;
1156
1157 match = of_match_device(dev->driver->of_match_table, dev);
1158 if (!match)
1159 return -ENXIO;
1160
1161 np = of_get_child_by_name(parent, "ports");
1162 if (np)
1163 parent = np;
1164 port = of_get_child_by_name(parent, "port");
1165 of_node_put(np);
1166 if (!port) {
1167 dev_err(dev, "no port node found in %s\n",
1168 parent->full_name);
1169 return -ENXIO;
1170 }
1171
1172 variant = match->data;
1173 }
1174
1175 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1176 }
1177
1178 static void
1179 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1180 {
1181 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1182
1183 armada_drm_crtc_destroy(&dcrtc->crtc);
1184 }
1185
1186 static const struct component_ops armada_lcd_ops = {
1187 .bind = armada_lcd_bind,
1188 .unbind = armada_lcd_unbind,
1189 };
1190
1191 static int armada_lcd_probe(struct platform_device *pdev)
1192 {
1193 return component_add(&pdev->dev, &armada_lcd_ops);
1194 }
1195
1196 static int armada_lcd_remove(struct platform_device *pdev)
1197 {
1198 component_del(&pdev->dev, &armada_lcd_ops);
1199 return 0;
1200 }
1201
1202 static struct of_device_id armada_lcd_of_match[] = {
1203 {
1204 .compatible = "marvell,dove-lcd",
1205 .data = &armada510_ops,
1206 },
1207 {}
1208 };
1209 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1210
1211 static const struct platform_device_id armada_lcd_platform_ids[] = {
1212 {
1213 .name = "armada-lcd",
1214 .driver_data = (unsigned long)&armada510_ops,
1215 }, {
1216 .name = "armada-510-lcd",
1217 .driver_data = (unsigned long)&armada510_ops,
1218 },
1219 { },
1220 };
1221 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1222
1223 struct platform_driver armada_lcd_platform_driver = {
1224 .probe = armada_lcd_probe,
1225 .remove = armada_lcd_remove,
1226 .driver = {
1227 .name = "armada-lcd",
1228 .owner = THIS_MODULE,
1229 .of_match_table = armada_lcd_of_match,
1230 },
1231 .id_table = armada_lcd_platform_ids,
1232 };
Linux with added FPC-III support