2 * Samsung SoC DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/interrupt.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_graph.h>
22 #include <linux/gpio.h>
23 #include <linux/component.h>
24 #include <linux/phy/phy.h>
25 #include <video/of_display_timing.h>
26 #include <video/of_videomode.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_panel.h>
34 #include "exynos_dp_core.h"
36 #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
39 static inline struct exynos_drm_crtc
*dp_to_crtc(struct exynos_dp_device
*dp
)
41 return to_exynos_crtc(dp
->encoder
->crtc
);
44 static inline struct exynos_dp_device
*
45 display_to_dp(struct exynos_drm_display
*d
)
47 return container_of(d
, struct exynos_dp_device
, display
);
51 struct i2c_client
*client
;
52 struct device_node
*node
;
55 static void exynos_dp_init_dp(struct exynos_dp_device
*dp
)
59 exynos_dp_swreset(dp
);
61 exynos_dp_init_analog_param(dp
);
62 exynos_dp_init_interrupt(dp
);
64 /* SW defined function Normal operation */
65 exynos_dp_enable_sw_function(dp
);
67 exynos_dp_config_interrupt(dp
);
68 exynos_dp_init_analog_func(dp
);
70 exynos_dp_init_hpd(dp
);
71 exynos_dp_init_aux(dp
);
74 static int exynos_dp_detect_hpd(struct exynos_dp_device
*dp
)
78 while (exynos_dp_get_plug_in_status(dp
) != 0) {
80 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
81 dev_err(dp
->dev
, "failed to get hpd plug status\n");
90 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data
)
93 unsigned char sum
= 0;
95 for (i
= 0; i
< EDID_BLOCK_LENGTH
; i
++)
96 sum
= sum
+ edid_data
[i
];
101 static int exynos_dp_read_edid(struct exynos_dp_device
*dp
)
103 unsigned char edid
[EDID_BLOCK_LENGTH
* 2];
104 unsigned int extend_block
= 0;
106 unsigned char test_vector
;
110 * EDID device address is 0x50.
111 * However, if necessary, you must have set upper address
112 * into E-EDID in I2C device, 0x30.
115 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
116 retval
= exynos_dp_read_byte_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
122 if (extend_block
> 0) {
123 dev_dbg(dp
->dev
, "EDID data includes a single extension!\n");
126 retval
= exynos_dp_read_bytes_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
129 &edid
[EDID_HEADER_PATTERN
]);
131 dev_err(dp
->dev
, "EDID Read failed!\n");
134 sum
= exynos_dp_calc_edid_check_sum(edid
);
136 dev_err(dp
->dev
, "EDID bad checksum!\n");
140 /* Read additional EDID data */
141 retval
= exynos_dp_read_bytes_from_i2c(dp
,
142 I2C_EDID_DEVICE_ADDR
,
145 &edid
[EDID_BLOCK_LENGTH
]);
147 dev_err(dp
->dev
, "EDID Read failed!\n");
150 sum
= exynos_dp_calc_edid_check_sum(&edid
[EDID_BLOCK_LENGTH
]);
152 dev_err(dp
->dev
, "EDID bad checksum!\n");
156 exynos_dp_read_byte_from_dpcd(dp
, DP_TEST_REQUEST
,
158 if (test_vector
& DP_TEST_LINK_EDID_READ
) {
159 exynos_dp_write_byte_to_dpcd(dp
,
160 DP_TEST_EDID_CHECKSUM
,
161 edid
[EDID_BLOCK_LENGTH
+ EDID_CHECKSUM
]);
162 exynos_dp_write_byte_to_dpcd(dp
,
164 DP_TEST_EDID_CHECKSUM_WRITE
);
167 dev_info(dp
->dev
, "EDID data does not include any extensions.\n");
170 retval
= exynos_dp_read_bytes_from_i2c(dp
,
171 I2C_EDID_DEVICE_ADDR
,
174 &edid
[EDID_HEADER_PATTERN
]);
176 dev_err(dp
->dev
, "EDID Read failed!\n");
179 sum
= exynos_dp_calc_edid_check_sum(edid
);
181 dev_err(dp
->dev
, "EDID bad checksum!\n");
185 exynos_dp_read_byte_from_dpcd(dp
,
188 if (test_vector
& DP_TEST_LINK_EDID_READ
) {
189 exynos_dp_write_byte_to_dpcd(dp
,
190 DP_TEST_EDID_CHECKSUM
,
191 edid
[EDID_CHECKSUM
]);
192 exynos_dp_write_byte_to_dpcd(dp
,
194 DP_TEST_EDID_CHECKSUM_WRITE
);
198 dev_dbg(dp
->dev
, "EDID Read success!\n");
202 static int exynos_dp_handle_edid(struct exynos_dp_device
*dp
)
208 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
209 retval
= exynos_dp_read_bytes_from_dpcd(dp
, DP_DPCD_REV
,
215 for (i
= 0; i
< 3; i
++) {
216 retval
= exynos_dp_read_edid(dp
);
224 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device
*dp
,
229 exynos_dp_read_byte_from_dpcd(dp
, DP_LANE_COUNT_SET
, &data
);
232 exynos_dp_write_byte_to_dpcd(dp
, DP_LANE_COUNT_SET
,
233 DP_LANE_COUNT_ENHANCED_FRAME_EN
|
234 DPCD_LANE_COUNT_SET(data
));
236 exynos_dp_write_byte_to_dpcd(dp
, DP_LANE_COUNT_SET
,
237 DPCD_LANE_COUNT_SET(data
));
240 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device
*dp
)
245 exynos_dp_read_byte_from_dpcd(dp
, DP_MAX_LANE_COUNT
, &data
);
246 retval
= DPCD_ENHANCED_FRAME_CAP(data
);
251 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device
*dp
)
255 data
= exynos_dp_is_enhanced_mode_available(dp
);
256 exynos_dp_enable_rx_to_enhanced_mode(dp
, data
);
257 exynos_dp_enable_enhanced_mode(dp
, data
);
260 static void exynos_dp_training_pattern_dis(struct exynos_dp_device
*dp
)
262 exynos_dp_set_training_pattern(dp
, DP_NONE
);
264 exynos_dp_write_byte_to_dpcd(dp
,
265 DP_TRAINING_PATTERN_SET
,
266 DP_TRAINING_PATTERN_DISABLE
);
269 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device
*dp
,
270 int pre_emphasis
, int lane
)
274 exynos_dp_set_lane0_pre_emphasis(dp
, pre_emphasis
);
277 exynos_dp_set_lane1_pre_emphasis(dp
, pre_emphasis
);
281 exynos_dp_set_lane2_pre_emphasis(dp
, pre_emphasis
);
285 exynos_dp_set_lane3_pre_emphasis(dp
, pre_emphasis
);
290 static int exynos_dp_link_start(struct exynos_dp_device
*dp
)
293 int lane
, lane_count
, pll_tries
, retval
;
295 lane_count
= dp
->link_train
.lane_count
;
297 dp
->link_train
.lt_state
= CLOCK_RECOVERY
;
298 dp
->link_train
.eq_loop
= 0;
300 for (lane
= 0; lane
< lane_count
; lane
++)
301 dp
->link_train
.cr_loop
[lane
] = 0;
303 /* Set link rate and count as you want to establish*/
304 exynos_dp_set_link_bandwidth(dp
, dp
->link_train
.link_rate
);
305 exynos_dp_set_lane_count(dp
, dp
->link_train
.lane_count
);
307 /* Setup RX configuration */
308 buf
[0] = dp
->link_train
.link_rate
;
309 buf
[1] = dp
->link_train
.lane_count
;
310 retval
= exynos_dp_write_bytes_to_dpcd(dp
, DP_LINK_BW_SET
,
315 /* Set TX pre-emphasis to minimum */
316 for (lane
= 0; lane
< lane_count
; lane
++)
317 exynos_dp_set_lane_lane_pre_emphasis(dp
,
318 PRE_EMPHASIS_LEVEL_0
, lane
);
320 /* Wait for PLL lock */
322 while (exynos_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
323 if (pll_tries
== DP_TIMEOUT_LOOP_COUNT
) {
324 dev_err(dp
->dev
, "Wait for PLL lock timed out\n");
329 usleep_range(90, 120);
332 /* Set training pattern 1 */
333 exynos_dp_set_training_pattern(dp
, TRAINING_PTN1
);
335 /* Set RX training pattern */
336 retval
= exynos_dp_write_byte_to_dpcd(dp
,
337 DP_TRAINING_PATTERN_SET
,
338 DP_LINK_SCRAMBLING_DISABLE
| DP_TRAINING_PATTERN_1
);
342 for (lane
= 0; lane
< lane_count
; lane
++)
343 buf
[lane
] = DP_TRAIN_PRE_EMPH_LEVEL_0
|
344 DP_TRAIN_VOLTAGE_SWING_LEVEL_0
;
346 retval
= exynos_dp_write_bytes_to_dpcd(dp
, DP_TRAINING_LANE0_SET
,
352 static unsigned char exynos_dp_get_lane_status(u8 link_status
[2], int lane
)
354 int shift
= (lane
& 1) * 4;
355 u8 link_value
= link_status
[lane
>>1];
357 return (link_value
>> shift
) & 0xf;
360 static int exynos_dp_clock_recovery_ok(u8 link_status
[2], int lane_count
)
365 for (lane
= 0; lane
< lane_count
; lane
++) {
366 lane_status
= exynos_dp_get_lane_status(link_status
, lane
);
367 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
373 static int exynos_dp_channel_eq_ok(u8 link_status
[2], u8 link_align
,
379 if ((link_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
382 for (lane
= 0; lane
< lane_count
; lane
++) {
383 lane_status
= exynos_dp_get_lane_status(link_status
, lane
);
384 lane_status
&= DP_CHANNEL_EQ_BITS
;
385 if (lane_status
!= DP_CHANNEL_EQ_BITS
)
392 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request
[2],
395 int shift
= (lane
& 1) * 4;
396 u8 link_value
= adjust_request
[lane
>>1];
398 return (link_value
>> shift
) & 0x3;
401 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
402 u8 adjust_request
[2],
405 int shift
= (lane
& 1) * 4;
406 u8 link_value
= adjust_request
[lane
>>1];
408 return ((link_value
>> shift
) & 0xc) >> 2;
411 static void exynos_dp_set_lane_link_training(struct exynos_dp_device
*dp
,
412 u8 training_lane_set
, int lane
)
416 exynos_dp_set_lane0_link_training(dp
, training_lane_set
);
419 exynos_dp_set_lane1_link_training(dp
, training_lane_set
);
423 exynos_dp_set_lane2_link_training(dp
, training_lane_set
);
427 exynos_dp_set_lane3_link_training(dp
, training_lane_set
);
432 static unsigned int exynos_dp_get_lane_link_training(
433 struct exynos_dp_device
*dp
,
440 reg
= exynos_dp_get_lane0_link_training(dp
);
443 reg
= exynos_dp_get_lane1_link_training(dp
);
446 reg
= exynos_dp_get_lane2_link_training(dp
);
449 reg
= exynos_dp_get_lane3_link_training(dp
);
459 static void exynos_dp_reduce_link_rate(struct exynos_dp_device
*dp
)
461 exynos_dp_training_pattern_dis(dp
);
462 exynos_dp_set_enhanced_mode(dp
);
464 dp
->link_train
.lt_state
= FAILED
;
467 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device
*dp
,
468 u8 adjust_request
[2])
470 int lane
, lane_count
;
471 u8 voltage_swing
, pre_emphasis
, training_lane
;
473 lane_count
= dp
->link_train
.lane_count
;
474 for (lane
= 0; lane
< lane_count
; lane
++) {
475 voltage_swing
= exynos_dp_get_adjust_request_voltage(
476 adjust_request
, lane
);
477 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
478 adjust_request
, lane
);
479 training_lane
= DPCD_VOLTAGE_SWING_SET(voltage_swing
) |
480 DPCD_PRE_EMPHASIS_SET(pre_emphasis
);
482 if (voltage_swing
== VOLTAGE_LEVEL_3
)
483 training_lane
|= DP_TRAIN_MAX_SWING_REACHED
;
484 if (pre_emphasis
== PRE_EMPHASIS_LEVEL_3
)
485 training_lane
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
487 dp
->link_train
.training_lane
[lane
] = training_lane
;
491 static int exynos_dp_process_clock_recovery(struct exynos_dp_device
*dp
)
493 int lane
, lane_count
, retval
;
494 u8 voltage_swing
, pre_emphasis
, training_lane
;
495 u8 link_status
[2], adjust_request
[2];
497 usleep_range(100, 101);
499 lane_count
= dp
->link_train
.lane_count
;
501 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
502 DP_LANE0_1_STATUS
, 2, link_status
);
506 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
507 DP_ADJUST_REQUEST_LANE0_1
, 2, adjust_request
);
511 if (exynos_dp_clock_recovery_ok(link_status
, lane_count
) == 0) {
512 /* set training pattern 2 for EQ */
513 exynos_dp_set_training_pattern(dp
, TRAINING_PTN2
);
515 retval
= exynos_dp_write_byte_to_dpcd(dp
,
516 DP_TRAINING_PATTERN_SET
,
517 DP_LINK_SCRAMBLING_DISABLE
|
518 DP_TRAINING_PATTERN_2
);
522 dev_info(dp
->dev
, "Link Training Clock Recovery success\n");
523 dp
->link_train
.lt_state
= EQUALIZER_TRAINING
;
525 for (lane
= 0; lane
< lane_count
; lane
++) {
526 training_lane
= exynos_dp_get_lane_link_training(
528 voltage_swing
= exynos_dp_get_adjust_request_voltage(
529 adjust_request
, lane
);
530 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
531 adjust_request
, lane
);
533 if (DPCD_VOLTAGE_SWING_GET(training_lane
) ==
535 DPCD_PRE_EMPHASIS_GET(training_lane
) ==
537 dp
->link_train
.cr_loop
[lane
]++;
539 if (dp
->link_train
.cr_loop
[lane
] == MAX_CR_LOOP
||
540 voltage_swing
== VOLTAGE_LEVEL_3
||
541 pre_emphasis
== PRE_EMPHASIS_LEVEL_3
) {
542 dev_err(dp
->dev
, "CR Max reached (%d,%d,%d)\n",
543 dp
->link_train
.cr_loop
[lane
],
544 voltage_swing
, pre_emphasis
);
545 exynos_dp_reduce_link_rate(dp
);
551 exynos_dp_get_adjust_training_lane(dp
, adjust_request
);
553 for (lane
= 0; lane
< lane_count
; lane
++)
554 exynos_dp_set_lane_link_training(dp
,
555 dp
->link_train
.training_lane
[lane
], lane
);
557 retval
= exynos_dp_write_bytes_to_dpcd(dp
,
558 DP_TRAINING_LANE0_SET
, lane_count
,
559 dp
->link_train
.training_lane
);
566 static int exynos_dp_process_equalizer_training(struct exynos_dp_device
*dp
)
568 int lane
, lane_count
, retval
;
570 u8 link_align
, link_status
[2], adjust_request
[2];
572 usleep_range(400, 401);
574 lane_count
= dp
->link_train
.lane_count
;
576 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
577 DP_LANE0_1_STATUS
, 2, link_status
);
581 if (exynos_dp_clock_recovery_ok(link_status
, lane_count
)) {
582 exynos_dp_reduce_link_rate(dp
);
586 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
587 DP_ADJUST_REQUEST_LANE0_1
, 2, adjust_request
);
591 retval
= exynos_dp_read_byte_from_dpcd(dp
,
592 DP_LANE_ALIGN_STATUS_UPDATED
, &link_align
);
596 exynos_dp_get_adjust_training_lane(dp
, adjust_request
);
598 if (!exynos_dp_channel_eq_ok(link_status
, link_align
, lane_count
)) {
599 /* traing pattern Set to Normal */
600 exynos_dp_training_pattern_dis(dp
);
602 dev_info(dp
->dev
, "Link Training success!\n");
604 exynos_dp_get_link_bandwidth(dp
, ®
);
605 dp
->link_train
.link_rate
= reg
;
606 dev_dbg(dp
->dev
, "final bandwidth = %.2x\n",
607 dp
->link_train
.link_rate
);
609 exynos_dp_get_lane_count(dp
, ®
);
610 dp
->link_train
.lane_count
= reg
;
611 dev_dbg(dp
->dev
, "final lane count = %.2x\n",
612 dp
->link_train
.lane_count
);
614 /* set enhanced mode if available */
615 exynos_dp_set_enhanced_mode(dp
);
616 dp
->link_train
.lt_state
= FINISHED
;
622 dp
->link_train
.eq_loop
++;
624 if (dp
->link_train
.eq_loop
> MAX_EQ_LOOP
) {
625 dev_err(dp
->dev
, "EQ Max loop\n");
626 exynos_dp_reduce_link_rate(dp
);
630 for (lane
= 0; lane
< lane_count
; lane
++)
631 exynos_dp_set_lane_link_training(dp
,
632 dp
->link_train
.training_lane
[lane
], lane
);
634 retval
= exynos_dp_write_bytes_to_dpcd(dp
, DP_TRAINING_LANE0_SET
,
635 lane_count
, dp
->link_train
.training_lane
);
640 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device
*dp
,
646 * For DP rev.1.1, Maximum link rate of Main Link lanes
647 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
649 exynos_dp_read_byte_from_dpcd(dp
, DP_MAX_LINK_RATE
, &data
);
653 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device
*dp
,
659 * For DP rev.1.1, Maximum number of Main Link lanes
660 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
662 exynos_dp_read_byte_from_dpcd(dp
, DP_MAX_LANE_COUNT
, &data
);
663 *lane_count
= DPCD_MAX_LANE_COUNT(data
);
666 static void exynos_dp_init_training(struct exynos_dp_device
*dp
,
667 enum link_lane_count_type max_lane
,
668 enum link_rate_type max_rate
)
671 * MACRO_RST must be applied after the PLL_LOCK to avoid
672 * the DP inter pair skew issue for at least 10 us
674 exynos_dp_reset_macro(dp
);
676 /* Initialize by reading RX's DPCD */
677 exynos_dp_get_max_rx_bandwidth(dp
, &dp
->link_train
.link_rate
);
678 exynos_dp_get_max_rx_lane_count(dp
, &dp
->link_train
.lane_count
);
680 if ((dp
->link_train
.link_rate
!= LINK_RATE_1_62GBPS
) &&
681 (dp
->link_train
.link_rate
!= LINK_RATE_2_70GBPS
)) {
682 dev_err(dp
->dev
, "Rx Max Link Rate is abnormal :%x !\n",
683 dp
->link_train
.link_rate
);
684 dp
->link_train
.link_rate
= LINK_RATE_1_62GBPS
;
687 if (dp
->link_train
.lane_count
== 0) {
688 dev_err(dp
->dev
, "Rx Max Lane count is abnormal :%x !\n",
689 dp
->link_train
.lane_count
);
690 dp
->link_train
.lane_count
= (u8
)LANE_COUNT1
;
693 /* Setup TX lane count & rate */
694 if (dp
->link_train
.lane_count
> max_lane
)
695 dp
->link_train
.lane_count
= max_lane
;
696 if (dp
->link_train
.link_rate
> max_rate
)
697 dp
->link_train
.link_rate
= max_rate
;
699 /* All DP analog module power up */
700 exynos_dp_set_analog_power_down(dp
, POWER_ALL
, 0);
703 static int exynos_dp_sw_link_training(struct exynos_dp_device
*dp
)
705 int retval
= 0, training_finished
= 0;
707 dp
->link_train
.lt_state
= START
;
710 while (!retval
&& !training_finished
) {
711 switch (dp
->link_train
.lt_state
) {
713 retval
= exynos_dp_link_start(dp
);
715 dev_err(dp
->dev
, "LT link start failed!\n");
718 retval
= exynos_dp_process_clock_recovery(dp
);
720 dev_err(dp
->dev
, "LT CR failed!\n");
722 case EQUALIZER_TRAINING
:
723 retval
= exynos_dp_process_equalizer_training(dp
);
725 dev_err(dp
->dev
, "LT EQ failed!\n");
728 training_finished
= 1;
735 dev_err(dp
->dev
, "eDP link training failed (%d)\n", retval
);
740 static int exynos_dp_set_link_train(struct exynos_dp_device
*dp
,
747 for (i
= 0; i
< DP_TIMEOUT_LOOP_COUNT
; i
++) {
748 exynos_dp_init_training(dp
, count
, bwtype
);
749 retval
= exynos_dp_sw_link_training(dp
);
753 usleep_range(100, 110);
759 static int exynos_dp_config_video(struct exynos_dp_device
*dp
)
762 int timeout_loop
= 0;
765 exynos_dp_config_video_slave_mode(dp
);
767 exynos_dp_set_video_color_format(dp
);
769 if (exynos_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
770 dev_err(dp
->dev
, "PLL is not locked yet.\n");
776 if (exynos_dp_is_slave_video_stream_clock_on(dp
) == 0)
778 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
779 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
786 /* Set to use the register calculated M/N video */
787 exynos_dp_set_video_cr_mn(dp
, CALCULATED_M
, 0, 0);
789 /* For video bist, Video timing must be generated by register */
790 exynos_dp_set_video_timing_mode(dp
, VIDEO_TIMING_FROM_CAPTURE
);
792 /* Disable video mute */
793 exynos_dp_enable_video_mute(dp
, 0);
795 /* Configure video slave mode */
796 exynos_dp_enable_video_master(dp
, 0);
799 exynos_dp_start_video(dp
);
805 if (exynos_dp_is_video_stream_on(dp
) == 0) {
809 } else if (done_count
) {
812 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
813 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
817 usleep_range(1000, 1001);
821 dev_err(dp
->dev
, "Video stream is not detected!\n");
826 static void exynos_dp_enable_scramble(struct exynos_dp_device
*dp
, bool enable
)
831 exynos_dp_enable_scrambling(dp
);
833 exynos_dp_read_byte_from_dpcd(dp
,
834 DP_TRAINING_PATTERN_SET
,
836 exynos_dp_write_byte_to_dpcd(dp
,
837 DP_TRAINING_PATTERN_SET
,
838 (u8
)(data
& ~DP_LINK_SCRAMBLING_DISABLE
));
840 exynos_dp_disable_scrambling(dp
);
842 exynos_dp_read_byte_from_dpcd(dp
,
843 DP_TRAINING_PATTERN_SET
,
845 exynos_dp_write_byte_to_dpcd(dp
,
846 DP_TRAINING_PATTERN_SET
,
847 (u8
)(data
| DP_LINK_SCRAMBLING_DISABLE
));
851 static irqreturn_t
exynos_dp_irq_handler(int irq
, void *arg
)
853 struct exynos_dp_device
*dp
= arg
;
855 enum dp_irq_type irq_type
;
857 irq_type
= exynos_dp_get_irq_type(dp
);
859 case DP_IRQ_TYPE_HP_CABLE_IN
:
860 dev_dbg(dp
->dev
, "Received irq - cable in\n");
861 schedule_work(&dp
->hotplug_work
);
862 exynos_dp_clear_hotplug_interrupts(dp
);
864 case DP_IRQ_TYPE_HP_CABLE_OUT
:
865 dev_dbg(dp
->dev
, "Received irq - cable out\n");
866 exynos_dp_clear_hotplug_interrupts(dp
);
868 case DP_IRQ_TYPE_HP_CHANGE
:
870 * We get these change notifications once in a while, but there
871 * is nothing we can do with them. Just ignore it for now and
872 * only handle cable changes.
874 dev_dbg(dp
->dev
, "Received irq - hotplug change; ignoring.\n");
875 exynos_dp_clear_hotplug_interrupts(dp
);
878 dev_err(dp
->dev
, "Received irq - unknown type!\n");
884 static void exynos_dp_hotplug(struct work_struct
*work
)
886 struct exynos_dp_device
*dp
;
888 dp
= container_of(work
, struct exynos_dp_device
, hotplug_work
);
891 drm_helper_hpd_irq_event(dp
->drm_dev
);
894 static void exynos_dp_commit(struct exynos_drm_display
*display
)
896 struct exynos_dp_device
*dp
= display_to_dp(display
);
899 /* Keep the panel disabled while we configure video */
901 if (drm_panel_disable(dp
->panel
))
902 DRM_ERROR("failed to disable the panel\n");
905 ret
= exynos_dp_detect_hpd(dp
);
907 /* Cable has been disconnected, we're done */
911 ret
= exynos_dp_handle_edid(dp
);
913 dev_err(dp
->dev
, "unable to handle edid\n");
917 ret
= exynos_dp_set_link_train(dp
, dp
->video_info
->lane_count
,
918 dp
->video_info
->link_rate
);
920 dev_err(dp
->dev
, "unable to do link train\n");
924 exynos_dp_enable_scramble(dp
, 1);
925 exynos_dp_enable_rx_to_enhanced_mode(dp
, 1);
926 exynos_dp_enable_enhanced_mode(dp
, 1);
928 exynos_dp_set_lane_count(dp
, dp
->video_info
->lane_count
);
929 exynos_dp_set_link_bandwidth(dp
, dp
->video_info
->link_rate
);
931 exynos_dp_init_video(dp
);
932 ret
= exynos_dp_config_video(dp
);
934 dev_err(dp
->dev
, "unable to config video\n");
936 /* Safe to enable the panel now */
938 if (drm_panel_enable(dp
->panel
))
939 DRM_ERROR("failed to enable the panel\n");
943 static enum drm_connector_status
exynos_dp_detect(
944 struct drm_connector
*connector
, bool force
)
946 return connector_status_connected
;
949 static void exynos_dp_connector_destroy(struct drm_connector
*connector
)
951 drm_connector_unregister(connector
);
952 drm_connector_cleanup(connector
);
955 static struct drm_connector_funcs exynos_dp_connector_funcs
= {
956 .dpms
= drm_atomic_helper_connector_dpms
,
957 .fill_modes
= drm_helper_probe_single_connector_modes
,
958 .detect
= exynos_dp_detect
,
959 .destroy
= exynos_dp_connector_destroy
,
960 .reset
= drm_atomic_helper_connector_reset
,
961 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
962 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
965 static int exynos_dp_get_modes(struct drm_connector
*connector
)
967 struct exynos_dp_device
*dp
= ctx_from_connector(connector
);
968 struct drm_display_mode
*mode
;
971 return drm_panel_get_modes(dp
->panel
);
973 mode
= drm_mode_create(connector
->dev
);
975 DRM_ERROR("failed to create a new display mode.\n");
979 drm_display_mode_from_videomode(&dp
->priv
.vm
, mode
);
980 mode
->width_mm
= dp
->priv
.width_mm
;
981 mode
->height_mm
= dp
->priv
.height_mm
;
982 connector
->display_info
.width_mm
= mode
->width_mm
;
983 connector
->display_info
.height_mm
= mode
->height_mm
;
985 mode
->type
= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
986 drm_mode_set_name(mode
);
987 drm_mode_probed_add(connector
, mode
);
992 static struct drm_encoder
*exynos_dp_best_encoder(
993 struct drm_connector
*connector
)
995 struct exynos_dp_device
*dp
= ctx_from_connector(connector
);
1000 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs
= {
1001 .get_modes
= exynos_dp_get_modes
,
1002 .best_encoder
= exynos_dp_best_encoder
,
1005 /* returns the number of bridges attached */
1006 static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device
*dp
,
1007 struct drm_encoder
*encoder
)
1011 encoder
->bridge
= dp
->bridge
;
1012 dp
->bridge
->encoder
= encoder
;
1013 ret
= drm_bridge_attach(encoder
->dev
, dp
->bridge
);
1015 DRM_ERROR("Failed to attach bridge to drm\n");
1022 static int exynos_dp_create_connector(struct exynos_drm_display
*display
,
1023 struct drm_encoder
*encoder
)
1025 struct exynos_dp_device
*dp
= display_to_dp(display
);
1026 struct drm_connector
*connector
= &dp
->connector
;
1029 dp
->encoder
= encoder
;
1031 /* Pre-empt DP connector creation if there's a bridge */
1033 ret
= exynos_drm_attach_lcd_bridge(dp
, encoder
);
1038 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1040 ret
= drm_connector_init(dp
->drm_dev
, connector
,
1041 &exynos_dp_connector_funcs
, DRM_MODE_CONNECTOR_eDP
);
1043 DRM_ERROR("Failed to initialize connector with drm\n");
1047 drm_connector_helper_add(connector
, &exynos_dp_connector_helper_funcs
);
1048 drm_connector_register(connector
);
1049 drm_mode_connector_attach_encoder(connector
, encoder
);
1052 ret
= drm_panel_attach(dp
->panel
, &dp
->connector
);
1057 static void exynos_dp_phy_init(struct exynos_dp_device
*dp
)
1060 phy_power_on(dp
->phy
);
1063 static void exynos_dp_phy_exit(struct exynos_dp_device
*dp
)
1066 phy_power_off(dp
->phy
);
1069 static void exynos_dp_poweron(struct exynos_dp_device
*dp
)
1071 struct exynos_drm_crtc
*crtc
= dp_to_crtc(dp
);
1073 if (dp
->dpms_mode
== DRM_MODE_DPMS_ON
)
1077 if (drm_panel_prepare(dp
->panel
)) {
1078 DRM_ERROR("failed to setup the panel\n");
1083 if (crtc
->ops
->clock_enable
)
1084 crtc
->ops
->clock_enable(dp_to_crtc(dp
), true);
1086 clk_prepare_enable(dp
->clock
);
1087 exynos_dp_phy_init(dp
);
1088 exynos_dp_init_dp(dp
);
1089 enable_irq(dp
->irq
);
1090 exynos_dp_commit(&dp
->display
);
1093 static void exynos_dp_poweroff(struct exynos_dp_device
*dp
)
1095 struct exynos_drm_crtc
*crtc
= dp_to_crtc(dp
);
1097 if (dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1101 if (drm_panel_disable(dp
->panel
)) {
1102 DRM_ERROR("failed to disable the panel\n");
1107 disable_irq(dp
->irq
);
1108 flush_work(&dp
->hotplug_work
);
1109 exynos_dp_phy_exit(dp
);
1110 clk_disable_unprepare(dp
->clock
);
1112 if (crtc
->ops
->clock_enable
)
1113 crtc
->ops
->clock_enable(dp_to_crtc(dp
), false);
1116 if (drm_panel_unprepare(dp
->panel
))
1117 DRM_ERROR("failed to turnoff the panel\n");
1121 static void exynos_dp_dpms(struct exynos_drm_display
*display
, int mode
)
1123 struct exynos_dp_device
*dp
= display_to_dp(display
);
1126 case DRM_MODE_DPMS_ON
:
1127 exynos_dp_poweron(dp
);
1129 case DRM_MODE_DPMS_STANDBY
:
1130 case DRM_MODE_DPMS_SUSPEND
:
1131 case DRM_MODE_DPMS_OFF
:
1132 exynos_dp_poweroff(dp
);
1137 dp
->dpms_mode
= mode
;
1140 static struct exynos_drm_display_ops exynos_dp_display_ops
= {
1141 .create_connector
= exynos_dp_create_connector
,
1142 .dpms
= exynos_dp_dpms
,
1143 .commit
= exynos_dp_commit
,
1146 static struct video_info
*exynos_dp_dt_parse_pdata(struct device
*dev
)
1148 struct device_node
*dp_node
= dev
->of_node
;
1149 struct video_info
*dp_video_config
;
1151 dp_video_config
= devm_kzalloc(dev
,
1152 sizeof(*dp_video_config
), GFP_KERNEL
);
1153 if (!dp_video_config
)
1154 return ERR_PTR(-ENOMEM
);
1156 dp_video_config
->h_sync_polarity
=
1157 of_property_read_bool(dp_node
, "hsync-active-high");
1159 dp_video_config
->v_sync_polarity
=
1160 of_property_read_bool(dp_node
, "vsync-active-high");
1162 dp_video_config
->interlaced
=
1163 of_property_read_bool(dp_node
, "interlaced");
1165 if (of_property_read_u32(dp_node
, "samsung,color-space",
1166 &dp_video_config
->color_space
)) {
1167 dev_err(dev
, "failed to get color-space\n");
1168 return ERR_PTR(-EINVAL
);
1171 if (of_property_read_u32(dp_node
, "samsung,dynamic-range",
1172 &dp_video_config
->dynamic_range
)) {
1173 dev_err(dev
, "failed to get dynamic-range\n");
1174 return ERR_PTR(-EINVAL
);
1177 if (of_property_read_u32(dp_node
, "samsung,ycbcr-coeff",
1178 &dp_video_config
->ycbcr_coeff
)) {
1179 dev_err(dev
, "failed to get ycbcr-coeff\n");
1180 return ERR_PTR(-EINVAL
);
1183 if (of_property_read_u32(dp_node
, "samsung,color-depth",
1184 &dp_video_config
->color_depth
)) {
1185 dev_err(dev
, "failed to get color-depth\n");
1186 return ERR_PTR(-EINVAL
);
1189 if (of_property_read_u32(dp_node
, "samsung,link-rate",
1190 &dp_video_config
->link_rate
)) {
1191 dev_err(dev
, "failed to get link-rate\n");
1192 return ERR_PTR(-EINVAL
);
1195 if (of_property_read_u32(dp_node
, "samsung,lane-count",
1196 &dp_video_config
->lane_count
)) {
1197 dev_err(dev
, "failed to get lane-count\n");
1198 return ERR_PTR(-EINVAL
);
1201 return dp_video_config
;
1204 static int exynos_dp_dt_parse_panel(struct exynos_dp_device
*dp
)
1208 ret
= of_get_videomode(dp
->dev
->of_node
, &dp
->priv
.vm
,
1209 OF_USE_NATIVE_MODE
);
1211 DRM_ERROR("failed: of_get_videomode() : %d\n", ret
);
1217 static int exynos_dp_bind(struct device
*dev
, struct device
*master
, void *data
)
1219 struct exynos_dp_device
*dp
= dev_get_drvdata(dev
);
1220 struct platform_device
*pdev
= to_platform_device(dev
);
1221 struct drm_device
*drm_dev
= data
;
1222 struct resource
*res
;
1223 unsigned int irq_flags
;
1226 dp
->dev
= &pdev
->dev
;
1227 dp
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1229 dp
->video_info
= exynos_dp_dt_parse_pdata(&pdev
->dev
);
1230 if (IS_ERR(dp
->video_info
))
1231 return PTR_ERR(dp
->video_info
);
1233 dp
->phy
= devm_phy_get(dp
->dev
, "dp");
1234 if (IS_ERR(dp
->phy
)) {
1235 dev_err(dp
->dev
, "no DP phy configured\n");
1236 ret
= PTR_ERR(dp
->phy
);
1239 * phy itself is not enabled, so we can move forward
1240 * assigning NULL to phy pointer.
1242 if (ret
== -ENOSYS
|| ret
== -ENODEV
)
1249 if (!dp
->panel
&& !dp
->bridge
) {
1250 ret
= exynos_dp_dt_parse_panel(dp
);
1255 dp
->clock
= devm_clk_get(&pdev
->dev
, "dp");
1256 if (IS_ERR(dp
->clock
)) {
1257 dev_err(&pdev
->dev
, "failed to get clock\n");
1258 return PTR_ERR(dp
->clock
);
1261 clk_prepare_enable(dp
->clock
);
1263 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1265 dp
->reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1266 if (IS_ERR(dp
->reg_base
))
1267 return PTR_ERR(dp
->reg_base
);
1269 dp
->hpd_gpio
= of_get_named_gpio(dev
->of_node
, "samsung,hpd-gpio", 0);
1271 if (gpio_is_valid(dp
->hpd_gpio
)) {
1273 * Set up the hotplug GPIO from the device tree as an interrupt.
1274 * Simply specifying a different interrupt in the device tree
1275 * doesn't work since we handle hotplug rather differently when
1276 * using a GPIO. We also need the actual GPIO specifier so
1277 * that we can get the current state of the GPIO.
1279 ret
= devm_gpio_request_one(&pdev
->dev
, dp
->hpd_gpio
, GPIOF_IN
,
1282 dev_err(&pdev
->dev
, "failed to get hpd gpio\n");
1285 dp
->irq
= gpio_to_irq(dp
->hpd_gpio
);
1286 irq_flags
= IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
;
1288 dp
->hpd_gpio
= -ENODEV
;
1289 dp
->irq
= platform_get_irq(pdev
, 0);
1293 if (dp
->irq
== -ENXIO
) {
1294 dev_err(&pdev
->dev
, "failed to get irq\n");
1298 INIT_WORK(&dp
->hotplug_work
, exynos_dp_hotplug
);
1300 exynos_dp_phy_init(dp
);
1302 exynos_dp_init_dp(dp
);
1304 ret
= devm_request_irq(&pdev
->dev
, dp
->irq
, exynos_dp_irq_handler
,
1305 irq_flags
, "exynos-dp", dp
);
1307 dev_err(&pdev
->dev
, "failed to request irq\n");
1310 disable_irq(dp
->irq
);
1312 dp
->drm_dev
= drm_dev
;
1314 return exynos_drm_create_enc_conn(drm_dev
, &dp
->display
);
1317 static void exynos_dp_unbind(struct device
*dev
, struct device
*master
,
1320 struct exynos_dp_device
*dp
= dev_get_drvdata(dev
);
1322 exynos_dp_dpms(&dp
->display
, DRM_MODE_DPMS_OFF
);
1325 static const struct component_ops exynos_dp_ops
= {
1326 .bind
= exynos_dp_bind
,
1327 .unbind
= exynos_dp_unbind
,
1330 static int exynos_dp_probe(struct platform_device
*pdev
)
1332 struct device
*dev
= &pdev
->dev
;
1333 struct device_node
*panel_node
, *bridge_node
, *endpoint
;
1334 struct exynos_dp_device
*dp
;
1336 dp
= devm_kzalloc(&pdev
->dev
, sizeof(struct exynos_dp_device
),
1341 dp
->display
.type
= EXYNOS_DISPLAY_TYPE_LCD
;
1342 dp
->display
.ops
= &exynos_dp_display_ops
;
1343 platform_set_drvdata(pdev
, dp
);
1345 panel_node
= of_parse_phandle(dev
->of_node
, "panel", 0);
1347 dp
->panel
= of_drm_find_panel(panel_node
);
1348 of_node_put(panel_node
);
1350 return -EPROBE_DEFER
;
1353 endpoint
= of_graph_get_next_endpoint(dev
->of_node
, NULL
);
1355 bridge_node
= of_graph_get_remote_port_parent(endpoint
);
1357 dp
->bridge
= of_drm_find_bridge(bridge_node
);
1358 of_node_put(bridge_node
);
1360 return -EPROBE_DEFER
;
1362 return -EPROBE_DEFER
;
1365 return component_add(&pdev
->dev
, &exynos_dp_ops
);
1368 static int exynos_dp_remove(struct platform_device
*pdev
)
1370 component_del(&pdev
->dev
, &exynos_dp_ops
);
1375 #ifdef CONFIG_PM_SLEEP
1376 static int exynos_dp_suspend(struct device
*dev
)
1378 struct exynos_dp_device
*dp
= dev_get_drvdata(dev
);
1380 exynos_dp_dpms(&dp
->display
, DRM_MODE_DPMS_OFF
);
1384 static int exynos_dp_resume(struct device
*dev
)
1386 struct exynos_dp_device
*dp
= dev_get_drvdata(dev
);
1388 exynos_dp_dpms(&dp
->display
, DRM_MODE_DPMS_ON
);
1393 static const struct dev_pm_ops exynos_dp_pm_ops
= {
1394 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend
, exynos_dp_resume
)
1397 static const struct of_device_id exynos_dp_match
[] = {
1398 { .compatible
= "samsung,exynos5-dp" },
1401 MODULE_DEVICE_TABLE(of
, exynos_dp_match
);
1403 struct platform_driver dp_driver
= {
1404 .probe
= exynos_dp_probe
,
1405 .remove
= exynos_dp_remove
,
1407 .name
= "exynos-dp",
1408 .owner
= THIS_MODULE
,
1409 .pm
= &exynos_dp_pm_ops
,
1410 .of_match_table
= exynos_dp_match
,
1414 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1415 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1416 MODULE_LICENSE("GPL v2");