2 * Header file for Samsung DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef _EXYNOS_DP_CORE_H
14 #define _EXYNOS_DP_CORE_H
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_dp_helper.h>
18 #include <drm/exynos_drm.h>
20 #include "exynos_drm_drv.h"
22 #define DP_TIMEOUT_LOOP_COUNT 100
27 LINK_RATE_1_62GBPS
= 0x06,
28 LINK_RATE_2_70GBPS
= 0x0a
31 enum link_lane_count_type
{
37 enum link_training_state
{
45 enum voltage_swing_level
{
52 enum pre_emphasis_level
{
80 enum color_coefficient
{
95 enum clock_recovery_m_value_type
{
100 enum video_timing_recognition_type
{
101 VIDEO_TIMING_FROM_CAPTURE
,
102 VIDEO_TIMING_FROM_REGISTER
105 enum analog_power_block
{
116 DP_IRQ_TYPE_HP_CABLE_IN
,
117 DP_IRQ_TYPE_HP_CABLE_OUT
,
118 DP_IRQ_TYPE_HP_CHANGE
,
125 bool h_sync_polarity
;
126 bool v_sync_polarity
;
129 enum color_space color_space
;
130 enum dynamic_range dynamic_range
;
131 enum color_coefficient ycbcr_coeff
;
132 enum color_depth color_depth
;
134 enum link_rate_type link_rate
;
135 enum link_lane_count_type lane_count
;
146 enum link_training_state lt_state
;
149 struct exynos_dp_device
{
150 struct exynos_drm_display display
;
152 struct drm_device
*drm_dev
;
153 struct drm_connector connector
;
154 struct drm_encoder
*encoder
;
155 struct drm_panel
*panel
;
156 struct drm_bridge
*bridge
;
159 void __iomem
*reg_base
;
161 struct video_info
*video_info
;
162 struct link_train link_train
;
163 struct work_struct hotplug_work
;
168 struct exynos_drm_panel_info priv
;
171 /* exynos_dp_reg.c */
172 void exynos_dp_enable_video_mute(struct exynos_dp_device
*dp
, bool enable
);
173 void exynos_dp_stop_video(struct exynos_dp_device
*dp
);
174 void exynos_dp_lane_swap(struct exynos_dp_device
*dp
, bool enable
);
175 void exynos_dp_init_analog_param(struct exynos_dp_device
*dp
);
176 void exynos_dp_init_interrupt(struct exynos_dp_device
*dp
);
177 void exynos_dp_reset(struct exynos_dp_device
*dp
);
178 void exynos_dp_swreset(struct exynos_dp_device
*dp
);
179 void exynos_dp_config_interrupt(struct exynos_dp_device
*dp
);
180 enum pll_status
exynos_dp_get_pll_lock_status(struct exynos_dp_device
*dp
);
181 void exynos_dp_set_pll_power_down(struct exynos_dp_device
*dp
, bool enable
);
182 void exynos_dp_set_analog_power_down(struct exynos_dp_device
*dp
,
183 enum analog_power_block block
,
185 void exynos_dp_init_analog_func(struct exynos_dp_device
*dp
);
186 void exynos_dp_init_hpd(struct exynos_dp_device
*dp
);
187 enum dp_irq_type
exynos_dp_get_irq_type(struct exynos_dp_device
*dp
);
188 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device
*dp
);
189 void exynos_dp_reset_aux(struct exynos_dp_device
*dp
);
190 void exynos_dp_init_aux(struct exynos_dp_device
*dp
);
191 int exynos_dp_get_plug_in_status(struct exynos_dp_device
*dp
);
192 void exynos_dp_enable_sw_function(struct exynos_dp_device
*dp
);
193 int exynos_dp_start_aux_transaction(struct exynos_dp_device
*dp
);
194 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device
*dp
,
195 unsigned int reg_addr
,
197 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device
*dp
,
198 unsigned int reg_addr
,
199 unsigned char *data
);
200 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device
*dp
,
201 unsigned int reg_addr
,
203 unsigned char data
[]);
204 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device
*dp
,
205 unsigned int reg_addr
,
207 unsigned char data
[]);
208 int exynos_dp_select_i2c_device(struct exynos_dp_device
*dp
,
209 unsigned int device_addr
,
210 unsigned int reg_addr
);
211 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device
*dp
,
212 unsigned int device_addr
,
213 unsigned int reg_addr
,
215 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device
*dp
,
216 unsigned int device_addr
,
217 unsigned int reg_addr
,
219 unsigned char edid
[]);
220 void exynos_dp_set_link_bandwidth(struct exynos_dp_device
*dp
, u32 bwtype
);
221 void exynos_dp_get_link_bandwidth(struct exynos_dp_device
*dp
, u32
*bwtype
);
222 void exynos_dp_set_lane_count(struct exynos_dp_device
*dp
, u32 count
);
223 void exynos_dp_get_lane_count(struct exynos_dp_device
*dp
, u32
*count
);
224 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device
*dp
, bool enable
);
225 void exynos_dp_set_training_pattern(struct exynos_dp_device
*dp
,
226 enum pattern_set pattern
);
227 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device
*dp
, u32 level
);
228 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device
*dp
, u32 level
);
229 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device
*dp
, u32 level
);
230 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device
*dp
, u32 level
);
231 void exynos_dp_set_lane0_link_training(struct exynos_dp_device
*dp
,
233 void exynos_dp_set_lane1_link_training(struct exynos_dp_device
*dp
,
235 void exynos_dp_set_lane2_link_training(struct exynos_dp_device
*dp
,
237 void exynos_dp_set_lane3_link_training(struct exynos_dp_device
*dp
,
239 u32
exynos_dp_get_lane0_link_training(struct exynos_dp_device
*dp
);
240 u32
exynos_dp_get_lane1_link_training(struct exynos_dp_device
*dp
);
241 u32
exynos_dp_get_lane2_link_training(struct exynos_dp_device
*dp
);
242 u32
exynos_dp_get_lane3_link_training(struct exynos_dp_device
*dp
);
243 void exynos_dp_reset_macro(struct exynos_dp_device
*dp
);
244 void exynos_dp_init_video(struct exynos_dp_device
*dp
);
246 void exynos_dp_set_video_color_format(struct exynos_dp_device
*dp
);
247 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device
*dp
);
248 void exynos_dp_set_video_cr_mn(struct exynos_dp_device
*dp
,
249 enum clock_recovery_m_value_type type
,
252 void exynos_dp_set_video_timing_mode(struct exynos_dp_device
*dp
, u32 type
);
253 void exynos_dp_enable_video_master(struct exynos_dp_device
*dp
, bool enable
);
254 void exynos_dp_start_video(struct exynos_dp_device
*dp
);
255 int exynos_dp_is_video_stream_on(struct exynos_dp_device
*dp
);
256 void exynos_dp_config_video_slave_mode(struct exynos_dp_device
*dp
);
257 void exynos_dp_enable_scrambling(struct exynos_dp_device
*dp
);
258 void exynos_dp_disable_scrambling(struct exynos_dp_device
*dp
);
260 /* I2C EDID Chip ID, Slave Address */
261 #define I2C_EDID_DEVICE_ADDR 0x50
262 #define I2C_E_EDID_DEVICE_ADDR 0x30
264 #define EDID_BLOCK_LENGTH 0x80
265 #define EDID_HEADER_PATTERN 0x00
266 #define EDID_EXTENSION_FLAG 0x7e
267 #define EDID_CHECKSUM 0x7f
269 /* DP_MAX_LANE_COUNT */
270 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
271 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
273 /* DP_LANE_COUNT_SET */
274 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
276 /* DP_TRAINING_LANE0_SET */
277 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
278 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
279 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
280 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
282 #endif /* _EXYNOS_DP_CORE_H */