1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
21 **************************************************************************/
28 #include "psb_intel_reg.h"
31 #include "mdfld_output.h"
38 psb_pipestat(int pipe
)
50 mid_pipe_event(int pipe
)
53 return _PSB_PIPEA_EVENT_FLAG
;
55 return _MDFLD_PIPEB_EVENT_FLAG
;
57 return _MDFLD_PIPEC_EVENT_FLAG
;
62 mid_pipe_vsync(int pipe
)
65 return _PSB_VSYNC_PIPEA_FLAG
;
67 return _PSB_VSYNC_PIPEB_FLAG
;
69 return _MDFLD_PIPEC_VBLANK_FLAG
;
74 mid_pipeconf(int pipe
)
86 psb_enable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
)
88 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
89 u32 reg
= psb_pipestat(pipe
);
90 dev_priv
->pipestat
[pipe
] |= mask
;
91 /* Enable the interrupt, clear any pending status */
92 if (gma_power_begin(dev_priv
->dev
, false)) {
93 u32 writeVal
= PSB_RVDC32(reg
);
94 writeVal
|= (mask
| (mask
>> 16));
95 PSB_WVDC32(writeVal
, reg
);
96 (void) PSB_RVDC32(reg
);
97 gma_power_end(dev_priv
->dev
);
103 psb_disable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
)
105 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
106 u32 reg
= psb_pipestat(pipe
);
107 dev_priv
->pipestat
[pipe
] &= ~mask
;
108 if (gma_power_begin(dev_priv
->dev
, false)) {
109 u32 writeVal
= PSB_RVDC32(reg
);
111 PSB_WVDC32(writeVal
, reg
);
112 (void) PSB_RVDC32(reg
);
113 gma_power_end(dev_priv
->dev
);
118 static void mid_enable_pipe_event(struct drm_psb_private
*dev_priv
, int pipe
)
120 if (gma_power_begin(dev_priv
->dev
, false)) {
121 u32 pipe_event
= mid_pipe_event(pipe
);
122 dev_priv
->vdc_irq_mask
|= pipe_event
;
123 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
124 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
125 gma_power_end(dev_priv
->dev
);
129 static void mid_disable_pipe_event(struct drm_psb_private
*dev_priv
, int pipe
)
131 if (dev_priv
->pipestat
[pipe
] == 0) {
132 if (gma_power_begin(dev_priv
->dev
, false)) {
133 u32 pipe_event
= mid_pipe_event(pipe
);
134 dev_priv
->vdc_irq_mask
&= ~pipe_event
;
135 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
136 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
137 gma_power_end(dev_priv
->dev
);
143 * Display controller interrupt handler for pipe event.
146 static void mid_pipe_event_handler(struct drm_device
*dev
, int pipe
)
148 struct drm_psb_private
*dev_priv
=
149 (struct drm_psb_private
*) dev
->dev_private
;
151 uint32_t pipe_stat_val
= 0;
152 uint32_t pipe_stat_reg
= psb_pipestat(pipe
);
153 uint32_t pipe_enable
= dev_priv
->pipestat
[pipe
];
154 uint32_t pipe_status
= dev_priv
->pipestat
[pipe
] >> 16;
158 spin_lock(&dev_priv
->irqmask_lock
);
160 pipe_stat_val
= PSB_RVDC32(pipe_stat_reg
);
161 pipe_stat_val
&= pipe_enable
| pipe_status
;
162 pipe_stat_val
&= pipe_stat_val
>> 16;
164 spin_unlock(&dev_priv
->irqmask_lock
);
166 /* Clear the 2nd level interrupt status bits
167 * Sometimes the bits are very sticky so we repeat until they unstick */
168 for (i
= 0; i
< 0xffff; i
++) {
169 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg
), pipe_stat_reg
);
170 pipe_clear
= PSB_RVDC32(pipe_stat_reg
) & pipe_status
;
178 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
179 __func__
, pipe
, PSB_RVDC32(pipe_stat_reg
));
181 if (pipe_stat_val
& PIPE_VBLANK_STATUS
)
182 drm_handle_vblank(dev
, pipe
);
184 if (pipe_stat_val
& PIPE_TE_STATUS
)
185 drm_handle_vblank(dev
, pipe
);
189 * Display controller interrupt handler.
191 static void psb_vdc_interrupt(struct drm_device
*dev
, uint32_t vdc_stat
)
193 if (vdc_stat
& _PSB_IRQ_ASLE
)
194 psb_intel_opregion_asle_intr(dev
);
196 if (vdc_stat
& _PSB_VSYNC_PIPEA_FLAG
)
197 mid_pipe_event_handler(dev
, 0);
199 if (vdc_stat
& _PSB_VSYNC_PIPEB_FLAG
)
200 mid_pipe_event_handler(dev
, 1);
204 * SGX interrupt handler
206 static void psb_sgx_interrupt(struct drm_device
*dev
, u32 stat_1
, u32 stat_2
)
208 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
212 if (stat_1
& _PSB_CE_TWOD_COMPLETE
)
213 val
= PSB_RSGX32(PSB_CR_2D_BLIT_STATUS
);
215 if (stat_2
& _PSB_CE2_BIF_REQUESTER_FAULT
) {
216 val
= PSB_RSGX32(PSB_CR_BIF_INT_STAT
);
217 addr
= PSB_RSGX32(PSB_CR_BIF_FAULT
);
219 if (val
& _PSB_CBI_STAT_PF_N_RW
)
220 DRM_ERROR("SGX MMU page fault:");
222 DRM_ERROR("SGX MMU read / write protection fault:");
224 if (val
& _PSB_CBI_STAT_FAULT_CACHE
)
225 DRM_ERROR("\tCache requestor");
226 if (val
& _PSB_CBI_STAT_FAULT_TA
)
227 DRM_ERROR("\tTA requestor");
228 if (val
& _PSB_CBI_STAT_FAULT_VDM
)
229 DRM_ERROR("\tVDM requestor");
230 if (val
& _PSB_CBI_STAT_FAULT_2D
)
231 DRM_ERROR("\t2D requestor");
232 if (val
& _PSB_CBI_STAT_FAULT_PBE
)
233 DRM_ERROR("\tPBE requestor");
234 if (val
& _PSB_CBI_STAT_FAULT_TSP
)
235 DRM_ERROR("\tTSP requestor");
236 if (val
& _PSB_CBI_STAT_FAULT_ISP
)
237 DRM_ERROR("\tISP requestor");
238 if (val
& _PSB_CBI_STAT_FAULT_USSEPDS
)
239 DRM_ERROR("\tUSSEPDS requestor");
240 if (val
& _PSB_CBI_STAT_FAULT_HOST
)
241 DRM_ERROR("\tHost requestor");
243 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
250 PSB_WSGX32(stat_1
, PSB_CR_EVENT_HOST_CLEAR
);
251 PSB_WSGX32(stat_2
, PSB_CR_EVENT_HOST_CLEAR2
);
252 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2
);
255 irqreturn_t
psb_irq_handler(int irq
, void *arg
)
257 struct drm_device
*dev
= arg
;
258 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
259 uint32_t vdc_stat
, dsp_int
= 0, sgx_int
= 0, hotplug_int
= 0;
260 u32 sgx_stat_1
, sgx_stat_2
;
263 spin_lock(&dev_priv
->irqmask_lock
);
265 vdc_stat
= PSB_RVDC32(PSB_INT_IDENTITY_R
);
267 if (vdc_stat
& (_PSB_PIPE_EVENT_FLAG
|_PSB_IRQ_ASLE
))
270 /* FIXME: Handle Medfield
271 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
275 if (vdc_stat
& _PSB_IRQ_SGX_FLAG
)
277 if (vdc_stat
& _PSB_IRQ_DISP_HOTSYNC
)
280 vdc_stat
&= dev_priv
->vdc_irq_mask
;
281 spin_unlock(&dev_priv
->irqmask_lock
);
283 if (dsp_int
&& gma_power_is_on(dev
)) {
284 psb_vdc_interrupt(dev
, vdc_stat
);
289 sgx_stat_1
= PSB_RSGX32(PSB_CR_EVENT_STATUS
);
290 sgx_stat_2
= PSB_RSGX32(PSB_CR_EVENT_STATUS2
);
291 psb_sgx_interrupt(dev
, sgx_stat_1
, sgx_stat_2
);
295 /* Note: this bit has other meanings on some devices, so we will
296 need to address that later if it ever matters */
297 if (hotplug_int
&& dev_priv
->ops
->hotplug
) {
298 handled
= dev_priv
->ops
->hotplug(dev
);
299 REG_WRITE(PORT_HOTPLUG_STAT
, REG_READ(PORT_HOTPLUG_STAT
));
302 PSB_WVDC32(vdc_stat
, PSB_INT_IDENTITY_R
);
303 (void) PSB_RVDC32(PSB_INT_IDENTITY_R
);
312 void psb_irq_preinstall(struct drm_device
*dev
)
314 struct drm_psb_private
*dev_priv
=
315 (struct drm_psb_private
*) dev
->dev_private
;
316 unsigned long irqflags
;
318 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
320 if (gma_power_is_on(dev
)) {
321 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
322 PSB_WVDC32(0x00000000, PSB_INT_MASK_R
);
323 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R
);
324 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE
);
325 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE
);
327 if (dev
->vblank
[0].enabled
)
328 dev_priv
->vdc_irq_mask
|= _PSB_VSYNC_PIPEA_FLAG
;
329 if (dev
->vblank
[1].enabled
)
330 dev_priv
->vdc_irq_mask
|= _PSB_VSYNC_PIPEB_FLAG
;
332 /* FIXME: Handle Medfield irq mask
333 if (dev->vblank[1].enabled)
334 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
335 if (dev->vblank[2].enabled)
336 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
339 /* Revisit this area - want per device masks ? */
340 if (dev_priv
->ops
->hotplug
)
341 dev_priv
->vdc_irq_mask
|= _PSB_IRQ_DISP_HOTSYNC
;
342 dev_priv
->vdc_irq_mask
|= _PSB_IRQ_ASLE
| _PSB_IRQ_SGX_FLAG
;
344 /* This register is safe even if display island is off */
345 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
346 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
349 int psb_irq_postinstall(struct drm_device
*dev
)
351 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
352 unsigned long irqflags
;
354 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
356 /* Enable 2D and MMU fault interrupts */
357 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT
, PSB_CR_EVENT_HOST_ENABLE2
);
358 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE
, PSB_CR_EVENT_HOST_ENABLE
);
359 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE
); /* Post */
361 /* This register is safe even if display island is off */
362 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
363 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
365 if (dev
->vblank
[0].enabled
)
366 psb_enable_pipestat(dev_priv
, 0, PIPE_VBLANK_INTERRUPT_ENABLE
);
368 psb_disable_pipestat(dev_priv
, 0, PIPE_VBLANK_INTERRUPT_ENABLE
);
370 if (dev
->vblank
[1].enabled
)
371 psb_enable_pipestat(dev_priv
, 1, PIPE_VBLANK_INTERRUPT_ENABLE
);
373 psb_disable_pipestat(dev_priv
, 1, PIPE_VBLANK_INTERRUPT_ENABLE
);
375 if (dev
->vblank
[2].enabled
)
376 psb_enable_pipestat(dev_priv
, 2, PIPE_VBLANK_INTERRUPT_ENABLE
);
378 psb_disable_pipestat(dev_priv
, 2, PIPE_VBLANK_INTERRUPT_ENABLE
);
380 if (dev_priv
->ops
->hotplug_enable
)
381 dev_priv
->ops
->hotplug_enable(dev
, true);
383 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
387 void psb_irq_uninstall(struct drm_device
*dev
)
389 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
390 unsigned long irqflags
;
392 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
394 if (dev_priv
->ops
->hotplug_enable
)
395 dev_priv
->ops
->hotplug_enable(dev
, false);
397 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
399 if (dev
->vblank
[0].enabled
)
400 psb_disable_pipestat(dev_priv
, 0, PIPE_VBLANK_INTERRUPT_ENABLE
);
402 if (dev
->vblank
[1].enabled
)
403 psb_disable_pipestat(dev_priv
, 1, PIPE_VBLANK_INTERRUPT_ENABLE
);
405 if (dev
->vblank
[2].enabled
)
406 psb_disable_pipestat(dev_priv
, 2, PIPE_VBLANK_INTERRUPT_ENABLE
);
408 dev_priv
->vdc_irq_mask
&= _PSB_IRQ_SGX_FLAG
|
409 _PSB_IRQ_MSVDX_FLAG
|
412 /* These two registers are safe even if display island is off */
413 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
414 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
418 /* This register is safe even if display island is off */
419 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R
), PSB_INT_IDENTITY_R
);
420 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
423 void psb_irq_turn_on_dpst(struct drm_device
*dev
)
425 struct drm_psb_private
*dev_priv
=
426 (struct drm_psb_private
*) dev
->dev_private
;
430 if (gma_power_begin(dev
, false)) {
431 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL
);
432 hist_reg
= PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL
);
433 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL
);
434 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
436 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC
);
437 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
438 PSB_WVDC32(pwm_reg
| PWM_PHASEIN_ENABLE
439 | PWM_PHASEIN_INT_ENABLE
,
441 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
443 psb_enable_pipestat(dev_priv
, 0, PIPE_DPST_EVENT_ENABLE
);
445 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
446 PSB_WVDC32(hist_reg
| HISTOGRAM_INT_CTRL_CLEAR
,
447 HISTOGRAM_INT_CONTROL
);
448 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
449 PSB_WVDC32(pwm_reg
| 0x80010100 | PWM_PHASEIN_ENABLE
,
456 int psb_irq_enable_dpst(struct drm_device
*dev
)
458 struct drm_psb_private
*dev_priv
=
459 (struct drm_psb_private
*) dev
->dev_private
;
460 unsigned long irqflags
;
462 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
465 mid_enable_pipe_event(dev_priv
, 0);
466 psb_irq_turn_on_dpst(dev
);
468 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
472 void psb_irq_turn_off_dpst(struct drm_device
*dev
)
474 struct drm_psb_private
*dev_priv
=
475 (struct drm_psb_private
*) dev
->dev_private
;
479 if (gma_power_begin(dev
, false)) {
480 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL
);
481 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
483 psb_disable_pipestat(dev_priv
, 0, PIPE_DPST_EVENT_ENABLE
);
485 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
486 PSB_WVDC32(pwm_reg
& ~PWM_PHASEIN_INT_ENABLE
,
488 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
494 int psb_irq_disable_dpst(struct drm_device
*dev
)
496 struct drm_psb_private
*dev_priv
=
497 (struct drm_psb_private
*) dev
->dev_private
;
498 unsigned long irqflags
;
500 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
502 mid_disable_pipe_event(dev_priv
, 0);
503 psb_irq_turn_off_dpst(dev
);
505 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
511 * It is used to enable VBLANK interrupt
513 int psb_enable_vblank(struct drm_device
*dev
, int pipe
)
515 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
516 unsigned long irqflags
;
517 uint32_t reg_val
= 0;
518 uint32_t pipeconf_reg
= mid_pipeconf(pipe
);
520 /* Medfield is different - we should perhaps extract out vblank
521 and blacklight etc ops */
523 return mdfld_enable_te(dev
, pipe
);
525 if (gma_power_begin(dev
, false)) {
526 reg_val
= REG_READ(pipeconf_reg
);
530 if (!(reg_val
& PIPEACONF_ENABLE
))
533 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
536 dev_priv
->vdc_irq_mask
|= _PSB_VSYNC_PIPEA_FLAG
;
538 dev_priv
->vdc_irq_mask
|= _PSB_VSYNC_PIPEB_FLAG
;
540 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
541 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
542 psb_enable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_ENABLE
);
544 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
550 * It is used to disable VBLANK interrupt
552 void psb_disable_vblank(struct drm_device
*dev
, int pipe
)
554 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
555 unsigned long irqflags
;
558 mdfld_disable_te(dev
, pipe
);
559 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
562 dev_priv
->vdc_irq_mask
&= ~_PSB_VSYNC_PIPEA_FLAG
;
564 dev_priv
->vdc_irq_mask
&= ~_PSB_VSYNC_PIPEB_FLAG
;
566 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
567 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
568 psb_disable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_ENABLE
);
570 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
574 * It is used to enable TE interrupt
576 int mdfld_enable_te(struct drm_device
*dev
, int pipe
)
578 struct drm_psb_private
*dev_priv
=
579 (struct drm_psb_private
*) dev
->dev_private
;
580 unsigned long irqflags
;
581 uint32_t reg_val
= 0;
582 uint32_t pipeconf_reg
= mid_pipeconf(pipe
);
584 if (gma_power_begin(dev
, false)) {
585 reg_val
= REG_READ(pipeconf_reg
);
589 if (!(reg_val
& PIPEACONF_ENABLE
))
592 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
594 mid_enable_pipe_event(dev_priv
, pipe
);
595 psb_enable_pipestat(dev_priv
, pipe
, PIPE_TE_ENABLE
);
597 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
603 * It is used to disable TE interrupt
605 void mdfld_disable_te(struct drm_device
*dev
, int pipe
)
607 struct drm_psb_private
*dev_priv
=
608 (struct drm_psb_private
*) dev
->dev_private
;
609 unsigned long irqflags
;
611 if (!dev_priv
->dsr_enable
)
614 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
616 mid_disable_pipe_event(dev_priv
, pipe
);
617 psb_disable_pipestat(dev_priv
, pipe
, PIPE_TE_ENABLE
);
619 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
622 /* Called from drm generic code, passed a 'crtc', which
623 * we use as a pipe index
625 u32
psb_get_vblank_counter(struct drm_device
*dev
, int pipe
)
627 uint32_t high_frame
= PIPEAFRAMEHIGH
;
628 uint32_t low_frame
= PIPEAFRAMEPIXEL
;
629 uint32_t pipeconf_reg
= PIPEACONF
;
630 uint32_t reg_val
= 0;
631 uint32_t high1
= 0, high2
= 0, low
= 0, count
= 0;
637 high_frame
= PIPEBFRAMEHIGH
;
638 low_frame
= PIPEBFRAMEPIXEL
;
639 pipeconf_reg
= PIPEBCONF
;
642 high_frame
= PIPECFRAMEHIGH
;
643 low_frame
= PIPECFRAMEPIXEL
;
644 pipeconf_reg
= PIPECCONF
;
647 dev_err(dev
->dev
, "%s, invalid pipe.\n", __func__
);
651 if (!gma_power_begin(dev
, false))
654 reg_val
= REG_READ(pipeconf_reg
);
656 if (!(reg_val
& PIPEACONF_ENABLE
)) {
657 dev_err(dev
->dev
, "trying to get vblank count for disabled pipe %d\n",
659 goto psb_get_vblank_counter_exit
;
663 * High & low register fields aren't synchronized, so make sure
664 * we get a low value that's stable across two reads of the high
668 high1
= ((REG_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
669 PIPE_FRAME_HIGH_SHIFT
);
670 low
= ((REG_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
671 PIPE_FRAME_LOW_SHIFT
);
672 high2
= ((REG_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
673 PIPE_FRAME_HIGH_SHIFT
);
674 } while (high1
!= high2
);
676 count
= (high1
<< 8) | low
;
678 psb_get_vblank_counter_exit
: