drivers/gpu/drm/i915/dvo_ivch.c

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Minor modifications (Dithering enable):
  27  *    Thomas Richter <thor@math.tu-berlin.de>
  28  *
  29  */
  30
  31 #include "dvo.h"
  32
  33 /*
  34  * register definitions for the i82807aa.
  35  *
  36  * Documentation on this chipset can be found in datasheet #29069001 at
  37  * intel.com.
  38  */
  39
  40 /*
  41  * VCH Revision & GMBus Base Addr
  42  */
  43 #define VR00            0x00
  44 # define VR00_BASE_ADDRESS_MASK         0x007f
  45
  46 /*
  47  * Functionality Enable
  48  */
  49 #define VR01            0x01
  50
  51 /*
  52  * Enable the panel fitter
  53  */
  54 # define VR01_PANEL_FIT_ENABLE          (1 << 3)
  55 /*
  56  * Enables the LCD display.
  57  *
  58  * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
  59  */
  60 # define VR01_LCD_ENABLE                (1 << 2)
  61 /** Enables the DVO repeater. */
  62 # define VR01_DVO_BYPASS_ENABLE         (1 << 1)
  63 /** Enables the DVO clock */
  64 # define VR01_DVO_ENABLE                (1 << 0)
  65 /** Enable dithering for 18bpp panels. Not documented. */
  66 # define VR01_DITHER_ENABLE             (1 << 4)
  67
  68 /*
  69  * LCD Interface Format
  70  */
  71 #define VR10            0x10
  72 /** Enables LVDS output instead of CMOS */
  73 # define VR10_LVDS_ENABLE               (1 << 4)
  74 /** Enables 18-bit LVDS output. */
  75 # define VR10_INTERFACE_1X18            (0 << 2)
  76 /** Enables 24-bit LVDS or CMOS output */
  77 # define VR10_INTERFACE_1X24            (1 << 2)
  78 /** Enables 2x18-bit LVDS or CMOS output. */
  79 # define VR10_INTERFACE_2X18            (2 << 2)
  80 /** Enables 2x24-bit LVDS output */
  81 # define VR10_INTERFACE_2X24            (3 << 2)
  82 /** Mask that defines the depth of the pipeline */
  83 # define VR10_INTERFACE_DEPTH_MASK      (3 << 2)
  84
  85 /*
  86  * VR20 LCD Horizontal Display Size
  87  */
  88 #define VR20    0x20
  89
  90 /*
  91  * LCD Vertical Display Size
  92  */
  93 #define VR21    0x20
  94
  95 /*
  96  * Panel power down status
  97  */
  98 #define VR30            0x30
  99 /** Read only bit indicating that the panel is not in a safe poweroff state. */
 100 # define VR30_PANEL_ON                  (1 << 15)
 101
 102 #define VR40            0x40
 103 # define VR40_STALL_ENABLE              (1 << 13)
 104 # define VR40_VERTICAL_INTERP_ENABLE    (1 << 12)
 105 # define VR40_ENHANCED_PANEL_FITTING    (1 << 11)
 106 # define VR40_HORIZONTAL_INTERP_ENABLE  (1 << 10)
 107 # define VR40_AUTO_RATIO_ENABLE         (1 << 9)
 108 # define VR40_CLOCK_GATING_ENABLE       (1 << 8)
 109
 110 /*
 111  * Panel Fitting Vertical Ratio
 112  * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
 113  */
 114 #define VR41            0x41
 115
 116 /*
 117  * Panel Fitting Horizontal Ratio
 118  * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
 119  */
 120 #define VR42            0x42
 121
 122 /*
 123  * Horizontal Image Size
 124  */
 125 #define VR43            0x43
 126
 127 /* VR80 GPIO 0
 128  */
 129 #define VR80        0x80
 130 #define VR81        0x81
 131 #define VR82        0x82
 132 #define VR83        0x83
 133 #define VR84        0x84
 134 #define VR85        0x85
 135 #define VR86        0x86
 136 #define VR87        0x87
 137
 138 /* VR88 GPIO 8
 139  */
 140 #define VR88        0x88
 141
 142 /* Graphics BIOS scratch 0
 143  */
 144 #define VR8E        0x8E
 145 # define VR8E_PANEL_TYPE_MASK           (0xf << 0)
 146 # define VR8E_PANEL_INTERFACE_CMOS      (0 << 4)
 147 # define VR8E_PANEL_INTERFACE_LVDS      (1 << 4)
 148 # define VR8E_FORCE_DEFAULT_PANEL       (1 << 5)
 149
 150 /* Graphics BIOS scratch 1
 151  */
 152 #define VR8F        0x8F
 153 # define VR8F_VCH_PRESENT               (1 << 0)
 154 # define VR8F_DISPLAY_CONN              (1 << 1)
 155 # define VR8F_POWER_MASK                (0x3c)
 156 # define VR8F_POWER_POS                 (2)
 157
 158
 159 struct ivch_priv {
 160         bool quiet;
 161
 162         uint16_t width, height;
 163 };
 164
 165
 166 static void ivch_dump_regs(struct intel_dvo_device *dvo);
 167
 168 /**
 169  * Reads a register on the ivch.
 170  *
 171  * Each of the 256 registers are 16 bits long.
 172  */
 173 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
 174 {
 175         struct ivch_priv *priv = dvo->dev_priv;
 176         struct i2c_adapter *adapter = dvo->i2c_bus;
 177         u8 out_buf[1];
 178         u8 in_buf[2];
 179
 180         struct i2c_msg msgs[] = {
 181                 {
 182                         .addr = dvo->slave_addr,
 183                         .flags = I2C_M_RD,
 184                         .len = 0,
 185                 },
 186                 {
 187                         .addr = 0,
 188                         .flags = I2C_M_NOSTART,
 189                         .len = 1,
 190                         .buf = out_buf,
 191                 },
 192                 {
 193                         .addr = dvo->slave_addr,
 194                         .flags = I2C_M_RD | I2C_M_NOSTART,
 195                         .len = 2,
 196                         .buf = in_buf,
 197                 }
 198         };
 199
 200         out_buf[0] = addr;
 201
 202         if (i2c_transfer(adapter, msgs, 3) == 3) {
 203                 *data = (in_buf[1] << 8) | in_buf[0];
 204                 return true;
 205         }
 206
 207         if (!priv->quiet) {
 208                 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
 209                                 "%s:%02x.\n",
 210                           addr, adapter->name, dvo->slave_addr);
 211         }
 212         return false;
 213 }
 214
 215 /** Writes a 16-bit register on the ivch */
 216 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
 217 {
 218         struct ivch_priv *priv = dvo->dev_priv;
 219         struct i2c_adapter *adapter = dvo->i2c_bus;
 220         u8 out_buf[3];
 221         struct i2c_msg msg = {
 222                 .addr = dvo->slave_addr,
 223                 .flags = 0,
 224                 .len = 3,
 225                 .buf = out_buf,
 226         };
 227
 228         out_buf[0] = addr;
 229         out_buf[1] = data & 0xff;
 230         out_buf[2] = data >> 8;
 231
 232         if (i2c_transfer(adapter, &msg, 1) == 1)
 233                 return true;
 234
 235         if (!priv->quiet) {
 236                 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
 237                           addr, adapter->name, dvo->slave_addr);
 238         }
 239
 240         return false;
 241 }
 242
 243 /** Probes the given bus and slave address for an ivch */
 244 static bool ivch_init(struct intel_dvo_device *dvo,
 245                       struct i2c_adapter *adapter)
 246 {
 247         struct ivch_priv *priv;
 248         uint16_t temp;
 249
 250         priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
 251         if (priv == NULL)
 252                 return false;
 253
 254         dvo->i2c_bus = adapter;
 255         dvo->dev_priv = priv;
 256         priv->quiet = true;
 257
 258         if (!ivch_read(dvo, VR00, &temp))
 259                 goto out;
 260         priv->quiet = false;
 261
 262         /* Since the identification bits are probably zeroes, which doesn't seem
 263          * very unique, check that the value in the base address field matches
 264          * the address it's responding on.
 265          */
 266         if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
 267                 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
 268                           "(%d vs %d)\n",
 269                           (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
 270                 goto out;
 271         }
 272
 273         ivch_read(dvo, VR20, &priv->width);
 274         ivch_read(dvo, VR21, &priv->height);
 275
 276         return true;
 277
 278 out:
 279         kfree(priv);
 280         return false;
 281 }
 282
 283 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
 284 {
 285         return connector_status_connected;
 286 }
 287
 288 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
 289                                             struct drm_display_mode *mode)
 290 {
 291         if (mode->clock > 112000)
 292                 return MODE_CLOCK_HIGH;
 293
 294         return MODE_OK;
 295 }
 296
 297 /** Sets the power state of the panel connected to the ivch */
 298 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
 299 {
 300         int i;
 301         uint16_t vr01, vr30, backlight;
 302
 303         /* Set the new power state of the panel. */
 304         if (!ivch_read(dvo, VR01, &vr01))
 305                 return;
 306
 307         if (enable)
 308                 backlight = 1;
 309         else
 310                 backlight = 0;
 311         ivch_write(dvo, VR80, backlight);
 312
 313         if (enable)
 314                 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
 315         else
 316                 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
 317
 318         ivch_write(dvo, VR01, vr01);
 319
 320         /* Wait for the panel to make its state transition */
 321         for (i = 0; i < 100; i++) {
 322                 if (!ivch_read(dvo, VR30, &vr30))
 323                         break;
 324
 325                 if (((vr30 & VR30_PANEL_ON) != 0) == enable)
 326                         break;
 327                 udelay(1000);
 328         }
 329         /* wait some more; vch may fail to resync sometimes without this */
 330         udelay(16 * 1000);
 331 }
 332
 333 static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
 334 {
 335         uint16_t vr01;
 336
 337         /* Set the new power state of the panel. */
 338         if (!ivch_read(dvo, VR01, &vr01))
 339                 return false;
 340
 341         if (vr01 & VR01_LCD_ENABLE)
 342                 return true;
 343         else
 344                 return false;
 345 }
 346
 347 static void ivch_mode_set(struct intel_dvo_device *dvo,
 348                           struct drm_display_mode *mode,
 349                           struct drm_display_mode *adjusted_mode)
 350 {
 351         uint16_t vr40 = 0;
 352         uint16_t vr01 = 0;
 353         uint16_t vr10;
 354
 355         ivch_read(dvo, VR10, &vr10);
 356         /* Enable dithering for 18 bpp pipelines */
 357         vr10 &= VR10_INTERFACE_DEPTH_MASK;
 358         if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
 359                 vr01 = VR01_DITHER_ENABLE;
 360
 361         vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
 362                 VR40_HORIZONTAL_INTERP_ENABLE);
 363
 364         if (mode->hdisplay != adjusted_mode->hdisplay ||
 365             mode->vdisplay != adjusted_mode->vdisplay) {
 366                 uint16_t x_ratio, y_ratio;
 367
 368                 vr01 |= VR01_PANEL_FIT_ENABLE;
 369                 vr40 |= VR40_CLOCK_GATING_ENABLE | VR40_ENHANCED_PANEL_FITTING;
 370                 x_ratio = (((mode->hdisplay - 1) << 16) /
 371                            (adjusted_mode->hdisplay - 1)) >> 2;
 372                 y_ratio = (((mode->vdisplay - 1) << 16) /
 373                            (adjusted_mode->vdisplay - 1)) >> 2;
 374                 ivch_write(dvo, VR42, x_ratio);
 375                 ivch_write(dvo, VR41, y_ratio);
 376         } else {
 377                 vr01 &= ~VR01_PANEL_FIT_ENABLE;
 378                 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
 379         }
 380         vr40 &= ~VR40_AUTO_RATIO_ENABLE;
 381
 382         ivch_write(dvo, VR01, vr01);
 383         ivch_write(dvo, VR40, vr40);
 384
 385         ivch_dump_regs(dvo);
 386 }
 387
 388 static void ivch_dump_regs(struct intel_dvo_device *dvo)
 389 {
 390         uint16_t val;
 391
 392         ivch_read(dvo, VR00, &val);
 393         DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
 394         ivch_read(dvo, VR01, &val);
 395         DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
 396         ivch_read(dvo, VR10, &val);
 397         DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
 398         ivch_read(dvo, VR30, &val);
 399         DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
 400         ivch_read(dvo, VR40, &val);
 401         DRM_DEBUG_KMS("VR40: 0x%04x\n", val);
 402
 403         /* GPIO registers */
 404         ivch_read(dvo, VR80, &val);
 405         DRM_DEBUG_KMS("VR80: 0x%04x\n", val);
 406         ivch_read(dvo, VR81, &val);
 407         DRM_DEBUG_KMS("VR81: 0x%04x\n", val);
 408         ivch_read(dvo, VR82, &val);
 409         DRM_DEBUG_KMS("VR82: 0x%04x\n", val);
 410         ivch_read(dvo, VR83, &val);
 411         DRM_DEBUG_KMS("VR83: 0x%04x\n", val);
 412         ivch_read(dvo, VR84, &val);
 413         DRM_DEBUG_KMS("VR84: 0x%04x\n", val);
 414         ivch_read(dvo, VR85, &val);
 415         DRM_DEBUG_KMS("VR85: 0x%04x\n", val);
 416         ivch_read(dvo, VR86, &val);
 417         DRM_DEBUG_KMS("VR86: 0x%04x\n", val);
 418         ivch_read(dvo, VR87, &val);
 419         DRM_DEBUG_KMS("VR87: 0x%04x\n", val);
 420         ivch_read(dvo, VR88, &val);
 421         DRM_DEBUG_KMS("VR88: 0x%04x\n", val);
 422
 423         /* Scratch register 0 - AIM Panel type */
 424         ivch_read(dvo, VR8E, &val);
 425         DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);
 426
 427         /* Scratch register 1 - Status register */
 428         ivch_read(dvo, VR8F, &val);
 429         DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);
 430 }
 431
 432 static void ivch_destroy(struct intel_dvo_device *dvo)
 433 {
 434         struct ivch_priv *priv = dvo->dev_priv;
 435
 436         if (priv) {
 437                 kfree(priv);
 438                 dvo->dev_priv = NULL;
 439         }
 440 }
 441
 442 struct intel_dvo_dev_ops ivch_ops = {
 443         .init = ivch_init,
 444         .dpms = ivch_dpms,
 445         .get_hw_state = ivch_get_hw_state,
 446         .mode_valid = ivch_mode_valid,
 447         .mode_set = ivch_mode_set,
 448         .detect = ivch_detect,
 449         .dump_regs = ivch_dump_regs,
 450         .destroy = ivch_destroy,
 451 };