drivers/gpu/drm/i915/intel_bios.h

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #ifndef _I830_BIOS_H_
  29 #define _I830_BIOS_H_
  30
  31 #include <drm/drmP.h>
  32
  33 struct vbt_header {
  34         u8 signature[20];               /**< Always starts with 'VBT$' */
  35         u16 version;                    /**< decimal */
  36         u16 header_size;                /**< in bytes */
  37         u16 vbt_size;                   /**< in bytes */
  38         u8 vbt_checksum;
  39         u8 reserved0;
  40         u32 bdb_offset;                 /**< from beginning of VBT */
  41         u32 aim_offset[4];              /**< from beginning of VBT */
  42 } __packed;
  43
  44 struct bdb_header {
  45         u8 signature[16];               /**< Always 'BIOS_DATA_BLOCK' */
  46         u16 version;                    /**< decimal */
  47         u16 header_size;                /**< in bytes */
  48         u16 bdb_size;                   /**< in bytes */
  49 } __packed;
  50
  51 /* strictly speaking, this is a "skip" block, but it has interesting info */
  52 struct vbios_data {
  53         u8 type; /* 0 == desktop, 1 == mobile */
  54         u8 relstage;
  55         u8 chipset;
  56         u8 lvds_present:1;
  57         u8 tv_present:1;
  58         u8 rsvd2:6; /* finish byte */
  59         u8 rsvd3[4];
  60         u8 signon[155];
  61         u8 copyright[61];
  62         u16 code_segment;
  63         u8 dos_boot_mode;
  64         u8 bandwidth_percent;
  65         u8 rsvd4; /* popup memory size */
  66         u8 resize_pci_bios;
  67         u8 rsvd5; /* is crt already on ddc2 */
  68 } __packed;
  69
  70 /*
  71  * There are several types of BIOS data blocks (BDBs), each block has
  72  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  73  * Known types are listed below.
  74  */
  75 #define BDB_GENERAL_FEATURES      1
  76 #define BDB_GENERAL_DEFINITIONS   2
  77 #define BDB_OLD_TOGGLE_LIST       3
  78 #define BDB_MODE_SUPPORT_LIST     4
  79 #define BDB_GENERIC_MODE_TABLE    5
  80 #define BDB_EXT_MMIO_REGS         6
  81 #define BDB_SWF_IO                7
  82 #define BDB_SWF_MMIO              8
  83 #define BDB_PSR                   9
  84 #define BDB_MODE_REMOVAL_TABLE   10
  85 #define BDB_CHILD_DEVICE_TABLE   11
  86 #define BDB_DRIVER_FEATURES      12
  87 #define BDB_DRIVER_PERSISTENCE   13
  88 #define BDB_EXT_TABLE_PTRS       14
  89 #define BDB_DOT_CLOCK_OVERRIDE   15
  90 #define BDB_DISPLAY_SELECT       16
  91 /* 17 rsvd */
  92 #define BDB_DRIVER_ROTATION      18
  93 #define BDB_DISPLAY_REMOVE       19
  94 #define BDB_OEM_CUSTOM           20
  95 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
  96 #define BDB_SDVO_LVDS_OPTIONS    22
  97 #define BDB_SDVO_PANEL_DTDS      23
  98 #define BDB_SDVO_LVDS_PNP_IDS    24
  99 #define BDB_SDVO_LVDS_POWER_SEQ  25
 100 #define BDB_TV_OPTIONS           26
 101 #define BDB_EDP                  27
 102 #define BDB_LVDS_OPTIONS         40
 103 #define BDB_LVDS_LFP_DATA_PTRS   41
 104 #define BDB_LVDS_LFP_DATA        42
 105 #define BDB_LVDS_BACKLIGHT       43
 106 #define BDB_LVDS_POWER           44
 107 #define BDB_MIPI_CONFIG          52
 108 #define BDB_MIPI_SEQUENCE        53
 109 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 110
 111 struct bdb_general_features {
 112         /* bits 1 */
 113         u8 panel_fitting:2;
 114         u8 flexaim:1;
 115         u8 msg_enable:1;
 116         u8 clear_screen:3;
 117         u8 color_flip:1;
 118
 119         /* bits 2 */
 120         u8 download_ext_vbt:1;
 121         u8 enable_ssc:1;
 122         u8 ssc_freq:1;
 123         u8 enable_lfp_on_override:1;
 124         u8 disable_ssc_ddt:1;
 125         u8 rsvd7:1;
 126         u8 display_clock_mode:1;
 127         u8 rsvd8:1; /* finish byte */
 128
 129         /* bits 3 */
 130         u8 disable_smooth_vision:1;
 131         u8 single_dvi:1;
 132         u8 rsvd9:1;
 133         u8 fdi_rx_polarity_inverted:1;
 134         u8 rsvd10:4; /* finish byte */
 135
 136         /* bits 4 */
 137         u8 legacy_monitor_detect;
 138
 139         /* bits 5 */
 140         u8 int_crt_support:1;
 141         u8 int_tv_support:1;
 142         u8 int_efp_support:1;
 143         u8 dp_ssc_enb:1;        /* PCH attached eDP supports SSC */
 144         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 145         u8 rsvd11:3; /* finish byte */
 146 } __packed;
 147
 148 /* pre-915 */
 149 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 150 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 151 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 152 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 153
 154 /* Pre 915 */
 155 #define DEVICE_TYPE_NONE        0x00
 156 #define DEVICE_TYPE_CRT         0x01
 157 #define DEVICE_TYPE_TV          0x09
 158 #define DEVICE_TYPE_EFP         0x12
 159 #define DEVICE_TYPE_LFP         0x22
 160 /* On 915+ */
 161 #define DEVICE_TYPE_CRT_DPMS            0x6001
 162 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 163 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 164 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 165 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 166 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 167 #define DEVICE_TYPE_TV_SCART            0x0209
 168 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 169 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 170 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 171 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 172 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 173 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 174 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 175 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 176 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 177 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 178 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 179 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 180 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 181
 182 #define DEVICE_CFG_NONE         0x00
 183 #define DEVICE_CFG_12BIT_DVOB   0x01
 184 #define DEVICE_CFG_12BIT_DVOC   0x02
 185 #define DEVICE_CFG_24BIT_DVOBC  0x09
 186 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 187 #define DEVICE_CFG_DUAL_DVOB    0x11
 188 #define DEVICE_CFG_DUAL_DVOC    0x12
 189 #define DEVICE_CFG_DUAL_DVOBC   0x13
 190 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 191 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 192
 193 #define DEVICE_WIRE_NONE        0x00
 194 #define DEVICE_WIRE_DVOB        0x01
 195 #define DEVICE_WIRE_DVOC        0x02
 196 #define DEVICE_WIRE_DVOBC       0x03
 197 #define DEVICE_WIRE_DVOBB       0x05
 198 #define DEVICE_WIRE_DVOCC       0x06
 199 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 200 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 201
 202 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 203 #define DEVICE_PORT_DVOB        0x01
 204 #define DEVICE_PORT_DVOC        0x02
 205
 206 /* We used to keep this struct but without any version control. We should avoid
 207  * using it in the future, but it should be safe to keep using it in the old
 208  * code. */
 209 struct old_child_dev_config {
 210         u16 handle;
 211         u16 device_type;
 212         u8  device_id[10]; /* ascii string */
 213         u16 addin_offset;
 214         u8  dvo_port; /* See Device_PORT_* above */
 215         u8  i2c_pin;
 216         u8  slave_addr;
 217         u8  ddc_pin;
 218         u16 edid_ptr;
 219         u8  dvo_cfg; /* See DEVICE_CFG_* above */
 220         u8  dvo2_port;
 221         u8  i2c2_pin;
 222         u8  slave2_addr;
 223         u8  ddc2_pin;
 224         u8  capabilities;
 225         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
 226         u8  dvo2_wiring;
 227         u16 extended_type;
 228         u8  dvo_function;
 229 } __packed;
 230
 231 /* This one contains field offsets that are known to be common for all BDB
 232  * versions. Notice that the meaning of the contents contents may still change,
 233  * but at least the offsets are consistent. */
 234 struct common_child_dev_config {
 235         u16 handle;
 236         u16 device_type;
 237         u8 not_common1[12];
 238         u8 dvo_port;
 239         u8 not_common2[2];
 240         u8 ddc_pin;
 241         u16 edid_ptr;
 242 } __packed;
 243
 244 /* This field changes depending on the BDB version, so the most reliable way to
 245  * read it is by checking the BDB version and reading the raw pointer. */
 246 union child_device_config {
 247         /* This one is safe to be used anywhere, but the code should still check
 248          * the BDB version. */
 249         u8 raw[33];
 250         /* This one should only be kept for legacy code. */
 251         struct old_child_dev_config old;
 252         /* This one should also be safe to use anywhere, even without version
 253          * checks. */
 254         struct common_child_dev_config common;
 255 } __packed;
 256
 257 struct bdb_general_definitions {
 258         /* DDC GPIO */
 259         u8 crt_ddc_gmbus_pin;
 260
 261         /* DPMS bits */
 262         u8 dpms_acpi:1;
 263         u8 skip_boot_crt_detect:1;
 264         u8 dpms_aim:1;
 265         u8 rsvd1:5; /* finish byte */
 266
 267         /* boot device bits */
 268         u8 boot_display[2];
 269         u8 child_dev_size;
 270
 271         /*
 272          * Device info:
 273          * If TV is present, it'll be at devices[0].
 274          * LVDS will be next, either devices[0] or [1], if present.
 275          * On some platforms the number of device is 6. But could be as few as
 276          * 4 if both TV and LVDS are missing.
 277          * And the device num is related with the size of general definition
 278          * block. It is obtained by using the following formula:
 279          * number = (block_size - sizeof(bdb_general_definitions))/
 280          *           defs->child_dev_size;
 281          */
 282         uint8_t devices[0];
 283 } __packed;
 284
 285 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
 286 #define MODE_MASK               0x3
 287
 288 struct bdb_lvds_options {
 289         u8 panel_type;
 290         u8 rsvd1;
 291         /* LVDS capabilities, stored in a dword */
 292         u8 pfit_mode:2;
 293         u8 pfit_text_mode_enhanced:1;
 294         u8 pfit_gfx_mode_enhanced:1;
 295         u8 pfit_ratio_auto:1;
 296         u8 pixel_dither:1;
 297         u8 lvds_edid:1;
 298         u8 rsvd2:1;
 299         u8 rsvd4;
 300         /* LVDS Panel channel bits stored here */
 301         u32 lvds_panel_channel_bits;
 302         /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
 303         u16 ssc_bits;
 304         u16 ssc_freq;
 305         u16 ssc_ddt;
 306         /* Panel color depth defined here */
 307         u16 panel_color_depth;
 308         /* LVDS panel type bits stored here */
 309         u32 dps_panel_type_bits;
 310         /* LVDS backlight control type bits stored here */
 311         u32 blt_control_type_bits;
 312 } __packed;
 313
 314 /* LFP pointer table contains entries to the struct below */
 315 struct bdb_lvds_lfp_data_ptr {
 316         u16 fp_timing_offset; /* offsets are from start of bdb */
 317         u8 fp_table_size;
 318         u16 dvo_timing_offset;
 319         u8 dvo_table_size;
 320         u16 panel_pnp_id_offset;
 321         u8 pnp_table_size;
 322 } __packed;
 323
 324 struct bdb_lvds_lfp_data_ptrs {
 325         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 326         struct bdb_lvds_lfp_data_ptr ptr[16];
 327 } __packed;
 328
 329 /* LFP data has 3 blocks per entry */
 330 struct lvds_fp_timing {
 331         u16 x_res;
 332         u16 y_res;
 333         u32 lvds_reg;
 334         u32 lvds_reg_val;
 335         u32 pp_on_reg;
 336         u32 pp_on_reg_val;
 337         u32 pp_off_reg;
 338         u32 pp_off_reg_val;
 339         u32 pp_cycle_reg;
 340         u32 pp_cycle_reg_val;
 341         u32 pfit_reg;
 342         u32 pfit_reg_val;
 343         u16 terminator;
 344 } __packed;
 345
 346 struct lvds_dvo_timing {
 347         u16 clock;              /**< In 10khz */
 348         u8 hactive_lo;
 349         u8 hblank_lo;
 350         u8 hblank_hi:4;
 351         u8 hactive_hi:4;
 352         u8 vactive_lo;
 353         u8 vblank_lo;
 354         u8 vblank_hi:4;
 355         u8 vactive_hi:4;
 356         u8 hsync_off_lo;
 357         u8 hsync_pulse_width;
 358         u8 vsync_pulse_width:4;
 359         u8 vsync_off:4;
 360         u8 rsvd0:6;
 361         u8 hsync_off_hi:2;
 362         u8 h_image;
 363         u8 v_image;
 364         u8 max_hv;
 365         u8 h_border;
 366         u8 v_border;
 367         u8 rsvd1:3;
 368         u8 digital:2;
 369         u8 vsync_positive:1;
 370         u8 hsync_positive:1;
 371         u8 rsvd2:1;
 372 } __packed;
 373
 374 struct lvds_pnp_id {
 375         u16 mfg_name;
 376         u16 product_code;
 377         u32 serial;
 378         u8 mfg_week;
 379         u8 mfg_year;
 380 } __packed;
 381
 382 struct bdb_lvds_lfp_data_entry {
 383         struct lvds_fp_timing fp_timing;
 384         struct lvds_dvo_timing dvo_timing;
 385         struct lvds_pnp_id pnp_id;
 386 } __packed;
 387
 388 struct bdb_lvds_lfp_data {
 389         struct bdb_lvds_lfp_data_entry data[16];
 390 } __packed;
 391
 392 #define BDB_BACKLIGHT_TYPE_NONE 0
 393 #define BDB_BACKLIGHT_TYPE_PWM  2
 394
 395 struct bdb_lfp_backlight_data_entry {
 396         u8 type:2;
 397         u8 active_low_pwm:1;
 398         u8 obsolete1:5;
 399         u16 pwm_freq_hz;
 400         u8 min_brightness;
 401         u8 obsolete2;
 402         u8 obsolete3;
 403 } __packed;
 404
 405 struct bdb_lfp_backlight_data {
 406         u8 entry_size;
 407         struct bdb_lfp_backlight_data_entry data[16];
 408         u8 level[16];
 409 } __packed;
 410
 411 struct aimdb_header {
 412         char signature[16];
 413         char oem_device[20];
 414         u16 aimdb_version;
 415         u16 aimdb_header_size;
 416         u16 aimdb_size;
 417 } __packed;
 418
 419 struct aimdb_block {
 420         u8 aimdb_id;
 421         u16 aimdb_size;
 422 } __packed;
 423
 424 struct vch_panel_data {
 425         u16 fp_timing_offset;
 426         u8 fp_timing_size;
 427         u16 dvo_timing_offset;
 428         u8 dvo_timing_size;
 429         u16 text_fitting_offset;
 430         u8 text_fitting_size;
 431         u16 graphics_fitting_offset;
 432         u8 graphics_fitting_size;
 433 } __packed;
 434
 435 struct vch_bdb_22 {
 436         struct aimdb_block aimdb_block;
 437         struct vch_panel_data panels[16];
 438 } __packed;
 439
 440 struct bdb_sdvo_lvds_options {
 441         u8 panel_backlight;
 442         u8 h40_set_panel_type;
 443         u8 panel_type;
 444         u8 ssc_clk_freq;
 445         u16 als_low_trip;
 446         u16 als_high_trip;
 447         u8 sclalarcoeff_tab_row_num;
 448         u8 sclalarcoeff_tab_row_size;
 449         u8 coefficient[8];
 450         u8 panel_misc_bits_1;
 451         u8 panel_misc_bits_2;
 452         u8 panel_misc_bits_3;
 453         u8 panel_misc_bits_4;
 454 } __packed;
 455
 456
 457 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 458 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 459 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 460 #define BDB_DRIVER_FEATURE_EDP                  3
 461
 462 struct bdb_driver_features {
 463         u8 boot_dev_algorithm:1;
 464         u8 block_display_switch:1;
 465         u8 allow_display_switch:1;
 466         u8 hotplug_dvo:1;
 467         u8 dual_view_zoom:1;
 468         u8 int15h_hook:1;
 469         u8 sprite_in_clone:1;
 470         u8 primary_lfp_id:1;
 471
 472         u16 boot_mode_x;
 473         u16 boot_mode_y;
 474         u8 boot_mode_bpp;
 475         u8 boot_mode_refresh;
 476
 477         u16 enable_lfp_primary:1;
 478         u16 selective_mode_pruning:1;
 479         u16 dual_frequency:1;
 480         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 481         u16 nt_clone_support:1;
 482         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 483         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 484         u16 cui_aspect_scaling:1;
 485         u16 preserve_aspect_ratio:1;
 486         u16 sdvo_device_power_down:1;
 487         u16 crt_hotplug:1;
 488         u16 lvds_config:2;
 489         u16 tv_hotplug:1;
 490         u16 hdmi_config:2;
 491
 492         u8 static_display:1;
 493         u8 reserved2:7;
 494         u16 legacy_crt_max_x;
 495         u16 legacy_crt_max_y;
 496         u8 legacy_crt_max_refresh;
 497
 498         u8 hdmi_termination;
 499         u8 custom_vbt_version;
 500         /* Driver features data block */
 501         u16 rmpm_enabled:1;
 502         u16 s2ddt_enabled:1;
 503         u16 dpst_enabled:1;
 504         u16 bltclt_enabled:1;
 505         u16 adb_enabled:1;
 506         u16 drrs_enabled:1;
 507         u16 grs_enabled:1;
 508         u16 gpmt_enabled:1;
 509         u16 tbt_enabled:1;
 510         u16 psr_enabled:1;
 511         u16 ips_enabled:1;
 512         u16 reserved3:4;
 513         u16 pc_feature_valid:1;
 514 } __packed;
 515
 516 #define EDP_18BPP       0
 517 #define EDP_24BPP       1
 518 #define EDP_30BPP       2
 519 #define EDP_RATE_1_62   0
 520 #define EDP_RATE_2_7    1
 521 #define EDP_LANE_1      0
 522 #define EDP_LANE_2      1
 523 #define EDP_LANE_4      3
 524 #define EDP_PREEMPHASIS_NONE    0
 525 #define EDP_PREEMPHASIS_3_5dB   1
 526 #define EDP_PREEMPHASIS_6dB     2
 527 #define EDP_PREEMPHASIS_9_5dB   3
 528 #define EDP_VSWING_0_4V         0
 529 #define EDP_VSWING_0_6V         1
 530 #define EDP_VSWING_0_8V         2
 531 #define EDP_VSWING_1_2V         3
 532
 533 struct edp_power_seq {
 534         u16 t1_t3;
 535         u16 t8;
 536         u16 t9;
 537         u16 t10;
 538         u16 t11_t12;
 539 } __packed;
 540
 541 struct edp_link_params {
 542         u8 rate:4;
 543         u8 lanes:4;
 544         u8 preemphasis:4;
 545         u8 vswing:4;
 546 } __packed;
 547
 548 struct bdb_edp {
 549         struct edp_power_seq power_seqs[16];
 550         u32 color_depth;
 551         struct edp_link_params link_params[16];
 552         u32 sdrrs_msa_timing_delay;
 553
 554         /* ith bit indicates enabled/disabled for (i+1)th panel */
 555         u16 edp_s3d_feature;
 556         u16 edp_t3_optimization;
 557         u64 edp_vswing_preemph;         /* v173 */
 558 } __packed;
 559
 560 struct psr_table {
 561         /* Feature bits */
 562         u8 full_link:1;
 563         u8 require_aux_to_wakeup:1;
 564         u8 feature_bits_rsvd:6;
 565
 566         /* Wait times */
 567         u8 idle_frames:4;
 568         u8 lines_to_wait:3;
 569         u8 wait_times_rsvd:1;
 570
 571         /* TP wake up time in multiple of 100 */
 572         u16 tp1_wakeup_time;
 573         u16 tp2_tp3_wakeup_time;
 574 } __packed;
 575
 576 struct bdb_psr {
 577         struct psr_table psr_table[16];
 578 } __packed;
 579
 580 void intel_setup_bios(struct drm_device *dev);
 581 int intel_parse_bios(struct drm_device *dev);
 582
 583 /*
 584  * Driver<->VBIOS interaction occurs through scratch bits in
 585  * GR18 & SWF*.
 586  */
 587
 588 /* GR18 bits are set on display switch and hotkey events */
 589 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 590 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 591 #define   GR18_HK_NONE          (0x0<<3)
 592 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 593 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 594 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 595 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 596 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 597 #define   GR18_HK_PFIT          (0x8<<3)
 598 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 599 #define   GR18_HK_MULTIPLE      (0xc<<3)
 600 #define GR18_USER_INT_EN        (1<<2)
 601 #define GR18_A0000_FLUSH_EN     (1<<1)
 602 #define GR18_SMM_EN             (1<<0)
 603
 604 /* Set by driver, cleared by VBIOS */
 605 #define SWF00_YRES_SHIFT        16
 606 #define SWF00_XRES_SHIFT        0
 607 #define SWF00_RES_MASK          0xffff
 608
 609 /* Set by VBIOS at boot time and driver at runtime */
 610 #define SWF01_TV2_FORMAT_SHIFT  8
 611 #define SWF01_TV1_FORMAT_SHIFT  0
 612 #define SWF01_TV_FORMAT_MASK    0xffff
 613
 614 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 615 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 616 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 617 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 618 #define   SWF10_OLD_TOGGLE      0x0
 619 #define   SWF10_TOGGLE_LIST_1   0x1
 620 #define   SWF10_TOGGLE_LIST_2   0x2
 621 #define   SWF10_TOGGLE_LIST_3   0x3
 622 #define   SWF10_TOGGLE_LIST_4   0x4
 623 #define SWF10_PANNING_EN        (1<<23)
 624 #define SWF10_DRIVER_LOADED     (1<<22)
 625 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 626 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 627 #define SWF10_OVERLAY_EN        (1<<19)
 628 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 629 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 630 #define SWF10_VGA_HOLDOFF       (1<<16)
 631 #define SWF10_ACTIVE_DISP_MASK  0xffff
 632 #define   SWF10_PIPEB_LFP2      (1<<15)
 633 #define   SWF10_PIPEB_EFP2      (1<<14)
 634 #define   SWF10_PIPEB_TV2       (1<<13)
 635 #define   SWF10_PIPEB_CRT2      (1<<12)
 636 #define   SWF10_PIPEB_LFP       (1<<11)
 637 #define   SWF10_PIPEB_EFP       (1<<10)
 638 #define   SWF10_PIPEB_TV        (1<<9)
 639 #define   SWF10_PIPEB_CRT       (1<<8)
 640 #define   SWF10_PIPEA_LFP2      (1<<7)
 641 #define   SWF10_PIPEA_EFP2      (1<<6)
 642 #define   SWF10_PIPEA_TV2       (1<<5)
 643 #define   SWF10_PIPEA_CRT2      (1<<4)
 644 #define   SWF10_PIPEA_LFP       (1<<3)
 645 #define   SWF10_PIPEA_EFP       (1<<2)
 646 #define   SWF10_PIPEA_TV        (1<<1)
 647 #define   SWF10_PIPEA_CRT       (1<<0)
 648
 649 #define SWF11_MEMORY_SIZE_SHIFT 16
 650 #define SWF11_SV_TEST_EN        (1<<15)
 651 #define SWF11_IS_AGP            (1<<14)
 652 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 653 #define SWF11_DPMS_REDUCED      (1<<12)
 654 #define SWF11_IS_VBE_MODE       (1<<11)
 655 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 656 #define SWF11_DPMS_MASK         0x07
 657 #define   SWF11_DPMS_OFF        (1<<2)
 658 #define   SWF11_DPMS_SUSPEND    (1<<1)
 659 #define   SWF11_DPMS_STANDBY    (1<<0)
 660 #define   SWF11_DPMS_ON         0
 661
 662 #define SWF14_GFX_PFIT_EN       (1<<31)
 663 #define SWF14_TEXT_PFIT_EN      (1<<30)
 664 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 665 #define SWF14_POPUP_EN          (1<<28)
 666 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 667 #define SWF14_DISP_DETECT_EN    (1<<26)
 668 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 669 #define SWF14_DRIVER_STATUS     (1<<24)
 670 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 671 #define SWF14_OS_TYPE_WINNT     (1<<22)
 672 /* 21:19 rsvd */
 673 #define SWF14_PM_TYPE_MASK      0x00070000
 674 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 675 #define   SWF14_PM_ACPI         (0x3 << 16)
 676 #define   SWF14_PM_APM_12       (0x2 << 16)
 677 #define   SWF14_PM_APM_11       (0x1 << 16)
 678 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 679           /* if GR18 indicates a display switch */
 680 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 681 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 682 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 683 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 684 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 685 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 686 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 687 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 688 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 689 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 690 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 691 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 692 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 693 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 694 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 695 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 696           /* if GR18 indicates a panel fitting request */
 697 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 698           /* if GR18 indicates an APM change request */
 699 #define   SWF14_APM_HIBERNATE   0x4
 700 #define   SWF14_APM_SUSPEND     0x3
 701 #define   SWF14_APM_STANDBY     0x1
 702 #define   SWF14_APM_RESTORE     0x0
 703
 704 /* Add the device class for LFP, TV, HDMI */
 705 #define  DEVICE_TYPE_INT_LFP    0x1022
 706 #define  DEVICE_TYPE_INT_TV     0x1009
 707 #define  DEVICE_TYPE_HDMI       0x60D2
 708 #define  DEVICE_TYPE_DP         0x68C6
 709 #define  DEVICE_TYPE_eDP        0x78C6
 710
 711 #define  DEVICE_TYPE_CLASS_EXTENSION    (1 << 15)
 712 #define  DEVICE_TYPE_POWER_MANAGEMENT   (1 << 14)
 713 #define  DEVICE_TYPE_HOTPLUG_SIGNALING  (1 << 13)
 714 #define  DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
 715 #define  DEVICE_TYPE_NOT_HDMI_OUTPUT    (1 << 11)
 716 #define  DEVICE_TYPE_MIPI_OUTPUT        (1 << 10)
 717 #define  DEVICE_TYPE_COMPOSITE_OUTPUT   (1 << 9)
 718 #define  DEVICE_TYPE_DUAL_CHANNEL       (1 << 8)
 719 #define  DEVICE_TYPE_HIGH_SPEED_LINK    (1 << 6)
 720 #define  DEVICE_TYPE_LVDS_SINGALING     (1 << 5)
 721 #define  DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
 722 #define  DEVICE_TYPE_VIDEO_SIGNALING    (1 << 3)
 723 #define  DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
 724 #define  DEVICE_TYPE_DIGITAL_OUTPUT     (1 << 1)
 725 #define  DEVICE_TYPE_ANALOG_OUTPUT      (1 << 0)
 726
 727 /*
 728  * Bits we care about when checking for DEVICE_TYPE_eDP
 729  * Depending on the system, the other bits may or may not
 730  * be set for eDP outputs.
 731  */
 732 #define DEVICE_TYPE_eDP_BITS \
 733         (DEVICE_TYPE_INTERNAL_CONNECTOR | \
 734          DEVICE_TYPE_NOT_HDMI_OUTPUT | \
 735          DEVICE_TYPE_MIPI_OUTPUT | \
 736          DEVICE_TYPE_COMPOSITE_OUTPUT | \
 737          DEVICE_TYPE_DUAL_CHANNEL | \
 738          DEVICE_TYPE_LVDS_SINGALING | \
 739          DEVICE_TYPE_TMDS_DVI_SIGNALING | \
 740          DEVICE_TYPE_VIDEO_SIGNALING | \
 741          DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
 742          DEVICE_TYPE_DIGITAL_OUTPUT | \
 743          DEVICE_TYPE_ANALOG_OUTPUT)
 744
 745 /* define the DVO port for HDMI output type */
 746 #define         DVO_B           1
 747 #define         DVO_C           2
 748 #define         DVO_D           3
 749
 750 /* define the PORT for DP output type */
 751 #define         PORT_IDPB       7
 752 #define         PORT_IDPC       8
 753 #define         PORT_IDPD       9
 754
 755 /* Possible values for the "DVO Port" field for versions >= 155: */
 756 #define DVO_PORT_HDMIA  0
 757 #define DVO_PORT_HDMIB  1
 758 #define DVO_PORT_HDMIC  2
 759 #define DVO_PORT_HDMID  3
 760 #define DVO_PORT_LVDS   4
 761 #define DVO_PORT_TV     5
 762 #define DVO_PORT_CRT    6
 763 #define DVO_PORT_DPB    7
 764 #define DVO_PORT_DPC    8
 765 #define DVO_PORT_DPD    9
 766 #define DVO_PORT_DPA    10
 767 #define DVO_PORT_MIPIA  21
 768 #define DVO_PORT_MIPIB  22
 769 #define DVO_PORT_MIPIC  23
 770 #define DVO_PORT_MIPID  24
 771
 772 /* Block 52 contains MIPI Panel info
 773  * 6 such enteries will there. Index into correct
 774  * entery is based on the panel_index in #40 LFP
 775  */
 776 #define MAX_MIPI_CONFIGURATIONS 6
 777
 778 #define MIPI_DSI_UNDEFINED_PANEL_ID     0
 779 #define MIPI_DSI_GENERIC_PANEL_ID       1
 780
 781 struct mipi_config {
 782         u16 panel_id;
 783
 784         /* General Params */
 785         u32 enable_dithering:1;
 786         u32 rsvd1:1;
 787         u32 is_bridge:1;
 788
 789         u32 panel_arch_type:2;
 790         u32 is_cmd_mode:1;
 791
 792 #define NON_BURST_SYNC_PULSE    0x1
 793 #define NON_BURST_SYNC_EVENTS   0x2
 794 #define BURST_MODE              0x3
 795         u32 video_transfer_mode:2;
 796
 797         u32 cabc_supported:1;
 798         u32 pwm_blc:1;
 799
 800         /* Bit 13:10 */
 801 #define PIXEL_FORMAT_RGB565                     0x1
 802 #define PIXEL_FORMAT_RGB666                     0x2
 803 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED      0x3
 804 #define PIXEL_FORMAT_RGB888                     0x4
 805         u32 videomode_color_format:4;
 806
 807         /* Bit 15:14 */
 808 #define ENABLE_ROTATION_0       0x0
 809 #define ENABLE_ROTATION_90      0x1
 810 #define ENABLE_ROTATION_180     0x2
 811 #define ENABLE_ROTATION_270     0x3
 812         u32 rotation:2;
 813         u32 bta_enabled:1;
 814         u32 rsvd2:15;
 815
 816         /* 2 byte Port Description */
 817 #define DUAL_LINK_NOT_SUPPORTED 0
 818 #define DUAL_LINK_FRONT_BACK    1
 819 #define DUAL_LINK_PIXEL_ALT     2
 820         u16 dual_link:2;
 821         u16 lane_cnt:2;
 822         u16 pixel_overlap:3;
 823         u16 rsvd3:9;
 824
 825         u16 rsvd4;
 826
 827         u8 rsvd5;
 828         u32 target_burst_mode_freq;
 829         u32 dsi_ddr_clk;
 830         u32 bridge_ref_clk;
 831
 832 #define  BYTE_CLK_SEL_20MHZ             0
 833 #define  BYTE_CLK_SEL_10MHZ             1
 834 #define  BYTE_CLK_SEL_5MHZ              2
 835         u8 byte_clk_sel:2;
 836
 837         u8 rsvd6:6;
 838
 839         /* DPHY Flags */
 840         u16 dphy_param_valid:1;
 841         u16 eot_pkt_disabled:1;
 842         u16 enable_clk_stop:1;
 843         u16 rsvd7:13;
 844
 845         u32 hs_tx_timeout;
 846         u32 lp_rx_timeout;
 847         u32 turn_around_timeout;
 848         u32 device_reset_timer;
 849         u32 master_init_timer;
 850         u32 dbi_bw_timer;
 851         u32 lp_byte_clk_val;
 852
 853         /*  4 byte Dphy Params */
 854         u32 prepare_cnt:6;
 855         u32 rsvd8:2;
 856         u32 clk_zero_cnt:8;
 857         u32 trail_cnt:5;
 858         u32 rsvd9:3;
 859         u32 exit_zero_cnt:6;
 860         u32 rsvd10:2;
 861
 862         u32 clk_lane_switch_cnt;
 863         u32 hl_switch_cnt;
 864
 865         u32 rsvd11[6];
 866
 867         /* timings based on dphy spec */
 868         u8 tclk_miss;
 869         u8 tclk_post;
 870         u8 rsvd12;
 871         u8 tclk_pre;
 872         u8 tclk_prepare;
 873         u8 tclk_settle;
 874         u8 tclk_term_enable;
 875         u8 tclk_trail;
 876         u16 tclk_prepare_clkzero;
 877         u8 rsvd13;
 878         u8 td_term_enable;
 879         u8 teot;
 880         u8 ths_exit;
 881         u8 ths_prepare;
 882         u16 ths_prepare_hszero;
 883         u8 rsvd14;
 884         u8 ths_settle;
 885         u8 ths_skip;
 886         u8 ths_trail;
 887         u8 tinit;
 888         u8 tlpx;
 889         u8 rsvd15[3];
 890
 891         /* GPIOs */
 892         u8 panel_enable;
 893         u8 bl_enable;
 894         u8 pwm_enable;
 895         u8 reset_r_n;
 896         u8 pwr_down_r;
 897         u8 stdby_r_n;
 898
 899 } __packed;
 900
 901 /* Block 52 contains MIPI configuration block
 902  * 6 * bdb_mipi_config, followed by 6 pps data
 903  * block below
 904  *
 905  * all delays has a unit of 100us
 906  */
 907 struct mipi_pps_data {
 908         u16 panel_on_delay;
 909         u16 bl_enable_delay;
 910         u16 bl_disable_delay;
 911         u16 panel_off_delay;
 912         u16 panel_power_cycle_delay;
 913 } __packed;
 914
 915 struct bdb_mipi_config {
 916         struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
 917         struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
 918 } __packed;
 919
 920 /* Block 53 contains MIPI sequences as needed by the panel
 921  * for enabling it. This block can be variable in size and
 922  * can be maximum of 6 blocks
 923  */
 924 struct bdb_mipi_sequence {
 925         u8 version;
 926         u8 data[0];
 927 } __packed;
 928
 929 /* MIPI Sequnece Block definitions */
 930 enum mipi_seq {
 931         MIPI_SEQ_UNDEFINED = 0,
 932         MIPI_SEQ_ASSERT_RESET,
 933         MIPI_SEQ_INIT_OTP,
 934         MIPI_SEQ_DISPLAY_ON,
 935         MIPI_SEQ_DISPLAY_OFF,
 936         MIPI_SEQ_DEASSERT_RESET,
 937         MIPI_SEQ_MAX
 938 };
 939
 940 enum mipi_seq_element {
 941         MIPI_SEQ_ELEM_UNDEFINED = 0,
 942         MIPI_SEQ_ELEM_SEND_PKT,
 943         MIPI_SEQ_ELEM_DELAY,
 944         MIPI_SEQ_ELEM_GPIO,
 945         MIPI_SEQ_ELEM_STATUS,
 946         MIPI_SEQ_ELEM_MAX
 947 };
 948
 949 enum mipi_gpio_pin_index {
 950         MIPI_GPIO_UNDEFINED = 0,
 951         MIPI_GPIO_PANEL_ENABLE,
 952         MIPI_GPIO_BL_ENABLE,
 953         MIPI_GPIO_PWM_ENABLE,
 954         MIPI_GPIO_RESET_N,
 955         MIPI_GPIO_PWR_DOWN_R,
 956         MIPI_GPIO_STDBY_RST_N,
 957         MIPI_GPIO_MAX
 958 };
 959
 960 #endif /* _I830_BIOS_H_ */