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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob107c6c0519fd87cf42a842b9d41bfec93595a309
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_crtc *crtc,
90 struct drm_atomic_state *state,
91 bool force_restore);
92 static int intel_framebuffer_init(struct drm_device *dev,
93 struct intel_framebuffer *ifb,
94 struct drm_mode_fb_cmd2 *mode_cmd,
95 struct drm_i915_gem_object *obj);
96 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
97 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
98 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
99 struct intel_link_m_n *m_n,
100 struct intel_link_m_n *m2_n2);
101 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
102 static void haswell_set_pipeconf(struct drm_crtc *crtc);
103 static void intel_set_pipe_csc(struct drm_crtc *crtc);
104 static void vlv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void chv_prepare_pll(struct intel_crtc *crtc,
107 const struct intel_crtc_state *pipe_config);
108 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
109 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
110 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
111 struct intel_crtc_state *crtc_state);
112 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
113 int num_connectors);
114 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
115 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
116
117 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
118 {
119 if (!connector->mst_port)
120 return connector->encoder;
121 else
122 return &connector->mst_port->mst_encoders[pipe]->base;
123 }
124
125 typedef struct {
126 int min, max;
127 } intel_range_t;
128
129 typedef struct {
130 int dot_limit;
131 int p2_slow, p2_fast;
132 } intel_p2_t;
133
134 typedef struct intel_limit intel_limit_t;
135 struct intel_limit {
136 intel_range_t dot, vco, n, m, m1, m2, p, p1;
137 intel_p2_t p2;
138 };
139
140 int
141 intel_pch_rawclk(struct drm_device *dev)
142 {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 WARN_ON(!HAS_PCH_SPLIT(dev));
146
147 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
148 }
149
150 static inline u32 /* units of 100MHz */
151 intel_fdi_link_freq(struct drm_device *dev)
152 {
153 if (IS_GEN5(dev)) {
154 struct drm_i915_private *dev_priv = dev->dev_private;
155 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
156 } else
157 return 27;
158 }
159
160 static const intel_limit_t intel_limits_i8xx_dac = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 2 },
171 };
172
173 static const intel_limit_t intel_limits_i8xx_dvo = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 2, .max = 33 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 4, .p2_fast = 4 },
184 };
185
186 static const intel_limit_t intel_limits_i8xx_lvds = {
187 .dot = { .min = 25000, .max = 350000 },
188 .vco = { .min = 908000, .max = 1512000 },
189 .n = { .min = 2, .max = 16 },
190 .m = { .min = 96, .max = 140 },
191 .m1 = { .min = 18, .max = 26 },
192 .m2 = { .min = 6, .max = 16 },
193 .p = { .min = 4, .max = 128 },
194 .p1 = { .min = 1, .max = 6 },
195 .p2 = { .dot_limit = 165000,
196 .p2_slow = 14, .p2_fast = 7 },
197 };
198
199 static const intel_limit_t intel_limits_i9xx_sdvo = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 200000,
209 .p2_slow = 10, .p2_fast = 5 },
210 };
211
212 static const intel_limit_t intel_limits_i9xx_lvds = {
213 .dot = { .min = 20000, .max = 400000 },
214 .vco = { .min = 1400000, .max = 2800000 },
215 .n = { .min = 1, .max = 6 },
216 .m = { .min = 70, .max = 120 },
217 .m1 = { .min = 8, .max = 18 },
218 .m2 = { .min = 3, .max = 7 },
219 .p = { .min = 7, .max = 98 },
220 .p1 = { .min = 1, .max = 8 },
221 .p2 = { .dot_limit = 112000,
222 .p2_slow = 14, .p2_fast = 7 },
223 };
224
225
226 static const intel_limit_t intel_limits_g4x_sdvo = {
227 .dot = { .min = 25000, .max = 270000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 10, .max = 30 },
234 .p1 = { .min = 1, .max = 3},
235 .p2 = { .dot_limit = 270000,
236 .p2_slow = 10,
237 .p2_fast = 10
238 },
239 };
240
241 static const intel_limit_t intel_limits_g4x_hdmi = {
242 .dot = { .min = 22000, .max = 400000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 4 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 16, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8},
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 10, .p2_fast = 5 },
252 };
253
254 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
255 .dot = { .min = 20000, .max = 115000 },
256 .vco = { .min = 1750000, .max = 3500000 },
257 .n = { .min = 1, .max = 3 },
258 .m = { .min = 104, .max = 138 },
259 .m1 = { .min = 17, .max = 23 },
260 .m2 = { .min = 5, .max = 11 },
261 .p = { .min = 28, .max = 112 },
262 .p1 = { .min = 2, .max = 8 },
263 .p2 = { .dot_limit = 0,
264 .p2_slow = 14, .p2_fast = 14
265 },
266 };
267
268 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
269 .dot = { .min = 80000, .max = 224000 },
270 .vco = { .min = 1750000, .max = 3500000 },
271 .n = { .min = 1, .max = 3 },
272 .m = { .min = 104, .max = 138 },
273 .m1 = { .min = 17, .max = 23 },
274 .m2 = { .min = 5, .max = 11 },
275 .p = { .min = 14, .max = 42 },
276 .p1 = { .min = 2, .max = 6 },
277 .p2 = { .dot_limit = 0,
278 .p2_slow = 7, .p2_fast = 7
279 },
280 };
281
282 static const intel_limit_t intel_limits_pineview_sdvo = {
283 .dot = { .min = 20000, .max = 400000},
284 .vco = { .min = 1700000, .max = 3500000 },
285 /* Pineview's Ncounter is a ring counter */
286 .n = { .min = 3, .max = 6 },
287 .m = { .min = 2, .max = 256 },
288 /* Pineview only has one combined m divider, which we treat as m2. */
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 200000,
294 .p2_slow = 10, .p2_fast = 5 },
295 };
296
297 static const intel_limit_t intel_limits_pineview_lvds = {
298 .dot = { .min = 20000, .max = 400000 },
299 .vco = { .min = 1700000, .max = 3500000 },
300 .n = { .min = 3, .max = 6 },
301 .m = { .min = 2, .max = 256 },
302 .m1 = { .min = 0, .max = 0 },
303 .m2 = { .min = 0, .max = 254 },
304 .p = { .min = 7, .max = 112 },
305 .p1 = { .min = 1, .max = 8 },
306 .p2 = { .dot_limit = 112000,
307 .p2_slow = 14, .p2_fast = 14 },
308 };
309
310 /* Ironlake / Sandybridge
311 *
312 * We calculate clock using (register_value + 2) for N/M1/M2, so here
313 * the range value for them is (actual_value - 2).
314 */
315 static const intel_limit_t intel_limits_ironlake_dac = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 5 },
319 .m = { .min = 79, .max = 127 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 5, .max = 80 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 10, .p2_fast = 5 },
326 };
327
328 static const intel_limit_t intel_limits_ironlake_single_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 118 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 28, .max = 112 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 14, .p2_fast = 14 },
339 };
340
341 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
342 .dot = { .min = 25000, .max = 350000 },
343 .vco = { .min = 1760000, .max = 3510000 },
344 .n = { .min = 1, .max = 3 },
345 .m = { .min = 79, .max = 127 },
346 .m1 = { .min = 12, .max = 22 },
347 .m2 = { .min = 5, .max = 9 },
348 .p = { .min = 14, .max = 56 },
349 .p1 = { .min = 2, .max = 8 },
350 .p2 = { .dot_limit = 225000,
351 .p2_slow = 7, .p2_fast = 7 },
352 };
353
354 /* LVDS 100mhz refclk limits. */
355 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 2 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 28, .max = 112 },
363 .p1 = { .min = 2, .max = 8 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 14, .p2_fast = 14 },
366 };
367
368 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
369 .dot = { .min = 25000, .max = 350000 },
370 .vco = { .min = 1760000, .max = 3510000 },
371 .n = { .min = 1, .max = 3 },
372 .m = { .min = 79, .max = 126 },
373 .m1 = { .min = 12, .max = 22 },
374 .m2 = { .min = 5, .max = 9 },
375 .p = { .min = 14, .max = 42 },
376 .p1 = { .min = 2, .max = 6 },
377 .p2 = { .dot_limit = 225000,
378 .p2_slow = 7, .p2_fast = 7 },
379 };
380
381 static const intel_limit_t intel_limits_vlv = {
382 /*
383 * These are the data rate limits (measured in fast clocks)
384 * since those are the strictest limits we have. The fast
385 * clock and actual rate limits are more relaxed, so checking
386 * them would make no difference.
387 */
388 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
389 .vco = { .min = 4000000, .max = 6000000 },
390 .n = { .min = 1, .max = 7 },
391 .m1 = { .min = 2, .max = 3 },
392 .m2 = { .min = 11, .max = 156 },
393 .p1 = { .min = 2, .max = 3 },
394 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
395 };
396
397 static const intel_limit_t intel_limits_chv = {
398 /*
399 * These are the data rate limits (measured in fast clocks)
400 * since those are the strictest limits we have. The fast
401 * clock and actual rate limits are more relaxed, so checking
402 * them would make no difference.
403 */
404 .dot = { .min = 25000 * 5, .max = 540000 * 5},
405 .vco = { .min = 4800000, .max = 6480000 },
406 .n = { .min = 1, .max = 1 },
407 .m1 = { .min = 2, .max = 2 },
408 .m2 = { .min = 24 << 22, .max = 175 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 14 },
411 };
412
413 static const intel_limit_t intel_limits_bxt = {
414 /* FIXME: find real dot limits */
415 .dot = { .min = 0, .max = INT_MAX },
416 .vco = { .min = 4800000, .max = 6480000 },
417 .n = { .min = 1, .max = 1 },
418 .m1 = { .min = 2, .max = 2 },
419 /* FIXME: find real m2 limits */
420 .m2 = { .min = 2 << 22, .max = 255 << 22 },
421 .p1 = { .min = 2, .max = 4 },
422 .p2 = { .p2_slow = 1, .p2_fast = 20 },
423 };
424
425 static void vlv_clock(int refclk, intel_clock_t *clock)
426 {
427 clock->m = clock->m1 * clock->m2;
428 clock->p = clock->p1 * clock->p2;
429 if (WARN_ON(clock->n == 0 || clock->p == 0))
430 return;
431 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
432 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
433 }
434
435 /**
436 * Returns whether any output on the specified pipe is of the specified type
437 */
438 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
439 {
440 struct drm_device *dev = crtc->base.dev;
441 struct intel_encoder *encoder;
442
443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
444 if (encoder->type == type)
445 return true;
446
447 return false;
448 }
449
450 /**
451 * Returns whether any output on the specified pipe will have the specified
452 * type after a staged modeset is complete, i.e., the same as
453 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
454 * encoder->crtc.
455 */
456 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
457 int type)
458 {
459 struct drm_atomic_state *state = crtc_state->base.state;
460 struct drm_connector *connector;
461 struct drm_connector_state *connector_state;
462 struct intel_encoder *encoder;
463 int i, num_connectors = 0;
464
465 for_each_connector_in_state(state, connector, connector_state, i) {
466 if (connector_state->crtc != crtc_state->base.crtc)
467 continue;
468
469 num_connectors++;
470
471 encoder = to_intel_encoder(connector_state->best_encoder);
472 if (encoder->type == type)
473 return true;
474 }
475
476 WARN_ON(num_connectors == 0);
477
478 return false;
479 }
480
481 static const intel_limit_t *
482 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
483 {
484 struct drm_device *dev = crtc_state->base.crtc->dev;
485 const intel_limit_t *limit;
486
487 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
488 if (intel_is_dual_link_lvds(dev)) {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_dual_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_dual_lvds;
493 } else {
494 if (refclk == 100000)
495 limit = &intel_limits_ironlake_single_lvds_100m;
496 else
497 limit = &intel_limits_ironlake_single_lvds;
498 }
499 } else
500 limit = &intel_limits_ironlake_dac;
501
502 return limit;
503 }
504
505 static const intel_limit_t *
506 intel_g4x_limit(struct intel_crtc_state *crtc_state)
507 {
508 struct drm_device *dev = crtc_state->base.crtc->dev;
509 const intel_limit_t *limit;
510
511 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
512 if (intel_is_dual_link_lvds(dev))
513 limit = &intel_limits_g4x_dual_channel_lvds;
514 else
515 limit = &intel_limits_g4x_single_channel_lvds;
516 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
517 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
518 limit = &intel_limits_g4x_hdmi;
519 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
520 limit = &intel_limits_g4x_sdvo;
521 } else /* The option is for other outputs */
522 limit = &intel_limits_i9xx_sdvo;
523
524 return limit;
525 }
526
527 static const intel_limit_t *
528 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
529 {
530 struct drm_device *dev = crtc_state->base.crtc->dev;
531 const intel_limit_t *limit;
532
533 if (IS_BROXTON(dev))
534 limit = &intel_limits_bxt;
535 else if (HAS_PCH_SPLIT(dev))
536 limit = intel_ironlake_limit(crtc_state, refclk);
537 else if (IS_G4X(dev)) {
538 limit = intel_g4x_limit(crtc_state);
539 } else if (IS_PINEVIEW(dev)) {
540 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
541 limit = &intel_limits_pineview_lvds;
542 else
543 limit = &intel_limits_pineview_sdvo;
544 } else if (IS_CHERRYVIEW(dev)) {
545 limit = &intel_limits_chv;
546 } else if (IS_VALLEYVIEW(dev)) {
547 limit = &intel_limits_vlv;
548 } else if (!IS_GEN2(dev)) {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i9xx_lvds;
551 else
552 limit = &intel_limits_i9xx_sdvo;
553 } else {
554 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i8xx_lvds;
556 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
557 limit = &intel_limits_i8xx_dvo;
558 else
559 limit = &intel_limits_i8xx_dac;
560 }
561 return limit;
562 }
563
564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
565 static void pineview_clock(int refclk, intel_clock_t *clock)
566 {
567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
569 if (WARN_ON(clock->n == 0 || clock->p == 0))
570 return;
571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
573 }
574
575 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
576 {
577 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
578 }
579
580 static void i9xx_clock(int refclk, intel_clock_t *clock)
581 {
582 clock->m = i9xx_dpll_compute_m(clock);
583 clock->p = clock->p1 * clock->p2;
584 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
585 return;
586 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
587 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
588 }
589
590 static void chv_clock(int refclk, intel_clock_t *clock)
591 {
592 clock->m = clock->m1 * clock->m2;
593 clock->p = clock->p1 * clock->p2;
594 if (WARN_ON(clock->n == 0 || clock->p == 0))
595 return;
596 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
597 clock->n << 22);
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
599 }
600
601 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
602 /**
603 * Returns whether the given set of divisors are valid for a given refclk with
604 * the given connectors.
605 */
606
607 static bool intel_PLL_is_valid(struct drm_device *dev,
608 const intel_limit_t *limit,
609 const intel_clock_t *clock)
610 {
611 if (clock->n < limit->n.min || limit->n.max < clock->n)
612 INTELPllInvalid("n out of range\n");
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
616 INTELPllInvalid("m2 out of range\n");
617 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
618 INTELPllInvalid("m1 out of range\n");
619
620 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
621 if (clock->m1 <= clock->m2)
622 INTELPllInvalid("m1 <= m2\n");
623
624 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
625 if (clock->p < limit->p.min || limit->p.max < clock->p)
626 INTELPllInvalid("p out of range\n");
627 if (clock->m < limit->m.min || limit->m.max < clock->m)
628 INTELPllInvalid("m out of range\n");
629 }
630
631 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
632 INTELPllInvalid("vco out of range\n");
633 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
634 * connector, etc., rather than just a single range.
635 */
636 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
637 INTELPllInvalid("dot out of range\n");
638
639 return true;
640 }
641
642 static bool
643 i9xx_find_best_dpll(const intel_limit_t *limit,
644 struct intel_crtc_state *crtc_state,
645 int target, int refclk, intel_clock_t *match_clock,
646 intel_clock_t *best_clock)
647 {
648 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
649 struct drm_device *dev = crtc->base.dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 if (clock.m2 >= clock.m1)
677 break;
678 for (clock.n = limit->n.min;
679 clock.n <= limit->n.max; clock.n++) {
680 for (clock.p1 = limit->p1.min;
681 clock.p1 <= limit->p1.max; clock.p1++) {
682 int this_err;
683
684 i9xx_clock(refclk, &clock);
685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
687 continue;
688 if (match_clock &&
689 clock.p != match_clock->p)
690 continue;
691
692 this_err = abs(clock.dot - target);
693 if (this_err < err) {
694 *best_clock = clock;
695 err = this_err;
696 }
697 }
698 }
699 }
700 }
701
702 return (err != target);
703 }
704
705 static bool
706 pnv_find_best_dpll(const intel_limit_t *limit,
707 struct intel_crtc_state *crtc_state,
708 int target, int refclk, intel_clock_t *match_clock,
709 intel_clock_t *best_clock)
710 {
711 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
712 struct drm_device *dev = crtc->base.dev;
713 intel_clock_t clock;
714 int err = target;
715
716 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
717 /*
718 * For LVDS just rely on its current settings for dual-channel.
719 * We haven't figured out how to reliably set up different
720 * single/dual channel state, if we even can.
721 */
722 if (intel_is_dual_link_lvds(dev))
723 clock.p2 = limit->p2.p2_fast;
724 else
725 clock.p2 = limit->p2.p2_slow;
726 } else {
727 if (target < limit->p2.dot_limit)
728 clock.p2 = limit->p2.p2_slow;
729 else
730 clock.p2 = limit->p2.p2_fast;
731 }
732
733 memset(best_clock, 0, sizeof(*best_clock));
734
735 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
736 clock.m1++) {
737 for (clock.m2 = limit->m2.min;
738 clock.m2 <= limit->m2.max; clock.m2++) {
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
743 int this_err;
744
745 pineview_clock(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764 }
765
766 static bool
767 g4x_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
773 struct drm_device *dev = crtc->base.dev;
774 intel_clock_t clock;
775 int max_n;
776 bool found;
777 /* approximately equals target * 0.00585 */
778 int err_most = (target >> 8) + (target >> 9);
779 found = false;
780
781 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
782 if (intel_is_dual_link_lvds(dev))
783 clock.p2 = limit->p2.p2_fast;
784 else
785 clock.p2 = limit->p2.p2_slow;
786 } else {
787 if (target < limit->p2.dot_limit)
788 clock.p2 = limit->p2.p2_slow;
789 else
790 clock.p2 = limit->p2.p2_fast;
791 }
792
793 memset(best_clock, 0, sizeof(*best_clock));
794 max_n = limit->n.max;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
804 int this_err;
805
806 i9xx_clock(refclk, &clock);
807 if (!intel_PLL_is_valid(dev, limit,
808 &clock))
809 continue;
810
811 this_err = abs(clock.dot - target);
812 if (this_err < err_most) {
813 *best_clock = clock;
814 err_most = this_err;
815 max_n = clock.n;
816 found = true;
817 }
818 }
819 }
820 }
821 }
822 return found;
823 }
824
825 /*
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
828 */
829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
834 {
835 /*
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
838 */
839 if (IS_CHERRYVIEW(dev)) {
840 *error_ppm = 0;
841
842 return calculated_clock->p > best_clock->p;
843 }
844
845 if (WARN_ON_ONCE(!target_freq))
846 return false;
847
848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
850 target_freq);
851 /*
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
855 */
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
857 *error_ppm = 0;
858
859 return true;
860 }
861
862 return *error_ppm + 10 < best_error_ppm;
863 }
864
865 static bool
866 vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
870 {
871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
872 struct drm_device *dev = crtc->base.dev;
873 intel_clock_t clock;
874 unsigned int bestppm = 1000000;
875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
877 bool found = false;
878
879 target *= 5; /* fast clock */
880
881 memset(best_clock, 0, sizeof(*best_clock));
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
888 clock.p = clock.p1 * clock.p2;
889 /* based on hardware requirement, prefer bigger m1,m2 values */
890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
891 unsigned int ppm;
892
893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
894 refclk * clock.m1);
895
896 vlv_clock(refclk, &clock);
897
898 if (!intel_PLL_is_valid(dev, limit,
899 &clock))
900 continue;
901
902 if (!vlv_PLL_is_optimal(dev, target,
903 &clock,
904 best_clock,
905 bestppm, &ppm))
906 continue;
907
908 *best_clock = clock;
909 bestppm = ppm;
910 found = true;
911 }
912 }
913 }
914 }
915
916 return found;
917 }
918
919 static bool
920 chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
924 {
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
926 struct drm_device *dev = crtc->base.dev;
927 unsigned int best_error_ppm;
928 intel_clock_t clock;
929 uint64_t m2;
930 int found = false;
931
932 memset(best_clock, 0, sizeof(*best_clock));
933 best_error_ppm = 1000000;
934
935 /*
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
939 */
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
942
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 unsigned int error_ppm;
948
949 clock.p = clock.p1 * clock.p2;
950
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
953
954 if (m2 > INT_MAX/clock.m1)
955 continue;
956
957 clock.m2 = m2;
958
959 chv_clock(refclk, &clock);
960
961 if (!intel_PLL_is_valid(dev, limit, &clock))
962 continue;
963
964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
966 continue;
967
968 *best_clock = clock;
969 best_error_ppm = error_ppm;
970 found = true;
971 }
972 }
973
974 return found;
975 }
976
977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
979 {
980 int refclk = i9xx_get_refclk(crtc_state, 0);
981
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
984 }
985
986 bool intel_crtc_active(struct drm_crtc *crtc)
987 {
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
989
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
992 *
993 * We can ditch the adjusted_mode.crtc_clock check as soon
994 * as Haswell has gained clock readout/fastboot support.
995 *
996 * We can ditch the crtc->primary->fb check as soon as we can
997 * properly reconstruct framebuffers.
998 *
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1001 * for atomic.
1002 */
1003 return intel_crtc->active && crtc->primary->state->fb &&
1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
1005 }
1006
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009 {
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
1013 return intel_crtc->config->cpu_transcoder;
1014 }
1015
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1020 u32 line1, line2;
1021 u32 line_mask;
1022
1023 if (IS_GEN2(dev))
1024 line_mask = DSL_LINEMASK_GEN2;
1025 else
1026 line_mask = DSL_LINEMASK_GEN3;
1027
1028 line1 = I915_READ(reg) & line_mask;
1029 mdelay(5);
1030 line2 = I915_READ(reg) & line_mask;
1031
1032 return line1 == line2;
1033 }
1034
1035 /*
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
1037 * @crtc: crtc whose pipe to wait for
1038 *
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1042 *
1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1045 *
1046 * Otherwise:
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
1049 *
1050 */
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1052 {
1053 struct drm_device *dev = crtc->base.dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056 enum pipe pipe = crtc->pipe;
1057
1058 if (INTEL_INFO(dev)->gen >= 4) {
1059 int reg = PIPECONF(cpu_transcoder);
1060
1061 /* Wait for the Pipe State to go off */
1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063 100))
1064 WARN(1, "pipe_off wait timed out\n");
1065 } else {
1066 /* Wait for the display line to settle */
1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 }
1070 }
1071
1072 /*
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1076 *
1077 * Returns true if @port is connected, false otherwise.
1078 */
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1081 {
1082 u32 bit;
1083
1084 if (HAS_PCH_IBX(dev_priv->dev)) {
1085 switch (port->port) {
1086 case PORT_B:
1087 bit = SDE_PORTB_HOTPLUG;
1088 break;
1089 case PORT_C:
1090 bit = SDE_PORTC_HOTPLUG;
1091 break;
1092 case PORT_D:
1093 bit = SDE_PORTD_HOTPLUG;
1094 break;
1095 default:
1096 return true;
1097 }
1098 } else {
1099 switch (port->port) {
1100 case PORT_B:
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1102 break;
1103 case PORT_C:
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1105 break;
1106 case PORT_D:
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1108 break;
1109 default:
1110 return true;
1111 }
1112 }
1113
1114 return I915_READ(SDEISR) & bit;
1115 }
1116
1117 static const char *state_string(bool enabled)
1118 {
1119 return enabled ? "on" : "off";
1120 }
1121
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
1133 I915_STATE_WARN(cur_state != state,
1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136 }
1137
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140 {
1141 u32 val;
1142 bool cur_state;
1143
1144 mutex_lock(&dev_priv->sb_lock);
1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146 mutex_unlock(&dev_priv->sb_lock);
1147
1148 cur_state = val & DSI_PLL_VCO_EN;
1149 I915_STATE_WARN(cur_state != state,
1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1152 }
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158 {
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
1161 if (crtc->config->shared_dpll < 0)
1162 return NULL;
1163
1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1165 }
1166
1167 /* For ILK+ */
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1170 bool state)
1171 {
1172 bool cur_state;
1173 struct intel_dpll_hw_state hw_state;
1174
1175 if (WARN (!pll,
1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
1177 return;
1178
1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180 I915_STATE_WARN(cur_state != state,
1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
1183 }
1184
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 int reg;
1189 u32 val;
1190 bool cur_state;
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
1193
1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1199 } else {
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1203 }
1204 I915_STATE_WARN(cur_state != state,
1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1207 }
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1213 {
1214 int reg;
1215 u32 val;
1216 bool cur_state;
1217
1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
1221 I915_STATE_WARN(cur_state != state,
1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1224 }
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230 {
1231 int reg;
1232 u32 val;
1233
1234 /* ILK FDI PLL is always enabled */
1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1236 return;
1237
1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239 if (HAS_DDI(dev_priv->dev))
1240 return;
1241
1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1245 }
1246
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
1260 }
1261
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 struct drm_device *dev = dev_priv->dev;
1266 int pp_reg;
1267 u32 val;
1268 enum pipe panel_pipe = PIPE_A;
1269 bool locked = true;
1270
1271 if (WARN_ON(HAS_DDI(dev)))
1272 return;
1273
1274 if (HAS_PCH_SPLIT(dev)) {
1275 u32 port_sel;
1276
1277 pp_reg = PCH_PP_CONTROL;
1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287 panel_pipe = pipe;
1288 } else {
1289 pp_reg = PP_CONTROL;
1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
1292 }
1293
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1297 locked = false;
1298
1299 I915_STATE_WARN(panel_pipe == pipe && locked,
1300 "panel assertion failure, pipe %c regs locked\n",
1301 pipe_name(pipe));
1302 }
1303
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1306 {
1307 struct drm_device *dev = dev_priv->dev;
1308 bool cur_state;
1309
1310 if (IS_845G(dev) || IS_I865G(dev))
1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1312 else
1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1314
1315 I915_STATE_WARN(cur_state != state,
1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1324 {
1325 int reg;
1326 u32 val;
1327 bool cur_state;
1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329 pipe);
1330
1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1334 state = true;
1335
1336 if (!intel_display_power_is_enabled(dev_priv,
1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1338 cur_state = false;
1339 } else {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1343 }
1344
1345 I915_STATE_WARN(cur_state != state,
1346 "pipe %c assertion failure (expected %s, current %s)\n",
1347 pipe_name(pipe), state_string(state), state_string(cur_state));
1348 }
1349
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
1352 {
1353 int reg;
1354 u32 val;
1355 bool cur_state;
1356
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360 I915_STATE_WARN(cur_state != state,
1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
1363 }
1364
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370 {
1371 struct drm_device *dev = dev_priv->dev;
1372 int reg, i;
1373 u32 val;
1374 int cur_pipe;
1375
1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381 "plane %c assertion failure, should be disabled but not\n",
1382 plane_name(pipe));
1383 return;
1384 }
1385
1386 /* Need to check both planes against the pipe */
1387 for_each_pipe(dev_priv, i) {
1388 reg = DSPCNTR(i);
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
1395 }
1396 }
1397
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400 {
1401 struct drm_device *dev = dev_priv->dev;
1402 int reg, sprite;
1403 u32 val;
1404
1405 if (INTEL_INFO(dev)->gen >= 9) {
1406 for_each_sprite(dev_priv, pipe, sprite) {
1407 val = I915_READ(PLANE_CTL(pipe, sprite));
1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1411 }
1412 } else if (IS_VALLEYVIEW(dev)) {
1413 for_each_sprite(dev_priv, pipe, sprite) {
1414 reg = SPCNTR(pipe, sprite);
1415 val = I915_READ(reg);
1416 I915_STATE_WARN(val & SP_ENABLE,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 sprite_name(pipe, sprite), pipe_name(pipe));
1419 }
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1421 reg = SPRCTL(pipe);
1422 val = I915_READ(reg);
1423 I915_STATE_WARN(val & SPRITE_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
1428 val = I915_READ(reg);
1429 I915_STATE_WARN(val & DVS_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1432 }
1433 }
1434
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1436 {
1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438 drm_crtc_vblank_put(crtc);
1439 }
1440
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1442 {
1443 u32 val;
1444 bool enabled;
1445
1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1447
1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1452 }
1453
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe)
1456 {
1457 int reg;
1458 u32 val;
1459 bool enabled;
1460
1461 reg = PCH_TRANSCONF(pipe);
1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
1464 I915_STATE_WARN(enabled,
1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 pipe_name(pipe));
1467 }
1468
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
1471 {
1472 if ((val & DP_PORT_EN) == 0)
1473 return false;
1474
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479 return false;
1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482 return false;
1483 } else {
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 return false;
1486 }
1487 return true;
1488 }
1489
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1492 {
1493 if ((val & SDVO_ENABLE) == 0)
1494 return false;
1495
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1498 return false;
1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501 return false;
1502 } else {
1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1504 return false;
1505 }
1506 return true;
1507 }
1508
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511 {
1512 if ((val & LVDS_PORT_EN) == 0)
1513 return false;
1514
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517 return false;
1518 } else {
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 return false;
1521 }
1522 return true;
1523 }
1524
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1527 {
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1529 return false;
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532 return false;
1533 } else {
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 return false;
1536 }
1537 return true;
1538 }
1539
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg, u32 port_sel)
1542 {
1543 u32 val = I915_READ(reg);
1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg, pipe_name(pipe));
1547
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549 && (val & DP_PIPEB_SELECT),
1550 "IBX PCH dp port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1555 {
1556 u32 val = I915_READ(reg);
1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559 reg, pipe_name(pipe));
1560
1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562 && (val & SDVO_PIPE_B_SELECT),
1563 "IBX PCH hdmi port still using transcoder B\n");
1564 }
1565
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568 {
1569 int reg;
1570 u32 val;
1571
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1575
1576 reg = PCH_ADPA;
1577 val = I915_READ(reg);
1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
1580 pipe_name(pipe));
1581
1582 reg = PCH_LVDS;
1583 val = I915_READ(reg);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586 pipe_name(pipe));
1587
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void intel_init_dpio(struct drm_device *dev)
1594 {
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 if (!IS_VALLEYVIEW(dev))
1598 return;
1599
1600 /*
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 */
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608 } else {
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610 }
1611 }
1612
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614 const struct intel_crtc_state *pipe_config)
1615 {
1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
1620
1621 assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626 /* PLL is protected by panel, make sure we can write it */
1627 if (IS_MOBILE(dev_priv->dev))
1628 assert_panel_unlocked(dev_priv, crtc->pipe);
1629
1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638 POSTING_READ(DPLL_MD(crtc->pipe));
1639
1640 /* We do this three times for luck */
1641 I915_WRITE(reg, dpll);
1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 }
1651
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653 const struct intel_crtc_state *pipe_config)
1654 {
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1659 u32 tmp;
1660
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
1665 mutex_lock(&dev_priv->sb_lock);
1666
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
1672 mutex_unlock(&dev_priv->sb_lock);
1673
1674 /*
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676 */
1677 udelay(1);
1678
1679 /* Enable PLL */
1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1681
1682 /* Check PLL is locked */
1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
1686 /* not sure when this should be written */
1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688 POSTING_READ(DPLL_MD(pipe));
1689 }
1690
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1692 {
1693 struct intel_crtc *crtc;
1694 int count = 0;
1695
1696 for_each_intel_crtc(dev, crtc)
1697 count += crtc->active &&
1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1699
1700 return count;
1701 }
1702
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1704 {
1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
1709
1710 assert_pipe_disabled(dev_priv, crtc->pipe);
1711
1712 /* No really, not for ILK+ */
1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1714
1715 /* PLL is protected by panel, make sure we can write it */
1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
1718
1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721 /*
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1726 */
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730 }
1731
1732 /* Wait for the clocks to stabilize. */
1733 POSTING_READ(reg);
1734 udelay(150);
1735
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
1738 crtc->config->dpll_hw_state.dpll_md);
1739 } else {
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1742 *
1743 * So write it again.
1744 */
1745 I915_WRITE(reg, dpll);
1746 }
1747
1748 /* We do this three times for luck */
1749 I915_WRITE(reg, dpll);
1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
1752 I915_WRITE(reg, dpll);
1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
1755 I915_WRITE(reg, dpll);
1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758 }
1759
1760 /**
1761 * i9xx_disable_pll - disable a PLL
1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1764 *
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 *
1767 * Note! This is for pre-ILK only.
1768 */
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1770 {
1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1774
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1776 if (IS_I830(dev) &&
1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778 intel_num_dvo_pipes(dev) == 1) {
1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783 }
1784
1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1788 return;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
1793 I915_WRITE(DPLL(pipe), 0);
1794 POSTING_READ(DPLL(pipe));
1795 }
1796
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798 {
1799 u32 val = 0;
1800
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1803
1804 /*
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1807 */
1808 if (pipe == PIPE_B)
1809 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1810 I915_WRITE(DPLL(pipe), val);
1811 POSTING_READ(DPLL(pipe));
1812
1813 }
1814
1815 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1816 {
1817 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1818 u32 val;
1819
1820 /* Make sure the pipe isn't still relying on us */
1821 assert_pipe_disabled(dev_priv, pipe);
1822
1823 /* Set PLL en = 0 */
1824 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1825 if (pipe != PIPE_A)
1826 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827 I915_WRITE(DPLL(pipe), val);
1828 POSTING_READ(DPLL(pipe));
1829
1830 mutex_lock(&dev_priv->sb_lock);
1831
1832 /* Disable 10bit clock to display controller */
1833 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834 val &= ~DPIO_DCLKP_EN;
1835 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1836
1837 /* disable left/right clock distribution */
1838 if (pipe != PIPE_B) {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1842 } else {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1846 }
1847
1848 mutex_unlock(&dev_priv->sb_lock);
1849 }
1850
1851 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1852 struct intel_digital_port *dport,
1853 unsigned int expected_mask)
1854 {
1855 u32 port_mask;
1856 int dpll_reg;
1857
1858 switch (dport->port) {
1859 case PORT_B:
1860 port_mask = DPLL_PORTB_READY_MASK;
1861 dpll_reg = DPLL(0);
1862 break;
1863 case PORT_C:
1864 port_mask = DPLL_PORTC_READY_MASK;
1865 dpll_reg = DPLL(0);
1866 expected_mask <<= 4;
1867 break;
1868 case PORT_D:
1869 port_mask = DPLL_PORTD_READY_MASK;
1870 dpll_reg = DPIO_PHY_STATUS;
1871 break;
1872 default:
1873 BUG();
1874 }
1875
1876 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1879 }
1880
1881 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1882 {
1883 struct drm_device *dev = crtc->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1886
1887 if (WARN_ON(pll == NULL))
1888 return;
1889
1890 WARN_ON(!pll->config.crtc_mask);
1891 if (pll->active == 0) {
1892 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1893 WARN_ON(pll->on);
1894 assert_shared_dpll_disabled(dev_priv, pll);
1895
1896 pll->mode_set(dev_priv, pll);
1897 }
1898 }
1899
1900 /**
1901 * intel_enable_shared_dpll - enable PCH PLL
1902 * @dev_priv: i915 private structure
1903 * @pipe: pipe PLL to enable
1904 *
1905 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906 * drives the transcoder clock.
1907 */
1908 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1909 {
1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1913
1914 if (WARN_ON(pll == NULL))
1915 return;
1916
1917 if (WARN_ON(pll->config.crtc_mask == 0))
1918 return;
1919
1920 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
1922 crtc->base.base.id);
1923
1924 if (pll->active++) {
1925 WARN_ON(!pll->on);
1926 assert_shared_dpll_enabled(dev_priv, pll);
1927 return;
1928 }
1929 WARN_ON(pll->on);
1930
1931 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1932
1933 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1934 pll->enable(dev_priv, pll);
1935 pll->on = true;
1936 }
1937
1938 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1939 {
1940 struct drm_device *dev = crtc->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1943
1944 /* PCH only available on ILK+ */
1945 BUG_ON(INTEL_INFO(dev)->gen < 5);
1946 if (WARN_ON(pll == NULL))
1947 return;
1948
1949 if (WARN_ON(pll->config.crtc_mask == 0))
1950 return;
1951
1952 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953 pll->name, pll->active, pll->on,
1954 crtc->base.base.id);
1955
1956 if (WARN_ON(pll->active == 0)) {
1957 assert_shared_dpll_disabled(dev_priv, pll);
1958 return;
1959 }
1960
1961 assert_shared_dpll_enabled(dev_priv, pll);
1962 WARN_ON(!pll->on);
1963 if (--pll->active)
1964 return;
1965
1966 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1967 pll->disable(dev_priv, pll);
1968 pll->on = false;
1969
1970 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1971 }
1972
1973 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1974 enum pipe pipe)
1975 {
1976 struct drm_device *dev = dev_priv->dev;
1977 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979 uint32_t reg, val, pipeconf_val;
1980
1981 /* PCH only available on ILK+ */
1982 BUG_ON(!HAS_PCH_SPLIT(dev));
1983
1984 /* Make sure PCH DPLL is enabled */
1985 assert_shared_dpll_enabled(dev_priv,
1986 intel_crtc_to_shared_dpll(intel_crtc));
1987
1988 /* FDI must be feeding us bits for PCH ports */
1989 assert_fdi_tx_enabled(dev_priv, pipe);
1990 assert_fdi_rx_enabled(dev_priv, pipe);
1991
1992 if (HAS_PCH_CPT(dev)) {
1993 /* Workaround: Set the timing override bit before enabling the
1994 * pch transcoder. */
1995 reg = TRANS_CHICKEN2(pipe);
1996 val = I915_READ(reg);
1997 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(reg, val);
1999 }
2000
2001 reg = PCH_TRANSCONF(pipe);
2002 val = I915_READ(reg);
2003 pipeconf_val = I915_READ(PIPECONF(pipe));
2004
2005 if (HAS_PCH_IBX(dev_priv->dev)) {
2006 /*
2007 * make the BPC in transcoder be consistent with
2008 * that in pipeconf reg.
2009 */
2010 val &= ~PIPECONF_BPC_MASK;
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
2012 }
2013
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016 if (HAS_PCH_IBX(dev_priv->dev) &&
2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2019 else
2020 val |= TRANS_INTERLACED;
2021 else
2022 val |= TRANS_PROGRESSIVE;
2023
2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030 enum transcoder cpu_transcoder)
2031 {
2032 u32 val, pipeconf_val;
2033
2034 /* PCH only available on ILK+ */
2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037 /* FDI must be feeding us bits for PCH ports */
2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046 val = TRANS_ENABLE;
2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
2051 val |= TRANS_INTERLACED;
2052 else
2053 val |= TRANS_PROGRESSIVE;
2054
2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
2062 {
2063 struct drm_device *dev = dev_priv->dev;
2064 uint32_t reg, val;
2065
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2072
2073 reg = PCH_TRANSCONF(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2087 }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092 u32 val;
2093
2094 val = I915_READ(LPT_TRANSCONF);
2095 val &= ~TRANS_ENABLE;
2096 I915_WRITE(LPT_TRANSCONF, val);
2097 /* wait for PCH transcoder off, transcoder state */
2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104 I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108 * intel_enable_pipe - enable a pipe, asserting requirements
2109 * @crtc: crtc responsible for the pipe
2110 *
2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113 */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120 pipe);
2121 enum pipe pch_transcoder;
2122 int reg;
2123 u32 val;
2124
2125 assert_planes_disabled(dev_priv, pipe);
2126 assert_cursor_disabled(dev_priv, pipe);
2127 assert_sprites_disabled(dev_priv, pipe);
2128
2129 if (HAS_PCH_LPT(dev_priv->dev))
2130 pch_transcoder = TRANSCODER_A;
2131 else
2132 pch_transcoder = pipe;
2133
2134 /*
2135 * A pipe without a PLL won't actually be able to drive bits from
2136 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2137 * need the check.
2138 */
2139 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2140 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2141 assert_dsi_pll_enabled(dev_priv);
2142 else
2143 assert_pll_enabled(dev_priv, pipe);
2144 else {
2145 if (crtc->config->has_pch_encoder) {
2146 /* if driving the PCH, we need FDI enabled */
2147 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2148 assert_fdi_tx_pll_enabled(dev_priv,
2149 (enum pipe) cpu_transcoder);
2150 }
2151 /* FIXME: assert CPU port conditions for SNB+ */
2152 }
2153
2154 reg = PIPECONF(cpu_transcoder);
2155 val = I915_READ(reg);
2156 if (val & PIPECONF_ENABLE) {
2157 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2159 return;
2160 }
2161
2162 I915_WRITE(reg, val | PIPECONF_ENABLE);
2163 POSTING_READ(reg);
2164 }
2165
2166 /**
2167 * intel_disable_pipe - disable a pipe, asserting requirements
2168 * @crtc: crtc whose pipes is to be disabled
2169 *
2170 * Disable the pipe of @crtc, making sure that various hardware
2171 * specific requirements are met, if applicable, e.g. plane
2172 * disabled, panel fitter off, etc.
2173 *
2174 * Will wait until the pipe has shut down before returning.
2175 */
2176 static void intel_disable_pipe(struct intel_crtc *crtc)
2177 {
2178 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2179 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2180 enum pipe pipe = crtc->pipe;
2181 int reg;
2182 u32 val;
2183
2184 /*
2185 * Make sure planes won't keep trying to pump pixels to us,
2186 * or we might hang the display.
2187 */
2188 assert_planes_disabled(dev_priv, pipe);
2189 assert_cursor_disabled(dev_priv, pipe);
2190 assert_sprites_disabled(dev_priv, pipe);
2191
2192 reg = PIPECONF(cpu_transcoder);
2193 val = I915_READ(reg);
2194 if ((val & PIPECONF_ENABLE) == 0)
2195 return;
2196
2197 /*
2198 * Double wide has implications for planes
2199 * so best keep it disabled when not needed.
2200 */
2201 if (crtc->config->double_wide)
2202 val &= ~PIPECONF_DOUBLE_WIDE;
2203
2204 /* Don't disable pipe or pipe PLLs if needed */
2205 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2206 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2207 val &= ~PIPECONF_ENABLE;
2208
2209 I915_WRITE(reg, val);
2210 if ((val & PIPECONF_ENABLE) == 0)
2211 intel_wait_for_pipe_off(crtc);
2212 }
2213
2214 /**
2215 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2216 * @plane: plane to be enabled
2217 * @crtc: crtc for the plane
2218 *
2219 * Enable @plane on @crtc, making sure that the pipe is running first.
2220 */
2221 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2222 struct drm_crtc *crtc)
2223 {
2224 struct drm_device *dev = plane->dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2227
2228 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2229 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2230 to_intel_plane_state(plane->state)->visible = true;
2231
2232 dev_priv->display.update_primary_plane(crtc, plane->fb,
2233 crtc->x, crtc->y);
2234 }
2235
2236 static bool need_vtd_wa(struct drm_device *dev)
2237 {
2238 #ifdef CONFIG_INTEL_IOMMU
2239 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2240 return true;
2241 #endif
2242 return false;
2243 }
2244
2245 unsigned int
2246 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2247 uint64_t fb_format_modifier)
2248 {
2249 unsigned int tile_height;
2250 uint32_t pixel_bytes;
2251
2252 switch (fb_format_modifier) {
2253 case DRM_FORMAT_MOD_NONE:
2254 tile_height = 1;
2255 break;
2256 case I915_FORMAT_MOD_X_TILED:
2257 tile_height = IS_GEN2(dev) ? 16 : 8;
2258 break;
2259 case I915_FORMAT_MOD_Y_TILED:
2260 tile_height = 32;
2261 break;
2262 case I915_FORMAT_MOD_Yf_TILED:
2263 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2264 switch (pixel_bytes) {
2265 default:
2266 case 1:
2267 tile_height = 64;
2268 break;
2269 case 2:
2270 case 4:
2271 tile_height = 32;
2272 break;
2273 case 8:
2274 tile_height = 16;
2275 break;
2276 case 16:
2277 WARN_ONCE(1,
2278 "128-bit pixels are not supported for display!");
2279 tile_height = 16;
2280 break;
2281 }
2282 break;
2283 default:
2284 MISSING_CASE(fb_format_modifier);
2285 tile_height = 1;
2286 break;
2287 }
2288
2289 return tile_height;
2290 }
2291
2292 unsigned int
2293 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2294 uint32_t pixel_format, uint64_t fb_format_modifier)
2295 {
2296 return ALIGN(height, intel_tile_height(dev, pixel_format,
2297 fb_format_modifier));
2298 }
2299
2300 static int
2301 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2302 const struct drm_plane_state *plane_state)
2303 {
2304 struct intel_rotation_info *info = &view->rotation_info;
2305
2306 *view = i915_ggtt_view_normal;
2307
2308 if (!plane_state)
2309 return 0;
2310
2311 if (!intel_rotation_90_or_270(plane_state->rotation))
2312 return 0;
2313
2314 *view = i915_ggtt_view_rotated;
2315
2316 info->height = fb->height;
2317 info->pixel_format = fb->pixel_format;
2318 info->pitch = fb->pitches[0];
2319 info->fb_modifier = fb->modifier[0];
2320
2321 return 0;
2322 }
2323
2324 int
2325 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326 struct drm_framebuffer *fb,
2327 const struct drm_plane_state *plane_state,
2328 struct intel_engine_cs *pipelined)
2329 {
2330 struct drm_device *dev = fb->dev;
2331 struct drm_i915_private *dev_priv = dev->dev_private;
2332 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333 struct i915_ggtt_view view;
2334 u32 alignment;
2335 int ret;
2336
2337 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
2339 switch (fb->modifier[0]) {
2340 case DRM_FORMAT_MOD_NONE:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2344 alignment = 128 * 1024;
2345 else if (INTEL_INFO(dev)->gen >= 4)
2346 alignment = 4 * 1024;
2347 else
2348 alignment = 64 * 1024;
2349 break;
2350 case I915_FORMAT_MOD_X_TILED:
2351 if (INTEL_INFO(dev)->gen >= 9)
2352 alignment = 256 * 1024;
2353 else {
2354 /* pin() will align the object as required by fence */
2355 alignment = 0;
2356 }
2357 break;
2358 case I915_FORMAT_MOD_Y_TILED:
2359 case I915_FORMAT_MOD_Yf_TILED:
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361 "Y tiling bo slipped through, driver bug!\n"))
2362 return -EINVAL;
2363 alignment = 1 * 1024 * 1024;
2364 break;
2365 default:
2366 MISSING_CASE(fb->modifier[0]);
2367 return -EINVAL;
2368 }
2369
2370 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371 if (ret)
2372 return ret;
2373
2374 /* Note that the w/a also requires 64 PTE of padding following the
2375 * bo. We currently fill all unused PTE with the shadow page and so
2376 * we should always have valid PTE following the scanout preventing
2377 * the VT-d warning.
2378 */
2379 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380 alignment = 256 * 1024;
2381
2382 /*
2383 * Global gtt pte registers are special registers which actually forward
2384 * writes to a chunk of system memory. Which means that there is no risk
2385 * that the register values disappear as soon as we call
2386 * intel_runtime_pm_put(), so it is correct to wrap only the
2387 * pin/unpin/fence and not more.
2388 */
2389 intel_runtime_pm_get(dev_priv);
2390
2391 dev_priv->mm.interruptible = false;
2392 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393 &view);
2394 if (ret)
2395 goto err_interruptible;
2396
2397 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398 * fence, whereas 965+ only requires a fence if using
2399 * framebuffer compression. For simplicity, we always install
2400 * a fence as the cost is not that onerous.
2401 */
2402 ret = i915_gem_object_get_fence(obj);
2403 if (ret)
2404 goto err_unpin;
2405
2406 i915_gem_object_pin_fence(obj);
2407
2408 dev_priv->mm.interruptible = true;
2409 intel_runtime_pm_put(dev_priv);
2410 return 0;
2411
2412 err_unpin:
2413 i915_gem_object_unpin_from_display_plane(obj, &view);
2414 err_interruptible:
2415 dev_priv->mm.interruptible = true;
2416 intel_runtime_pm_put(dev_priv);
2417 return ret;
2418 }
2419
2420 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421 const struct drm_plane_state *plane_state)
2422 {
2423 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2424 struct i915_ggtt_view view;
2425 int ret;
2426
2427 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
2429 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430 WARN_ONCE(ret, "Couldn't get view from plane state!");
2431
2432 i915_gem_object_unpin_fence(obj);
2433 i915_gem_object_unpin_from_display_plane(obj, &view);
2434 }
2435
2436 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437 * is assumed to be a power-of-two. */
2438 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439 unsigned int tiling_mode,
2440 unsigned int cpp,
2441 unsigned int pitch)
2442 {
2443 if (tiling_mode != I915_TILING_NONE) {
2444 unsigned int tile_rows, tiles;
2445
2446 tile_rows = *y / 8;
2447 *y %= 8;
2448
2449 tiles = *x / (512/cpp);
2450 *x %= 512/cpp;
2451
2452 return tile_rows * pitch * 8 + tiles * 4096;
2453 } else {
2454 unsigned int offset;
2455
2456 offset = *y * pitch + *x * cpp;
2457 *y = 0;
2458 *x = (offset & 4095) / cpp;
2459 return offset & -4096;
2460 }
2461 }
2462
2463 static int i9xx_format_to_fourcc(int format)
2464 {
2465 switch (format) {
2466 case DISPPLANE_8BPP:
2467 return DRM_FORMAT_C8;
2468 case DISPPLANE_BGRX555:
2469 return DRM_FORMAT_XRGB1555;
2470 case DISPPLANE_BGRX565:
2471 return DRM_FORMAT_RGB565;
2472 default:
2473 case DISPPLANE_BGRX888:
2474 return DRM_FORMAT_XRGB8888;
2475 case DISPPLANE_RGBX888:
2476 return DRM_FORMAT_XBGR8888;
2477 case DISPPLANE_BGRX101010:
2478 return DRM_FORMAT_XRGB2101010;
2479 case DISPPLANE_RGBX101010:
2480 return DRM_FORMAT_XBGR2101010;
2481 }
2482 }
2483
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485 {
2486 switch (format) {
2487 case PLANE_CTL_FORMAT_RGB_565:
2488 return DRM_FORMAT_RGB565;
2489 default:
2490 case PLANE_CTL_FORMAT_XRGB_8888:
2491 if (rgb_order) {
2492 if (alpha)
2493 return DRM_FORMAT_ABGR8888;
2494 else
2495 return DRM_FORMAT_XBGR8888;
2496 } else {
2497 if (alpha)
2498 return DRM_FORMAT_ARGB8888;
2499 else
2500 return DRM_FORMAT_XRGB8888;
2501 }
2502 case PLANE_CTL_FORMAT_XRGB_2101010:
2503 if (rgb_order)
2504 return DRM_FORMAT_XBGR2101010;
2505 else
2506 return DRM_FORMAT_XRGB2101010;
2507 }
2508 }
2509
2510 static bool
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512 struct intel_initial_plane_config *plane_config)
2513 {
2514 struct drm_device *dev = crtc->base.dev;
2515 struct drm_i915_gem_object *obj = NULL;
2516 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2517 struct drm_framebuffer *fb = &plane_config->fb->base;
2518 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2520 PAGE_SIZE);
2521
2522 size_aligned -= base_aligned;
2523
2524 if (plane_config->size == 0)
2525 return false;
2526
2527 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2528 base_aligned,
2529 base_aligned,
2530 size_aligned);
2531 if (!obj)
2532 return false;
2533
2534 obj->tiling_mode = plane_config->tiling;
2535 if (obj->tiling_mode == I915_TILING_X)
2536 obj->stride = fb->pitches[0];
2537
2538 mode_cmd.pixel_format = fb->pixel_format;
2539 mode_cmd.width = fb->width;
2540 mode_cmd.height = fb->height;
2541 mode_cmd.pitches[0] = fb->pitches[0];
2542 mode_cmd.modifier[0] = fb->modifier[0];
2543 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2544
2545 mutex_lock(&dev->struct_mutex);
2546 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2547 &mode_cmd, obj)) {
2548 DRM_DEBUG_KMS("intel fb init failed\n");
2549 goto out_unref_obj;
2550 }
2551 mutex_unlock(&dev->struct_mutex);
2552
2553 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2554 return true;
2555
2556 out_unref_obj:
2557 drm_gem_object_unreference(&obj->base);
2558 mutex_unlock(&dev->struct_mutex);
2559 return false;
2560 }
2561
2562 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 static void
2564 update_state_fb(struct drm_plane *plane)
2565 {
2566 if (plane->fb == plane->state->fb)
2567 return;
2568
2569 if (plane->state->fb)
2570 drm_framebuffer_unreference(plane->state->fb);
2571 plane->state->fb = plane->fb;
2572 if (plane->state->fb)
2573 drm_framebuffer_reference(plane->state->fb);
2574 }
2575
2576 static void
2577 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2578 struct intel_initial_plane_config *plane_config)
2579 {
2580 struct drm_device *dev = intel_crtc->base.dev;
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2582 struct drm_crtc *c;
2583 struct intel_crtc *i;
2584 struct drm_i915_gem_object *obj;
2585 struct drm_plane *primary = intel_crtc->base.primary;
2586 struct drm_framebuffer *fb;
2587
2588 if (!plane_config->fb)
2589 return;
2590
2591 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592 fb = &plane_config->fb->base;
2593 goto valid_fb;
2594 }
2595
2596 kfree(plane_config->fb);
2597
2598 /*
2599 * Failed to alloc the obj, check to see if we should share
2600 * an fb with another CRTC instead
2601 */
2602 for_each_crtc(dev, c) {
2603 i = to_intel_crtc(c);
2604
2605 if (c == &intel_crtc->base)
2606 continue;
2607
2608 if (!i->active)
2609 continue;
2610
2611 fb = c->primary->fb;
2612 if (!fb)
2613 continue;
2614
2615 obj = intel_fb_obj(fb);
2616 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617 drm_framebuffer_reference(fb);
2618 goto valid_fb;
2619 }
2620 }
2621
2622 return;
2623
2624 valid_fb:
2625 obj = intel_fb_obj(fb);
2626 if (obj->tiling_mode != I915_TILING_NONE)
2627 dev_priv->preserve_bios_swizzle = true;
2628
2629 primary->fb = fb;
2630 primary->state->crtc = &intel_crtc->base;
2631 primary->crtc = &intel_crtc->base;
2632 update_state_fb(primary);
2633 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2634 }
2635
2636 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2637 struct drm_framebuffer *fb,
2638 int x, int y)
2639 {
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 struct drm_plane *primary = crtc->primary;
2644 bool visible = to_intel_plane_state(primary->state)->visible;
2645 struct drm_i915_gem_object *obj;
2646 int plane = intel_crtc->plane;
2647 unsigned long linear_offset;
2648 u32 dspcntr;
2649 u32 reg = DSPCNTR(plane);
2650 int pixel_size;
2651
2652 if (!visible || !fb) {
2653 I915_WRITE(reg, 0);
2654 if (INTEL_INFO(dev)->gen >= 4)
2655 I915_WRITE(DSPSURF(plane), 0);
2656 else
2657 I915_WRITE(DSPADDR(plane), 0);
2658 POSTING_READ(reg);
2659 return;
2660 }
2661
2662 obj = intel_fb_obj(fb);
2663 if (WARN_ON(obj == NULL))
2664 return;
2665
2666 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2667
2668 dspcntr = DISPPLANE_GAMMA_ENABLE;
2669
2670 dspcntr |= DISPLAY_PLANE_ENABLE;
2671
2672 if (INTEL_INFO(dev)->gen < 4) {
2673 if (intel_crtc->pipe == PIPE_B)
2674 dspcntr |= DISPPLANE_SEL_PIPE_B;
2675
2676 /* pipesrc and dspsize control the size that is scaled from,
2677 * which should always be the user's requested size.
2678 */
2679 I915_WRITE(DSPSIZE(plane),
2680 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681 (intel_crtc->config->pipe_src_w - 1));
2682 I915_WRITE(DSPPOS(plane), 0);
2683 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2684 I915_WRITE(PRIMSIZE(plane),
2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
2687 I915_WRITE(PRIMPOS(plane), 0);
2688 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2689 }
2690
2691 switch (fb->pixel_format) {
2692 case DRM_FORMAT_C8:
2693 dspcntr |= DISPPLANE_8BPP;
2694 break;
2695 case DRM_FORMAT_XRGB1555:
2696 dspcntr |= DISPPLANE_BGRX555;
2697 break;
2698 case DRM_FORMAT_RGB565:
2699 dspcntr |= DISPPLANE_BGRX565;
2700 break;
2701 case DRM_FORMAT_XRGB8888:
2702 dspcntr |= DISPPLANE_BGRX888;
2703 break;
2704 case DRM_FORMAT_XBGR8888:
2705 dspcntr |= DISPPLANE_RGBX888;
2706 break;
2707 case DRM_FORMAT_XRGB2101010:
2708 dspcntr |= DISPPLANE_BGRX101010;
2709 break;
2710 case DRM_FORMAT_XBGR2101010:
2711 dspcntr |= DISPPLANE_RGBX101010;
2712 break;
2713 default:
2714 BUG();
2715 }
2716
2717 if (INTEL_INFO(dev)->gen >= 4 &&
2718 obj->tiling_mode != I915_TILING_NONE)
2719 dspcntr |= DISPPLANE_TILED;
2720
2721 if (IS_G4X(dev))
2722 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2723
2724 linear_offset = y * fb->pitches[0] + x * pixel_size;
2725
2726 if (INTEL_INFO(dev)->gen >= 4) {
2727 intel_crtc->dspaddr_offset =
2728 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2729 pixel_size,
2730 fb->pitches[0]);
2731 linear_offset -= intel_crtc->dspaddr_offset;
2732 } else {
2733 intel_crtc->dspaddr_offset = linear_offset;
2734 }
2735
2736 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2737 dspcntr |= DISPPLANE_ROTATE_180;
2738
2739 x += (intel_crtc->config->pipe_src_w - 1);
2740 y += (intel_crtc->config->pipe_src_h - 1);
2741
2742 /* Finding the last pixel of the last line of the display
2743 data and adding to linear_offset*/
2744 linear_offset +=
2745 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2746 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2747 }
2748
2749 I915_WRITE(reg, dspcntr);
2750
2751 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2752 if (INTEL_INFO(dev)->gen >= 4) {
2753 I915_WRITE(DSPSURF(plane),
2754 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2755 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2756 I915_WRITE(DSPLINOFF(plane), linear_offset);
2757 } else
2758 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2759 POSTING_READ(reg);
2760 }
2761
2762 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2763 struct drm_framebuffer *fb,
2764 int x, int y)
2765 {
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 struct drm_plane *primary = crtc->primary;
2770 bool visible = to_intel_plane_state(primary->state)->visible;
2771 struct drm_i915_gem_object *obj;
2772 int plane = intel_crtc->plane;
2773 unsigned long linear_offset;
2774 u32 dspcntr;
2775 u32 reg = DSPCNTR(plane);
2776 int pixel_size;
2777
2778 if (!visible || !fb) {
2779 I915_WRITE(reg, 0);
2780 I915_WRITE(DSPSURF(plane), 0);
2781 POSTING_READ(reg);
2782 return;
2783 }
2784
2785 obj = intel_fb_obj(fb);
2786 if (WARN_ON(obj == NULL))
2787 return;
2788
2789 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2790
2791 dspcntr = DISPPLANE_GAMMA_ENABLE;
2792
2793 dspcntr |= DISPLAY_PLANE_ENABLE;
2794
2795 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2796 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2797
2798 switch (fb->pixel_format) {
2799 case DRM_FORMAT_C8:
2800 dspcntr |= DISPPLANE_8BPP;
2801 break;
2802 case DRM_FORMAT_RGB565:
2803 dspcntr |= DISPPLANE_BGRX565;
2804 break;
2805 case DRM_FORMAT_XRGB8888:
2806 dspcntr |= DISPPLANE_BGRX888;
2807 break;
2808 case DRM_FORMAT_XBGR8888:
2809 dspcntr |= DISPPLANE_RGBX888;
2810 break;
2811 case DRM_FORMAT_XRGB2101010:
2812 dspcntr |= DISPPLANE_BGRX101010;
2813 break;
2814 case DRM_FORMAT_XBGR2101010:
2815 dspcntr |= DISPPLANE_RGBX101010;
2816 break;
2817 default:
2818 BUG();
2819 }
2820
2821 if (obj->tiling_mode != I915_TILING_NONE)
2822 dspcntr |= DISPPLANE_TILED;
2823
2824 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2825 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2826
2827 linear_offset = y * fb->pitches[0] + x * pixel_size;
2828 intel_crtc->dspaddr_offset =
2829 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2830 pixel_size,
2831 fb->pitches[0]);
2832 linear_offset -= intel_crtc->dspaddr_offset;
2833 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834 dspcntr |= DISPPLANE_ROTATE_180;
2835
2836 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837 x += (intel_crtc->config->pipe_src_w - 1);
2838 y += (intel_crtc->config->pipe_src_h - 1);
2839
2840 /* Finding the last pixel of the last line of the display
2841 data and adding to linear_offset*/
2842 linear_offset +=
2843 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2845 }
2846 }
2847
2848 I915_WRITE(reg, dspcntr);
2849
2850 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2851 I915_WRITE(DSPSURF(plane),
2852 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2853 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2854 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2855 } else {
2856 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2857 I915_WRITE(DSPLINOFF(plane), linear_offset);
2858 }
2859 POSTING_READ(reg);
2860 }
2861
2862 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2863 uint32_t pixel_format)
2864 {
2865 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2866
2867 /*
2868 * The stride is either expressed as a multiple of 64 bytes
2869 * chunks for linear buffers or in number of tiles for tiled
2870 * buffers.
2871 */
2872 switch (fb_modifier) {
2873 case DRM_FORMAT_MOD_NONE:
2874 return 64;
2875 case I915_FORMAT_MOD_X_TILED:
2876 if (INTEL_INFO(dev)->gen == 2)
2877 return 128;
2878 return 512;
2879 case I915_FORMAT_MOD_Y_TILED:
2880 /* No need to check for old gens and Y tiling since this is
2881 * about the display engine and those will be blocked before
2882 * we get here.
2883 */
2884 return 128;
2885 case I915_FORMAT_MOD_Yf_TILED:
2886 if (bits_per_pixel == 8)
2887 return 64;
2888 else
2889 return 128;
2890 default:
2891 MISSING_CASE(fb_modifier);
2892 return 64;
2893 }
2894 }
2895
2896 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2897 struct drm_i915_gem_object *obj)
2898 {
2899 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2900
2901 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2902 view = &i915_ggtt_view_rotated;
2903
2904 return i915_gem_obj_ggtt_offset_view(obj, view);
2905 }
2906
2907 /*
2908 * This function detaches (aka. unbinds) unused scalers in hardware
2909 */
2910 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2911 {
2912 struct drm_device *dev;
2913 struct drm_i915_private *dev_priv;
2914 struct intel_crtc_scaler_state *scaler_state;
2915 int i;
2916
2917 if (!intel_crtc || !intel_crtc->config)
2918 return;
2919
2920 dev = intel_crtc->base.dev;
2921 dev_priv = dev->dev_private;
2922 scaler_state = &intel_crtc->config->scaler_state;
2923
2924 /* loop through and disable scalers that aren't in use */
2925 for (i = 0; i < intel_crtc->num_scalers; i++) {
2926 if (!scaler_state->scalers[i].in_use) {
2927 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2929 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2930 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2931 intel_crtc->base.base.id, intel_crtc->pipe, i);
2932 }
2933 }
2934 }
2935
2936 u32 skl_plane_ctl_format(uint32_t pixel_format)
2937 {
2938 switch (pixel_format) {
2939 case DRM_FORMAT_C8:
2940 return PLANE_CTL_FORMAT_INDEXED;
2941 case DRM_FORMAT_RGB565:
2942 return PLANE_CTL_FORMAT_RGB_565;
2943 case DRM_FORMAT_XBGR8888:
2944 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2945 case DRM_FORMAT_XRGB8888:
2946 return PLANE_CTL_FORMAT_XRGB_8888;
2947 /*
2948 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2949 * to be already pre-multiplied. We need to add a knob (or a different
2950 * DRM_FORMAT) for user-space to configure that.
2951 */
2952 case DRM_FORMAT_ABGR8888:
2953 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2954 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2955 case DRM_FORMAT_ARGB8888:
2956 return PLANE_CTL_FORMAT_XRGB_8888 |
2957 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2958 case DRM_FORMAT_XRGB2101010:
2959 return PLANE_CTL_FORMAT_XRGB_2101010;
2960 case DRM_FORMAT_XBGR2101010:
2961 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2962 case DRM_FORMAT_YUYV:
2963 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2964 case DRM_FORMAT_YVYU:
2965 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2966 case DRM_FORMAT_UYVY:
2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2968 case DRM_FORMAT_VYUY:
2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2970 default:
2971 MISSING_CASE(pixel_format);
2972 }
2973
2974 return 0;
2975 }
2976
2977 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2978 {
2979 switch (fb_modifier) {
2980 case DRM_FORMAT_MOD_NONE:
2981 break;
2982 case I915_FORMAT_MOD_X_TILED:
2983 return PLANE_CTL_TILED_X;
2984 case I915_FORMAT_MOD_Y_TILED:
2985 return PLANE_CTL_TILED_Y;
2986 case I915_FORMAT_MOD_Yf_TILED:
2987 return PLANE_CTL_TILED_YF;
2988 default:
2989 MISSING_CASE(fb_modifier);
2990 }
2991
2992 return 0;
2993 }
2994
2995 u32 skl_plane_ctl_rotation(unsigned int rotation)
2996 {
2997 switch (rotation) {
2998 case BIT(DRM_ROTATE_0):
2999 break;
3000 /*
3001 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3002 * while i915 HW rotation is clockwise, thats why this swapping.
3003 */
3004 case BIT(DRM_ROTATE_90):
3005 return PLANE_CTL_ROTATE_270;
3006 case BIT(DRM_ROTATE_180):
3007 return PLANE_CTL_ROTATE_180;
3008 case BIT(DRM_ROTATE_270):
3009 return PLANE_CTL_ROTATE_90;
3010 default:
3011 MISSING_CASE(rotation);
3012 }
3013
3014 return 0;
3015 }
3016
3017 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3018 struct drm_framebuffer *fb,
3019 int x, int y)
3020 {
3021 struct drm_device *dev = crtc->dev;
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3024 struct drm_plane *plane = crtc->primary;
3025 bool visible = to_intel_plane_state(plane->state)->visible;
3026 struct drm_i915_gem_object *obj;
3027 int pipe = intel_crtc->pipe;
3028 u32 plane_ctl, stride_div, stride;
3029 u32 tile_height, plane_offset, plane_size;
3030 unsigned int rotation;
3031 int x_offset, y_offset;
3032 unsigned long surf_addr;
3033 struct intel_crtc_state *crtc_state = intel_crtc->config;
3034 struct intel_plane_state *plane_state;
3035 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3036 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3037 int scaler_id = -1;
3038
3039 plane_state = to_intel_plane_state(plane->state);
3040
3041 if (!visible || !fb) {
3042 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3043 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3044 POSTING_READ(PLANE_CTL(pipe, 0));
3045 return;
3046 }
3047
3048 plane_ctl = PLANE_CTL_ENABLE |
3049 PLANE_CTL_PIPE_GAMMA_ENABLE |
3050 PLANE_CTL_PIPE_CSC_ENABLE;
3051
3052 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3053 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3054 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3055
3056 rotation = plane->state->rotation;
3057 plane_ctl |= skl_plane_ctl_rotation(rotation);
3058
3059 obj = intel_fb_obj(fb);
3060 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3061 fb->pixel_format);
3062 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3063
3064 /*
3065 * FIXME: intel_plane_state->src, dst aren't set when transitional
3066 * update_plane helpers are called from legacy paths.
3067 * Once full atomic crtc is available, below check can be avoided.
3068 */
3069 if (drm_rect_width(&plane_state->src)) {
3070 scaler_id = plane_state->scaler_id;
3071 src_x = plane_state->src.x1 >> 16;
3072 src_y = plane_state->src.y1 >> 16;
3073 src_w = drm_rect_width(&plane_state->src) >> 16;
3074 src_h = drm_rect_height(&plane_state->src) >> 16;
3075 dst_x = plane_state->dst.x1;
3076 dst_y = plane_state->dst.y1;
3077 dst_w = drm_rect_width(&plane_state->dst);
3078 dst_h = drm_rect_height(&plane_state->dst);
3079
3080 WARN_ON(x != src_x || y != src_y);
3081 } else {
3082 src_w = intel_crtc->config->pipe_src_w;
3083 src_h = intel_crtc->config->pipe_src_h;
3084 }
3085
3086 if (intel_rotation_90_or_270(rotation)) {
3087 /* stride = Surface height in tiles */
3088 tile_height = intel_tile_height(dev, fb->pixel_format,
3089 fb->modifier[0]);
3090 stride = DIV_ROUND_UP(fb->height, tile_height);
3091 x_offset = stride * tile_height - y - src_h;
3092 y_offset = x;
3093 plane_size = (src_w - 1) << 16 | (src_h - 1);
3094 } else {
3095 stride = fb->pitches[0] / stride_div;
3096 x_offset = x;
3097 y_offset = y;
3098 plane_size = (src_h - 1) << 16 | (src_w - 1);
3099 }
3100 plane_offset = y_offset << 16 | x_offset;
3101
3102 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3103 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3104 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3105 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3106
3107 if (scaler_id >= 0) {
3108 uint32_t ps_ctrl = 0;
3109
3110 WARN_ON(!dst_w || !dst_h);
3111 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3112 crtc_state->scaler_state.scalers[scaler_id].mode;
3113 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3114 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3115 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3116 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3117 I915_WRITE(PLANE_POS(pipe, 0), 0);
3118 } else {
3119 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3120 }
3121
3122 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3123
3124 POSTING_READ(PLANE_SURF(pipe, 0));
3125 }
3126
3127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3128 static int
3129 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3130 int x, int y, enum mode_set_atomic state)
3131 {
3132 struct drm_device *dev = crtc->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134
3135 if (dev_priv->display.disable_fbc)
3136 dev_priv->display.disable_fbc(dev);
3137
3138 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3139
3140 return 0;
3141 }
3142
3143 static void intel_complete_page_flips(struct drm_device *dev)
3144 {
3145 struct drm_crtc *crtc;
3146
3147 for_each_crtc(dev, crtc) {
3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149 enum plane plane = intel_crtc->plane;
3150
3151 intel_prepare_page_flip(dev, plane);
3152 intel_finish_page_flip_plane(dev, plane);
3153 }
3154 }
3155
3156 static void intel_update_primary_planes(struct drm_device *dev)
3157 {
3158 struct drm_i915_private *dev_priv = dev->dev_private;
3159 struct drm_crtc *crtc;
3160
3161 for_each_crtc(dev, crtc) {
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163
3164 drm_modeset_lock(&crtc->mutex, NULL);
3165 /*
3166 * FIXME: Once we have proper support for primary planes (and
3167 * disabling them without disabling the entire crtc) allow again
3168 * a NULL crtc->primary->fb.
3169 */
3170 if (intel_crtc->active && crtc->primary->fb)
3171 dev_priv->display.update_primary_plane(crtc,
3172 crtc->primary->fb,
3173 crtc->x,
3174 crtc->y);
3175 drm_modeset_unlock(&crtc->mutex);
3176 }
3177 }
3178
3179 void intel_crtc_reset(struct intel_crtc *crtc)
3180 {
3181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3182
3183 if (!crtc->active)
3184 return;
3185
3186 intel_crtc_disable_planes(&crtc->base);
3187 dev_priv->display.crtc_disable(&crtc->base);
3188 dev_priv->display.crtc_enable(&crtc->base);
3189 intel_crtc_enable_planes(&crtc->base);
3190 }
3191
3192 void intel_prepare_reset(struct drm_device *dev)
3193 {
3194 struct drm_i915_private *dev_priv = to_i915(dev);
3195 struct intel_crtc *crtc;
3196
3197 /* no reset support for gen2 */
3198 if (IS_GEN2(dev))
3199 return;
3200
3201 /* reset doesn't touch the display */
3202 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3203 return;
3204
3205 drm_modeset_lock_all(dev);
3206
3207 /*
3208 * Disabling the crtcs gracefully seems nicer. Also the
3209 * g33 docs say we should at least disable all the planes.
3210 */
3211 for_each_intel_crtc(dev, crtc) {
3212 if (!crtc->active)
3213 continue;
3214
3215 intel_crtc_disable_planes(&crtc->base);
3216 dev_priv->display.crtc_disable(&crtc->base);
3217 }
3218 }
3219
3220 void intel_finish_reset(struct drm_device *dev)
3221 {
3222 struct drm_i915_private *dev_priv = to_i915(dev);
3223
3224 /*
3225 * Flips in the rings will be nuked by the reset,
3226 * so complete all pending flips so that user space
3227 * will get its events and not get stuck.
3228 */
3229 intel_complete_page_flips(dev);
3230
3231 /* no reset support for gen2 */
3232 if (IS_GEN2(dev))
3233 return;
3234
3235 /* reset doesn't touch the display */
3236 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3237 /*
3238 * Flips in the rings have been nuked by the reset,
3239 * so update the base address of all primary
3240 * planes to the the last fb to make sure we're
3241 * showing the correct fb after a reset.
3242 */
3243 intel_update_primary_planes(dev);
3244 return;
3245 }
3246
3247 /*
3248 * The display has been reset as well,
3249 * so need a full re-initialization.
3250 */
3251 intel_runtime_pm_disable_interrupts(dev_priv);
3252 intel_runtime_pm_enable_interrupts(dev_priv);
3253
3254 intel_modeset_init_hw(dev);
3255
3256 spin_lock_irq(&dev_priv->irq_lock);
3257 if (dev_priv->display.hpd_irq_setup)
3258 dev_priv->display.hpd_irq_setup(dev);
3259 spin_unlock_irq(&dev_priv->irq_lock);
3260
3261 intel_modeset_setup_hw_state(dev, true);
3262
3263 intel_hpd_init(dev_priv);
3264
3265 drm_modeset_unlock_all(dev);
3266 }
3267
3268 static void
3269 intel_finish_fb(struct drm_framebuffer *old_fb)
3270 {
3271 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3272 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3273 bool was_interruptible = dev_priv->mm.interruptible;
3274 int ret;
3275
3276 /* Big Hammer, we also need to ensure that any pending
3277 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3278 * current scanout is retired before unpinning the old
3279 * framebuffer. Note that we rely on userspace rendering
3280 * into the buffer attached to the pipe they are waiting
3281 * on. If not, userspace generates a GPU hang with IPEHR
3282 * point to the MI_WAIT_FOR_EVENT.
3283 *
3284 * This should only fail upon a hung GPU, in which case we
3285 * can safely continue.
3286 */
3287 dev_priv->mm.interruptible = false;
3288 ret = i915_gem_object_wait_rendering(obj, true);
3289 dev_priv->mm.interruptible = was_interruptible;
3290
3291 WARN_ON(ret);
3292 }
3293
3294 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3295 {
3296 struct drm_device *dev = crtc->dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3299 bool pending;
3300
3301 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3302 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3303 return false;
3304
3305 spin_lock_irq(&dev->event_lock);
3306 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3307 spin_unlock_irq(&dev->event_lock);
3308
3309 return pending;
3310 }
3311
3312 static void intel_update_pipe_size(struct intel_crtc *crtc)
3313 {
3314 struct drm_device *dev = crtc->base.dev;
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 const struct drm_display_mode *adjusted_mode;
3317
3318 if (!i915.fastboot)
3319 return;
3320
3321 /*
3322 * Update pipe size and adjust fitter if needed: the reason for this is
3323 * that in compute_mode_changes we check the native mode (not the pfit
3324 * mode) to see if we can flip rather than do a full mode set. In the
3325 * fastboot case, we'll flip, but if we don't update the pipesrc and
3326 * pfit state, we'll end up with a big fb scanned out into the wrong
3327 * sized surface.
3328 *
3329 * To fix this properly, we need to hoist the checks up into
3330 * compute_mode_changes (or above), check the actual pfit state and
3331 * whether the platform allows pfit disable with pipe active, and only
3332 * then update the pipesrc and pfit state, even on the flip path.
3333 */
3334
3335 adjusted_mode = &crtc->config->base.adjusted_mode;
3336
3337 I915_WRITE(PIPESRC(crtc->pipe),
3338 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3339 (adjusted_mode->crtc_vdisplay - 1));
3340 if (!crtc->config->pch_pfit.enabled &&
3341 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3342 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3343 I915_WRITE(PF_CTL(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3345 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3346 }
3347 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3348 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3349 }
3350
3351 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3352 {
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356 int pipe = intel_crtc->pipe;
3357 u32 reg, temp;
3358
3359 /* enable normal train */
3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 if (IS_IVYBRIDGE(dev)) {
3363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3364 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3365 } else {
3366 temp &= ~FDI_LINK_TRAIN_NONE;
3367 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3368 }
3369 I915_WRITE(reg, temp);
3370
3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (HAS_PCH_CPT(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3376 } else {
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_NONE;
3379 }
3380 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3381
3382 /* wait one idle pattern time */
3383 POSTING_READ(reg);
3384 udelay(1000);
3385
3386 /* IVB wants error correction enabled */
3387 if (IS_IVYBRIDGE(dev))
3388 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3389 FDI_FE_ERRC_ENABLE);
3390 }
3391
3392 /* The FDI link training functions for ILK/Ibexpeak. */
3393 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3394 {
3395 struct drm_device *dev = crtc->dev;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398 int pipe = intel_crtc->pipe;
3399 u32 reg, temp, tries;
3400
3401 /* FDI needs bits from pipe first */
3402 assert_pipe_enabled(dev_priv, pipe);
3403
3404 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3405 for train result */
3406 reg = FDI_RX_IMR(pipe);
3407 temp = I915_READ(reg);
3408 temp &= ~FDI_RX_SYMBOL_LOCK;
3409 temp &= ~FDI_RX_BIT_LOCK;
3410 I915_WRITE(reg, temp);
3411 I915_READ(reg);
3412 udelay(150);
3413
3414 /* enable CPU FDI TX and PCH FDI RX */
3415 reg = FDI_TX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3418 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_1;
3421 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3422
3423 reg = FDI_RX_CTL(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_LINK_TRAIN_NONE;
3426 temp |= FDI_LINK_TRAIN_PATTERN_1;
3427 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3428
3429 POSTING_READ(reg);
3430 udelay(150);
3431
3432 /* Ironlake workaround, enable clock pointer after FDI enable*/
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3434 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3435 FDI_RX_PHASE_SYNC_POINTER_EN);
3436
3437 reg = FDI_RX_IIR(pipe);
3438 for (tries = 0; tries < 5; tries++) {
3439 temp = I915_READ(reg);
3440 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3441
3442 if ((temp & FDI_RX_BIT_LOCK)) {
3443 DRM_DEBUG_KMS("FDI train 1 done.\n");
3444 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3445 break;
3446 }
3447 }
3448 if (tries == 5)
3449 DRM_ERROR("FDI train 1 fail!\n");
3450
3451 /* Train 2 */
3452 reg = FDI_TX_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~FDI_LINK_TRAIN_NONE;
3455 temp |= FDI_LINK_TRAIN_PATTERN_2;
3456 I915_WRITE(reg, temp);
3457
3458 reg = FDI_RX_CTL(pipe);
3459 temp = I915_READ(reg);
3460 temp &= ~FDI_LINK_TRAIN_NONE;
3461 temp |= FDI_LINK_TRAIN_PATTERN_2;
3462 I915_WRITE(reg, temp);
3463
3464 POSTING_READ(reg);
3465 udelay(150);
3466
3467 reg = FDI_RX_IIR(pipe);
3468 for (tries = 0; tries < 5; tries++) {
3469 temp = I915_READ(reg);
3470 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3471
3472 if (temp & FDI_RX_SYMBOL_LOCK) {
3473 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3474 DRM_DEBUG_KMS("FDI train 2 done.\n");
3475 break;
3476 }
3477 }
3478 if (tries == 5)
3479 DRM_ERROR("FDI train 2 fail!\n");
3480
3481 DRM_DEBUG_KMS("FDI train done\n");
3482
3483 }
3484
3485 static const int snb_b_fdi_train_param[] = {
3486 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3487 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3488 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3489 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3490 };
3491
3492 /* The FDI link training functions for SNB/Cougarpoint. */
3493 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3494 {
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 int pipe = intel_crtc->pipe;
3499 u32 reg, temp, i, retry;
3500
3501 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502 for train result */
3503 reg = FDI_RX_IMR(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_RX_SYMBOL_LOCK;
3506 temp &= ~FDI_RX_BIT_LOCK;
3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
3510 udelay(150);
3511
3512 /* enable CPU FDI TX and PCH FDI RX */
3513 reg = FDI_TX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517 temp &= ~FDI_LINK_TRAIN_NONE;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1;
3519 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520 /* SNB-B */
3521 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3523
3524 I915_WRITE(FDI_RX_MISC(pipe),
3525 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3526
3527 reg = FDI_RX_CTL(pipe);
3528 temp = I915_READ(reg);
3529 if (HAS_PCH_CPT(dev)) {
3530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3532 } else {
3533 temp &= ~FDI_LINK_TRAIN_NONE;
3534 temp |= FDI_LINK_TRAIN_PATTERN_1;
3535 }
3536 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3537
3538 POSTING_READ(reg);
3539 udelay(150);
3540
3541 for (i = 0; i < 4; i++) {
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545 temp |= snb_b_fdi_train_param[i];
3546 I915_WRITE(reg, temp);
3547
3548 POSTING_READ(reg);
3549 udelay(500);
3550
3551 for (retry = 0; retry < 5; retry++) {
3552 reg = FDI_RX_IIR(pipe);
3553 temp = I915_READ(reg);
3554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555 if (temp & FDI_RX_BIT_LOCK) {
3556 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558 break;
3559 }
3560 udelay(50);
3561 }
3562 if (retry < 5)
3563 break;
3564 }
3565 if (i == 4)
3566 DRM_ERROR("FDI train 1 fail!\n");
3567
3568 /* Train 2 */
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573 if (IS_GEN6(dev)) {
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 /* SNB-B */
3576 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577 }
3578 I915_WRITE(reg, temp);
3579
3580 reg = FDI_RX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 if (HAS_PCH_CPT(dev)) {
3583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3585 } else {
3586 temp &= ~FDI_LINK_TRAIN_NONE;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2;
3588 }
3589 I915_WRITE(reg, temp);
3590
3591 POSTING_READ(reg);
3592 udelay(150);
3593
3594 for (i = 0; i < 4; i++) {
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598 temp |= snb_b_fdi_train_param[i];
3599 I915_WRITE(reg, temp);
3600
3601 POSTING_READ(reg);
3602 udelay(500);
3603
3604 for (retry = 0; retry < 5; retry++) {
3605 reg = FDI_RX_IIR(pipe);
3606 temp = I915_READ(reg);
3607 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608 if (temp & FDI_RX_SYMBOL_LOCK) {
3609 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611 break;
3612 }
3613 udelay(50);
3614 }
3615 if (retry < 5)
3616 break;
3617 }
3618 if (i == 4)
3619 DRM_ERROR("FDI train 2 fail!\n");
3620
3621 DRM_DEBUG_KMS("FDI train done.\n");
3622 }
3623
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3626 {
3627 struct drm_device *dev = crtc->dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630 int pipe = intel_crtc->pipe;
3631 u32 reg, temp, i, j;
3632
3633 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634 for train result */
3635 reg = FDI_RX_IMR(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_RX_SYMBOL_LOCK;
3638 temp &= ~FDI_RX_BIT_LOCK;
3639 I915_WRITE(reg, temp);
3640
3641 POSTING_READ(reg);
3642 udelay(150);
3643
3644 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3645 I915_READ(FDI_RX_IIR(pipe)));
3646
3647 /* Try each vswing and preemphasis setting twice before moving on */
3648 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3649 /* disable first in case we need to retry */
3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3653 temp &= ~FDI_TX_ENABLE;
3654 I915_WRITE(reg, temp);
3655
3656 reg = FDI_RX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 temp &= ~FDI_LINK_TRAIN_AUTO;
3659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3660 temp &= ~FDI_RX_ENABLE;
3661 I915_WRITE(reg, temp);
3662
3663 /* enable CPU FDI TX and PCH FDI RX */
3664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3667 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3668 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3669 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3670 temp |= snb_b_fdi_train_param[j/2];
3671 temp |= FDI_COMPOSITE_SYNC;
3672 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3673
3674 I915_WRITE(FDI_RX_MISC(pipe),
3675 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3676
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3680 temp |= FDI_COMPOSITE_SYNC;
3681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3682
3683 POSTING_READ(reg);
3684 udelay(1); /* should be 0.5us */
3685
3686 for (i = 0; i < 4; i++) {
3687 reg = FDI_RX_IIR(pipe);
3688 temp = I915_READ(reg);
3689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3690
3691 if (temp & FDI_RX_BIT_LOCK ||
3692 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3693 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3694 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3695 i);
3696 break;
3697 }
3698 udelay(1); /* should be 0.5us */
3699 }
3700 if (i == 4) {
3701 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3702 continue;
3703 }
3704
3705 /* Train 2 */
3706 reg = FDI_TX_CTL(pipe);
3707 temp = I915_READ(reg);
3708 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3709 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3710 I915_WRITE(reg, temp);
3711
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3716 I915_WRITE(reg, temp);
3717
3718 POSTING_READ(reg);
3719 udelay(2); /* should be 1.5us */
3720
3721 for (i = 0; i < 4; i++) {
3722 reg = FDI_RX_IIR(pipe);
3723 temp = I915_READ(reg);
3724 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3725
3726 if (temp & FDI_RX_SYMBOL_LOCK ||
3727 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3728 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3729 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3730 i);
3731 goto train_done;
3732 }
3733 udelay(2); /* should be 1.5us */
3734 }
3735 if (i == 4)
3736 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3737 }
3738
3739 train_done:
3740 DRM_DEBUG_KMS("FDI train done.\n");
3741 }
3742
3743 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3744 {
3745 struct drm_device *dev = intel_crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 int pipe = intel_crtc->pipe;
3748 u32 reg, temp;
3749
3750
3751 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3752 reg = FDI_RX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3755 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3756 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3758
3759 POSTING_READ(reg);
3760 udelay(200);
3761
3762 /* Switch from Rawclk to PCDclk */
3763 temp = I915_READ(reg);
3764 I915_WRITE(reg, temp | FDI_PCDCLK);
3765
3766 POSTING_READ(reg);
3767 udelay(200);
3768
3769 /* Enable CPU FDI TX PLL, always on for Ironlake */
3770 reg = FDI_TX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3773 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3774
3775 POSTING_READ(reg);
3776 udelay(100);
3777 }
3778 }
3779
3780 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3781 {
3782 struct drm_device *dev = intel_crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 int pipe = intel_crtc->pipe;
3785 u32 reg, temp;
3786
3787 /* Switch from PCDclk to Rawclk */
3788 reg = FDI_RX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3791
3792 /* Disable CPU FDI TX PLL */
3793 reg = FDI_TX_CTL(pipe);
3794 temp = I915_READ(reg);
3795 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3796
3797 POSTING_READ(reg);
3798 udelay(100);
3799
3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3803
3804 /* Wait for the clocks to turn off. */
3805 POSTING_READ(reg);
3806 udelay(100);
3807 }
3808
3809 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3810 {
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814 int pipe = intel_crtc->pipe;
3815 u32 reg, temp;
3816
3817 /* disable CPU FDI tx and PCH FDI rx */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3821 POSTING_READ(reg);
3822
3823 reg = FDI_RX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 temp &= ~(0x7 << 16);
3826 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3827 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3828
3829 POSTING_READ(reg);
3830 udelay(100);
3831
3832 /* Ironlake workaround, disable clock pointer after downing FDI */
3833 if (HAS_PCH_IBX(dev))
3834 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3835
3836 /* still set train pattern 1 */
3837 reg = FDI_TX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 temp &= ~FDI_LINK_TRAIN_NONE;
3840 temp |= FDI_LINK_TRAIN_PATTERN_1;
3841 I915_WRITE(reg, temp);
3842
3843 reg = FDI_RX_CTL(pipe);
3844 temp = I915_READ(reg);
3845 if (HAS_PCH_CPT(dev)) {
3846 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3847 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3848 } else {
3849 temp &= ~FDI_LINK_TRAIN_NONE;
3850 temp |= FDI_LINK_TRAIN_PATTERN_1;
3851 }
3852 /* BPC in FDI rx is consistent with that in PIPECONF */
3853 temp &= ~(0x07 << 16);
3854 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3855 I915_WRITE(reg, temp);
3856
3857 POSTING_READ(reg);
3858 udelay(100);
3859 }
3860
3861 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3862 {
3863 struct intel_crtc *crtc;
3864
3865 /* Note that we don't need to be called with mode_config.lock here
3866 * as our list of CRTC objects is static for the lifetime of the
3867 * device and so cannot disappear as we iterate. Similarly, we can
3868 * happily treat the predicates as racy, atomic checks as userspace
3869 * cannot claim and pin a new fb without at least acquring the
3870 * struct_mutex and so serialising with us.
3871 */
3872 for_each_intel_crtc(dev, crtc) {
3873 if (atomic_read(&crtc->unpin_work_count) == 0)
3874 continue;
3875
3876 if (crtc->unpin_work)
3877 intel_wait_for_vblank(dev, crtc->pipe);
3878
3879 return true;
3880 }
3881
3882 return false;
3883 }
3884
3885 static void page_flip_completed(struct intel_crtc *intel_crtc)
3886 {
3887 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3888 struct intel_unpin_work *work = intel_crtc->unpin_work;
3889
3890 /* ensure that the unpin work is consistent wrt ->pending. */
3891 smp_rmb();
3892 intel_crtc->unpin_work = NULL;
3893
3894 if (work->event)
3895 drm_send_vblank_event(intel_crtc->base.dev,
3896 intel_crtc->pipe,
3897 work->event);
3898
3899 drm_crtc_vblank_put(&intel_crtc->base);
3900
3901 wake_up_all(&dev_priv->pending_flip_queue);
3902 queue_work(dev_priv->wq, &work->work);
3903
3904 trace_i915_flip_complete(intel_crtc->plane,
3905 work->pending_flip_obj);
3906 }
3907
3908 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3909 {
3910 struct drm_device *dev = crtc->dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3912
3913 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3914 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3915 !intel_crtc_has_pending_flip(crtc),
3916 60*HZ) == 0)) {
3917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918
3919 spin_lock_irq(&dev->event_lock);
3920 if (intel_crtc->unpin_work) {
3921 WARN_ONCE(1, "Removing stuck page flip\n");
3922 page_flip_completed(intel_crtc);
3923 }
3924 spin_unlock_irq(&dev->event_lock);
3925 }
3926
3927 if (crtc->primary->fb) {
3928 mutex_lock(&dev->struct_mutex);
3929 intel_finish_fb(crtc->primary->fb);
3930 mutex_unlock(&dev->struct_mutex);
3931 }
3932 }
3933
3934 /* Program iCLKIP clock to the desired frequency */
3935 static void lpt_program_iclkip(struct drm_crtc *crtc)
3936 {
3937 struct drm_device *dev = crtc->dev;
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3940 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3941 u32 temp;
3942
3943 mutex_lock(&dev_priv->sb_lock);
3944
3945 /* It is necessary to ungate the pixclk gate prior to programming
3946 * the divisors, and gate it back when it is done.
3947 */
3948 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3949
3950 /* Disable SSCCTL */
3951 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3952 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3953 SBI_SSCCTL_DISABLE,
3954 SBI_ICLK);
3955
3956 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3957 if (clock == 20000) {
3958 auxdiv = 1;
3959 divsel = 0x41;
3960 phaseinc = 0x20;
3961 } else {
3962 /* The iCLK virtual clock root frequency is in MHz,
3963 * but the adjusted_mode->crtc_clock in in KHz. To get the
3964 * divisors, it is necessary to divide one by another, so we
3965 * convert the virtual clock precision to KHz here for higher
3966 * precision.
3967 */
3968 u32 iclk_virtual_root_freq = 172800 * 1000;
3969 u32 iclk_pi_range = 64;
3970 u32 desired_divisor, msb_divisor_value, pi_value;
3971
3972 desired_divisor = (iclk_virtual_root_freq / clock);
3973 msb_divisor_value = desired_divisor / iclk_pi_range;
3974 pi_value = desired_divisor % iclk_pi_range;
3975
3976 auxdiv = 0;
3977 divsel = msb_divisor_value - 2;
3978 phaseinc = pi_value;
3979 }
3980
3981 /* This should not happen with any sane values */
3982 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3983 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3984 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3985 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3986
3987 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3988 clock,
3989 auxdiv,
3990 divsel,
3991 phasedir,
3992 phaseinc);
3993
3994 /* Program SSCDIVINTPHASE6 */
3995 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3996 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3997 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3998 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3999 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4000 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4001 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4002 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4003
4004 /* Program SSCAUXDIV */
4005 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4006 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4007 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4008 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4009
4010 /* Enable modulator and associated divider */
4011 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4012 temp &= ~SBI_SSCCTL_DISABLE;
4013 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4014
4015 /* Wait for initialization time */
4016 udelay(24);
4017
4018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4019
4020 mutex_unlock(&dev_priv->sb_lock);
4021 }
4022
4023 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4024 enum pipe pch_transcoder)
4025 {
4026 struct drm_device *dev = crtc->base.dev;
4027 struct drm_i915_private *dev_priv = dev->dev_private;
4028 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4029
4030 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4031 I915_READ(HTOTAL(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4033 I915_READ(HBLANK(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4035 I915_READ(HSYNC(cpu_transcoder)));
4036
4037 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4038 I915_READ(VTOTAL(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4040 I915_READ(VBLANK(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4042 I915_READ(VSYNC(cpu_transcoder)));
4043 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4044 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4045 }
4046
4047 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4048 {
4049 struct drm_i915_private *dev_priv = dev->dev_private;
4050 uint32_t temp;
4051
4052 temp = I915_READ(SOUTH_CHICKEN1);
4053 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4054 return;
4055
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4058
4059 temp &= ~FDI_BC_BIFURCATION_SELECT;
4060 if (enable)
4061 temp |= FDI_BC_BIFURCATION_SELECT;
4062
4063 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4064 I915_WRITE(SOUTH_CHICKEN1, temp);
4065 POSTING_READ(SOUTH_CHICKEN1);
4066 }
4067
4068 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4069 {
4070 struct drm_device *dev = intel_crtc->base.dev;
4071
4072 switch (intel_crtc->pipe) {
4073 case PIPE_A:
4074 break;
4075 case PIPE_B:
4076 if (intel_crtc->config->fdi_lanes > 2)
4077 cpt_set_fdi_bc_bifurcation(dev, false);
4078 else
4079 cpt_set_fdi_bc_bifurcation(dev, true);
4080
4081 break;
4082 case PIPE_C:
4083 cpt_set_fdi_bc_bifurcation(dev, true);
4084
4085 break;
4086 default:
4087 BUG();
4088 }
4089 }
4090
4091 /*
4092 * Enable PCH resources required for PCH ports:
4093 * - PCH PLLs
4094 * - FDI training & RX/TX
4095 * - update transcoder timings
4096 * - DP transcoding bits
4097 * - transcoder
4098 */
4099 static void ironlake_pch_enable(struct drm_crtc *crtc)
4100 {
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104 int pipe = intel_crtc->pipe;
4105 u32 reg, temp;
4106
4107 assert_pch_transcoder_disabled(dev_priv, pipe);
4108
4109 if (IS_IVYBRIDGE(dev))
4110 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4111
4112 /* Write the TU size bits before fdi link training, so that error
4113 * detection works. */
4114 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4115 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4116
4117 /* For PCH output, training FDI link */
4118 dev_priv->display.fdi_link_train(crtc);
4119
4120 /* We need to program the right clock selection before writing the pixel
4121 * mutliplier into the DPLL. */
4122 if (HAS_PCH_CPT(dev)) {
4123 u32 sel;
4124
4125 temp = I915_READ(PCH_DPLL_SEL);
4126 temp |= TRANS_DPLL_ENABLE(pipe);
4127 sel = TRANS_DPLLB_SEL(pipe);
4128 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4129 temp |= sel;
4130 else
4131 temp &= ~sel;
4132 I915_WRITE(PCH_DPLL_SEL, temp);
4133 }
4134
4135 /* XXX: pch pll's can be enabled any time before we enable the PCH
4136 * transcoder, and we actually should do this to not upset any PCH
4137 * transcoder that already use the clock when we share it.
4138 *
4139 * Note that enable_shared_dpll tries to do the right thing, but
4140 * get_shared_dpll unconditionally resets the pll - we need that to have
4141 * the right LVDS enable sequence. */
4142 intel_enable_shared_dpll(intel_crtc);
4143
4144 /* set transcoder timing, panel must allow it */
4145 assert_panel_unlocked(dev_priv, pipe);
4146 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4147
4148 intel_fdi_normal_train(crtc);
4149
4150 /* For PCH DP, enable TRANS_DP_CTL */
4151 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4152 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4153 reg = TRANS_DP_CTL(pipe);
4154 temp = I915_READ(reg);
4155 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4156 TRANS_DP_SYNC_MASK |
4157 TRANS_DP_BPC_MASK);
4158 temp |= TRANS_DP_OUTPUT_ENABLE;
4159 temp |= bpc << 9; /* same format but at 11:9 */
4160
4161 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4162 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4163 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4164 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4165
4166 switch (intel_trans_dp_port_sel(crtc)) {
4167 case PCH_DP_B:
4168 temp |= TRANS_DP_PORT_SEL_B;
4169 break;
4170 case PCH_DP_C:
4171 temp |= TRANS_DP_PORT_SEL_C;
4172 break;
4173 case PCH_DP_D:
4174 temp |= TRANS_DP_PORT_SEL_D;
4175 break;
4176 default:
4177 BUG();
4178 }
4179
4180 I915_WRITE(reg, temp);
4181 }
4182
4183 ironlake_enable_pch_transcoder(dev_priv, pipe);
4184 }
4185
4186 static void lpt_pch_enable(struct drm_crtc *crtc)
4187 {
4188 struct drm_device *dev = crtc->dev;
4189 struct drm_i915_private *dev_priv = dev->dev_private;
4190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4192
4193 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4194
4195 lpt_program_iclkip(crtc);
4196
4197 /* Set transcoder timing. */
4198 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4199
4200 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4201 }
4202
4203 void intel_put_shared_dpll(struct intel_crtc *crtc)
4204 {
4205 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4206
4207 if (pll == NULL)
4208 return;
4209
4210 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4211 WARN(1, "bad %s crtc mask\n", pll->name);
4212 return;
4213 }
4214
4215 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4216 if (pll->config.crtc_mask == 0) {
4217 WARN_ON(pll->on);
4218 WARN_ON(pll->active);
4219 }
4220
4221 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4222 }
4223
4224 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4225 struct intel_crtc_state *crtc_state)
4226 {
4227 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4228 struct intel_shared_dpll *pll;
4229 enum intel_dpll_id i;
4230
4231 if (HAS_PCH_IBX(dev_priv->dev)) {
4232 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4233 i = (enum intel_dpll_id) crtc->pipe;
4234 pll = &dev_priv->shared_dplls[i];
4235
4236 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4237 crtc->base.base.id, pll->name);
4238
4239 WARN_ON(pll->new_config->crtc_mask);
4240
4241 goto found;
4242 }
4243
4244 if (IS_BROXTON(dev_priv->dev)) {
4245 /* PLL is attached to port in bxt */
4246 struct intel_encoder *encoder;
4247 struct intel_digital_port *intel_dig_port;
4248
4249 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4250 if (WARN_ON(!encoder))
4251 return NULL;
4252
4253 intel_dig_port = enc_to_dig_port(&encoder->base);
4254 /* 1:1 mapping between ports and PLLs */
4255 i = (enum intel_dpll_id)intel_dig_port->port;
4256 pll = &dev_priv->shared_dplls[i];
4257 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4258 crtc->base.base.id, pll->name);
4259 WARN_ON(pll->new_config->crtc_mask);
4260
4261 goto found;
4262 }
4263
4264 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4265 pll = &dev_priv->shared_dplls[i];
4266
4267 /* Only want to check enabled timings first */
4268 if (pll->new_config->crtc_mask == 0)
4269 continue;
4270
4271 if (memcmp(&crtc_state->dpll_hw_state,
4272 &pll->new_config->hw_state,
4273 sizeof(pll->new_config->hw_state)) == 0) {
4274 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4275 crtc->base.base.id, pll->name,
4276 pll->new_config->crtc_mask,
4277 pll->active);
4278 goto found;
4279 }
4280 }
4281
4282 /* Ok no matching timings, maybe there's a free one? */
4283 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4284 pll = &dev_priv->shared_dplls[i];
4285 if (pll->new_config->crtc_mask == 0) {
4286 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4287 crtc->base.base.id, pll->name);
4288 goto found;
4289 }
4290 }
4291
4292 return NULL;
4293
4294 found:
4295 if (pll->new_config->crtc_mask == 0)
4296 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4297
4298 crtc_state->shared_dpll = i;
4299 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4300 pipe_name(crtc->pipe));
4301
4302 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4303
4304 return pll;
4305 }
4306
4307 /**
4308 * intel_shared_dpll_start_config - start a new PLL staged config
4309 * @dev_priv: DRM device
4310 * @clear_pipes: mask of pipes that will have their PLLs freed
4311 *
4312 * Starts a new PLL staged config, copying the current config but
4313 * releasing the references of pipes specified in clear_pipes.
4314 */
4315 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4316 unsigned clear_pipes)
4317 {
4318 struct intel_shared_dpll *pll;
4319 enum intel_dpll_id i;
4320
4321 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4322 pll = &dev_priv->shared_dplls[i];
4323
4324 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4325 GFP_KERNEL);
4326 if (!pll->new_config)
4327 goto cleanup;
4328
4329 pll->new_config->crtc_mask &= ~clear_pipes;
4330 }
4331
4332 return 0;
4333
4334 cleanup:
4335 while (--i >= 0) {
4336 pll = &dev_priv->shared_dplls[i];
4337 kfree(pll->new_config);
4338 pll->new_config = NULL;
4339 }
4340
4341 return -ENOMEM;
4342 }
4343
4344 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4345 {
4346 struct intel_shared_dpll *pll;
4347 enum intel_dpll_id i;
4348
4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
4351
4352 WARN_ON(pll->new_config == &pll->config);
4353
4354 pll->config = *pll->new_config;
4355 kfree(pll->new_config);
4356 pll->new_config = NULL;
4357 }
4358 }
4359
4360 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4361 {
4362 struct intel_shared_dpll *pll;
4363 enum intel_dpll_id i;
4364
4365 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4366 pll = &dev_priv->shared_dplls[i];
4367
4368 WARN_ON(pll->new_config == &pll->config);
4369
4370 kfree(pll->new_config);
4371 pll->new_config = NULL;
4372 }
4373 }
4374
4375 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4376 {
4377 struct drm_i915_private *dev_priv = dev->dev_private;
4378 int dslreg = PIPEDSL(pipe);
4379 u32 temp;
4380
4381 temp = I915_READ(dslreg);
4382 udelay(500);
4383 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4384 if (wait_for(I915_READ(dslreg) != temp, 5))
4385 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4386 }
4387 }
4388
4389 /**
4390 * skl_update_scaler_users - Stages update to crtc's scaler state
4391 * @intel_crtc: crtc
4392 * @crtc_state: crtc_state
4393 * @plane: plane (NULL indicates crtc is requesting update)
4394 * @plane_state: plane's state
4395 * @force_detach: request unconditional detachment of scaler
4396 *
4397 * This function updates scaler state for requested plane or crtc.
4398 * To request scaler usage update for a plane, caller shall pass plane pointer.
4399 * To request scaler usage update for crtc, caller shall pass plane pointer
4400 * as NULL.
4401 *
4402 * Return
4403 * 0 - scaler_usage updated successfully
4404 * error - requested scaling cannot be supported or other error condition
4405 */
4406 int
4407 skl_update_scaler_users(
4408 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4409 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4410 int force_detach)
4411 {
4412 int need_scaling;
4413 int idx;
4414 int src_w, src_h, dst_w, dst_h;
4415 int *scaler_id;
4416 struct drm_framebuffer *fb;
4417 struct intel_crtc_scaler_state *scaler_state;
4418 unsigned int rotation;
4419
4420 if (!intel_crtc || !crtc_state)
4421 return 0;
4422
4423 scaler_state = &crtc_state->scaler_state;
4424
4425 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4426 fb = intel_plane ? plane_state->base.fb : NULL;
4427
4428 if (intel_plane) {
4429 src_w = drm_rect_width(&plane_state->src) >> 16;
4430 src_h = drm_rect_height(&plane_state->src) >> 16;
4431 dst_w = drm_rect_width(&plane_state->dst);
4432 dst_h = drm_rect_height(&plane_state->dst);
4433 scaler_id = &plane_state->scaler_id;
4434 rotation = plane_state->base.rotation;
4435 } else {
4436 struct drm_display_mode *adjusted_mode =
4437 &crtc_state->base.adjusted_mode;
4438 src_w = crtc_state->pipe_src_w;
4439 src_h = crtc_state->pipe_src_h;
4440 dst_w = adjusted_mode->hdisplay;
4441 dst_h = adjusted_mode->vdisplay;
4442 scaler_id = &scaler_state->scaler_id;
4443 rotation = DRM_ROTATE_0;
4444 }
4445
4446 need_scaling = intel_rotation_90_or_270(rotation) ?
4447 (src_h != dst_w || src_w != dst_h):
4448 (src_w != dst_w || src_h != dst_h);
4449
4450 /*
4451 * if plane is being disabled or scaler is no more required or force detach
4452 * - free scaler binded to this plane/crtc
4453 * - in order to do this, update crtc->scaler_usage
4454 *
4455 * Here scaler state in crtc_state is set free so that
4456 * scaler can be assigned to other user. Actual register
4457 * update to free the scaler is done in plane/panel-fit programming.
4458 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4459 */
4460 if (force_detach || !need_scaling || (intel_plane &&
4461 (!fb || !plane_state->visible))) {
4462 if (*scaler_id >= 0) {
4463 scaler_state->scaler_users &= ~(1 << idx);
4464 scaler_state->scalers[*scaler_id].in_use = 0;
4465
4466 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4467 "crtc_state = %p scaler_users = 0x%x\n",
4468 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4469 intel_plane ? intel_plane->base.base.id :
4470 intel_crtc->base.base.id, crtc_state,
4471 scaler_state->scaler_users);
4472 *scaler_id = -1;
4473 }
4474 return 0;
4475 }
4476
4477 /* range checks */
4478 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4479 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4480
4481 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4482 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4483 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4484 "size is out of scaler range\n",
4485 intel_plane ? "PLANE" : "CRTC",
4486 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4487 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4488 return -EINVAL;
4489 }
4490
4491 /* check colorkey */
4492 if (WARN_ON(intel_plane &&
4493 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4494 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4495 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4496 return -EINVAL;
4497 }
4498
4499 /* Check src format */
4500 if (intel_plane) {
4501 switch (fb->pixel_format) {
4502 case DRM_FORMAT_RGB565:
4503 case DRM_FORMAT_XBGR8888:
4504 case DRM_FORMAT_XRGB8888:
4505 case DRM_FORMAT_ABGR8888:
4506 case DRM_FORMAT_ARGB8888:
4507 case DRM_FORMAT_XRGB2101010:
4508 case DRM_FORMAT_XBGR2101010:
4509 case DRM_FORMAT_YUYV:
4510 case DRM_FORMAT_YVYU:
4511 case DRM_FORMAT_UYVY:
4512 case DRM_FORMAT_VYUY:
4513 break;
4514 default:
4515 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4516 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4517 return -EINVAL;
4518 }
4519 }
4520
4521 /* mark this plane as a scaler user in crtc_state */
4522 scaler_state->scaler_users |= (1 << idx);
4523 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4524 "crtc_state = %p scaler_users = 0x%x\n",
4525 intel_plane ? "PLANE" : "CRTC",
4526 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4527 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4528 return 0;
4529 }
4530
4531 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4532 {
4533 struct drm_device *dev = crtc->base.dev;
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 int pipe = crtc->pipe;
4536 struct intel_crtc_scaler_state *scaler_state =
4537 &crtc->config->scaler_state;
4538
4539 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4540
4541 /* To update pfit, first update scaler state */
4542 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4543 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4544 skl_detach_scalers(crtc);
4545 if (!enable)
4546 return;
4547
4548 if (crtc->config->pch_pfit.enabled) {
4549 int id;
4550
4551 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4552 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4553 return;
4554 }
4555
4556 id = scaler_state->scaler_id;
4557 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4558 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4559 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4560 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4561
4562 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4563 }
4564 }
4565
4566 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4567 {
4568 struct drm_device *dev = crtc->base.dev;
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 int pipe = crtc->pipe;
4571
4572 if (crtc->config->pch_pfit.enabled) {
4573 /* Force use of hard-coded filter coefficients
4574 * as some pre-programmed values are broken,
4575 * e.g. x201.
4576 */
4577 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4578 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4579 PF_PIPE_SEL_IVB(pipe));
4580 else
4581 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4582 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4583 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4584 }
4585 }
4586
4587 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4588 {
4589 struct drm_device *dev = crtc->dev;
4590 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4591 struct drm_plane *plane;
4592 struct intel_plane *intel_plane;
4593
4594 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4595 intel_plane = to_intel_plane(plane);
4596 if (intel_plane->pipe == pipe)
4597 intel_plane_restore(&intel_plane->base);
4598 }
4599 }
4600
4601 void hsw_enable_ips(struct intel_crtc *crtc)
4602 {
4603 struct drm_device *dev = crtc->base.dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606 if (!crtc->config->ips_enabled)
4607 return;
4608
4609 /* We can only enable IPS after we enable a plane and wait for a vblank */
4610 intel_wait_for_vblank(dev, crtc->pipe);
4611
4612 assert_plane_enabled(dev_priv, crtc->plane);
4613 if (IS_BROADWELL(dev)) {
4614 mutex_lock(&dev_priv->rps.hw_lock);
4615 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4616 mutex_unlock(&dev_priv->rps.hw_lock);
4617 /* Quoting Art Runyan: "its not safe to expect any particular
4618 * value in IPS_CTL bit 31 after enabling IPS through the
4619 * mailbox." Moreover, the mailbox may return a bogus state,
4620 * so we need to just enable it and continue on.
4621 */
4622 } else {
4623 I915_WRITE(IPS_CTL, IPS_ENABLE);
4624 /* The bit only becomes 1 in the next vblank, so this wait here
4625 * is essentially intel_wait_for_vblank. If we don't have this
4626 * and don't wait for vblanks until the end of crtc_enable, then
4627 * the HW state readout code will complain that the expected
4628 * IPS_CTL value is not the one we read. */
4629 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4630 DRM_ERROR("Timed out waiting for IPS enable\n");
4631 }
4632 }
4633
4634 void hsw_disable_ips(struct intel_crtc *crtc)
4635 {
4636 struct drm_device *dev = crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639 if (!crtc->config->ips_enabled)
4640 return;
4641
4642 assert_plane_enabled(dev_priv, crtc->plane);
4643 if (IS_BROADWELL(dev)) {
4644 mutex_lock(&dev_priv->rps.hw_lock);
4645 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4646 mutex_unlock(&dev_priv->rps.hw_lock);
4647 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4648 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4649 DRM_ERROR("Timed out waiting for IPS disable\n");
4650 } else {
4651 I915_WRITE(IPS_CTL, 0);
4652 POSTING_READ(IPS_CTL);
4653 }
4654
4655 /* We need to wait for a vblank before we can disable the plane. */
4656 intel_wait_for_vblank(dev, crtc->pipe);
4657 }
4658
4659 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4660 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4661 {
4662 struct drm_device *dev = crtc->dev;
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4665 enum pipe pipe = intel_crtc->pipe;
4666 int palreg = PALETTE(pipe);
4667 int i;
4668 bool reenable_ips = false;
4669
4670 /* The clocks have to be on to load the palette. */
4671 if (!crtc->state->enable || !intel_crtc->active)
4672 return;
4673
4674 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4675 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4676 assert_dsi_pll_enabled(dev_priv);
4677 else
4678 assert_pll_enabled(dev_priv, pipe);
4679 }
4680
4681 /* use legacy palette for Ironlake */
4682 if (!HAS_GMCH_DISPLAY(dev))
4683 palreg = LGC_PALETTE(pipe);
4684
4685 /* Workaround : Do not read or write the pipe palette/gamma data while
4686 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4687 */
4688 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4689 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4690 GAMMA_MODE_MODE_SPLIT)) {
4691 hsw_disable_ips(intel_crtc);
4692 reenable_ips = true;
4693 }
4694
4695 for (i = 0; i < 256; i++) {
4696 I915_WRITE(palreg + 4 * i,
4697 (intel_crtc->lut_r[i] << 16) |
4698 (intel_crtc->lut_g[i] << 8) |
4699 intel_crtc->lut_b[i]);
4700 }
4701
4702 if (reenable_ips)
4703 hsw_enable_ips(intel_crtc);
4704 }
4705
4706 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4707 {
4708 if (intel_crtc->overlay) {
4709 struct drm_device *dev = intel_crtc->base.dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711
4712 mutex_lock(&dev->struct_mutex);
4713 dev_priv->mm.interruptible = false;
4714 (void) intel_overlay_switch_off(intel_crtc->overlay);
4715 dev_priv->mm.interruptible = true;
4716 mutex_unlock(&dev->struct_mutex);
4717 }
4718
4719 /* Let userspace switch the overlay on again. In most cases userspace
4720 * has to recompute where to put it anyway.
4721 */
4722 }
4723
4724 /**
4725 * intel_post_enable_primary - Perform operations after enabling primary plane
4726 * @crtc: the CRTC whose primary plane was just enabled
4727 *
4728 * Performs potentially sleeping operations that must be done after the primary
4729 * plane is enabled, such as updating FBC and IPS. Note that this may be
4730 * called due to an explicit primary plane update, or due to an implicit
4731 * re-enable that is caused when a sprite plane is updated to no longer
4732 * completely hide the primary plane.
4733 */
4734 static void
4735 intel_post_enable_primary(struct drm_crtc *crtc)
4736 {
4737 struct drm_device *dev = crtc->dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740 int pipe = intel_crtc->pipe;
4741
4742 /*
4743 * BDW signals flip done immediately if the plane
4744 * is disabled, even if the plane enable is already
4745 * armed to occur at the next vblank :(
4746 */
4747 if (IS_BROADWELL(dev))
4748 intel_wait_for_vblank(dev, pipe);
4749
4750 /*
4751 * FIXME IPS should be fine as long as one plane is
4752 * enabled, but in practice it seems to have problems
4753 * when going from primary only to sprite only and vice
4754 * versa.
4755 */
4756 hsw_enable_ips(intel_crtc);
4757
4758 mutex_lock(&dev->struct_mutex);
4759 intel_fbc_update(dev);
4760 mutex_unlock(&dev->struct_mutex);
4761
4762 /*
4763 * Gen2 reports pipe underruns whenever all planes are disabled.
4764 * So don't enable underrun reporting before at least some planes
4765 * are enabled.
4766 * FIXME: Need to fix the logic to work when we turn off all planes
4767 * but leave the pipe running.
4768 */
4769 if (IS_GEN2(dev))
4770 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4771
4772 /* Underruns don't raise interrupts, so check manually. */
4773 if (HAS_GMCH_DISPLAY(dev))
4774 i9xx_check_fifo_underruns(dev_priv);
4775 }
4776
4777 /**
4778 * intel_pre_disable_primary - Perform operations before disabling primary plane
4779 * @crtc: the CRTC whose primary plane is to be disabled
4780 *
4781 * Performs potentially sleeping operations that must be done before the
4782 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4783 * be called due to an explicit primary plane update, or due to an implicit
4784 * disable that is caused when a sprite plane completely hides the primary
4785 * plane.
4786 */
4787 static void
4788 intel_pre_disable_primary(struct drm_crtc *crtc)
4789 {
4790 struct drm_device *dev = crtc->dev;
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4793 int pipe = intel_crtc->pipe;
4794
4795 /*
4796 * Gen2 reports pipe underruns whenever all planes are disabled.
4797 * So diasble underrun reporting before all the planes get disabled.
4798 * FIXME: Need to fix the logic to work when we turn off all planes
4799 * but leave the pipe running.
4800 */
4801 if (IS_GEN2(dev))
4802 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4803
4804 /*
4805 * Vblank time updates from the shadow to live plane control register
4806 * are blocked if the memory self-refresh mode is active at that
4807 * moment. So to make sure the plane gets truly disabled, disable
4808 * first the self-refresh mode. The self-refresh enable bit in turn
4809 * will be checked/applied by the HW only at the next frame start
4810 * event which is after the vblank start event, so we need to have a
4811 * wait-for-vblank between disabling the plane and the pipe.
4812 */
4813 if (HAS_GMCH_DISPLAY(dev))
4814 intel_set_memory_cxsr(dev_priv, false);
4815
4816 mutex_lock(&dev->struct_mutex);
4817 if (dev_priv->fbc.crtc == intel_crtc)
4818 intel_fbc_disable(dev);
4819 mutex_unlock(&dev->struct_mutex);
4820
4821 /*
4822 * FIXME IPS should be fine as long as one plane is
4823 * enabled, but in practice it seems to have problems
4824 * when going from primary only to sprite only and vice
4825 * versa.
4826 */
4827 hsw_disable_ips(intel_crtc);
4828 }
4829
4830 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4831 {
4832 struct drm_device *dev = crtc->dev;
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 int pipe = intel_crtc->pipe;
4835
4836 intel_enable_primary_hw_plane(crtc->primary, crtc);
4837 intel_enable_sprite_planes(crtc);
4838 intel_crtc_update_cursor(crtc, true);
4839
4840 intel_post_enable_primary(crtc);
4841
4842 /*
4843 * FIXME: Once we grow proper nuclear flip support out of this we need
4844 * to compute the mask of flip planes precisely. For the time being
4845 * consider this a flip to a NULL plane.
4846 */
4847 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4848 }
4849
4850 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4851 {
4852 struct drm_device *dev = crtc->dev;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 struct intel_plane *intel_plane;
4855 int pipe = intel_crtc->pipe;
4856
4857 if (!intel_crtc->active)
4858 return;
4859
4860 intel_crtc_wait_for_pending_flips(crtc);
4861
4862 intel_pre_disable_primary(crtc);
4863
4864 intel_crtc_dpms_overlay_disable(intel_crtc);
4865 for_each_intel_plane(dev, intel_plane) {
4866 if (intel_plane->pipe == pipe) {
4867 struct drm_crtc *from = intel_plane->base.crtc;
4868
4869 intel_plane->disable_plane(&intel_plane->base,
4870 from ?: crtc, true);
4871 }
4872 }
4873
4874 /*
4875 * FIXME: Once we grow proper nuclear flip support out of this we need
4876 * to compute the mask of flip planes precisely. For the time being
4877 * consider this a flip to a NULL plane.
4878 */
4879 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4880 }
4881
4882 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct intel_encoder *encoder;
4888 int pipe = intel_crtc->pipe;
4889
4890 WARN_ON(!crtc->state->enable);
4891
4892 if (intel_crtc->active)
4893 return;
4894
4895 if (intel_crtc->config->has_pch_encoder)
4896 intel_prepare_shared_dpll(intel_crtc);
4897
4898 if (intel_crtc->config->has_dp_encoder)
4899 intel_dp_set_m_n(intel_crtc, M1_N1);
4900
4901 intel_set_pipe_timings(intel_crtc);
4902
4903 if (intel_crtc->config->has_pch_encoder) {
4904 intel_cpu_transcoder_set_m_n(intel_crtc,
4905 &intel_crtc->config->fdi_m_n, NULL);
4906 }
4907
4908 ironlake_set_pipeconf(crtc);
4909
4910 intel_crtc->active = true;
4911
4912 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4913 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4914
4915 for_each_encoder_on_crtc(dev, crtc, encoder)
4916 if (encoder->pre_enable)
4917 encoder->pre_enable(encoder);
4918
4919 if (intel_crtc->config->has_pch_encoder) {
4920 /* Note: FDI PLL enabling _must_ be done before we enable the
4921 * cpu pipes, hence this is separate from all the other fdi/pch
4922 * enabling. */
4923 ironlake_fdi_pll_enable(intel_crtc);
4924 } else {
4925 assert_fdi_tx_disabled(dev_priv, pipe);
4926 assert_fdi_rx_disabled(dev_priv, pipe);
4927 }
4928
4929 ironlake_pfit_enable(intel_crtc);
4930
4931 /*
4932 * On ILK+ LUT must be loaded before the pipe is running but with
4933 * clocks enabled
4934 */
4935 intel_crtc_load_lut(crtc);
4936
4937 intel_update_watermarks(crtc);
4938 intel_enable_pipe(intel_crtc);
4939
4940 if (intel_crtc->config->has_pch_encoder)
4941 ironlake_pch_enable(crtc);
4942
4943 assert_vblank_disabled(crtc);
4944 drm_crtc_vblank_on(crtc);
4945
4946 for_each_encoder_on_crtc(dev, crtc, encoder)
4947 encoder->enable(encoder);
4948
4949 if (HAS_PCH_CPT(dev))
4950 cpt_verify_modeset(dev, intel_crtc->pipe);
4951 }
4952
4953 /* IPS only exists on ULT machines and is tied to pipe A. */
4954 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4955 {
4956 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4957 }
4958
4959 /*
4960 * This implements the workaround described in the "notes" section of the mode
4961 * set sequence documentation. When going from no pipes or single pipe to
4962 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4963 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4964 */
4965 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4966 {
4967 struct drm_device *dev = crtc->base.dev;
4968 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4969
4970 /* We want to get the other_active_crtc only if there's only 1 other
4971 * active crtc. */
4972 for_each_intel_crtc(dev, crtc_it) {
4973 if (!crtc_it->active || crtc_it == crtc)
4974 continue;
4975
4976 if (other_active_crtc)
4977 return;
4978
4979 other_active_crtc = crtc_it;
4980 }
4981 if (!other_active_crtc)
4982 return;
4983
4984 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4986 }
4987
4988 static void haswell_crtc_enable(struct drm_crtc *crtc)
4989 {
4990 struct drm_device *dev = crtc->dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993 struct intel_encoder *encoder;
4994 int pipe = intel_crtc->pipe;
4995
4996 WARN_ON(!crtc->state->enable);
4997
4998 if (intel_crtc->active)
4999 return;
5000
5001 if (intel_crtc_to_shared_dpll(intel_crtc))
5002 intel_enable_shared_dpll(intel_crtc);
5003
5004 if (intel_crtc->config->has_dp_encoder)
5005 intel_dp_set_m_n(intel_crtc, M1_N1);
5006
5007 intel_set_pipe_timings(intel_crtc);
5008
5009 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5010 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5011 intel_crtc->config->pixel_multiplier - 1);
5012 }
5013
5014 if (intel_crtc->config->has_pch_encoder) {
5015 intel_cpu_transcoder_set_m_n(intel_crtc,
5016 &intel_crtc->config->fdi_m_n, NULL);
5017 }
5018
5019 haswell_set_pipeconf(crtc);
5020
5021 intel_set_pipe_csc(crtc);
5022
5023 intel_crtc->active = true;
5024
5025 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5026 for_each_encoder_on_crtc(dev, crtc, encoder)
5027 if (encoder->pre_enable)
5028 encoder->pre_enable(encoder);
5029
5030 if (intel_crtc->config->has_pch_encoder) {
5031 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5032 true);
5033 dev_priv->display.fdi_link_train(crtc);
5034 }
5035
5036 intel_ddi_enable_pipe_clock(intel_crtc);
5037
5038 if (INTEL_INFO(dev)->gen == 9)
5039 skylake_pfit_update(intel_crtc, 1);
5040 else if (INTEL_INFO(dev)->gen < 9)
5041 ironlake_pfit_enable(intel_crtc);
5042 else
5043 MISSING_CASE(INTEL_INFO(dev)->gen);
5044
5045 /*
5046 * On ILK+ LUT must be loaded before the pipe is running but with
5047 * clocks enabled
5048 */
5049 intel_crtc_load_lut(crtc);
5050
5051 intel_ddi_set_pipe_settings(crtc);
5052 intel_ddi_enable_transcoder_func(crtc);
5053
5054 intel_update_watermarks(crtc);
5055 intel_enable_pipe(intel_crtc);
5056
5057 if (intel_crtc->config->has_pch_encoder)
5058 lpt_pch_enable(crtc);
5059
5060 if (intel_crtc->config->dp_encoder_is_mst)
5061 intel_ddi_set_vc_payload_alloc(crtc, true);
5062
5063 assert_vblank_disabled(crtc);
5064 drm_crtc_vblank_on(crtc);
5065
5066 for_each_encoder_on_crtc(dev, crtc, encoder) {
5067 encoder->enable(encoder);
5068 intel_opregion_notify_encoder(encoder, true);
5069 }
5070
5071 /* If we change the relative order between pipe/planes enabling, we need
5072 * to change the workaround. */
5073 haswell_mode_set_planes_workaround(intel_crtc);
5074 }
5075
5076 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5077 {
5078 struct drm_device *dev = crtc->base.dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 int pipe = crtc->pipe;
5081
5082 /* To avoid upsetting the power well on haswell only disable the pfit if
5083 * it's in use. The hw state code will make sure we get this right. */
5084 if (crtc->config->pch_pfit.enabled) {
5085 I915_WRITE(PF_CTL(pipe), 0);
5086 I915_WRITE(PF_WIN_POS(pipe), 0);
5087 I915_WRITE(PF_WIN_SZ(pipe), 0);
5088 }
5089 }
5090
5091 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5092 {
5093 struct drm_device *dev = crtc->dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5096 struct intel_encoder *encoder;
5097 int pipe = intel_crtc->pipe;
5098 u32 reg, temp;
5099
5100 if (!intel_crtc->active)
5101 return;
5102
5103 for_each_encoder_on_crtc(dev, crtc, encoder)
5104 encoder->disable(encoder);
5105
5106 drm_crtc_vblank_off(crtc);
5107 assert_vblank_disabled(crtc);
5108
5109 if (intel_crtc->config->has_pch_encoder)
5110 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5111
5112 intel_disable_pipe(intel_crtc);
5113
5114 ironlake_pfit_disable(intel_crtc);
5115
5116 if (intel_crtc->config->has_pch_encoder)
5117 ironlake_fdi_disable(crtc);
5118
5119 for_each_encoder_on_crtc(dev, crtc, encoder)
5120 if (encoder->post_disable)
5121 encoder->post_disable(encoder);
5122
5123 if (intel_crtc->config->has_pch_encoder) {
5124 ironlake_disable_pch_transcoder(dev_priv, pipe);
5125
5126 if (HAS_PCH_CPT(dev)) {
5127 /* disable TRANS_DP_CTL */
5128 reg = TRANS_DP_CTL(pipe);
5129 temp = I915_READ(reg);
5130 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5131 TRANS_DP_PORT_SEL_MASK);
5132 temp |= TRANS_DP_PORT_SEL_NONE;
5133 I915_WRITE(reg, temp);
5134
5135 /* disable DPLL_SEL */
5136 temp = I915_READ(PCH_DPLL_SEL);
5137 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5138 I915_WRITE(PCH_DPLL_SEL, temp);
5139 }
5140
5141 /* disable PCH DPLL */
5142 intel_disable_shared_dpll(intel_crtc);
5143
5144 ironlake_fdi_pll_disable(intel_crtc);
5145 }
5146
5147 intel_crtc->active = false;
5148 intel_update_watermarks(crtc);
5149
5150 mutex_lock(&dev->struct_mutex);
5151 intel_fbc_update(dev);
5152 mutex_unlock(&dev->struct_mutex);
5153 }
5154
5155 static void haswell_crtc_disable(struct drm_crtc *crtc)
5156 {
5157 struct drm_device *dev = crtc->dev;
5158 struct drm_i915_private *dev_priv = dev->dev_private;
5159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5160 struct intel_encoder *encoder;
5161 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5162
5163 if (!intel_crtc->active)
5164 return;
5165
5166 for_each_encoder_on_crtc(dev, crtc, encoder) {
5167 intel_opregion_notify_encoder(encoder, false);
5168 encoder->disable(encoder);
5169 }
5170
5171 drm_crtc_vblank_off(crtc);
5172 assert_vblank_disabled(crtc);
5173
5174 if (intel_crtc->config->has_pch_encoder)
5175 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5176 false);
5177 intel_disable_pipe(intel_crtc);
5178
5179 if (intel_crtc->config->dp_encoder_is_mst)
5180 intel_ddi_set_vc_payload_alloc(crtc, false);
5181
5182 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5183
5184 if (INTEL_INFO(dev)->gen == 9)
5185 skylake_pfit_update(intel_crtc, 0);
5186 else if (INTEL_INFO(dev)->gen < 9)
5187 ironlake_pfit_disable(intel_crtc);
5188 else
5189 MISSING_CASE(INTEL_INFO(dev)->gen);
5190
5191 intel_ddi_disable_pipe_clock(intel_crtc);
5192
5193 if (intel_crtc->config->has_pch_encoder) {
5194 lpt_disable_pch_transcoder(dev_priv);
5195 intel_ddi_fdi_disable(crtc);
5196 }
5197
5198 for_each_encoder_on_crtc(dev, crtc, encoder)
5199 if (encoder->post_disable)
5200 encoder->post_disable(encoder);
5201
5202 intel_crtc->active = false;
5203 intel_update_watermarks(crtc);
5204
5205 mutex_lock(&dev->struct_mutex);
5206 intel_fbc_update(dev);
5207 mutex_unlock(&dev->struct_mutex);
5208
5209 if (intel_crtc_to_shared_dpll(intel_crtc))
5210 intel_disable_shared_dpll(intel_crtc);
5211 }
5212
5213 static void ironlake_crtc_off(struct drm_crtc *crtc)
5214 {
5215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216 intel_put_shared_dpll(intel_crtc);
5217 }
5218
5219
5220 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5221 {
5222 struct drm_device *dev = crtc->base.dev;
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224 struct intel_crtc_state *pipe_config = crtc->config;
5225
5226 if (!pipe_config->gmch_pfit.control)
5227 return;
5228
5229 /*
5230 * The panel fitter should only be adjusted whilst the pipe is disabled,
5231 * according to register description and PRM.
5232 */
5233 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5234 assert_pipe_disabled(dev_priv, crtc->pipe);
5235
5236 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5237 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5238
5239 /* Border color in case we don't scale up to the full screen. Black by
5240 * default, change to something else for debugging. */
5241 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5242 }
5243
5244 static enum intel_display_power_domain port_to_power_domain(enum port port)
5245 {
5246 switch (port) {
5247 case PORT_A:
5248 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5249 case PORT_B:
5250 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5251 case PORT_C:
5252 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5253 case PORT_D:
5254 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5255 default:
5256 WARN_ON_ONCE(1);
5257 return POWER_DOMAIN_PORT_OTHER;
5258 }
5259 }
5260
5261 #define for_each_power_domain(domain, mask) \
5262 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5263 if ((1 << (domain)) & (mask))
5264
5265 enum intel_display_power_domain
5266 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5267 {
5268 struct drm_device *dev = intel_encoder->base.dev;
5269 struct intel_digital_port *intel_dig_port;
5270
5271 switch (intel_encoder->type) {
5272 case INTEL_OUTPUT_UNKNOWN:
5273 /* Only DDI platforms should ever use this output type */
5274 WARN_ON_ONCE(!HAS_DDI(dev));
5275 case INTEL_OUTPUT_DISPLAYPORT:
5276 case INTEL_OUTPUT_HDMI:
5277 case INTEL_OUTPUT_EDP:
5278 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5279 return port_to_power_domain(intel_dig_port->port);
5280 case INTEL_OUTPUT_DP_MST:
5281 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5282 return port_to_power_domain(intel_dig_port->port);
5283 case INTEL_OUTPUT_ANALOG:
5284 return POWER_DOMAIN_PORT_CRT;
5285 case INTEL_OUTPUT_DSI:
5286 return POWER_DOMAIN_PORT_DSI;
5287 default:
5288 return POWER_DOMAIN_PORT_OTHER;
5289 }
5290 }
5291
5292 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5293 {
5294 struct drm_device *dev = crtc->dev;
5295 struct intel_encoder *intel_encoder;
5296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5297 enum pipe pipe = intel_crtc->pipe;
5298 unsigned long mask;
5299 enum transcoder transcoder;
5300
5301 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5302
5303 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5304 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5305 if (intel_crtc->config->pch_pfit.enabled ||
5306 intel_crtc->config->pch_pfit.force_thru)
5307 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5308
5309 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5310 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5311
5312 return mask;
5313 }
5314
5315 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5316 {
5317 struct drm_device *dev = state->dev;
5318 struct drm_i915_private *dev_priv = dev->dev_private;
5319 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5320 struct intel_crtc *crtc;
5321
5322 /*
5323 * First get all needed power domains, then put all unneeded, to avoid
5324 * any unnecessary toggling of the power wells.
5325 */
5326 for_each_intel_crtc(dev, crtc) {
5327 enum intel_display_power_domain domain;
5328
5329 if (!crtc->base.state->enable)
5330 continue;
5331
5332 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5333
5334 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5335 intel_display_power_get(dev_priv, domain);
5336 }
5337
5338 if (dev_priv->display.modeset_global_resources)
5339 dev_priv->display.modeset_global_resources(state);
5340
5341 for_each_intel_crtc(dev, crtc) {
5342 enum intel_display_power_domain domain;
5343
5344 for_each_power_domain(domain, crtc->enabled_power_domains)
5345 intel_display_power_put(dev_priv, domain);
5346
5347 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5348 }
5349
5350 intel_display_set_init_power(dev_priv, false);
5351 }
5352
5353 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5354 {
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356 uint32_t divider;
5357 uint32_t ratio;
5358 uint32_t current_freq;
5359 int ret;
5360
5361 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5362 switch (frequency) {
5363 case 144000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 288000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 384000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 576000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(60);
5378 break;
5379 case 624000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5381 ratio = BXT_DE_PLL_RATIO(65);
5382 break;
5383 case 19200:
5384 /*
5385 * Bypass frequency with DE PLL disabled. Init ratio, divider
5386 * to suppress GCC warning.
5387 */
5388 ratio = 0;
5389 divider = 0;
5390 break;
5391 default:
5392 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5393
5394 return;
5395 }
5396
5397 mutex_lock(&dev_priv->rps.hw_lock);
5398 /* Inform power controller of upcoming frequency change */
5399 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5400 0x80000000);
5401 mutex_unlock(&dev_priv->rps.hw_lock);
5402
5403 if (ret) {
5404 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5405 ret, frequency);
5406 return;
5407 }
5408
5409 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5410 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5411 current_freq = current_freq * 500 + 1000;
5412
5413 /*
5414 * DE PLL has to be disabled when
5415 * - setting to 19.2MHz (bypass, PLL isn't used)
5416 * - before setting to 624MHz (PLL needs toggling)
5417 * - before setting to any frequency from 624MHz (PLL needs toggling)
5418 */
5419 if (frequency == 19200 || frequency == 624000 ||
5420 current_freq == 624000) {
5421 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5424 1))
5425 DRM_ERROR("timout waiting for DE PLL unlock\n");
5426 }
5427
5428 if (frequency != 19200) {
5429 uint32_t val;
5430
5431 val = I915_READ(BXT_DE_PLL_CTL);
5432 val &= ~BXT_DE_PLL_RATIO_MASK;
5433 val |= ratio;
5434 I915_WRITE(BXT_DE_PLL_CTL, val);
5435
5436 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5437 /* Timeout 200us */
5438 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5439 DRM_ERROR("timeout waiting for DE PLL lock\n");
5440
5441 val = I915_READ(CDCLK_CTL);
5442 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5443 val |= divider;
5444 /*
5445 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5446 * enable otherwise.
5447 */
5448 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449 if (frequency >= 500000)
5450 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5451
5452 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5453 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5454 val |= (frequency - 1000) / 500;
5455 I915_WRITE(CDCLK_CTL, val);
5456 }
5457
5458 mutex_lock(&dev_priv->rps.hw_lock);
5459 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5460 DIV_ROUND_UP(frequency, 25000));
5461 mutex_unlock(&dev_priv->rps.hw_lock);
5462
5463 if (ret) {
5464 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5465 ret, frequency);
5466 return;
5467 }
5468
5469 dev_priv->cdclk_freq = frequency;
5470 }
5471
5472 void broxton_init_cdclk(struct drm_device *dev)
5473 {
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 uint32_t val;
5476
5477 /*
5478 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5479 * or else the reset will hang because there is no PCH to respond.
5480 * Move the handshake programming to initialization sequence.
5481 * Previously was left up to BIOS.
5482 */
5483 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5484 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5485 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5486
5487 /* Enable PG1 for cdclk */
5488 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5489
5490 /* check if cd clock is enabled */
5491 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5492 DRM_DEBUG_KMS("Display already initialized\n");
5493 return;
5494 }
5495
5496 /*
5497 * FIXME:
5498 * - The initial CDCLK needs to be read from VBT.
5499 * Need to make this change after VBT has changes for BXT.
5500 * - check if setting the max (or any) cdclk freq is really necessary
5501 * here, it belongs to modeset time
5502 */
5503 broxton_set_cdclk(dev, 624000);
5504
5505 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5506 POSTING_READ(DBUF_CTL);
5507
5508 udelay(10);
5509
5510 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5511 DRM_ERROR("DBuf power enable timeout!\n");
5512 }
5513
5514 void broxton_uninit_cdclk(struct drm_device *dev)
5515 {
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5519 POSTING_READ(DBUF_CTL);
5520
5521 udelay(10);
5522
5523 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5524 DRM_ERROR("DBuf power disable timeout!\n");
5525
5526 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5527 broxton_set_cdclk(dev, 19200);
5528
5529 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5530 }
5531
5532 static const struct skl_cdclk_entry {
5533 unsigned int freq;
5534 unsigned int vco;
5535 } skl_cdclk_frequencies[] = {
5536 { .freq = 308570, .vco = 8640 },
5537 { .freq = 337500, .vco = 8100 },
5538 { .freq = 432000, .vco = 8640 },
5539 { .freq = 450000, .vco = 8100 },
5540 { .freq = 540000, .vco = 8100 },
5541 { .freq = 617140, .vco = 8640 },
5542 { .freq = 675000, .vco = 8100 },
5543 };
5544
5545 static unsigned int skl_cdclk_decimal(unsigned int freq)
5546 {
5547 return (freq - 1000) / 500;
5548 }
5549
5550 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5551 {
5552 unsigned int i;
5553
5554 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5555 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5556
5557 if (e->freq == freq)
5558 return e->vco;
5559 }
5560
5561 return 8100;
5562 }
5563
5564 static void
5565 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5566 {
5567 unsigned int min_freq;
5568 u32 val;
5569
5570 /* select the minimum CDCLK before enabling DPLL 0 */
5571 val = I915_READ(CDCLK_CTL);
5572 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5573 val |= CDCLK_FREQ_337_308;
5574
5575 if (required_vco == 8640)
5576 min_freq = 308570;
5577 else
5578 min_freq = 337500;
5579
5580 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5581
5582 I915_WRITE(CDCLK_CTL, val);
5583 POSTING_READ(CDCLK_CTL);
5584
5585 /*
5586 * We always enable DPLL0 with the lowest link rate possible, but still
5587 * taking into account the VCO required to operate the eDP panel at the
5588 * desired frequency. The usual DP link rates operate with a VCO of
5589 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5590 * The modeset code is responsible for the selection of the exact link
5591 * rate later on, with the constraint of choosing a frequency that
5592 * works with required_vco.
5593 */
5594 val = I915_READ(DPLL_CTRL1);
5595
5596 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5597 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5598 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5599 if (required_vco == 8640)
5600 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5601 SKL_DPLL0);
5602 else
5603 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5604 SKL_DPLL0);
5605
5606 I915_WRITE(DPLL_CTRL1, val);
5607 POSTING_READ(DPLL_CTRL1);
5608
5609 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5610
5611 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5612 DRM_ERROR("DPLL0 not locked\n");
5613 }
5614
5615 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5616 {
5617 int ret;
5618 u32 val;
5619
5620 /* inform PCU we want to change CDCLK */
5621 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5622 mutex_lock(&dev_priv->rps.hw_lock);
5623 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5624 mutex_unlock(&dev_priv->rps.hw_lock);
5625
5626 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5627 }
5628
5629 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5630 {
5631 unsigned int i;
5632
5633 for (i = 0; i < 15; i++) {
5634 if (skl_cdclk_pcu_ready(dev_priv))
5635 return true;
5636 udelay(10);
5637 }
5638
5639 return false;
5640 }
5641
5642 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5643 {
5644 u32 freq_select, pcu_ack;
5645
5646 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5647
5648 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5649 DRM_ERROR("failed to inform PCU about cdclk change\n");
5650 return;
5651 }
5652
5653 /* set CDCLK_CTL */
5654 switch(freq) {
5655 case 450000:
5656 case 432000:
5657 freq_select = CDCLK_FREQ_450_432;
5658 pcu_ack = 1;
5659 break;
5660 case 540000:
5661 freq_select = CDCLK_FREQ_540;
5662 pcu_ack = 2;
5663 break;
5664 case 308570:
5665 case 337500:
5666 default:
5667 freq_select = CDCLK_FREQ_337_308;
5668 pcu_ack = 0;
5669 break;
5670 case 617140:
5671 case 675000:
5672 freq_select = CDCLK_FREQ_675_617;
5673 pcu_ack = 3;
5674 break;
5675 }
5676
5677 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5678 POSTING_READ(CDCLK_CTL);
5679
5680 /* inform PCU of the change */
5681 mutex_lock(&dev_priv->rps.hw_lock);
5682 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5683 mutex_unlock(&dev_priv->rps.hw_lock);
5684 }
5685
5686 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5687 {
5688 /* disable DBUF power */
5689 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5690 POSTING_READ(DBUF_CTL);
5691
5692 udelay(10);
5693
5694 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5695 DRM_ERROR("DBuf power disable timeout\n");
5696
5697 /* disable DPLL0 */
5698 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5699 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5700 DRM_ERROR("Couldn't disable DPLL0\n");
5701
5702 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5703 }
5704
5705 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5706 {
5707 u32 val;
5708 unsigned int required_vco;
5709
5710 /* enable PCH reset handshake */
5711 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5712 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5713
5714 /* enable PG1 and Misc I/O */
5715 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5716
5717 /* DPLL0 already enabed !? */
5718 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5719 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5720 return;
5721 }
5722
5723 /* enable DPLL0 */
5724 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5725 skl_dpll0_enable(dev_priv, required_vco);
5726
5727 /* set CDCLK to the frequency the BIOS chose */
5728 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5729
5730 /* enable DBUF power */
5731 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5732 POSTING_READ(DBUF_CTL);
5733
5734 udelay(10);
5735
5736 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5737 DRM_ERROR("DBuf power enable timeout\n");
5738 }
5739
5740 /* returns HPLL frequency in kHz */
5741 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5742 {
5743 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5744
5745 /* Obtain SKU information */
5746 mutex_lock(&dev_priv->sb_lock);
5747 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5748 CCK_FUSE_HPLL_FREQ_MASK;
5749 mutex_unlock(&dev_priv->sb_lock);
5750
5751 return vco_freq[hpll_freq] * 1000;
5752 }
5753
5754 static void vlv_update_cdclk(struct drm_device *dev)
5755 {
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5757
5758 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5759 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5760 dev_priv->cdclk_freq);
5761
5762 /*
5763 * Program the gmbus_freq based on the cdclk frequency.
5764 * BSpec erroneously claims we should aim for 4MHz, but
5765 * in fact 1MHz is the correct frequency.
5766 */
5767 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5768 }
5769
5770 /* Adjust CDclk dividers to allow high res or save power if possible */
5771 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5772 {
5773 struct drm_i915_private *dev_priv = dev->dev_private;
5774 u32 val, cmd;
5775
5776 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5777 != dev_priv->cdclk_freq);
5778
5779 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5780 cmd = 2;
5781 else if (cdclk == 266667)
5782 cmd = 1;
5783 else
5784 cmd = 0;
5785
5786 mutex_lock(&dev_priv->rps.hw_lock);
5787 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5788 val &= ~DSPFREQGUAR_MASK;
5789 val |= (cmd << DSPFREQGUAR_SHIFT);
5790 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5791 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5792 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5793 50)) {
5794 DRM_ERROR("timed out waiting for CDclk change\n");
5795 }
5796 mutex_unlock(&dev_priv->rps.hw_lock);
5797
5798 mutex_lock(&dev_priv->sb_lock);
5799
5800 if (cdclk == 400000) {
5801 u32 divider;
5802
5803 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5804
5805 /* adjust cdclk divider */
5806 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5807 val &= ~DISPLAY_FREQUENCY_VALUES;
5808 val |= divider;
5809 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5810
5811 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5812 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5813 50))
5814 DRM_ERROR("timed out waiting for CDclk change\n");
5815 }
5816
5817 /* adjust self-refresh exit latency value */
5818 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5819 val &= ~0x7f;
5820
5821 /*
5822 * For high bandwidth configs, we set a higher latency in the bunit
5823 * so that the core display fetch happens in time to avoid underruns.
5824 */
5825 if (cdclk == 400000)
5826 val |= 4500 / 250; /* 4.5 usec */
5827 else
5828 val |= 3000 / 250; /* 3.0 usec */
5829 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5830
5831 mutex_unlock(&dev_priv->sb_lock);
5832
5833 vlv_update_cdclk(dev);
5834 }
5835
5836 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5837 {
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 u32 val, cmd;
5840
5841 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5842 != dev_priv->cdclk_freq);
5843
5844 switch (cdclk) {
5845 case 333333:
5846 case 320000:
5847 case 266667:
5848 case 200000:
5849 break;
5850 default:
5851 MISSING_CASE(cdclk);
5852 return;
5853 }
5854
5855 /*
5856 * Specs are full of misinformation, but testing on actual
5857 * hardware has shown that we just need to write the desired
5858 * CCK divider into the Punit register.
5859 */
5860 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5861
5862 mutex_lock(&dev_priv->rps.hw_lock);
5863 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5864 val &= ~DSPFREQGUAR_MASK_CHV;
5865 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5866 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5867 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5868 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5869 50)) {
5870 DRM_ERROR("timed out waiting for CDclk change\n");
5871 }
5872 mutex_unlock(&dev_priv->rps.hw_lock);
5873
5874 vlv_update_cdclk(dev);
5875 }
5876
5877 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5878 int max_pixclk)
5879 {
5880 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5881 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5882
5883 /*
5884 * Really only a few cases to deal with, as only 4 CDclks are supported:
5885 * 200MHz
5886 * 267MHz
5887 * 320/333MHz (depends on HPLL freq)
5888 * 400MHz (VLV only)
5889 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5890 * of the lower bin and adjust if needed.
5891 *
5892 * We seem to get an unstable or solid color picture at 200MHz.
5893 * Not sure what's wrong. For now use 200MHz only when all pipes
5894 * are off.
5895 */
5896 if (!IS_CHERRYVIEW(dev_priv) &&
5897 max_pixclk > freq_320*limit/100)
5898 return 400000;
5899 else if (max_pixclk > 266667*limit/100)
5900 return freq_320;
5901 else if (max_pixclk > 0)
5902 return 266667;
5903 else
5904 return 200000;
5905 }
5906
5907 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5908 int max_pixclk)
5909 {
5910 /*
5911 * FIXME:
5912 * - remove the guardband, it's not needed on BXT
5913 * - set 19.2MHz bypass frequency if there are no active pipes
5914 */
5915 if (max_pixclk > 576000*9/10)
5916 return 624000;
5917 else if (max_pixclk > 384000*9/10)
5918 return 576000;
5919 else if (max_pixclk > 288000*9/10)
5920 return 384000;
5921 else if (max_pixclk > 144000*9/10)
5922 return 288000;
5923 else
5924 return 144000;
5925 }
5926
5927 /* Compute the max pixel clock for new configuration. Uses atomic state if
5928 * that's non-NULL, look at current state otherwise. */
5929 static int intel_mode_max_pixclk(struct drm_device *dev,
5930 struct drm_atomic_state *state)
5931 {
5932 struct intel_crtc *intel_crtc;
5933 struct intel_crtc_state *crtc_state;
5934 int max_pixclk = 0;
5935
5936 for_each_intel_crtc(dev, intel_crtc) {
5937 if (state)
5938 crtc_state =
5939 intel_atomic_get_crtc_state(state, intel_crtc);
5940 else
5941 crtc_state = intel_crtc->config;
5942 if (IS_ERR(crtc_state))
5943 return PTR_ERR(crtc_state);
5944
5945 if (!crtc_state->base.enable)
5946 continue;
5947
5948 max_pixclk = max(max_pixclk,
5949 crtc_state->base.adjusted_mode.crtc_clock);
5950 }
5951
5952 return max_pixclk;
5953 }
5954
5955 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5956 {
5957 struct drm_i915_private *dev_priv = to_i915(state->dev);
5958 struct drm_crtc *crtc;
5959 struct drm_crtc_state *crtc_state;
5960 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5961 int cdclk, i;
5962
5963 if (max_pixclk < 0)
5964 return max_pixclk;
5965
5966 if (IS_VALLEYVIEW(dev_priv))
5967 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5968 else
5969 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5970
5971 if (cdclk == dev_priv->cdclk_freq)
5972 return 0;
5973
5974 /* add all active pipes to the state */
5975 for_each_crtc(state->dev, crtc) {
5976 if (!crtc->state->enable)
5977 continue;
5978
5979 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5980 if (IS_ERR(crtc_state))
5981 return PTR_ERR(crtc_state);
5982 }
5983
5984 /* disable/enable all currently active pipes while we change cdclk */
5985 for_each_crtc_in_state(state, crtc, crtc_state, i)
5986 if (crtc_state->enable)
5987 crtc_state->mode_changed = true;
5988
5989 return 0;
5990 }
5991
5992 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5993 {
5994 unsigned int credits, default_credits;
5995
5996 if (IS_CHERRYVIEW(dev_priv))
5997 default_credits = PFI_CREDIT(12);
5998 else
5999 default_credits = PFI_CREDIT(8);
6000
6001 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
6002 /* CHV suggested value is 31 or 63 */
6003 if (IS_CHERRYVIEW(dev_priv))
6004 credits = PFI_CREDIT_31;
6005 else
6006 credits = PFI_CREDIT(15);
6007 } else {
6008 credits = default_credits;
6009 }
6010
6011 /*
6012 * WA - write default credits before re-programming
6013 * FIXME: should we also set the resend bit here?
6014 */
6015 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6016 default_credits);
6017
6018 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6019 credits | PFI_CREDIT_RESEND);
6020
6021 /*
6022 * FIXME is this guaranteed to clear
6023 * immediately or should we poll for it?
6024 */
6025 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6026 }
6027
6028 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6029 {
6030 struct drm_device *dev = old_state->dev;
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6033 int req_cdclk;
6034
6035 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6036 * never fail. */
6037 if (WARN_ON(max_pixclk < 0))
6038 return;
6039
6040 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6041
6042 if (req_cdclk != dev_priv->cdclk_freq) {
6043 /*
6044 * FIXME: We can end up here with all power domains off, yet
6045 * with a CDCLK frequency other than the minimum. To account
6046 * for this take the PIPE-A power domain, which covers the HW
6047 * blocks needed for the following programming. This can be
6048 * removed once it's guaranteed that we get here either with
6049 * the minimum CDCLK set, or the required power domains
6050 * enabled.
6051 */
6052 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6053
6054 if (IS_CHERRYVIEW(dev))
6055 cherryview_set_cdclk(dev, req_cdclk);
6056 else
6057 valleyview_set_cdclk(dev, req_cdclk);
6058
6059 vlv_program_pfi_credits(dev_priv);
6060
6061 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6062 }
6063 }
6064
6065 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6066 {
6067 struct drm_device *dev = crtc->dev;
6068 struct drm_i915_private *dev_priv = to_i915(dev);
6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070 struct intel_encoder *encoder;
6071 int pipe = intel_crtc->pipe;
6072 bool is_dsi;
6073
6074 WARN_ON(!crtc->state->enable);
6075
6076 if (intel_crtc->active)
6077 return;
6078
6079 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6080
6081 if (!is_dsi) {
6082 if (IS_CHERRYVIEW(dev))
6083 chv_prepare_pll(intel_crtc, intel_crtc->config);
6084 else
6085 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6086 }
6087
6088 if (intel_crtc->config->has_dp_encoder)
6089 intel_dp_set_m_n(intel_crtc, M1_N1);
6090
6091 intel_set_pipe_timings(intel_crtc);
6092
6093 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095
6096 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6097 I915_WRITE(CHV_CANVAS(pipe), 0);
6098 }
6099
6100 i9xx_set_pipeconf(intel_crtc);
6101
6102 intel_crtc->active = true;
6103
6104 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6105
6106 for_each_encoder_on_crtc(dev, crtc, encoder)
6107 if (encoder->pre_pll_enable)
6108 encoder->pre_pll_enable(encoder);
6109
6110 if (!is_dsi) {
6111 if (IS_CHERRYVIEW(dev))
6112 chv_enable_pll(intel_crtc, intel_crtc->config);
6113 else
6114 vlv_enable_pll(intel_crtc, intel_crtc->config);
6115 }
6116
6117 for_each_encoder_on_crtc(dev, crtc, encoder)
6118 if (encoder->pre_enable)
6119 encoder->pre_enable(encoder);
6120
6121 i9xx_pfit_enable(intel_crtc);
6122
6123 intel_crtc_load_lut(crtc);
6124
6125 intel_update_watermarks(crtc);
6126 intel_enable_pipe(intel_crtc);
6127
6128 assert_vblank_disabled(crtc);
6129 drm_crtc_vblank_on(crtc);
6130
6131 for_each_encoder_on_crtc(dev, crtc, encoder)
6132 encoder->enable(encoder);
6133 }
6134
6135 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6136 {
6137 struct drm_device *dev = crtc->base.dev;
6138 struct drm_i915_private *dev_priv = dev->dev_private;
6139
6140 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6141 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6142 }
6143
6144 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6145 {
6146 struct drm_device *dev = crtc->dev;
6147 struct drm_i915_private *dev_priv = to_i915(dev);
6148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6149 struct intel_encoder *encoder;
6150 int pipe = intel_crtc->pipe;
6151
6152 WARN_ON(!crtc->state->enable);
6153
6154 if (intel_crtc->active)
6155 return;
6156
6157 i9xx_set_pll_dividers(intel_crtc);
6158
6159 if (intel_crtc->config->has_dp_encoder)
6160 intel_dp_set_m_n(intel_crtc, M1_N1);
6161
6162 intel_set_pipe_timings(intel_crtc);
6163
6164 i9xx_set_pipeconf(intel_crtc);
6165
6166 intel_crtc->active = true;
6167
6168 if (!IS_GEN2(dev))
6169 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6170
6171 for_each_encoder_on_crtc(dev, crtc, encoder)
6172 if (encoder->pre_enable)
6173 encoder->pre_enable(encoder);
6174
6175 i9xx_enable_pll(intel_crtc);
6176
6177 i9xx_pfit_enable(intel_crtc);
6178
6179 intel_crtc_load_lut(crtc);
6180
6181 intel_update_watermarks(crtc);
6182 intel_enable_pipe(intel_crtc);
6183
6184 assert_vblank_disabled(crtc);
6185 drm_crtc_vblank_on(crtc);
6186
6187 for_each_encoder_on_crtc(dev, crtc, encoder)
6188 encoder->enable(encoder);
6189 }
6190
6191 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6192 {
6193 struct drm_device *dev = crtc->base.dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195
6196 if (!crtc->config->gmch_pfit.control)
6197 return;
6198
6199 assert_pipe_disabled(dev_priv, crtc->pipe);
6200
6201 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6202 I915_READ(PFIT_CONTROL));
6203 I915_WRITE(PFIT_CONTROL, 0);
6204 }
6205
6206 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6207 {
6208 struct drm_device *dev = crtc->dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211 struct intel_encoder *encoder;
6212 int pipe = intel_crtc->pipe;
6213
6214 if (!intel_crtc->active)
6215 return;
6216
6217 /*
6218 * On gen2 planes are double buffered but the pipe isn't, so we must
6219 * wait for planes to fully turn off before disabling the pipe.
6220 * We also need to wait on all gmch platforms because of the
6221 * self-refresh mode constraint explained above.
6222 */
6223 intel_wait_for_vblank(dev, pipe);
6224
6225 for_each_encoder_on_crtc(dev, crtc, encoder)
6226 encoder->disable(encoder);
6227
6228 drm_crtc_vblank_off(crtc);
6229 assert_vblank_disabled(crtc);
6230
6231 intel_disable_pipe(intel_crtc);
6232
6233 i9xx_pfit_disable(intel_crtc);
6234
6235 for_each_encoder_on_crtc(dev, crtc, encoder)
6236 if (encoder->post_disable)
6237 encoder->post_disable(encoder);
6238
6239 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6240 if (IS_CHERRYVIEW(dev))
6241 chv_disable_pll(dev_priv, pipe);
6242 else if (IS_VALLEYVIEW(dev))
6243 vlv_disable_pll(dev_priv, pipe);
6244 else
6245 i9xx_disable_pll(intel_crtc);
6246 }
6247
6248 if (!IS_GEN2(dev))
6249 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6250
6251 intel_crtc->active = false;
6252 intel_update_watermarks(crtc);
6253
6254 mutex_lock(&dev->struct_mutex);
6255 intel_fbc_update(dev);
6256 mutex_unlock(&dev->struct_mutex);
6257 }
6258
6259 static void i9xx_crtc_off(struct drm_crtc *crtc)
6260 {
6261 }
6262
6263 /* Master function to enable/disable CRTC and corresponding power wells */
6264 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6265 {
6266 struct drm_device *dev = crtc->dev;
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6269 enum intel_display_power_domain domain;
6270 unsigned long domains;
6271
6272 if (enable) {
6273 if (!intel_crtc->active) {
6274 domains = get_crtc_power_domains(crtc);
6275 for_each_power_domain(domain, domains)
6276 intel_display_power_get(dev_priv, domain);
6277 intel_crtc->enabled_power_domains = domains;
6278
6279 dev_priv->display.crtc_enable(crtc);
6280 intel_crtc_enable_planes(crtc);
6281 }
6282 } else {
6283 if (intel_crtc->active) {
6284 intel_crtc_disable_planes(crtc);
6285 dev_priv->display.crtc_disable(crtc);
6286
6287 domains = intel_crtc->enabled_power_domains;
6288 for_each_power_domain(domain, domains)
6289 intel_display_power_put(dev_priv, domain);
6290 intel_crtc->enabled_power_domains = 0;
6291 }
6292 }
6293 }
6294
6295 /**
6296 * Sets the power management mode of the pipe and plane.
6297 */
6298 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6299 {
6300 struct drm_device *dev = crtc->dev;
6301 struct intel_encoder *intel_encoder;
6302 bool enable = false;
6303
6304 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6305 enable |= intel_encoder->connectors_active;
6306
6307 intel_crtc_control(crtc, enable);
6308
6309 crtc->state->active = enable;
6310 }
6311
6312 static void intel_crtc_disable(struct drm_crtc *crtc)
6313 {
6314 struct drm_device *dev = crtc->dev;
6315 struct drm_connector *connector;
6316 struct drm_i915_private *dev_priv = dev->dev_private;
6317
6318 intel_crtc_disable_planes(crtc);
6319 dev_priv->display.crtc_disable(crtc);
6320 dev_priv->display.off(crtc);
6321
6322 drm_plane_helper_disable(crtc->primary);
6323
6324 /* Update computed state. */
6325 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6326 if (!connector->encoder || !connector->encoder->crtc)
6327 continue;
6328
6329 if (connector->encoder->crtc != crtc)
6330 continue;
6331
6332 connector->dpms = DRM_MODE_DPMS_OFF;
6333 to_intel_encoder(connector->encoder)->connectors_active = false;
6334 }
6335 }
6336
6337 void intel_encoder_destroy(struct drm_encoder *encoder)
6338 {
6339 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6340
6341 drm_encoder_cleanup(encoder);
6342 kfree(intel_encoder);
6343 }
6344
6345 /* Simple dpms helper for encoders with just one connector, no cloning and only
6346 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6347 * state of the entire output pipe. */
6348 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6349 {
6350 if (mode == DRM_MODE_DPMS_ON) {
6351 encoder->connectors_active = true;
6352
6353 intel_crtc_update_dpms(encoder->base.crtc);
6354 } else {
6355 encoder->connectors_active = false;
6356
6357 intel_crtc_update_dpms(encoder->base.crtc);
6358 }
6359 }
6360
6361 /* Cross check the actual hw state with our own modeset state tracking (and it's
6362 * internal consistency). */
6363 static void intel_connector_check_state(struct intel_connector *connector)
6364 {
6365 if (connector->get_hw_state(connector)) {
6366 struct intel_encoder *encoder = connector->encoder;
6367 struct drm_crtc *crtc;
6368 bool encoder_enabled;
6369 enum pipe pipe;
6370
6371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372 connector->base.base.id,
6373 connector->base.name);
6374
6375 /* there is no real hw state for MST connectors */
6376 if (connector->mst_port)
6377 return;
6378
6379 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6380 "wrong connector dpms state\n");
6381 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6382 "active connector not linked to encoder\n");
6383
6384 if (encoder) {
6385 I915_STATE_WARN(!encoder->connectors_active,
6386 "encoder->connectors_active not set\n");
6387
6388 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6389 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6390 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6391 return;
6392
6393 crtc = encoder->base.crtc;
6394
6395 I915_STATE_WARN(!crtc->state->enable,
6396 "crtc not enabled\n");
6397 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6398 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6399 "encoder active on the wrong pipe\n");
6400 }
6401 }
6402 }
6403
6404 int intel_connector_init(struct intel_connector *connector)
6405 {
6406 struct drm_connector_state *connector_state;
6407
6408 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6409 if (!connector_state)
6410 return -ENOMEM;
6411
6412 connector->base.state = connector_state;
6413 return 0;
6414 }
6415
6416 struct intel_connector *intel_connector_alloc(void)
6417 {
6418 struct intel_connector *connector;
6419
6420 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6421 if (!connector)
6422 return NULL;
6423
6424 if (intel_connector_init(connector) < 0) {
6425 kfree(connector);
6426 return NULL;
6427 }
6428
6429 return connector;
6430 }
6431
6432 /* Even simpler default implementation, if there's really no special case to
6433 * consider. */
6434 void intel_connector_dpms(struct drm_connector *connector, int mode)
6435 {
6436 /* All the simple cases only support two dpms states. */
6437 if (mode != DRM_MODE_DPMS_ON)
6438 mode = DRM_MODE_DPMS_OFF;
6439
6440 if (mode == connector->dpms)
6441 return;
6442
6443 connector->dpms = mode;
6444
6445 /* Only need to change hw state when actually enabled */
6446 if (connector->encoder)
6447 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6448
6449 intel_modeset_check_state(connector->dev);
6450 }
6451
6452 /* Simple connector->get_hw_state implementation for encoders that support only
6453 * one connector and no cloning and hence the encoder state determines the state
6454 * of the connector. */
6455 bool intel_connector_get_hw_state(struct intel_connector *connector)
6456 {
6457 enum pipe pipe = 0;
6458 struct intel_encoder *encoder = connector->encoder;
6459
6460 return encoder->get_hw_state(encoder, &pipe);
6461 }
6462
6463 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6464 {
6465 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6466 return crtc_state->fdi_lanes;
6467
6468 return 0;
6469 }
6470
6471 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6472 struct intel_crtc_state *pipe_config)
6473 {
6474 struct drm_atomic_state *state = pipe_config->base.state;
6475 struct intel_crtc *other_crtc;
6476 struct intel_crtc_state *other_crtc_state;
6477
6478 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6479 pipe_name(pipe), pipe_config->fdi_lanes);
6480 if (pipe_config->fdi_lanes > 4) {
6481 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6482 pipe_name(pipe), pipe_config->fdi_lanes);
6483 return -EINVAL;
6484 }
6485
6486 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6487 if (pipe_config->fdi_lanes > 2) {
6488 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6489 pipe_config->fdi_lanes);
6490 return -EINVAL;
6491 } else {
6492 return 0;
6493 }
6494 }
6495
6496 if (INTEL_INFO(dev)->num_pipes == 2)
6497 return 0;
6498
6499 /* Ivybridge 3 pipe is really complicated */
6500 switch (pipe) {
6501 case PIPE_A:
6502 return 0;
6503 case PIPE_B:
6504 if (pipe_config->fdi_lanes <= 2)
6505 return 0;
6506
6507 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6508 other_crtc_state =
6509 intel_atomic_get_crtc_state(state, other_crtc);
6510 if (IS_ERR(other_crtc_state))
6511 return PTR_ERR(other_crtc_state);
6512
6513 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6514 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6515 pipe_name(pipe), pipe_config->fdi_lanes);
6516 return -EINVAL;
6517 }
6518 return 0;
6519 case PIPE_C:
6520 if (pipe_config->fdi_lanes > 2) {
6521 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6522 pipe_name(pipe), pipe_config->fdi_lanes);
6523 return -EINVAL;
6524 }
6525
6526 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6527 other_crtc_state =
6528 intel_atomic_get_crtc_state(state, other_crtc);
6529 if (IS_ERR(other_crtc_state))
6530 return PTR_ERR(other_crtc_state);
6531
6532 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6533 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6534 return -EINVAL;
6535 }
6536 return 0;
6537 default:
6538 BUG();
6539 }
6540 }
6541
6542 #define RETRY 1
6543 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6544 struct intel_crtc_state *pipe_config)
6545 {
6546 struct drm_device *dev = intel_crtc->base.dev;
6547 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548 int lane, link_bw, fdi_dotclock, ret;
6549 bool needs_recompute = false;
6550
6551 retry:
6552 /* FDI is a binary signal running at ~2.7GHz, encoding
6553 * each output octet as 10 bits. The actual frequency
6554 * is stored as a divider into a 100MHz clock, and the
6555 * mode pixel clock is stored in units of 1KHz.
6556 * Hence the bw of each lane in terms of the mode signal
6557 * is:
6558 */
6559 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6560
6561 fdi_dotclock = adjusted_mode->crtc_clock;
6562
6563 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6564 pipe_config->pipe_bpp);
6565
6566 pipe_config->fdi_lanes = lane;
6567
6568 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6569 link_bw, &pipe_config->fdi_m_n);
6570
6571 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6572 intel_crtc->pipe, pipe_config);
6573 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6574 pipe_config->pipe_bpp -= 2*3;
6575 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6576 pipe_config->pipe_bpp);
6577 needs_recompute = true;
6578 pipe_config->bw_constrained = true;
6579
6580 goto retry;
6581 }
6582
6583 if (needs_recompute)
6584 return RETRY;
6585
6586 return ret;
6587 }
6588
6589 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6590 struct intel_crtc_state *pipe_config)
6591 {
6592 pipe_config->ips_enabled = i915.enable_ips &&
6593 hsw_crtc_supports_ips(crtc) &&
6594 pipe_config->pipe_bpp <= 24;
6595 }
6596
6597 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6598 struct intel_crtc_state *pipe_config)
6599 {
6600 struct drm_device *dev = crtc->base.dev;
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6602 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6603 int ret;
6604
6605 /* FIXME should check pixel clock limits on all platforms */
6606 if (INTEL_INFO(dev)->gen < 4) {
6607 int clock_limit =
6608 dev_priv->display.get_display_clock_speed(dev);
6609
6610 /*
6611 * Enable pixel doubling when the dot clock
6612 * is > 90% of the (display) core speed.
6613 *
6614 * GDG double wide on either pipe,
6615 * otherwise pipe A only.
6616 */
6617 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6618 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6619 clock_limit *= 2;
6620 pipe_config->double_wide = true;
6621 }
6622
6623 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6624 return -EINVAL;
6625 }
6626
6627 /*
6628 * Pipe horizontal size must be even in:
6629 * - DVO ganged mode
6630 * - LVDS dual channel mode
6631 * - Double wide pipe
6632 */
6633 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6634 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6635 pipe_config->pipe_src_w &= ~1;
6636
6637 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6638 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6639 */
6640 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6641 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6642 return -EINVAL;
6643
6644 if (HAS_IPS(dev))
6645 hsw_compute_ips_config(crtc, pipe_config);
6646
6647 if (pipe_config->has_pch_encoder)
6648 return ironlake_fdi_compute_config(crtc, pipe_config);
6649
6650 /* FIXME: remove below call once atomic mode set is place and all crtc
6651 * related checks called from atomic_crtc_check function */
6652 ret = 0;
6653 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6654 crtc, pipe_config->base.state);
6655 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6656
6657 return ret;
6658 }
6659
6660 static int skylake_get_display_clock_speed(struct drm_device *dev)
6661 {
6662 struct drm_i915_private *dev_priv = to_i915(dev);
6663 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6664 uint32_t cdctl = I915_READ(CDCLK_CTL);
6665 uint32_t linkrate;
6666
6667 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6668 WARN(1, "LCPLL1 not enabled\n");
6669 return 24000; /* 24MHz is the cd freq with NSSC ref */
6670 }
6671
6672 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6673 return 540000;
6674
6675 linkrate = (I915_READ(DPLL_CTRL1) &
6676 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6677
6678 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6679 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6680 /* vco 8640 */
6681 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6682 case CDCLK_FREQ_450_432:
6683 return 432000;
6684 case CDCLK_FREQ_337_308:
6685 return 308570;
6686 case CDCLK_FREQ_675_617:
6687 return 617140;
6688 default:
6689 WARN(1, "Unknown cd freq selection\n");
6690 }
6691 } else {
6692 /* vco 8100 */
6693 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6694 case CDCLK_FREQ_450_432:
6695 return 450000;
6696 case CDCLK_FREQ_337_308:
6697 return 337500;
6698 case CDCLK_FREQ_675_617:
6699 return 675000;
6700 default:
6701 WARN(1, "Unknown cd freq selection\n");
6702 }
6703 }
6704
6705 /* error case, do as if DPLL0 isn't enabled */
6706 return 24000;
6707 }
6708
6709 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6710 {
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 uint32_t lcpll = I915_READ(LCPLL_CTL);
6713 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6714
6715 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6716 return 800000;
6717 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6718 return 450000;
6719 else if (freq == LCPLL_CLK_FREQ_450)
6720 return 450000;
6721 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6722 return 540000;
6723 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6724 return 337500;
6725 else
6726 return 675000;
6727 }
6728
6729 static int haswell_get_display_clock_speed(struct drm_device *dev)
6730 {
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732 uint32_t lcpll = I915_READ(LCPLL_CTL);
6733 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6734
6735 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6736 return 800000;
6737 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6738 return 450000;
6739 else if (freq == LCPLL_CLK_FREQ_450)
6740 return 450000;
6741 else if (IS_HSW_ULT(dev))
6742 return 337500;
6743 else
6744 return 540000;
6745 }
6746
6747 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6748 {
6749 struct drm_i915_private *dev_priv = dev->dev_private;
6750 u32 val;
6751 int divider;
6752
6753 if (dev_priv->hpll_freq == 0)
6754 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6755
6756 mutex_lock(&dev_priv->sb_lock);
6757 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6758 mutex_unlock(&dev_priv->sb_lock);
6759
6760 divider = val & DISPLAY_FREQUENCY_VALUES;
6761
6762 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6763 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6764 "cdclk change in progress\n");
6765
6766 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6767 }
6768
6769 static int ilk_get_display_clock_speed(struct drm_device *dev)
6770 {
6771 return 450000;
6772 }
6773
6774 static int i945_get_display_clock_speed(struct drm_device *dev)
6775 {
6776 return 400000;
6777 }
6778
6779 static int i915_get_display_clock_speed(struct drm_device *dev)
6780 {
6781 return 333333;
6782 }
6783
6784 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6785 {
6786 return 200000;
6787 }
6788
6789 static int pnv_get_display_clock_speed(struct drm_device *dev)
6790 {
6791 u16 gcfgc = 0;
6792
6793 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6794
6795 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6797 return 266667;
6798 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6799 return 333333;
6800 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6801 return 444444;
6802 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6803 return 200000;
6804 default:
6805 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6806 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6807 return 133333;
6808 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6809 return 166667;
6810 }
6811 }
6812
6813 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6814 {
6815 u16 gcfgc = 0;
6816
6817 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6818
6819 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6820 return 133333;
6821 else {
6822 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6823 case GC_DISPLAY_CLOCK_333_MHZ:
6824 return 333333;
6825 default:
6826 case GC_DISPLAY_CLOCK_190_200_MHZ:
6827 return 190000;
6828 }
6829 }
6830 }
6831
6832 static int i865_get_display_clock_speed(struct drm_device *dev)
6833 {
6834 return 266667;
6835 }
6836
6837 static int i855_get_display_clock_speed(struct drm_device *dev)
6838 {
6839 u16 hpllcc = 0;
6840 /* Assume that the hardware is in the high speed state. This
6841 * should be the default.
6842 */
6843 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6844 case GC_CLOCK_133_200:
6845 case GC_CLOCK_100_200:
6846 return 200000;
6847 case GC_CLOCK_166_250:
6848 return 250000;
6849 case GC_CLOCK_100_133:
6850 return 133333;
6851 }
6852
6853 /* Shouldn't happen */
6854 return 0;
6855 }
6856
6857 static int i830_get_display_clock_speed(struct drm_device *dev)
6858 {
6859 return 133333;
6860 }
6861
6862 static void
6863 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6864 {
6865 while (*num > DATA_LINK_M_N_MASK ||
6866 *den > DATA_LINK_M_N_MASK) {
6867 *num >>= 1;
6868 *den >>= 1;
6869 }
6870 }
6871
6872 static void compute_m_n(unsigned int m, unsigned int n,
6873 uint32_t *ret_m, uint32_t *ret_n)
6874 {
6875 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6876 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6877 intel_reduce_m_n_ratio(ret_m, ret_n);
6878 }
6879
6880 void
6881 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6882 int pixel_clock, int link_clock,
6883 struct intel_link_m_n *m_n)
6884 {
6885 m_n->tu = 64;
6886
6887 compute_m_n(bits_per_pixel * pixel_clock,
6888 link_clock * nlanes * 8,
6889 &m_n->gmch_m, &m_n->gmch_n);
6890
6891 compute_m_n(pixel_clock, link_clock,
6892 &m_n->link_m, &m_n->link_n);
6893 }
6894
6895 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6896 {
6897 if (i915.panel_use_ssc >= 0)
6898 return i915.panel_use_ssc != 0;
6899 return dev_priv->vbt.lvds_use_ssc
6900 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6901 }
6902
6903 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6904 int num_connectors)
6905 {
6906 struct drm_device *dev = crtc_state->base.crtc->dev;
6907 struct drm_i915_private *dev_priv = dev->dev_private;
6908 int refclk;
6909
6910 WARN_ON(!crtc_state->base.state);
6911
6912 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6913 refclk = 100000;
6914 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6915 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6916 refclk = dev_priv->vbt.lvds_ssc_freq;
6917 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6918 } else if (!IS_GEN2(dev)) {
6919 refclk = 96000;
6920 } else {
6921 refclk = 48000;
6922 }
6923
6924 return refclk;
6925 }
6926
6927 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6928 {
6929 return (1 << dpll->n) << 16 | dpll->m2;
6930 }
6931
6932 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6933 {
6934 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6935 }
6936
6937 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6938 struct intel_crtc_state *crtc_state,
6939 intel_clock_t *reduced_clock)
6940 {
6941 struct drm_device *dev = crtc->base.dev;
6942 u32 fp, fp2 = 0;
6943
6944 if (IS_PINEVIEW(dev)) {
6945 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6946 if (reduced_clock)
6947 fp2 = pnv_dpll_compute_fp(reduced_clock);
6948 } else {
6949 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6950 if (reduced_clock)
6951 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6952 }
6953
6954 crtc_state->dpll_hw_state.fp0 = fp;
6955
6956 crtc->lowfreq_avail = false;
6957 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6958 reduced_clock) {
6959 crtc_state->dpll_hw_state.fp1 = fp2;
6960 crtc->lowfreq_avail = true;
6961 } else {
6962 crtc_state->dpll_hw_state.fp1 = fp;
6963 }
6964 }
6965
6966 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6967 pipe)
6968 {
6969 u32 reg_val;
6970
6971 /*
6972 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6973 * and set it to a reasonable value instead.
6974 */
6975 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6976 reg_val &= 0xffffff00;
6977 reg_val |= 0x00000030;
6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6979
6980 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6981 reg_val &= 0x8cffffff;
6982 reg_val = 0x8c000000;
6983 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6984
6985 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6986 reg_val &= 0xffffff00;
6987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6988
6989 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6990 reg_val &= 0x00ffffff;
6991 reg_val |= 0xb0000000;
6992 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6993 }
6994
6995 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6996 struct intel_link_m_n *m_n)
6997 {
6998 struct drm_device *dev = crtc->base.dev;
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 int pipe = crtc->pipe;
7001
7002 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7003 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7004 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7005 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7006 }
7007
7008 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7009 struct intel_link_m_n *m_n,
7010 struct intel_link_m_n *m2_n2)
7011 {
7012 struct drm_device *dev = crtc->base.dev;
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 int pipe = crtc->pipe;
7015 enum transcoder transcoder = crtc->config->cpu_transcoder;
7016
7017 if (INTEL_INFO(dev)->gen >= 5) {
7018 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7019 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7020 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7021 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7022 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7023 * for gen < 8) and if DRRS is supported (to make sure the
7024 * registers are not unnecessarily accessed).
7025 */
7026 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7027 crtc->config->has_drrs) {
7028 I915_WRITE(PIPE_DATA_M2(transcoder),
7029 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7030 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7031 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7032 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7033 }
7034 } else {
7035 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7036 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7037 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7038 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7039 }
7040 }
7041
7042 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7043 {
7044 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7045
7046 if (m_n == M1_N1) {
7047 dp_m_n = &crtc->config->dp_m_n;
7048 dp_m2_n2 = &crtc->config->dp_m2_n2;
7049 } else if (m_n == M2_N2) {
7050
7051 /*
7052 * M2_N2 registers are not supported. Hence m2_n2 divider value
7053 * needs to be programmed into M1_N1.
7054 */
7055 dp_m_n = &crtc->config->dp_m2_n2;
7056 } else {
7057 DRM_ERROR("Unsupported divider value\n");
7058 return;
7059 }
7060
7061 if (crtc->config->has_pch_encoder)
7062 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7063 else
7064 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7065 }
7066
7067 static void vlv_update_pll(struct intel_crtc *crtc,
7068 struct intel_crtc_state *pipe_config)
7069 {
7070 u32 dpll, dpll_md;
7071
7072 /*
7073 * Enable DPIO clock input. We should never disable the reference
7074 * clock for pipe B, since VGA hotplug / manual detection depends
7075 * on it.
7076 */
7077 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7078 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7079 /* We should never disable this, set it here for state tracking */
7080 if (crtc->pipe == PIPE_B)
7081 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7082 dpll |= DPLL_VCO_ENABLE;
7083 pipe_config->dpll_hw_state.dpll = dpll;
7084
7085 dpll_md = (pipe_config->pixel_multiplier - 1)
7086 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7087 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7088 }
7089
7090 static void vlv_prepare_pll(struct intel_crtc *crtc,
7091 const struct intel_crtc_state *pipe_config)
7092 {
7093 struct drm_device *dev = crtc->base.dev;
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095 int pipe = crtc->pipe;
7096 u32 mdiv;
7097 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7098 u32 coreclk, reg_val;
7099
7100 mutex_lock(&dev_priv->sb_lock);
7101
7102 bestn = pipe_config->dpll.n;
7103 bestm1 = pipe_config->dpll.m1;
7104 bestm2 = pipe_config->dpll.m2;
7105 bestp1 = pipe_config->dpll.p1;
7106 bestp2 = pipe_config->dpll.p2;
7107
7108 /* See eDP HDMI DPIO driver vbios notes doc */
7109
7110 /* PLL B needs special handling */
7111 if (pipe == PIPE_B)
7112 vlv_pllb_recal_opamp(dev_priv, pipe);
7113
7114 /* Set up Tx target for periodic Rcomp update */
7115 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7116
7117 /* Disable target IRef on PLL */
7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7119 reg_val &= 0x00ffffff;
7120 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7121
7122 /* Disable fast lock */
7123 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7124
7125 /* Set idtafcrecal before PLL is enabled */
7126 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7127 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7128 mdiv |= ((bestn << DPIO_N_SHIFT));
7129 mdiv |= (1 << DPIO_K_SHIFT);
7130
7131 /*
7132 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7133 * but we don't support that).
7134 * Note: don't use the DAC post divider as it seems unstable.
7135 */
7136 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7138
7139 mdiv |= DPIO_ENABLE_CALIBRATION;
7140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7141
7142 /* Set HBR and RBR LPF coefficients */
7143 if (pipe_config->port_clock == 162000 ||
7144 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7145 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7146 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7147 0x009f0003);
7148 else
7149 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7150 0x00d0000f);
7151
7152 if (pipe_config->has_dp_encoder) {
7153 /* Use SSC source */
7154 if (pipe == PIPE_A)
7155 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7156 0x0df40000);
7157 else
7158 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7159 0x0df70000);
7160 } else { /* HDMI or VGA */
7161 /* Use bend source */
7162 if (pipe == PIPE_A)
7163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7164 0x0df70000);
7165 else
7166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7167 0x0df40000);
7168 }
7169
7170 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7171 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7172 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7173 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7174 coreclk |= 0x01000000;
7175 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7176
7177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7178 mutex_unlock(&dev_priv->sb_lock);
7179 }
7180
7181 static void chv_update_pll(struct intel_crtc *crtc,
7182 struct intel_crtc_state *pipe_config)
7183 {
7184 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7185 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7186 DPLL_VCO_ENABLE;
7187 if (crtc->pipe != PIPE_A)
7188 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7189
7190 pipe_config->dpll_hw_state.dpll_md =
7191 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7192 }
7193
7194 static void chv_prepare_pll(struct intel_crtc *crtc,
7195 const struct intel_crtc_state *pipe_config)
7196 {
7197 struct drm_device *dev = crtc->base.dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 int pipe = crtc->pipe;
7200 int dpll_reg = DPLL(crtc->pipe);
7201 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7202 u32 loopfilter, tribuf_calcntr;
7203 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7204 u32 dpio_val;
7205 int vco;
7206
7207 bestn = pipe_config->dpll.n;
7208 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7209 bestm1 = pipe_config->dpll.m1;
7210 bestm2 = pipe_config->dpll.m2 >> 22;
7211 bestp1 = pipe_config->dpll.p1;
7212 bestp2 = pipe_config->dpll.p2;
7213 vco = pipe_config->dpll.vco;
7214 dpio_val = 0;
7215 loopfilter = 0;
7216
7217 /*
7218 * Enable Refclk and SSC
7219 */
7220 I915_WRITE(dpll_reg,
7221 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7222
7223 mutex_lock(&dev_priv->sb_lock);
7224
7225 /* p1 and p2 divider */
7226 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7227 5 << DPIO_CHV_S1_DIV_SHIFT |
7228 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7229 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7230 1 << DPIO_CHV_K_DIV_SHIFT);
7231
7232 /* Feedback post-divider - m2 */
7233 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7234
7235 /* Feedback refclk divider - n and m1 */
7236 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7237 DPIO_CHV_M1_DIV_BY_2 |
7238 1 << DPIO_CHV_N_DIV_SHIFT);
7239
7240 /* M2 fraction division */
7241 if (bestm2_frac)
7242 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7243
7244 /* M2 fraction division enable */
7245 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7246 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7247 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7248 if (bestm2_frac)
7249 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7250 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7251
7252 /* Program digital lock detect threshold */
7253 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7254 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7255 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7256 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7257 if (!bestm2_frac)
7258 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7259 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7260
7261 /* Loop filter */
7262 if (vco == 5400000) {
7263 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7264 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7265 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7266 tribuf_calcntr = 0x9;
7267 } else if (vco <= 6200000) {
7268 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7269 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7270 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7271 tribuf_calcntr = 0x9;
7272 } else if (vco <= 6480000) {
7273 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7274 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7275 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7276 tribuf_calcntr = 0x8;
7277 } else {
7278 /* Not supported. Apply the same limits as in the max case */
7279 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7280 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7281 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7282 tribuf_calcntr = 0;
7283 }
7284 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7285
7286 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7287 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7288 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7289 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7290
7291 /* AFC Recal */
7292 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7293 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7294 DPIO_AFC_RECAL);
7295
7296 mutex_unlock(&dev_priv->sb_lock);
7297 }
7298
7299 /**
7300 * vlv_force_pll_on - forcibly enable just the PLL
7301 * @dev_priv: i915 private structure
7302 * @pipe: pipe PLL to enable
7303 * @dpll: PLL configuration
7304 *
7305 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7306 * in cases where we need the PLL enabled even when @pipe is not going to
7307 * be enabled.
7308 */
7309 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7310 const struct dpll *dpll)
7311 {
7312 struct intel_crtc *crtc =
7313 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7314 struct intel_crtc_state pipe_config = {
7315 .base.crtc = &crtc->base,
7316 .pixel_multiplier = 1,
7317 .dpll = *dpll,
7318 };
7319
7320 if (IS_CHERRYVIEW(dev)) {
7321 chv_update_pll(crtc, &pipe_config);
7322 chv_prepare_pll(crtc, &pipe_config);
7323 chv_enable_pll(crtc, &pipe_config);
7324 } else {
7325 vlv_update_pll(crtc, &pipe_config);
7326 vlv_prepare_pll(crtc, &pipe_config);
7327 vlv_enable_pll(crtc, &pipe_config);
7328 }
7329 }
7330
7331 /**
7332 * vlv_force_pll_off - forcibly disable just the PLL
7333 * @dev_priv: i915 private structure
7334 * @pipe: pipe PLL to disable
7335 *
7336 * Disable the PLL for @pipe. To be used in cases where we need
7337 * the PLL enabled even when @pipe is not going to be enabled.
7338 */
7339 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7340 {
7341 if (IS_CHERRYVIEW(dev))
7342 chv_disable_pll(to_i915(dev), pipe);
7343 else
7344 vlv_disable_pll(to_i915(dev), pipe);
7345 }
7346
7347 static void i9xx_update_pll(struct intel_crtc *crtc,
7348 struct intel_crtc_state *crtc_state,
7349 intel_clock_t *reduced_clock,
7350 int num_connectors)
7351 {
7352 struct drm_device *dev = crtc->base.dev;
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354 u32 dpll;
7355 bool is_sdvo;
7356 struct dpll *clock = &crtc_state->dpll;
7357
7358 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7359
7360 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7361 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7362
7363 dpll = DPLL_VGA_MODE_DIS;
7364
7365 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7366 dpll |= DPLLB_MODE_LVDS;
7367 else
7368 dpll |= DPLLB_MODE_DAC_SERIAL;
7369
7370 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7371 dpll |= (crtc_state->pixel_multiplier - 1)
7372 << SDVO_MULTIPLIER_SHIFT_HIRES;
7373 }
7374
7375 if (is_sdvo)
7376 dpll |= DPLL_SDVO_HIGH_SPEED;
7377
7378 if (crtc_state->has_dp_encoder)
7379 dpll |= DPLL_SDVO_HIGH_SPEED;
7380
7381 /* compute bitmask from p1 value */
7382 if (IS_PINEVIEW(dev))
7383 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7384 else {
7385 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7386 if (IS_G4X(dev) && reduced_clock)
7387 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7388 }
7389 switch (clock->p2) {
7390 case 5:
7391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7392 break;
7393 case 7:
7394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7395 break;
7396 case 10:
7397 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7398 break;
7399 case 14:
7400 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7401 break;
7402 }
7403 if (INTEL_INFO(dev)->gen >= 4)
7404 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7405
7406 if (crtc_state->sdvo_tv_clock)
7407 dpll |= PLL_REF_INPUT_TVCLKINBC;
7408 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7409 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7410 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7411 else
7412 dpll |= PLL_REF_INPUT_DREFCLK;
7413
7414 dpll |= DPLL_VCO_ENABLE;
7415 crtc_state->dpll_hw_state.dpll = dpll;
7416
7417 if (INTEL_INFO(dev)->gen >= 4) {
7418 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7419 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7420 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7421 }
7422 }
7423
7424 static void i8xx_update_pll(struct intel_crtc *crtc,
7425 struct intel_crtc_state *crtc_state,
7426 intel_clock_t *reduced_clock,
7427 int num_connectors)
7428 {
7429 struct drm_device *dev = crtc->base.dev;
7430 struct drm_i915_private *dev_priv = dev->dev_private;
7431 u32 dpll;
7432 struct dpll *clock = &crtc_state->dpll;
7433
7434 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7435
7436 dpll = DPLL_VGA_MODE_DIS;
7437
7438 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7439 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7440 } else {
7441 if (clock->p1 == 2)
7442 dpll |= PLL_P1_DIVIDE_BY_TWO;
7443 else
7444 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7445 if (clock->p2 == 4)
7446 dpll |= PLL_P2_DIVIDE_BY_4;
7447 }
7448
7449 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7450 dpll |= DPLL_DVO_2X_MODE;
7451
7452 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7453 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7455 else
7456 dpll |= PLL_REF_INPUT_DREFCLK;
7457
7458 dpll |= DPLL_VCO_ENABLE;
7459 crtc_state->dpll_hw_state.dpll = dpll;
7460 }
7461
7462 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7463 {
7464 struct drm_device *dev = intel_crtc->base.dev;
7465 struct drm_i915_private *dev_priv = dev->dev_private;
7466 enum pipe pipe = intel_crtc->pipe;
7467 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7468 struct drm_display_mode *adjusted_mode =
7469 &intel_crtc->config->base.adjusted_mode;
7470 uint32_t crtc_vtotal, crtc_vblank_end;
7471 int vsyncshift = 0;
7472
7473 /* We need to be careful not to changed the adjusted mode, for otherwise
7474 * the hw state checker will get angry at the mismatch. */
7475 crtc_vtotal = adjusted_mode->crtc_vtotal;
7476 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7477
7478 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7479 /* the chip adds 2 halflines automatically */
7480 crtc_vtotal -= 1;
7481 crtc_vblank_end -= 1;
7482
7483 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7484 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7485 else
7486 vsyncshift = adjusted_mode->crtc_hsync_start -
7487 adjusted_mode->crtc_htotal / 2;
7488 if (vsyncshift < 0)
7489 vsyncshift += adjusted_mode->crtc_htotal;
7490 }
7491
7492 if (INTEL_INFO(dev)->gen > 3)
7493 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7494
7495 I915_WRITE(HTOTAL(cpu_transcoder),
7496 (adjusted_mode->crtc_hdisplay - 1) |
7497 ((adjusted_mode->crtc_htotal - 1) << 16));
7498 I915_WRITE(HBLANK(cpu_transcoder),
7499 (adjusted_mode->crtc_hblank_start - 1) |
7500 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7501 I915_WRITE(HSYNC(cpu_transcoder),
7502 (adjusted_mode->crtc_hsync_start - 1) |
7503 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7504
7505 I915_WRITE(VTOTAL(cpu_transcoder),
7506 (adjusted_mode->crtc_vdisplay - 1) |
7507 ((crtc_vtotal - 1) << 16));
7508 I915_WRITE(VBLANK(cpu_transcoder),
7509 (adjusted_mode->crtc_vblank_start - 1) |
7510 ((crtc_vblank_end - 1) << 16));
7511 I915_WRITE(VSYNC(cpu_transcoder),
7512 (adjusted_mode->crtc_vsync_start - 1) |
7513 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7514
7515 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7516 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7517 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7518 * bits. */
7519 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7520 (pipe == PIPE_B || pipe == PIPE_C))
7521 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7522
7523 /* pipesrc controls the size that is scaled from, which should
7524 * always be the user's requested size.
7525 */
7526 I915_WRITE(PIPESRC(pipe),
7527 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7528 (intel_crtc->config->pipe_src_h - 1));
7529 }
7530
7531 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7532 struct intel_crtc_state *pipe_config)
7533 {
7534 struct drm_device *dev = crtc->base.dev;
7535 struct drm_i915_private *dev_priv = dev->dev_private;
7536 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7537 uint32_t tmp;
7538
7539 tmp = I915_READ(HTOTAL(cpu_transcoder));
7540 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7541 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7542 tmp = I915_READ(HBLANK(cpu_transcoder));
7543 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7544 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7545 tmp = I915_READ(HSYNC(cpu_transcoder));
7546 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7547 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7548
7549 tmp = I915_READ(VTOTAL(cpu_transcoder));
7550 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7551 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7552 tmp = I915_READ(VBLANK(cpu_transcoder));
7553 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7554 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7555 tmp = I915_READ(VSYNC(cpu_transcoder));
7556 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7557 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7558
7559 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7560 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7561 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7562 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7563 }
7564
7565 tmp = I915_READ(PIPESRC(crtc->pipe));
7566 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7567 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7568
7569 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7570 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7571 }
7572
7573 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7574 struct intel_crtc_state *pipe_config)
7575 {
7576 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7577 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7578 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7579 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7580
7581 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7582 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7583 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7584 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7585
7586 mode->flags = pipe_config->base.adjusted_mode.flags;
7587
7588 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7589 mode->flags |= pipe_config->base.adjusted_mode.flags;
7590 }
7591
7592 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7593 {
7594 struct drm_device *dev = intel_crtc->base.dev;
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7596 uint32_t pipeconf;
7597
7598 pipeconf = 0;
7599
7600 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7601 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7602 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7603
7604 if (intel_crtc->config->double_wide)
7605 pipeconf |= PIPECONF_DOUBLE_WIDE;
7606
7607 /* only g4x and later have fancy bpc/dither controls */
7608 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7609 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7610 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7611 pipeconf |= PIPECONF_DITHER_EN |
7612 PIPECONF_DITHER_TYPE_SP;
7613
7614 switch (intel_crtc->config->pipe_bpp) {
7615 case 18:
7616 pipeconf |= PIPECONF_6BPC;
7617 break;
7618 case 24:
7619 pipeconf |= PIPECONF_8BPC;
7620 break;
7621 case 30:
7622 pipeconf |= PIPECONF_10BPC;
7623 break;
7624 default:
7625 /* Case prevented by intel_choose_pipe_bpp_dither. */
7626 BUG();
7627 }
7628 }
7629
7630 if (HAS_PIPE_CXSR(dev)) {
7631 if (intel_crtc->lowfreq_avail) {
7632 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7633 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7634 } else {
7635 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7636 }
7637 }
7638
7639 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7640 if (INTEL_INFO(dev)->gen < 4 ||
7641 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7642 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7643 else
7644 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7645 } else
7646 pipeconf |= PIPECONF_PROGRESSIVE;
7647
7648 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7649 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7650
7651 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7652 POSTING_READ(PIPECONF(intel_crtc->pipe));
7653 }
7654
7655 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7656 struct intel_crtc_state *crtc_state)
7657 {
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7660 int refclk, num_connectors = 0;
7661 intel_clock_t clock, reduced_clock;
7662 bool ok, has_reduced_clock = false;
7663 bool is_lvds = false, is_dsi = false;
7664 struct intel_encoder *encoder;
7665 const intel_limit_t *limit;
7666 struct drm_atomic_state *state = crtc_state->base.state;
7667 struct drm_connector *connector;
7668 struct drm_connector_state *connector_state;
7669 int i;
7670
7671 memset(&crtc_state->dpll_hw_state, 0,
7672 sizeof(crtc_state->dpll_hw_state));
7673
7674 for_each_connector_in_state(state, connector, connector_state, i) {
7675 if (connector_state->crtc != &crtc->base)
7676 continue;
7677
7678 encoder = to_intel_encoder(connector_state->best_encoder);
7679
7680 switch (encoder->type) {
7681 case INTEL_OUTPUT_LVDS:
7682 is_lvds = true;
7683 break;
7684 case INTEL_OUTPUT_DSI:
7685 is_dsi = true;
7686 break;
7687 default:
7688 break;
7689 }
7690
7691 num_connectors++;
7692 }
7693
7694 if (is_dsi)
7695 return 0;
7696
7697 if (!crtc_state->clock_set) {
7698 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7699
7700 /*
7701 * Returns a set of divisors for the desired target clock with
7702 * the given refclk, or FALSE. The returned values represent
7703 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7704 * 2) / p1 / p2.
7705 */
7706 limit = intel_limit(crtc_state, refclk);
7707 ok = dev_priv->display.find_dpll(limit, crtc_state,
7708 crtc_state->port_clock,
7709 refclk, NULL, &clock);
7710 if (!ok) {
7711 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7712 return -EINVAL;
7713 }
7714
7715 if (is_lvds && dev_priv->lvds_downclock_avail) {
7716 /*
7717 * Ensure we match the reduced clock's P to the target
7718 * clock. If the clocks don't match, we can't switch
7719 * the display clock by using the FP0/FP1. In such case
7720 * we will disable the LVDS downclock feature.
7721 */
7722 has_reduced_clock =
7723 dev_priv->display.find_dpll(limit, crtc_state,
7724 dev_priv->lvds_downclock,
7725 refclk, &clock,
7726 &reduced_clock);
7727 }
7728 /* Compat-code for transition, will disappear. */
7729 crtc_state->dpll.n = clock.n;
7730 crtc_state->dpll.m1 = clock.m1;
7731 crtc_state->dpll.m2 = clock.m2;
7732 crtc_state->dpll.p1 = clock.p1;
7733 crtc_state->dpll.p2 = clock.p2;
7734 }
7735
7736 if (IS_GEN2(dev)) {
7737 i8xx_update_pll(crtc, crtc_state,
7738 has_reduced_clock ? &reduced_clock : NULL,
7739 num_connectors);
7740 } else if (IS_CHERRYVIEW(dev)) {
7741 chv_update_pll(crtc, crtc_state);
7742 } else if (IS_VALLEYVIEW(dev)) {
7743 vlv_update_pll(crtc, crtc_state);
7744 } else {
7745 i9xx_update_pll(crtc, crtc_state,
7746 has_reduced_clock ? &reduced_clock : NULL,
7747 num_connectors);
7748 }
7749
7750 return 0;
7751 }
7752
7753 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7754 struct intel_crtc_state *pipe_config)
7755 {
7756 struct drm_device *dev = crtc->base.dev;
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7758 uint32_t tmp;
7759
7760 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7761 return;
7762
7763 tmp = I915_READ(PFIT_CONTROL);
7764 if (!(tmp & PFIT_ENABLE))
7765 return;
7766
7767 /* Check whether the pfit is attached to our pipe. */
7768 if (INTEL_INFO(dev)->gen < 4) {
7769 if (crtc->pipe != PIPE_B)
7770 return;
7771 } else {
7772 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7773 return;
7774 }
7775
7776 pipe_config->gmch_pfit.control = tmp;
7777 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7778 if (INTEL_INFO(dev)->gen < 5)
7779 pipe_config->gmch_pfit.lvds_border_bits =
7780 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7781 }
7782
7783 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7784 struct intel_crtc_state *pipe_config)
7785 {
7786 struct drm_device *dev = crtc->base.dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
7788 int pipe = pipe_config->cpu_transcoder;
7789 intel_clock_t clock;
7790 u32 mdiv;
7791 int refclk = 100000;
7792
7793 /* In case of MIPI DPLL will not even be used */
7794 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7795 return;
7796
7797 mutex_lock(&dev_priv->sb_lock);
7798 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7799 mutex_unlock(&dev_priv->sb_lock);
7800
7801 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7802 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7803 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7804 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7805 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7806
7807 vlv_clock(refclk, &clock);
7808
7809 /* clock.dot is the fast clock */
7810 pipe_config->port_clock = clock.dot / 5;
7811 }
7812
7813 static void
7814 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7815 struct intel_initial_plane_config *plane_config)
7816 {
7817 struct drm_device *dev = crtc->base.dev;
7818 struct drm_i915_private *dev_priv = dev->dev_private;
7819 u32 val, base, offset;
7820 int pipe = crtc->pipe, plane = crtc->plane;
7821 int fourcc, pixel_format;
7822 unsigned int aligned_height;
7823 struct drm_framebuffer *fb;
7824 struct intel_framebuffer *intel_fb;
7825
7826 val = I915_READ(DSPCNTR(plane));
7827 if (!(val & DISPLAY_PLANE_ENABLE))
7828 return;
7829
7830 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7831 if (!intel_fb) {
7832 DRM_DEBUG_KMS("failed to alloc fb\n");
7833 return;
7834 }
7835
7836 fb = &intel_fb->base;
7837
7838 if (INTEL_INFO(dev)->gen >= 4) {
7839 if (val & DISPPLANE_TILED) {
7840 plane_config->tiling = I915_TILING_X;
7841 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7842 }
7843 }
7844
7845 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7846 fourcc = i9xx_format_to_fourcc(pixel_format);
7847 fb->pixel_format = fourcc;
7848 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7849
7850 if (INTEL_INFO(dev)->gen >= 4) {
7851 if (plane_config->tiling)
7852 offset = I915_READ(DSPTILEOFF(plane));
7853 else
7854 offset = I915_READ(DSPLINOFF(plane));
7855 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7856 } else {
7857 base = I915_READ(DSPADDR(plane));
7858 }
7859 plane_config->base = base;
7860
7861 val = I915_READ(PIPESRC(pipe));
7862 fb->width = ((val >> 16) & 0xfff) + 1;
7863 fb->height = ((val >> 0) & 0xfff) + 1;
7864
7865 val = I915_READ(DSPSTRIDE(pipe));
7866 fb->pitches[0] = val & 0xffffffc0;
7867
7868 aligned_height = intel_fb_align_height(dev, fb->height,
7869 fb->pixel_format,
7870 fb->modifier[0]);
7871
7872 plane_config->size = fb->pitches[0] * aligned_height;
7873
7874 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7875 pipe_name(pipe), plane, fb->width, fb->height,
7876 fb->bits_per_pixel, base, fb->pitches[0],
7877 plane_config->size);
7878
7879 plane_config->fb = intel_fb;
7880 }
7881
7882 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7883 struct intel_crtc_state *pipe_config)
7884 {
7885 struct drm_device *dev = crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7887 int pipe = pipe_config->cpu_transcoder;
7888 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7889 intel_clock_t clock;
7890 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7891 int refclk = 100000;
7892
7893 mutex_lock(&dev_priv->sb_lock);
7894 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7895 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7896 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7897 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7898 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7899 mutex_unlock(&dev_priv->sb_lock);
7900
7901 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7902 clock.m2 = (pll_dw0 & 0xff) << 22;
7903 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7904 clock.m2 |= pll_dw2 & 0x3fffff;
7905 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7906 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7907 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7908
7909 chv_clock(refclk, &clock);
7910
7911 /* clock.dot is the fast clock */
7912 pipe_config->port_clock = clock.dot / 5;
7913 }
7914
7915 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7916 struct intel_crtc_state *pipe_config)
7917 {
7918 struct drm_device *dev = crtc->base.dev;
7919 struct drm_i915_private *dev_priv = dev->dev_private;
7920 uint32_t tmp;
7921
7922 if (!intel_display_power_is_enabled(dev_priv,
7923 POWER_DOMAIN_PIPE(crtc->pipe)))
7924 return false;
7925
7926 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7927 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7928
7929 tmp = I915_READ(PIPECONF(crtc->pipe));
7930 if (!(tmp & PIPECONF_ENABLE))
7931 return false;
7932
7933 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7934 switch (tmp & PIPECONF_BPC_MASK) {
7935 case PIPECONF_6BPC:
7936 pipe_config->pipe_bpp = 18;
7937 break;
7938 case PIPECONF_8BPC:
7939 pipe_config->pipe_bpp = 24;
7940 break;
7941 case PIPECONF_10BPC:
7942 pipe_config->pipe_bpp = 30;
7943 break;
7944 default:
7945 break;
7946 }
7947 }
7948
7949 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7950 pipe_config->limited_color_range = true;
7951
7952 if (INTEL_INFO(dev)->gen < 4)
7953 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7954
7955 intel_get_pipe_timings(crtc, pipe_config);
7956
7957 i9xx_get_pfit_config(crtc, pipe_config);
7958
7959 if (INTEL_INFO(dev)->gen >= 4) {
7960 tmp = I915_READ(DPLL_MD(crtc->pipe));
7961 pipe_config->pixel_multiplier =
7962 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7963 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7964 pipe_config->dpll_hw_state.dpll_md = tmp;
7965 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7966 tmp = I915_READ(DPLL(crtc->pipe));
7967 pipe_config->pixel_multiplier =
7968 ((tmp & SDVO_MULTIPLIER_MASK)
7969 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7970 } else {
7971 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7972 * port and will be fixed up in the encoder->get_config
7973 * function. */
7974 pipe_config->pixel_multiplier = 1;
7975 }
7976 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7977 if (!IS_VALLEYVIEW(dev)) {
7978 /*
7979 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7980 * on 830. Filter it out here so that we don't
7981 * report errors due to that.
7982 */
7983 if (IS_I830(dev))
7984 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7985
7986 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7987 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7988 } else {
7989 /* Mask out read-only status bits. */
7990 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7991 DPLL_PORTC_READY_MASK |
7992 DPLL_PORTB_READY_MASK);
7993 }
7994
7995 if (IS_CHERRYVIEW(dev))
7996 chv_crtc_clock_get(crtc, pipe_config);
7997 else if (IS_VALLEYVIEW(dev))
7998 vlv_crtc_clock_get(crtc, pipe_config);
7999 else
8000 i9xx_crtc_clock_get(crtc, pipe_config);
8001
8002 return true;
8003 }
8004
8005 static void ironlake_init_pch_refclk(struct drm_device *dev)
8006 {
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008 struct intel_encoder *encoder;
8009 u32 val, final;
8010 bool has_lvds = false;
8011 bool has_cpu_edp = false;
8012 bool has_panel = false;
8013 bool has_ck505 = false;
8014 bool can_ssc = false;
8015
8016 /* We need to take the global config into account */
8017 for_each_intel_encoder(dev, encoder) {
8018 switch (encoder->type) {
8019 case INTEL_OUTPUT_LVDS:
8020 has_panel = true;
8021 has_lvds = true;
8022 break;
8023 case INTEL_OUTPUT_EDP:
8024 has_panel = true;
8025 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8026 has_cpu_edp = true;
8027 break;
8028 default:
8029 break;
8030 }
8031 }
8032
8033 if (HAS_PCH_IBX(dev)) {
8034 has_ck505 = dev_priv->vbt.display_clock_mode;
8035 can_ssc = has_ck505;
8036 } else {
8037 has_ck505 = false;
8038 can_ssc = true;
8039 }
8040
8041 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8042 has_panel, has_lvds, has_ck505);
8043
8044 /* Ironlake: try to setup display ref clock before DPLL
8045 * enabling. This is only under driver's control after
8046 * PCH B stepping, previous chipset stepping should be
8047 * ignoring this setting.
8048 */
8049 val = I915_READ(PCH_DREF_CONTROL);
8050
8051 /* As we must carefully and slowly disable/enable each source in turn,
8052 * compute the final state we want first and check if we need to
8053 * make any changes at all.
8054 */
8055 final = val;
8056 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8057 if (has_ck505)
8058 final |= DREF_NONSPREAD_CK505_ENABLE;
8059 else
8060 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8061
8062 final &= ~DREF_SSC_SOURCE_MASK;
8063 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8064 final &= ~DREF_SSC1_ENABLE;
8065
8066 if (has_panel) {
8067 final |= DREF_SSC_SOURCE_ENABLE;
8068
8069 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8070 final |= DREF_SSC1_ENABLE;
8071
8072 if (has_cpu_edp) {
8073 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8074 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8075 else
8076 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8077 } else
8078 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8079 } else {
8080 final |= DREF_SSC_SOURCE_DISABLE;
8081 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8082 }
8083
8084 if (final == val)
8085 return;
8086
8087 /* Always enable nonspread source */
8088 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8089
8090 if (has_ck505)
8091 val |= DREF_NONSPREAD_CK505_ENABLE;
8092 else
8093 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8094
8095 if (has_panel) {
8096 val &= ~DREF_SSC_SOURCE_MASK;
8097 val |= DREF_SSC_SOURCE_ENABLE;
8098
8099 /* SSC must be turned on before enabling the CPU output */
8100 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8101 DRM_DEBUG_KMS("Using SSC on panel\n");
8102 val |= DREF_SSC1_ENABLE;
8103 } else
8104 val &= ~DREF_SSC1_ENABLE;
8105
8106 /* Get SSC going before enabling the outputs */
8107 I915_WRITE(PCH_DREF_CONTROL, val);
8108 POSTING_READ(PCH_DREF_CONTROL);
8109 udelay(200);
8110
8111 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8112
8113 /* Enable CPU source on CPU attached eDP */
8114 if (has_cpu_edp) {
8115 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8116 DRM_DEBUG_KMS("Using SSC on eDP\n");
8117 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8118 } else
8119 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8120 } else
8121 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8122
8123 I915_WRITE(PCH_DREF_CONTROL, val);
8124 POSTING_READ(PCH_DREF_CONTROL);
8125 udelay(200);
8126 } else {
8127 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8128
8129 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8130
8131 /* Turn off CPU output */
8132 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8133
8134 I915_WRITE(PCH_DREF_CONTROL, val);
8135 POSTING_READ(PCH_DREF_CONTROL);
8136 udelay(200);
8137
8138 /* Turn off the SSC source */
8139 val &= ~DREF_SSC_SOURCE_MASK;
8140 val |= DREF_SSC_SOURCE_DISABLE;
8141
8142 /* Turn off SSC1 */
8143 val &= ~DREF_SSC1_ENABLE;
8144
8145 I915_WRITE(PCH_DREF_CONTROL, val);
8146 POSTING_READ(PCH_DREF_CONTROL);
8147 udelay(200);
8148 }
8149
8150 BUG_ON(val != final);
8151 }
8152
8153 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8154 {
8155 uint32_t tmp;
8156
8157 tmp = I915_READ(SOUTH_CHICKEN2);
8158 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8159 I915_WRITE(SOUTH_CHICKEN2, tmp);
8160
8161 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8162 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8163 DRM_ERROR("FDI mPHY reset assert timeout\n");
8164
8165 tmp = I915_READ(SOUTH_CHICKEN2);
8166 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8167 I915_WRITE(SOUTH_CHICKEN2, tmp);
8168
8169 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8170 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8171 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8172 }
8173
8174 /* WaMPhyProgramming:hsw */
8175 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8176 {
8177 uint32_t tmp;
8178
8179 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8180 tmp &= ~(0xFF << 24);
8181 tmp |= (0x12 << 24);
8182 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8183
8184 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8185 tmp |= (1 << 11);
8186 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8187
8188 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8189 tmp |= (1 << 11);
8190 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8191
8192 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8193 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8194 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8195
8196 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8197 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8198 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8199
8200 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8201 tmp &= ~(7 << 13);
8202 tmp |= (5 << 13);
8203 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8204
8205 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8206 tmp &= ~(7 << 13);
8207 tmp |= (5 << 13);
8208 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8209
8210 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8211 tmp &= ~0xFF;
8212 tmp |= 0x1C;
8213 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8214
8215 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8216 tmp &= ~0xFF;
8217 tmp |= 0x1C;
8218 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8219
8220 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8221 tmp &= ~(0xFF << 16);
8222 tmp |= (0x1C << 16);
8223 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8224
8225 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8226 tmp &= ~(0xFF << 16);
8227 tmp |= (0x1C << 16);
8228 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8229
8230 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8231 tmp |= (1 << 27);
8232 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8233
8234 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8235 tmp |= (1 << 27);
8236 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8237
8238 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8239 tmp &= ~(0xF << 28);
8240 tmp |= (4 << 28);
8241 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8242
8243 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8244 tmp &= ~(0xF << 28);
8245 tmp |= (4 << 28);
8246 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8247 }
8248
8249 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8250 * Programming" based on the parameters passed:
8251 * - Sequence to enable CLKOUT_DP
8252 * - Sequence to enable CLKOUT_DP without spread
8253 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8254 */
8255 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8256 bool with_fdi)
8257 {
8258 struct drm_i915_private *dev_priv = dev->dev_private;
8259 uint32_t reg, tmp;
8260
8261 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8262 with_spread = true;
8263 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8264 with_fdi, "LP PCH doesn't have FDI\n"))
8265 with_fdi = false;
8266
8267 mutex_lock(&dev_priv->sb_lock);
8268
8269 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8270 tmp &= ~SBI_SSCCTL_DISABLE;
8271 tmp |= SBI_SSCCTL_PATHALT;
8272 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8273
8274 udelay(24);
8275
8276 if (with_spread) {
8277 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8278 tmp &= ~SBI_SSCCTL_PATHALT;
8279 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8280
8281 if (with_fdi) {
8282 lpt_reset_fdi_mphy(dev_priv);
8283 lpt_program_fdi_mphy(dev_priv);
8284 }
8285 }
8286
8287 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8288 SBI_GEN0 : SBI_DBUFF0;
8289 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8290 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8291 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8292
8293 mutex_unlock(&dev_priv->sb_lock);
8294 }
8295
8296 /* Sequence to disable CLKOUT_DP */
8297 static void lpt_disable_clkout_dp(struct drm_device *dev)
8298 {
8299 struct drm_i915_private *dev_priv = dev->dev_private;
8300 uint32_t reg, tmp;
8301
8302 mutex_lock(&dev_priv->sb_lock);
8303
8304 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8305 SBI_GEN0 : SBI_DBUFF0;
8306 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8307 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8308 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8309
8310 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8311 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8312 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8313 tmp |= SBI_SSCCTL_PATHALT;
8314 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8315 udelay(32);
8316 }
8317 tmp |= SBI_SSCCTL_DISABLE;
8318 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8319 }
8320
8321 mutex_unlock(&dev_priv->sb_lock);
8322 }
8323
8324 static void lpt_init_pch_refclk(struct drm_device *dev)
8325 {
8326 struct intel_encoder *encoder;
8327 bool has_vga = false;
8328
8329 for_each_intel_encoder(dev, encoder) {
8330 switch (encoder->type) {
8331 case INTEL_OUTPUT_ANALOG:
8332 has_vga = true;
8333 break;
8334 default:
8335 break;
8336 }
8337 }
8338
8339 if (has_vga)
8340 lpt_enable_clkout_dp(dev, true, true);
8341 else
8342 lpt_disable_clkout_dp(dev);
8343 }
8344
8345 /*
8346 * Initialize reference clocks when the driver loads
8347 */
8348 void intel_init_pch_refclk(struct drm_device *dev)
8349 {
8350 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8351 ironlake_init_pch_refclk(dev);
8352 else if (HAS_PCH_LPT(dev))
8353 lpt_init_pch_refclk(dev);
8354 }
8355
8356 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8357 {
8358 struct drm_device *dev = crtc_state->base.crtc->dev;
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8360 struct drm_atomic_state *state = crtc_state->base.state;
8361 struct drm_connector *connector;
8362 struct drm_connector_state *connector_state;
8363 struct intel_encoder *encoder;
8364 int num_connectors = 0, i;
8365 bool is_lvds = false;
8366
8367 for_each_connector_in_state(state, connector, connector_state, i) {
8368 if (connector_state->crtc != crtc_state->base.crtc)
8369 continue;
8370
8371 encoder = to_intel_encoder(connector_state->best_encoder);
8372
8373 switch (encoder->type) {
8374 case INTEL_OUTPUT_LVDS:
8375 is_lvds = true;
8376 break;
8377 default:
8378 break;
8379 }
8380 num_connectors++;
8381 }
8382
8383 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8384 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8385 dev_priv->vbt.lvds_ssc_freq);
8386 return dev_priv->vbt.lvds_ssc_freq;
8387 }
8388
8389 return 120000;
8390 }
8391
8392 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8393 {
8394 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8396 int pipe = intel_crtc->pipe;
8397 uint32_t val;
8398
8399 val = 0;
8400
8401 switch (intel_crtc->config->pipe_bpp) {
8402 case 18:
8403 val |= PIPECONF_6BPC;
8404 break;
8405 case 24:
8406 val |= PIPECONF_8BPC;
8407 break;
8408 case 30:
8409 val |= PIPECONF_10BPC;
8410 break;
8411 case 36:
8412 val |= PIPECONF_12BPC;
8413 break;
8414 default:
8415 /* Case prevented by intel_choose_pipe_bpp_dither. */
8416 BUG();
8417 }
8418
8419 if (intel_crtc->config->dither)
8420 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8421
8422 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8423 val |= PIPECONF_INTERLACED_ILK;
8424 else
8425 val |= PIPECONF_PROGRESSIVE;
8426
8427 if (intel_crtc->config->limited_color_range)
8428 val |= PIPECONF_COLOR_RANGE_SELECT;
8429
8430 I915_WRITE(PIPECONF(pipe), val);
8431 POSTING_READ(PIPECONF(pipe));
8432 }
8433
8434 /*
8435 * Set up the pipe CSC unit.
8436 *
8437 * Currently only full range RGB to limited range RGB conversion
8438 * is supported, but eventually this should handle various
8439 * RGB<->YCbCr scenarios as well.
8440 */
8441 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8442 {
8443 struct drm_device *dev = crtc->dev;
8444 struct drm_i915_private *dev_priv = dev->dev_private;
8445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8446 int pipe = intel_crtc->pipe;
8447 uint16_t coeff = 0x7800; /* 1.0 */
8448
8449 /*
8450 * TODO: Check what kind of values actually come out of the pipe
8451 * with these coeff/postoff values and adjust to get the best
8452 * accuracy. Perhaps we even need to take the bpc value into
8453 * consideration.
8454 */
8455
8456 if (intel_crtc->config->limited_color_range)
8457 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8458
8459 /*
8460 * GY/GU and RY/RU should be the other way around according
8461 * to BSpec, but reality doesn't agree. Just set them up in
8462 * a way that results in the correct picture.
8463 */
8464 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8465 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8466
8467 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8468 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8469
8470 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8471 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8472
8473 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8474 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8475 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8476
8477 if (INTEL_INFO(dev)->gen > 6) {
8478 uint16_t postoff = 0;
8479
8480 if (intel_crtc->config->limited_color_range)
8481 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8482
8483 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8484 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8485 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8486
8487 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8488 } else {
8489 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8490
8491 if (intel_crtc->config->limited_color_range)
8492 mode |= CSC_BLACK_SCREEN_OFFSET;
8493
8494 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8495 }
8496 }
8497
8498 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8499 {
8500 struct drm_device *dev = crtc->dev;
8501 struct drm_i915_private *dev_priv = dev->dev_private;
8502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8503 enum pipe pipe = intel_crtc->pipe;
8504 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8505 uint32_t val;
8506
8507 val = 0;
8508
8509 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8510 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8511
8512 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8513 val |= PIPECONF_INTERLACED_ILK;
8514 else
8515 val |= PIPECONF_PROGRESSIVE;
8516
8517 I915_WRITE(PIPECONF(cpu_transcoder), val);
8518 POSTING_READ(PIPECONF(cpu_transcoder));
8519
8520 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8521 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8522
8523 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8524 val = 0;
8525
8526 switch (intel_crtc->config->pipe_bpp) {
8527 case 18:
8528 val |= PIPEMISC_DITHER_6_BPC;
8529 break;
8530 case 24:
8531 val |= PIPEMISC_DITHER_8_BPC;
8532 break;
8533 case 30:
8534 val |= PIPEMISC_DITHER_10_BPC;
8535 break;
8536 case 36:
8537 val |= PIPEMISC_DITHER_12_BPC;
8538 break;
8539 default:
8540 /* Case prevented by pipe_config_set_bpp. */
8541 BUG();
8542 }
8543
8544 if (intel_crtc->config->dither)
8545 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8546
8547 I915_WRITE(PIPEMISC(pipe), val);
8548 }
8549 }
8550
8551 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8552 struct intel_crtc_state *crtc_state,
8553 intel_clock_t *clock,
8554 bool *has_reduced_clock,
8555 intel_clock_t *reduced_clock)
8556 {
8557 struct drm_device *dev = crtc->dev;
8558 struct drm_i915_private *dev_priv = dev->dev_private;
8559 int refclk;
8560 const intel_limit_t *limit;
8561 bool ret, is_lvds = false;
8562
8563 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8564
8565 refclk = ironlake_get_refclk(crtc_state);
8566
8567 /*
8568 * Returns a set of divisors for the desired target clock with the given
8569 * refclk, or FALSE. The returned values represent the clock equation:
8570 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8571 */
8572 limit = intel_limit(crtc_state, refclk);
8573 ret = dev_priv->display.find_dpll(limit, crtc_state,
8574 crtc_state->port_clock,
8575 refclk, NULL, clock);
8576 if (!ret)
8577 return false;
8578
8579 if (is_lvds && dev_priv->lvds_downclock_avail) {
8580 /*
8581 * Ensure we match the reduced clock's P to the target clock.
8582 * If the clocks don't match, we can't switch the display clock
8583 * by using the FP0/FP1. In such case we will disable the LVDS
8584 * downclock feature.
8585 */
8586 *has_reduced_clock =
8587 dev_priv->display.find_dpll(limit, crtc_state,
8588 dev_priv->lvds_downclock,
8589 refclk, clock,
8590 reduced_clock);
8591 }
8592
8593 return true;
8594 }
8595
8596 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8597 {
8598 /*
8599 * Account for spread spectrum to avoid
8600 * oversubscribing the link. Max center spread
8601 * is 2.5%; use 5% for safety's sake.
8602 */
8603 u32 bps = target_clock * bpp * 21 / 20;
8604 return DIV_ROUND_UP(bps, link_bw * 8);
8605 }
8606
8607 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8608 {
8609 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8610 }
8611
8612 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8613 struct intel_crtc_state *crtc_state,
8614 u32 *fp,
8615 intel_clock_t *reduced_clock, u32 *fp2)
8616 {
8617 struct drm_crtc *crtc = &intel_crtc->base;
8618 struct drm_device *dev = crtc->dev;
8619 struct drm_i915_private *dev_priv = dev->dev_private;
8620 struct drm_atomic_state *state = crtc_state->base.state;
8621 struct drm_connector *connector;
8622 struct drm_connector_state *connector_state;
8623 struct intel_encoder *encoder;
8624 uint32_t dpll;
8625 int factor, num_connectors = 0, i;
8626 bool is_lvds = false, is_sdvo = false;
8627
8628 for_each_connector_in_state(state, connector, connector_state, i) {
8629 if (connector_state->crtc != crtc_state->base.crtc)
8630 continue;
8631
8632 encoder = to_intel_encoder(connector_state->best_encoder);
8633
8634 switch (encoder->type) {
8635 case INTEL_OUTPUT_LVDS:
8636 is_lvds = true;
8637 break;
8638 case INTEL_OUTPUT_SDVO:
8639 case INTEL_OUTPUT_HDMI:
8640 is_sdvo = true;
8641 break;
8642 default:
8643 break;
8644 }
8645
8646 num_connectors++;
8647 }
8648
8649 /* Enable autotuning of the PLL clock (if permissible) */
8650 factor = 21;
8651 if (is_lvds) {
8652 if ((intel_panel_use_ssc(dev_priv) &&
8653 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8654 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8655 factor = 25;
8656 } else if (crtc_state->sdvo_tv_clock)
8657 factor = 20;
8658
8659 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8660 *fp |= FP_CB_TUNE;
8661
8662 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8663 *fp2 |= FP_CB_TUNE;
8664
8665 dpll = 0;
8666
8667 if (is_lvds)
8668 dpll |= DPLLB_MODE_LVDS;
8669 else
8670 dpll |= DPLLB_MODE_DAC_SERIAL;
8671
8672 dpll |= (crtc_state->pixel_multiplier - 1)
8673 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8674
8675 if (is_sdvo)
8676 dpll |= DPLL_SDVO_HIGH_SPEED;
8677 if (crtc_state->has_dp_encoder)
8678 dpll |= DPLL_SDVO_HIGH_SPEED;
8679
8680 /* compute bitmask from p1 value */
8681 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8682 /* also FPA1 */
8683 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8684
8685 switch (crtc_state->dpll.p2) {
8686 case 5:
8687 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8688 break;
8689 case 7:
8690 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8691 break;
8692 case 10:
8693 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8694 break;
8695 case 14:
8696 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8697 break;
8698 }
8699
8700 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8701 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8702 else
8703 dpll |= PLL_REF_INPUT_DREFCLK;
8704
8705 return dpll | DPLL_VCO_ENABLE;
8706 }
8707
8708 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8709 struct intel_crtc_state *crtc_state)
8710 {
8711 struct drm_device *dev = crtc->base.dev;
8712 intel_clock_t clock, reduced_clock;
8713 u32 dpll = 0, fp = 0, fp2 = 0;
8714 bool ok, has_reduced_clock = false;
8715 bool is_lvds = false;
8716 struct intel_shared_dpll *pll;
8717
8718 memset(&crtc_state->dpll_hw_state, 0,
8719 sizeof(crtc_state->dpll_hw_state));
8720
8721 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8722
8723 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8724 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8725
8726 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8727 &has_reduced_clock, &reduced_clock);
8728 if (!ok && !crtc_state->clock_set) {
8729 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8730 return -EINVAL;
8731 }
8732 /* Compat-code for transition, will disappear. */
8733 if (!crtc_state->clock_set) {
8734 crtc_state->dpll.n = clock.n;
8735 crtc_state->dpll.m1 = clock.m1;
8736 crtc_state->dpll.m2 = clock.m2;
8737 crtc_state->dpll.p1 = clock.p1;
8738 crtc_state->dpll.p2 = clock.p2;
8739 }
8740
8741 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8742 if (crtc_state->has_pch_encoder) {
8743 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8744 if (has_reduced_clock)
8745 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8746
8747 dpll = ironlake_compute_dpll(crtc, crtc_state,
8748 &fp, &reduced_clock,
8749 has_reduced_clock ? &fp2 : NULL);
8750
8751 crtc_state->dpll_hw_state.dpll = dpll;
8752 crtc_state->dpll_hw_state.fp0 = fp;
8753 if (has_reduced_clock)
8754 crtc_state->dpll_hw_state.fp1 = fp2;
8755 else
8756 crtc_state->dpll_hw_state.fp1 = fp;
8757
8758 pll = intel_get_shared_dpll(crtc, crtc_state);
8759 if (pll == NULL) {
8760 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8761 pipe_name(crtc->pipe));
8762 return -EINVAL;
8763 }
8764 }
8765
8766 if (is_lvds && has_reduced_clock)
8767 crtc->lowfreq_avail = true;
8768 else
8769 crtc->lowfreq_avail = false;
8770
8771 return 0;
8772 }
8773
8774 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8775 struct intel_link_m_n *m_n)
8776 {
8777 struct drm_device *dev = crtc->base.dev;
8778 struct drm_i915_private *dev_priv = dev->dev_private;
8779 enum pipe pipe = crtc->pipe;
8780
8781 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8782 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8783 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8784 & ~TU_SIZE_MASK;
8785 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8786 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8787 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8788 }
8789
8790 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8791 enum transcoder transcoder,
8792 struct intel_link_m_n *m_n,
8793 struct intel_link_m_n *m2_n2)
8794 {
8795 struct drm_device *dev = crtc->base.dev;
8796 struct drm_i915_private *dev_priv = dev->dev_private;
8797 enum pipe pipe = crtc->pipe;
8798
8799 if (INTEL_INFO(dev)->gen >= 5) {
8800 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8801 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8802 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8803 & ~TU_SIZE_MASK;
8804 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8805 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8806 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8807 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8808 * gen < 8) and if DRRS is supported (to make sure the
8809 * registers are not unnecessarily read).
8810 */
8811 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8812 crtc->config->has_drrs) {
8813 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8814 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8815 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8816 & ~TU_SIZE_MASK;
8817 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8818 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8819 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8820 }
8821 } else {
8822 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8823 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8824 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8825 & ~TU_SIZE_MASK;
8826 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8827 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8828 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8829 }
8830 }
8831
8832 void intel_dp_get_m_n(struct intel_crtc *crtc,
8833 struct intel_crtc_state *pipe_config)
8834 {
8835 if (pipe_config->has_pch_encoder)
8836 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8837 else
8838 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8839 &pipe_config->dp_m_n,
8840 &pipe_config->dp_m2_n2);
8841 }
8842
8843 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8844 struct intel_crtc_state *pipe_config)
8845 {
8846 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8847 &pipe_config->fdi_m_n, NULL);
8848 }
8849
8850 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8851 struct intel_crtc_state *pipe_config)
8852 {
8853 struct drm_device *dev = crtc->base.dev;
8854 struct drm_i915_private *dev_priv = dev->dev_private;
8855 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8856 uint32_t ps_ctrl = 0;
8857 int id = -1;
8858 int i;
8859
8860 /* find scaler attached to this pipe */
8861 for (i = 0; i < crtc->num_scalers; i++) {
8862 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8863 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8864 id = i;
8865 pipe_config->pch_pfit.enabled = true;
8866 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8867 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8868 break;
8869 }
8870 }
8871
8872 scaler_state->scaler_id = id;
8873 if (id >= 0) {
8874 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8875 } else {
8876 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8877 }
8878 }
8879
8880 static void
8881 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8882 struct intel_initial_plane_config *plane_config)
8883 {
8884 struct drm_device *dev = crtc->base.dev;
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 u32 val, base, offset, stride_mult, tiling;
8887 int pipe = crtc->pipe;
8888 int fourcc, pixel_format;
8889 unsigned int aligned_height;
8890 struct drm_framebuffer *fb;
8891 struct intel_framebuffer *intel_fb;
8892
8893 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8894 if (!intel_fb) {
8895 DRM_DEBUG_KMS("failed to alloc fb\n");
8896 return;
8897 }
8898
8899 fb = &intel_fb->base;
8900
8901 val = I915_READ(PLANE_CTL(pipe, 0));
8902 if (!(val & PLANE_CTL_ENABLE))
8903 goto error;
8904
8905 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8906 fourcc = skl_format_to_fourcc(pixel_format,
8907 val & PLANE_CTL_ORDER_RGBX,
8908 val & PLANE_CTL_ALPHA_MASK);
8909 fb->pixel_format = fourcc;
8910 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8911
8912 tiling = val & PLANE_CTL_TILED_MASK;
8913 switch (tiling) {
8914 case PLANE_CTL_TILED_LINEAR:
8915 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8916 break;
8917 case PLANE_CTL_TILED_X:
8918 plane_config->tiling = I915_TILING_X;
8919 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8920 break;
8921 case PLANE_CTL_TILED_Y:
8922 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8923 break;
8924 case PLANE_CTL_TILED_YF:
8925 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8926 break;
8927 default:
8928 MISSING_CASE(tiling);
8929 goto error;
8930 }
8931
8932 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8933 plane_config->base = base;
8934
8935 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8936
8937 val = I915_READ(PLANE_SIZE(pipe, 0));
8938 fb->height = ((val >> 16) & 0xfff) + 1;
8939 fb->width = ((val >> 0) & 0x1fff) + 1;
8940
8941 val = I915_READ(PLANE_STRIDE(pipe, 0));
8942 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8943 fb->pixel_format);
8944 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8945
8946 aligned_height = intel_fb_align_height(dev, fb->height,
8947 fb->pixel_format,
8948 fb->modifier[0]);
8949
8950 plane_config->size = fb->pitches[0] * aligned_height;
8951
8952 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8953 pipe_name(pipe), fb->width, fb->height,
8954 fb->bits_per_pixel, base, fb->pitches[0],
8955 plane_config->size);
8956
8957 plane_config->fb = intel_fb;
8958 return;
8959
8960 error:
8961 kfree(fb);
8962 }
8963
8964 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8965 struct intel_crtc_state *pipe_config)
8966 {
8967 struct drm_device *dev = crtc->base.dev;
8968 struct drm_i915_private *dev_priv = dev->dev_private;
8969 uint32_t tmp;
8970
8971 tmp = I915_READ(PF_CTL(crtc->pipe));
8972
8973 if (tmp & PF_ENABLE) {
8974 pipe_config->pch_pfit.enabled = true;
8975 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8976 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8977
8978 /* We currently do not free assignements of panel fitters on
8979 * ivb/hsw (since we don't use the higher upscaling modes which
8980 * differentiates them) so just WARN about this case for now. */
8981 if (IS_GEN7(dev)) {
8982 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8983 PF_PIPE_SEL_IVB(crtc->pipe));
8984 }
8985 }
8986 }
8987
8988 static void
8989 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8990 struct intel_initial_plane_config *plane_config)
8991 {
8992 struct drm_device *dev = crtc->base.dev;
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 u32 val, base, offset;
8995 int pipe = crtc->pipe;
8996 int fourcc, pixel_format;
8997 unsigned int aligned_height;
8998 struct drm_framebuffer *fb;
8999 struct intel_framebuffer *intel_fb;
9000
9001 val = I915_READ(DSPCNTR(pipe));
9002 if (!(val & DISPLAY_PLANE_ENABLE))
9003 return;
9004
9005 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9006 if (!intel_fb) {
9007 DRM_DEBUG_KMS("failed to alloc fb\n");
9008 return;
9009 }
9010
9011 fb = &intel_fb->base;
9012
9013 if (INTEL_INFO(dev)->gen >= 4) {
9014 if (val & DISPPLANE_TILED) {
9015 plane_config->tiling = I915_TILING_X;
9016 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9017 }
9018 }
9019
9020 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9021 fourcc = i9xx_format_to_fourcc(pixel_format);
9022 fb->pixel_format = fourcc;
9023 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9024
9025 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9026 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9027 offset = I915_READ(DSPOFFSET(pipe));
9028 } else {
9029 if (plane_config->tiling)
9030 offset = I915_READ(DSPTILEOFF(pipe));
9031 else
9032 offset = I915_READ(DSPLINOFF(pipe));
9033 }
9034 plane_config->base = base;
9035
9036 val = I915_READ(PIPESRC(pipe));
9037 fb->width = ((val >> 16) & 0xfff) + 1;
9038 fb->height = ((val >> 0) & 0xfff) + 1;
9039
9040 val = I915_READ(DSPSTRIDE(pipe));
9041 fb->pitches[0] = val & 0xffffffc0;
9042
9043 aligned_height = intel_fb_align_height(dev, fb->height,
9044 fb->pixel_format,
9045 fb->modifier[0]);
9046
9047 plane_config->size = fb->pitches[0] * aligned_height;
9048
9049 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9050 pipe_name(pipe), fb->width, fb->height,
9051 fb->bits_per_pixel, base, fb->pitches[0],
9052 plane_config->size);
9053
9054 plane_config->fb = intel_fb;
9055 }
9056
9057 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9058 struct intel_crtc_state *pipe_config)
9059 {
9060 struct drm_device *dev = crtc->base.dev;
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062 uint32_t tmp;
9063
9064 if (!intel_display_power_is_enabled(dev_priv,
9065 POWER_DOMAIN_PIPE(crtc->pipe)))
9066 return false;
9067
9068 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9069 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9070
9071 tmp = I915_READ(PIPECONF(crtc->pipe));
9072 if (!(tmp & PIPECONF_ENABLE))
9073 return false;
9074
9075 switch (tmp & PIPECONF_BPC_MASK) {
9076 case PIPECONF_6BPC:
9077 pipe_config->pipe_bpp = 18;
9078 break;
9079 case PIPECONF_8BPC:
9080 pipe_config->pipe_bpp = 24;
9081 break;
9082 case PIPECONF_10BPC:
9083 pipe_config->pipe_bpp = 30;
9084 break;
9085 case PIPECONF_12BPC:
9086 pipe_config->pipe_bpp = 36;
9087 break;
9088 default:
9089 break;
9090 }
9091
9092 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9093 pipe_config->limited_color_range = true;
9094
9095 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9096 struct intel_shared_dpll *pll;
9097
9098 pipe_config->has_pch_encoder = true;
9099
9100 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9101 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9102 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9103
9104 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9105
9106 if (HAS_PCH_IBX(dev_priv->dev)) {
9107 pipe_config->shared_dpll =
9108 (enum intel_dpll_id) crtc->pipe;
9109 } else {
9110 tmp = I915_READ(PCH_DPLL_SEL);
9111 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9112 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9113 else
9114 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9115 }
9116
9117 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9118
9119 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9120 &pipe_config->dpll_hw_state));
9121
9122 tmp = pipe_config->dpll_hw_state.dpll;
9123 pipe_config->pixel_multiplier =
9124 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9125 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9126
9127 ironlake_pch_clock_get(crtc, pipe_config);
9128 } else {
9129 pipe_config->pixel_multiplier = 1;
9130 }
9131
9132 intel_get_pipe_timings(crtc, pipe_config);
9133
9134 ironlake_get_pfit_config(crtc, pipe_config);
9135
9136 return true;
9137 }
9138
9139 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9140 {
9141 struct drm_device *dev = dev_priv->dev;
9142 struct intel_crtc *crtc;
9143
9144 for_each_intel_crtc(dev, crtc)
9145 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9146 pipe_name(crtc->pipe));
9147
9148 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9149 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9150 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9151 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9152 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9153 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9154 "CPU PWM1 enabled\n");
9155 if (IS_HASWELL(dev))
9156 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9157 "CPU PWM2 enabled\n");
9158 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9159 "PCH PWM1 enabled\n");
9160 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9161 "Utility pin enabled\n");
9162 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9163
9164 /*
9165 * In theory we can still leave IRQs enabled, as long as only the HPD
9166 * interrupts remain enabled. We used to check for that, but since it's
9167 * gen-specific and since we only disable LCPLL after we fully disable
9168 * the interrupts, the check below should be enough.
9169 */
9170 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9171 }
9172
9173 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9174 {
9175 struct drm_device *dev = dev_priv->dev;
9176
9177 if (IS_HASWELL(dev))
9178 return I915_READ(D_COMP_HSW);
9179 else
9180 return I915_READ(D_COMP_BDW);
9181 }
9182
9183 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9184 {
9185 struct drm_device *dev = dev_priv->dev;
9186
9187 if (IS_HASWELL(dev)) {
9188 mutex_lock(&dev_priv->rps.hw_lock);
9189 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9190 val))
9191 DRM_ERROR("Failed to write to D_COMP\n");
9192 mutex_unlock(&dev_priv->rps.hw_lock);
9193 } else {
9194 I915_WRITE(D_COMP_BDW, val);
9195 POSTING_READ(D_COMP_BDW);
9196 }
9197 }
9198
9199 /*
9200 * This function implements pieces of two sequences from BSpec:
9201 * - Sequence for display software to disable LCPLL
9202 * - Sequence for display software to allow package C8+
9203 * The steps implemented here are just the steps that actually touch the LCPLL
9204 * register. Callers should take care of disabling all the display engine
9205 * functions, doing the mode unset, fixing interrupts, etc.
9206 */
9207 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9208 bool switch_to_fclk, bool allow_power_down)
9209 {
9210 uint32_t val;
9211
9212 assert_can_disable_lcpll(dev_priv);
9213
9214 val = I915_READ(LCPLL_CTL);
9215
9216 if (switch_to_fclk) {
9217 val |= LCPLL_CD_SOURCE_FCLK;
9218 I915_WRITE(LCPLL_CTL, val);
9219
9220 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9221 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9222 DRM_ERROR("Switching to FCLK failed\n");
9223
9224 val = I915_READ(LCPLL_CTL);
9225 }
9226
9227 val |= LCPLL_PLL_DISABLE;
9228 I915_WRITE(LCPLL_CTL, val);
9229 POSTING_READ(LCPLL_CTL);
9230
9231 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9232 DRM_ERROR("LCPLL still locked\n");
9233
9234 val = hsw_read_dcomp(dev_priv);
9235 val |= D_COMP_COMP_DISABLE;
9236 hsw_write_dcomp(dev_priv, val);
9237 ndelay(100);
9238
9239 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9240 1))
9241 DRM_ERROR("D_COMP RCOMP still in progress\n");
9242
9243 if (allow_power_down) {
9244 val = I915_READ(LCPLL_CTL);
9245 val |= LCPLL_POWER_DOWN_ALLOW;
9246 I915_WRITE(LCPLL_CTL, val);
9247 POSTING_READ(LCPLL_CTL);
9248 }
9249 }
9250
9251 /*
9252 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9253 * source.
9254 */
9255 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9256 {
9257 uint32_t val;
9258
9259 val = I915_READ(LCPLL_CTL);
9260
9261 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9262 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9263 return;
9264
9265 /*
9266 * Make sure we're not on PC8 state before disabling PC8, otherwise
9267 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9268 */
9269 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9270
9271 if (val & LCPLL_POWER_DOWN_ALLOW) {
9272 val &= ~LCPLL_POWER_DOWN_ALLOW;
9273 I915_WRITE(LCPLL_CTL, val);
9274 POSTING_READ(LCPLL_CTL);
9275 }
9276
9277 val = hsw_read_dcomp(dev_priv);
9278 val |= D_COMP_COMP_FORCE;
9279 val &= ~D_COMP_COMP_DISABLE;
9280 hsw_write_dcomp(dev_priv, val);
9281
9282 val = I915_READ(LCPLL_CTL);
9283 val &= ~LCPLL_PLL_DISABLE;
9284 I915_WRITE(LCPLL_CTL, val);
9285
9286 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9287 DRM_ERROR("LCPLL not locked yet\n");
9288
9289 if (val & LCPLL_CD_SOURCE_FCLK) {
9290 val = I915_READ(LCPLL_CTL);
9291 val &= ~LCPLL_CD_SOURCE_FCLK;
9292 I915_WRITE(LCPLL_CTL, val);
9293
9294 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9295 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9296 DRM_ERROR("Switching back to LCPLL failed\n");
9297 }
9298
9299 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9300 }
9301
9302 /*
9303 * Package states C8 and deeper are really deep PC states that can only be
9304 * reached when all the devices on the system allow it, so even if the graphics
9305 * device allows PC8+, it doesn't mean the system will actually get to these
9306 * states. Our driver only allows PC8+ when going into runtime PM.
9307 *
9308 * The requirements for PC8+ are that all the outputs are disabled, the power
9309 * well is disabled and most interrupts are disabled, and these are also
9310 * requirements for runtime PM. When these conditions are met, we manually do
9311 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9312 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9313 * hang the machine.
9314 *
9315 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9316 * the state of some registers, so when we come back from PC8+ we need to
9317 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9318 * need to take care of the registers kept by RC6. Notice that this happens even
9319 * if we don't put the device in PCI D3 state (which is what currently happens
9320 * because of the runtime PM support).
9321 *
9322 * For more, read "Display Sequences for Package C8" on the hardware
9323 * documentation.
9324 */
9325 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9326 {
9327 struct drm_device *dev = dev_priv->dev;
9328 uint32_t val;
9329
9330 DRM_DEBUG_KMS("Enabling package C8+\n");
9331
9332 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9333 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9334 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9335 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9336 }
9337
9338 lpt_disable_clkout_dp(dev);
9339 hsw_disable_lcpll(dev_priv, true, true);
9340 }
9341
9342 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9343 {
9344 struct drm_device *dev = dev_priv->dev;
9345 uint32_t val;
9346
9347 DRM_DEBUG_KMS("Disabling package C8+\n");
9348
9349 hsw_restore_lcpll(dev_priv);
9350 lpt_init_pch_refclk(dev);
9351
9352 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9353 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9354 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9355 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9356 }
9357
9358 intel_prepare_ddi(dev);
9359 }
9360
9361 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9362 {
9363 struct drm_device *dev = old_state->dev;
9364 struct drm_i915_private *dev_priv = dev->dev_private;
9365 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9366 int req_cdclk;
9367
9368 /* see the comment in valleyview_modeset_global_resources */
9369 if (WARN_ON(max_pixclk < 0))
9370 return;
9371
9372 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9373
9374 if (req_cdclk != dev_priv->cdclk_freq)
9375 broxton_set_cdclk(dev, req_cdclk);
9376 }
9377
9378 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9379 struct intel_crtc_state *crtc_state)
9380 {
9381 if (!intel_ddi_pll_select(crtc, crtc_state))
9382 return -EINVAL;
9383
9384 crtc->lowfreq_avail = false;
9385
9386 return 0;
9387 }
9388
9389 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9390 enum port port,
9391 struct intel_crtc_state *pipe_config)
9392 {
9393 switch (port) {
9394 case PORT_A:
9395 pipe_config->ddi_pll_sel = SKL_DPLL0;
9396 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9397 break;
9398 case PORT_B:
9399 pipe_config->ddi_pll_sel = SKL_DPLL1;
9400 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9401 break;
9402 case PORT_C:
9403 pipe_config->ddi_pll_sel = SKL_DPLL2;
9404 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9405 break;
9406 default:
9407 DRM_ERROR("Incorrect port type\n");
9408 }
9409 }
9410
9411 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9412 enum port port,
9413 struct intel_crtc_state *pipe_config)
9414 {
9415 u32 temp, dpll_ctl1;
9416
9417 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9418 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9419
9420 switch (pipe_config->ddi_pll_sel) {
9421 case SKL_DPLL0:
9422 /*
9423 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9424 * of the shared DPLL framework and thus needs to be read out
9425 * separately
9426 */
9427 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9428 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9429 break;
9430 case SKL_DPLL1:
9431 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9432 break;
9433 case SKL_DPLL2:
9434 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9435 break;
9436 case SKL_DPLL3:
9437 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9438 break;
9439 }
9440 }
9441
9442 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9443 enum port port,
9444 struct intel_crtc_state *pipe_config)
9445 {
9446 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9447
9448 switch (pipe_config->ddi_pll_sel) {
9449 case PORT_CLK_SEL_WRPLL1:
9450 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9451 break;
9452 case PORT_CLK_SEL_WRPLL2:
9453 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9454 break;
9455 }
9456 }
9457
9458 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9459 struct intel_crtc_state *pipe_config)
9460 {
9461 struct drm_device *dev = crtc->base.dev;
9462 struct drm_i915_private *dev_priv = dev->dev_private;
9463 struct intel_shared_dpll *pll;
9464 enum port port;
9465 uint32_t tmp;
9466
9467 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9468
9469 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9470
9471 if (IS_SKYLAKE(dev))
9472 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9473 else if (IS_BROXTON(dev))
9474 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9475 else
9476 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9477
9478 if (pipe_config->shared_dpll >= 0) {
9479 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9480
9481 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9482 &pipe_config->dpll_hw_state));
9483 }
9484
9485 /*
9486 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9487 * DDI E. So just check whether this pipe is wired to DDI E and whether
9488 * the PCH transcoder is on.
9489 */
9490 if (INTEL_INFO(dev)->gen < 9 &&
9491 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9492 pipe_config->has_pch_encoder = true;
9493
9494 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9495 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9496 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9497
9498 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9499 }
9500 }
9501
9502 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9503 struct intel_crtc_state *pipe_config)
9504 {
9505 struct drm_device *dev = crtc->base.dev;
9506 struct drm_i915_private *dev_priv = dev->dev_private;
9507 enum intel_display_power_domain pfit_domain;
9508 uint32_t tmp;
9509
9510 if (!intel_display_power_is_enabled(dev_priv,
9511 POWER_DOMAIN_PIPE(crtc->pipe)))
9512 return false;
9513
9514 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9515 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9516
9517 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9518 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9519 enum pipe trans_edp_pipe;
9520 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9521 default:
9522 WARN(1, "unknown pipe linked to edp transcoder\n");
9523 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9524 case TRANS_DDI_EDP_INPUT_A_ON:
9525 trans_edp_pipe = PIPE_A;
9526 break;
9527 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9528 trans_edp_pipe = PIPE_B;
9529 break;
9530 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9531 trans_edp_pipe = PIPE_C;
9532 break;
9533 }
9534
9535 if (trans_edp_pipe == crtc->pipe)
9536 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9537 }
9538
9539 if (!intel_display_power_is_enabled(dev_priv,
9540 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9541 return false;
9542
9543 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9544 if (!(tmp & PIPECONF_ENABLE))
9545 return false;
9546
9547 haswell_get_ddi_port_state(crtc, pipe_config);
9548
9549 intel_get_pipe_timings(crtc, pipe_config);
9550
9551 if (INTEL_INFO(dev)->gen >= 9) {
9552 skl_init_scalers(dev, crtc, pipe_config);
9553 }
9554
9555 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9556
9557 if (INTEL_INFO(dev)->gen >= 9) {
9558 pipe_config->scaler_state.scaler_id = -1;
9559 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9560 }
9561
9562 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9563 if (INTEL_INFO(dev)->gen == 9)
9564 skylake_get_pfit_config(crtc, pipe_config);
9565 else if (INTEL_INFO(dev)->gen < 9)
9566 ironlake_get_pfit_config(crtc, pipe_config);
9567 else
9568 MISSING_CASE(INTEL_INFO(dev)->gen);
9569 }
9570
9571 if (IS_HASWELL(dev))
9572 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9573 (I915_READ(IPS_CTL) & IPS_ENABLE);
9574
9575 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9576 pipe_config->pixel_multiplier =
9577 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9578 } else {
9579 pipe_config->pixel_multiplier = 1;
9580 }
9581
9582 return true;
9583 }
9584
9585 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9586 {
9587 struct drm_device *dev = crtc->dev;
9588 struct drm_i915_private *dev_priv = dev->dev_private;
9589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9590 uint32_t cntl = 0, size = 0;
9591
9592 if (base) {
9593 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9594 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9595 unsigned int stride = roundup_pow_of_two(width) * 4;
9596
9597 switch (stride) {
9598 default:
9599 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9600 width, stride);
9601 stride = 256;
9602 /* fallthrough */
9603 case 256:
9604 case 512:
9605 case 1024:
9606 case 2048:
9607 break;
9608 }
9609
9610 cntl |= CURSOR_ENABLE |
9611 CURSOR_GAMMA_ENABLE |
9612 CURSOR_FORMAT_ARGB |
9613 CURSOR_STRIDE(stride);
9614
9615 size = (height << 12) | width;
9616 }
9617
9618 if (intel_crtc->cursor_cntl != 0 &&
9619 (intel_crtc->cursor_base != base ||
9620 intel_crtc->cursor_size != size ||
9621 intel_crtc->cursor_cntl != cntl)) {
9622 /* On these chipsets we can only modify the base/size/stride
9623 * whilst the cursor is disabled.
9624 */
9625 I915_WRITE(_CURACNTR, 0);
9626 POSTING_READ(_CURACNTR);
9627 intel_crtc->cursor_cntl = 0;
9628 }
9629
9630 if (intel_crtc->cursor_base != base) {
9631 I915_WRITE(_CURABASE, base);
9632 intel_crtc->cursor_base = base;
9633 }
9634
9635 if (intel_crtc->cursor_size != size) {
9636 I915_WRITE(CURSIZE, size);
9637 intel_crtc->cursor_size = size;
9638 }
9639
9640 if (intel_crtc->cursor_cntl != cntl) {
9641 I915_WRITE(_CURACNTR, cntl);
9642 POSTING_READ(_CURACNTR);
9643 intel_crtc->cursor_cntl = cntl;
9644 }
9645 }
9646
9647 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9648 {
9649 struct drm_device *dev = crtc->dev;
9650 struct drm_i915_private *dev_priv = dev->dev_private;
9651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9652 int pipe = intel_crtc->pipe;
9653 uint32_t cntl;
9654
9655 cntl = 0;
9656 if (base) {
9657 cntl = MCURSOR_GAMMA_ENABLE;
9658 switch (intel_crtc->base.cursor->state->crtc_w) {
9659 case 64:
9660 cntl |= CURSOR_MODE_64_ARGB_AX;
9661 break;
9662 case 128:
9663 cntl |= CURSOR_MODE_128_ARGB_AX;
9664 break;
9665 case 256:
9666 cntl |= CURSOR_MODE_256_ARGB_AX;
9667 break;
9668 default:
9669 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9670 return;
9671 }
9672 cntl |= pipe << 28; /* Connect to correct pipe */
9673
9674 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9675 cntl |= CURSOR_PIPE_CSC_ENABLE;
9676 }
9677
9678 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9679 cntl |= CURSOR_ROTATE_180;
9680
9681 if (intel_crtc->cursor_cntl != cntl) {
9682 I915_WRITE(CURCNTR(pipe), cntl);
9683 POSTING_READ(CURCNTR(pipe));
9684 intel_crtc->cursor_cntl = cntl;
9685 }
9686
9687 /* and commit changes on next vblank */
9688 I915_WRITE(CURBASE(pipe), base);
9689 POSTING_READ(CURBASE(pipe));
9690
9691 intel_crtc->cursor_base = base;
9692 }
9693
9694 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9695 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9696 bool on)
9697 {
9698 struct drm_device *dev = crtc->dev;
9699 struct drm_i915_private *dev_priv = dev->dev_private;
9700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9701 int pipe = intel_crtc->pipe;
9702 int x = crtc->cursor_x;
9703 int y = crtc->cursor_y;
9704 u32 base = 0, pos = 0;
9705
9706 if (on)
9707 base = intel_crtc->cursor_addr;
9708
9709 if (x >= intel_crtc->config->pipe_src_w)
9710 base = 0;
9711
9712 if (y >= intel_crtc->config->pipe_src_h)
9713 base = 0;
9714
9715 if (x < 0) {
9716 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9717 base = 0;
9718
9719 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9720 x = -x;
9721 }
9722 pos |= x << CURSOR_X_SHIFT;
9723
9724 if (y < 0) {
9725 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9726 base = 0;
9727
9728 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9729 y = -y;
9730 }
9731 pos |= y << CURSOR_Y_SHIFT;
9732
9733 if (base == 0 && intel_crtc->cursor_base == 0)
9734 return;
9735
9736 I915_WRITE(CURPOS(pipe), pos);
9737
9738 /* ILK+ do this automagically */
9739 if (HAS_GMCH_DISPLAY(dev) &&
9740 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9741 base += (intel_crtc->base.cursor->state->crtc_h *
9742 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9743 }
9744
9745 if (IS_845G(dev) || IS_I865G(dev))
9746 i845_update_cursor(crtc, base);
9747 else
9748 i9xx_update_cursor(crtc, base);
9749 }
9750
9751 static bool cursor_size_ok(struct drm_device *dev,
9752 uint32_t width, uint32_t height)
9753 {
9754 if (width == 0 || height == 0)
9755 return false;
9756
9757 /*
9758 * 845g/865g are special in that they are only limited by
9759 * the width of their cursors, the height is arbitrary up to
9760 * the precision of the register. Everything else requires
9761 * square cursors, limited to a few power-of-two sizes.
9762 */
9763 if (IS_845G(dev) || IS_I865G(dev)) {
9764 if ((width & 63) != 0)
9765 return false;
9766
9767 if (width > (IS_845G(dev) ? 64 : 512))
9768 return false;
9769
9770 if (height > 1023)
9771 return false;
9772 } else {
9773 switch (width | height) {
9774 case 256:
9775 case 128:
9776 if (IS_GEN2(dev))
9777 return false;
9778 case 64:
9779 break;
9780 default:
9781 return false;
9782 }
9783 }
9784
9785 return true;
9786 }
9787
9788 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9789 u16 *blue, uint32_t start, uint32_t size)
9790 {
9791 int end = (start + size > 256) ? 256 : start + size, i;
9792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9793
9794 for (i = start; i < end; i++) {
9795 intel_crtc->lut_r[i] = red[i] >> 8;
9796 intel_crtc->lut_g[i] = green[i] >> 8;
9797 intel_crtc->lut_b[i] = blue[i] >> 8;
9798 }
9799
9800 intel_crtc_load_lut(crtc);
9801 }
9802
9803 /* VESA 640x480x72Hz mode to set on the pipe */
9804 static struct drm_display_mode load_detect_mode = {
9805 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9806 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9807 };
9808
9809 struct drm_framebuffer *
9810 __intel_framebuffer_create(struct drm_device *dev,
9811 struct drm_mode_fb_cmd2 *mode_cmd,
9812 struct drm_i915_gem_object *obj)
9813 {
9814 struct intel_framebuffer *intel_fb;
9815 int ret;
9816
9817 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9818 if (!intel_fb) {
9819 drm_gem_object_unreference(&obj->base);
9820 return ERR_PTR(-ENOMEM);
9821 }
9822
9823 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9824 if (ret)
9825 goto err;
9826
9827 return &intel_fb->base;
9828 err:
9829 drm_gem_object_unreference(&obj->base);
9830 kfree(intel_fb);
9831
9832 return ERR_PTR(ret);
9833 }
9834
9835 static struct drm_framebuffer *
9836 intel_framebuffer_create(struct drm_device *dev,
9837 struct drm_mode_fb_cmd2 *mode_cmd,
9838 struct drm_i915_gem_object *obj)
9839 {
9840 struct drm_framebuffer *fb;
9841 int ret;
9842
9843 ret = i915_mutex_lock_interruptible(dev);
9844 if (ret)
9845 return ERR_PTR(ret);
9846 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9847 mutex_unlock(&dev->struct_mutex);
9848
9849 return fb;
9850 }
9851
9852 static u32
9853 intel_framebuffer_pitch_for_width(int width, int bpp)
9854 {
9855 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9856 return ALIGN(pitch, 64);
9857 }
9858
9859 static u32
9860 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9861 {
9862 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9863 return PAGE_ALIGN(pitch * mode->vdisplay);
9864 }
9865
9866 static struct drm_framebuffer *
9867 intel_framebuffer_create_for_mode(struct drm_device *dev,
9868 struct drm_display_mode *mode,
9869 int depth, int bpp)
9870 {
9871 struct drm_i915_gem_object *obj;
9872 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9873
9874 obj = i915_gem_alloc_object(dev,
9875 intel_framebuffer_size_for_mode(mode, bpp));
9876 if (obj == NULL)
9877 return ERR_PTR(-ENOMEM);
9878
9879 mode_cmd.width = mode->hdisplay;
9880 mode_cmd.height = mode->vdisplay;
9881 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9882 bpp);
9883 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9884
9885 return intel_framebuffer_create(dev, &mode_cmd, obj);
9886 }
9887
9888 static struct drm_framebuffer *
9889 mode_fits_in_fbdev(struct drm_device *dev,
9890 struct drm_display_mode *mode)
9891 {
9892 #ifdef CONFIG_DRM_I915_FBDEV
9893 struct drm_i915_private *dev_priv = dev->dev_private;
9894 struct drm_i915_gem_object *obj;
9895 struct drm_framebuffer *fb;
9896
9897 if (!dev_priv->fbdev)
9898 return NULL;
9899
9900 if (!dev_priv->fbdev->fb)
9901 return NULL;
9902
9903 obj = dev_priv->fbdev->fb->obj;
9904 BUG_ON(!obj);
9905
9906 fb = &dev_priv->fbdev->fb->base;
9907 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9908 fb->bits_per_pixel))
9909 return NULL;
9910
9911 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9912 return NULL;
9913
9914 return fb;
9915 #else
9916 return NULL;
9917 #endif
9918 }
9919
9920 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9921 struct drm_crtc *crtc,
9922 struct drm_display_mode *mode,
9923 struct drm_framebuffer *fb,
9924 int x, int y)
9925 {
9926 struct drm_plane_state *plane_state;
9927 int hdisplay, vdisplay;
9928 int ret;
9929
9930 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9931 if (IS_ERR(plane_state))
9932 return PTR_ERR(plane_state);
9933
9934 if (mode)
9935 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9936 else
9937 hdisplay = vdisplay = 0;
9938
9939 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9940 if (ret)
9941 return ret;
9942 drm_atomic_set_fb_for_plane(plane_state, fb);
9943 plane_state->crtc_x = 0;
9944 plane_state->crtc_y = 0;
9945 plane_state->crtc_w = hdisplay;
9946 plane_state->crtc_h = vdisplay;
9947 plane_state->src_x = x << 16;
9948 plane_state->src_y = y << 16;
9949 plane_state->src_w = hdisplay << 16;
9950 plane_state->src_h = vdisplay << 16;
9951
9952 return 0;
9953 }
9954
9955 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9956 struct drm_display_mode *mode,
9957 struct intel_load_detect_pipe *old,
9958 struct drm_modeset_acquire_ctx *ctx)
9959 {
9960 struct intel_crtc *intel_crtc;
9961 struct intel_encoder *intel_encoder =
9962 intel_attached_encoder(connector);
9963 struct drm_crtc *possible_crtc;
9964 struct drm_encoder *encoder = &intel_encoder->base;
9965 struct drm_crtc *crtc = NULL;
9966 struct drm_device *dev = encoder->dev;
9967 struct drm_framebuffer *fb;
9968 struct drm_mode_config *config = &dev->mode_config;
9969 struct drm_atomic_state *state = NULL;
9970 struct drm_connector_state *connector_state;
9971 struct intel_crtc_state *crtc_state;
9972 int ret, i = -1;
9973
9974 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9975 connector->base.id, connector->name,
9976 encoder->base.id, encoder->name);
9977
9978 retry:
9979 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9980 if (ret)
9981 goto fail_unlock;
9982
9983 /*
9984 * Algorithm gets a little messy:
9985 *
9986 * - if the connector already has an assigned crtc, use it (but make
9987 * sure it's on first)
9988 *
9989 * - try to find the first unused crtc that can drive this connector,
9990 * and use that if we find one
9991 */
9992
9993 /* See if we already have a CRTC for this connector */
9994 if (encoder->crtc) {
9995 crtc = encoder->crtc;
9996
9997 ret = drm_modeset_lock(&crtc->mutex, ctx);
9998 if (ret)
9999 goto fail_unlock;
10000 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10001 if (ret)
10002 goto fail_unlock;
10003
10004 old->dpms_mode = connector->dpms;
10005 old->load_detect_temp = false;
10006
10007 /* Make sure the crtc and connector are running */
10008 if (connector->dpms != DRM_MODE_DPMS_ON)
10009 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10010
10011 return true;
10012 }
10013
10014 /* Find an unused one (if possible) */
10015 for_each_crtc(dev, possible_crtc) {
10016 i++;
10017 if (!(encoder->possible_crtcs & (1 << i)))
10018 continue;
10019 if (possible_crtc->state->enable)
10020 continue;
10021 /* This can occur when applying the pipe A quirk on resume. */
10022 if (to_intel_crtc(possible_crtc)->new_enabled)
10023 continue;
10024
10025 crtc = possible_crtc;
10026 break;
10027 }
10028
10029 /*
10030 * If we didn't find an unused CRTC, don't use any.
10031 */
10032 if (!crtc) {
10033 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10034 goto fail_unlock;
10035 }
10036
10037 ret = drm_modeset_lock(&crtc->mutex, ctx);
10038 if (ret)
10039 goto fail_unlock;
10040 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10041 if (ret)
10042 goto fail_unlock;
10043 intel_encoder->new_crtc = to_intel_crtc(crtc);
10044 to_intel_connector(connector)->new_encoder = intel_encoder;
10045
10046 intel_crtc = to_intel_crtc(crtc);
10047 intel_crtc->new_enabled = true;
10048 old->dpms_mode = connector->dpms;
10049 old->load_detect_temp = true;
10050 old->release_fb = NULL;
10051
10052 state = drm_atomic_state_alloc(dev);
10053 if (!state)
10054 return false;
10055
10056 state->acquire_ctx = ctx;
10057
10058 connector_state = drm_atomic_get_connector_state(state, connector);
10059 if (IS_ERR(connector_state)) {
10060 ret = PTR_ERR(connector_state);
10061 goto fail;
10062 }
10063
10064 connector_state->crtc = crtc;
10065 connector_state->best_encoder = &intel_encoder->base;
10066
10067 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10068 if (IS_ERR(crtc_state)) {
10069 ret = PTR_ERR(crtc_state);
10070 goto fail;
10071 }
10072
10073 crtc_state->base.active = crtc_state->base.enable = true;
10074
10075 if (!mode)
10076 mode = &load_detect_mode;
10077
10078 /* We need a framebuffer large enough to accommodate all accesses
10079 * that the plane may generate whilst we perform load detection.
10080 * We can not rely on the fbcon either being present (we get called
10081 * during its initialisation to detect all boot displays, or it may
10082 * not even exist) or that it is large enough to satisfy the
10083 * requested mode.
10084 */
10085 fb = mode_fits_in_fbdev(dev, mode);
10086 if (fb == NULL) {
10087 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10088 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10089 old->release_fb = fb;
10090 } else
10091 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10092 if (IS_ERR(fb)) {
10093 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10094 goto fail;
10095 }
10096
10097 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10098 if (ret)
10099 goto fail;
10100
10101 drm_mode_copy(&crtc_state->base.mode, mode);
10102
10103 if (intel_set_mode(crtc, state, true)) {
10104 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10105 if (old->release_fb)
10106 old->release_fb->funcs->destroy(old->release_fb);
10107 goto fail;
10108 }
10109 crtc->primary->crtc = crtc;
10110
10111 /* let the connector get through one full cycle before testing */
10112 intel_wait_for_vblank(dev, intel_crtc->pipe);
10113 return true;
10114
10115 fail:
10116 intel_crtc->new_enabled = crtc->state->enable;
10117 fail_unlock:
10118 drm_atomic_state_free(state);
10119 state = NULL;
10120
10121 if (ret == -EDEADLK) {
10122 drm_modeset_backoff(ctx);
10123 goto retry;
10124 }
10125
10126 return false;
10127 }
10128
10129 void intel_release_load_detect_pipe(struct drm_connector *connector,
10130 struct intel_load_detect_pipe *old,
10131 struct drm_modeset_acquire_ctx *ctx)
10132 {
10133 struct drm_device *dev = connector->dev;
10134 struct intel_encoder *intel_encoder =
10135 intel_attached_encoder(connector);
10136 struct drm_encoder *encoder = &intel_encoder->base;
10137 struct drm_crtc *crtc = encoder->crtc;
10138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10139 struct drm_atomic_state *state;
10140 struct drm_connector_state *connector_state;
10141 struct intel_crtc_state *crtc_state;
10142 int ret;
10143
10144 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10145 connector->base.id, connector->name,
10146 encoder->base.id, encoder->name);
10147
10148 if (old->load_detect_temp) {
10149 state = drm_atomic_state_alloc(dev);
10150 if (!state)
10151 goto fail;
10152
10153 state->acquire_ctx = ctx;
10154
10155 connector_state = drm_atomic_get_connector_state(state, connector);
10156 if (IS_ERR(connector_state))
10157 goto fail;
10158
10159 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10160 if (IS_ERR(crtc_state))
10161 goto fail;
10162
10163 to_intel_connector(connector)->new_encoder = NULL;
10164 intel_encoder->new_crtc = NULL;
10165 intel_crtc->new_enabled = false;
10166
10167 connector_state->best_encoder = NULL;
10168 connector_state->crtc = NULL;
10169
10170 crtc_state->base.enable = crtc_state->base.active = false;
10171
10172 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10173 0, 0);
10174 if (ret)
10175 goto fail;
10176
10177 ret = intel_set_mode(crtc, state, true);
10178 if (ret)
10179 goto fail;
10180
10181 if (old->release_fb) {
10182 drm_framebuffer_unregister_private(old->release_fb);
10183 drm_framebuffer_unreference(old->release_fb);
10184 }
10185
10186 return;
10187 }
10188
10189 /* Switch crtc and encoder back off if necessary */
10190 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10191 connector->funcs->dpms(connector, old->dpms_mode);
10192
10193 return;
10194 fail:
10195 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10196 drm_atomic_state_free(state);
10197 }
10198
10199 static int i9xx_pll_refclk(struct drm_device *dev,
10200 const struct intel_crtc_state *pipe_config)
10201 {
10202 struct drm_i915_private *dev_priv = dev->dev_private;
10203 u32 dpll = pipe_config->dpll_hw_state.dpll;
10204
10205 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10206 return dev_priv->vbt.lvds_ssc_freq;
10207 else if (HAS_PCH_SPLIT(dev))
10208 return 120000;
10209 else if (!IS_GEN2(dev))
10210 return 96000;
10211 else
10212 return 48000;
10213 }
10214
10215 /* Returns the clock of the currently programmed mode of the given pipe. */
10216 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10217 struct intel_crtc_state *pipe_config)
10218 {
10219 struct drm_device *dev = crtc->base.dev;
10220 struct drm_i915_private *dev_priv = dev->dev_private;
10221 int pipe = pipe_config->cpu_transcoder;
10222 u32 dpll = pipe_config->dpll_hw_state.dpll;
10223 u32 fp;
10224 intel_clock_t clock;
10225 int refclk = i9xx_pll_refclk(dev, pipe_config);
10226
10227 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10228 fp = pipe_config->dpll_hw_state.fp0;
10229 else
10230 fp = pipe_config->dpll_hw_state.fp1;
10231
10232 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10233 if (IS_PINEVIEW(dev)) {
10234 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10235 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10236 } else {
10237 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10238 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10239 }
10240
10241 if (!IS_GEN2(dev)) {
10242 if (IS_PINEVIEW(dev))
10243 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10244 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10245 else
10246 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10247 DPLL_FPA01_P1_POST_DIV_SHIFT);
10248
10249 switch (dpll & DPLL_MODE_MASK) {
10250 case DPLLB_MODE_DAC_SERIAL:
10251 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10252 5 : 10;
10253 break;
10254 case DPLLB_MODE_LVDS:
10255 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10256 7 : 14;
10257 break;
10258 default:
10259 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10260 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10261 return;
10262 }
10263
10264 if (IS_PINEVIEW(dev))
10265 pineview_clock(refclk, &clock);
10266 else
10267 i9xx_clock(refclk, &clock);
10268 } else {
10269 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10270 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10271
10272 if (is_lvds) {
10273 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10274 DPLL_FPA01_P1_POST_DIV_SHIFT);
10275
10276 if (lvds & LVDS_CLKB_POWER_UP)
10277 clock.p2 = 7;
10278 else
10279 clock.p2 = 14;
10280 } else {
10281 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10282 clock.p1 = 2;
10283 else {
10284 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10285 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10286 }
10287 if (dpll & PLL_P2_DIVIDE_BY_4)
10288 clock.p2 = 4;
10289 else
10290 clock.p2 = 2;
10291 }
10292
10293 i9xx_clock(refclk, &clock);
10294 }
10295
10296 /*
10297 * This value includes pixel_multiplier. We will use
10298 * port_clock to compute adjusted_mode.crtc_clock in the
10299 * encoder's get_config() function.
10300 */
10301 pipe_config->port_clock = clock.dot;
10302 }
10303
10304 int intel_dotclock_calculate(int link_freq,
10305 const struct intel_link_m_n *m_n)
10306 {
10307 /*
10308 * The calculation for the data clock is:
10309 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10310 * But we want to avoid losing precison if possible, so:
10311 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10312 *
10313 * and the link clock is simpler:
10314 * link_clock = (m * link_clock) / n
10315 */
10316
10317 if (!m_n->link_n)
10318 return 0;
10319
10320 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10321 }
10322
10323 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10324 struct intel_crtc_state *pipe_config)
10325 {
10326 struct drm_device *dev = crtc->base.dev;
10327
10328 /* read out port_clock from the DPLL */
10329 i9xx_crtc_clock_get(crtc, pipe_config);
10330
10331 /*
10332 * This value does not include pixel_multiplier.
10333 * We will check that port_clock and adjusted_mode.crtc_clock
10334 * agree once we know their relationship in the encoder's
10335 * get_config() function.
10336 */
10337 pipe_config->base.adjusted_mode.crtc_clock =
10338 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10339 &pipe_config->fdi_m_n);
10340 }
10341
10342 /** Returns the currently programmed mode of the given pipe. */
10343 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10344 struct drm_crtc *crtc)
10345 {
10346 struct drm_i915_private *dev_priv = dev->dev_private;
10347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10348 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10349 struct drm_display_mode *mode;
10350 struct intel_crtc_state pipe_config;
10351 int htot = I915_READ(HTOTAL(cpu_transcoder));
10352 int hsync = I915_READ(HSYNC(cpu_transcoder));
10353 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10354 int vsync = I915_READ(VSYNC(cpu_transcoder));
10355 enum pipe pipe = intel_crtc->pipe;
10356
10357 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10358 if (!mode)
10359 return NULL;
10360
10361 /*
10362 * Construct a pipe_config sufficient for getting the clock info
10363 * back out of crtc_clock_get.
10364 *
10365 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10366 * to use a real value here instead.
10367 */
10368 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10369 pipe_config.pixel_multiplier = 1;
10370 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10371 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10372 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10373 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10374
10375 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10376 mode->hdisplay = (htot & 0xffff) + 1;
10377 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10378 mode->hsync_start = (hsync & 0xffff) + 1;
10379 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10380 mode->vdisplay = (vtot & 0xffff) + 1;
10381 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10382 mode->vsync_start = (vsync & 0xffff) + 1;
10383 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10384
10385 drm_mode_set_name(mode);
10386
10387 return mode;
10388 }
10389
10390 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10391 {
10392 struct drm_device *dev = crtc->dev;
10393 struct drm_i915_private *dev_priv = dev->dev_private;
10394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10395
10396 if (!HAS_GMCH_DISPLAY(dev))
10397 return;
10398
10399 if (!dev_priv->lvds_downclock_avail)
10400 return;
10401
10402 /*
10403 * Since this is called by a timer, we should never get here in
10404 * the manual case.
10405 */
10406 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10407 int pipe = intel_crtc->pipe;
10408 int dpll_reg = DPLL(pipe);
10409 int dpll;
10410
10411 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10412
10413 assert_panel_unlocked(dev_priv, pipe);
10414
10415 dpll = I915_READ(dpll_reg);
10416 dpll |= DISPLAY_RATE_SELECT_FPA1;
10417 I915_WRITE(dpll_reg, dpll);
10418 intel_wait_for_vblank(dev, pipe);
10419 dpll = I915_READ(dpll_reg);
10420 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10421 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10422 }
10423
10424 }
10425
10426 void intel_mark_busy(struct drm_device *dev)
10427 {
10428 struct drm_i915_private *dev_priv = dev->dev_private;
10429
10430 if (dev_priv->mm.busy)
10431 return;
10432
10433 intel_runtime_pm_get(dev_priv);
10434 i915_update_gfx_val(dev_priv);
10435 if (INTEL_INFO(dev)->gen >= 6)
10436 gen6_rps_busy(dev_priv);
10437 dev_priv->mm.busy = true;
10438 }
10439
10440 void intel_mark_idle(struct drm_device *dev)
10441 {
10442 struct drm_i915_private *dev_priv = dev->dev_private;
10443 struct drm_crtc *crtc;
10444
10445 if (!dev_priv->mm.busy)
10446 return;
10447
10448 dev_priv->mm.busy = false;
10449
10450 for_each_crtc(dev, crtc) {
10451 if (!crtc->primary->fb)
10452 continue;
10453
10454 intel_decrease_pllclock(crtc);
10455 }
10456
10457 if (INTEL_INFO(dev)->gen >= 6)
10458 gen6_rps_idle(dev->dev_private);
10459
10460 intel_runtime_pm_put(dev_priv);
10461 }
10462
10463 static void intel_crtc_destroy(struct drm_crtc *crtc)
10464 {
10465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10466 struct drm_device *dev = crtc->dev;
10467 struct intel_unpin_work *work;
10468
10469 spin_lock_irq(&dev->event_lock);
10470 work = intel_crtc->unpin_work;
10471 intel_crtc->unpin_work = NULL;
10472 spin_unlock_irq(&dev->event_lock);
10473
10474 if (work) {
10475 cancel_work_sync(&work->work);
10476 kfree(work);
10477 }
10478
10479 drm_crtc_cleanup(crtc);
10480
10481 kfree(intel_crtc);
10482 }
10483
10484 static void intel_unpin_work_fn(struct work_struct *__work)
10485 {
10486 struct intel_unpin_work *work =
10487 container_of(__work, struct intel_unpin_work, work);
10488 struct drm_device *dev = work->crtc->dev;
10489 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10490
10491 mutex_lock(&dev->struct_mutex);
10492 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10493 drm_gem_object_unreference(&work->pending_flip_obj->base);
10494
10495 intel_fbc_update(dev);
10496
10497 if (work->flip_queued_req)
10498 i915_gem_request_assign(&work->flip_queued_req, NULL);
10499 mutex_unlock(&dev->struct_mutex);
10500
10501 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10502 drm_framebuffer_unreference(work->old_fb);
10503
10504 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10505 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10506
10507 kfree(work);
10508 }
10509
10510 static void do_intel_finish_page_flip(struct drm_device *dev,
10511 struct drm_crtc *crtc)
10512 {
10513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10514 struct intel_unpin_work *work;
10515 unsigned long flags;
10516
10517 /* Ignore early vblank irqs */
10518 if (intel_crtc == NULL)
10519 return;
10520
10521 /*
10522 * This is called both by irq handlers and the reset code (to complete
10523 * lost pageflips) so needs the full irqsave spinlocks.
10524 */
10525 spin_lock_irqsave(&dev->event_lock, flags);
10526 work = intel_crtc->unpin_work;
10527
10528 /* Ensure we don't miss a work->pending update ... */
10529 smp_rmb();
10530
10531 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10532 spin_unlock_irqrestore(&dev->event_lock, flags);
10533 return;
10534 }
10535
10536 page_flip_completed(intel_crtc);
10537
10538 spin_unlock_irqrestore(&dev->event_lock, flags);
10539 }
10540
10541 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10542 {
10543 struct drm_i915_private *dev_priv = dev->dev_private;
10544 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10545
10546 do_intel_finish_page_flip(dev, crtc);
10547 }
10548
10549 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10550 {
10551 struct drm_i915_private *dev_priv = dev->dev_private;
10552 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10553
10554 do_intel_finish_page_flip(dev, crtc);
10555 }
10556
10557 /* Is 'a' after or equal to 'b'? */
10558 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10559 {
10560 return !((a - b) & 0x80000000);
10561 }
10562
10563 static bool page_flip_finished(struct intel_crtc *crtc)
10564 {
10565 struct drm_device *dev = crtc->base.dev;
10566 struct drm_i915_private *dev_priv = dev->dev_private;
10567
10568 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10569 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10570 return true;
10571
10572 /*
10573 * The relevant registers doen't exist on pre-ctg.
10574 * As the flip done interrupt doesn't trigger for mmio
10575 * flips on gmch platforms, a flip count check isn't
10576 * really needed there. But since ctg has the registers,
10577 * include it in the check anyway.
10578 */
10579 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10580 return true;
10581
10582 /*
10583 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10584 * used the same base address. In that case the mmio flip might
10585 * have completed, but the CS hasn't even executed the flip yet.
10586 *
10587 * A flip count check isn't enough as the CS might have updated
10588 * the base address just after start of vblank, but before we
10589 * managed to process the interrupt. This means we'd complete the
10590 * CS flip too soon.
10591 *
10592 * Combining both checks should get us a good enough result. It may
10593 * still happen that the CS flip has been executed, but has not
10594 * yet actually completed. But in case the base address is the same
10595 * anyway, we don't really care.
10596 */
10597 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10598 crtc->unpin_work->gtt_offset &&
10599 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10600 crtc->unpin_work->flip_count);
10601 }
10602
10603 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10604 {
10605 struct drm_i915_private *dev_priv = dev->dev_private;
10606 struct intel_crtc *intel_crtc =
10607 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10608 unsigned long flags;
10609
10610
10611 /*
10612 * This is called both by irq handlers and the reset code (to complete
10613 * lost pageflips) so needs the full irqsave spinlocks.
10614 *
10615 * NB: An MMIO update of the plane base pointer will also
10616 * generate a page-flip completion irq, i.e. every modeset
10617 * is also accompanied by a spurious intel_prepare_page_flip().
10618 */
10619 spin_lock_irqsave(&dev->event_lock, flags);
10620 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10621 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10622 spin_unlock_irqrestore(&dev->event_lock, flags);
10623 }
10624
10625 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10626 {
10627 /* Ensure that the work item is consistent when activating it ... */
10628 smp_wmb();
10629 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10630 /* and that it is marked active as soon as the irq could fire. */
10631 smp_wmb();
10632 }
10633
10634 static int intel_gen2_queue_flip(struct drm_device *dev,
10635 struct drm_crtc *crtc,
10636 struct drm_framebuffer *fb,
10637 struct drm_i915_gem_object *obj,
10638 struct intel_engine_cs *ring,
10639 uint32_t flags)
10640 {
10641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10642 u32 flip_mask;
10643 int ret;
10644
10645 ret = intel_ring_begin(ring, 6);
10646 if (ret)
10647 return ret;
10648
10649 /* Can't queue multiple flips, so wait for the previous
10650 * one to finish before executing the next.
10651 */
10652 if (intel_crtc->plane)
10653 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10654 else
10655 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10656 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10657 intel_ring_emit(ring, MI_NOOP);
10658 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10659 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10660 intel_ring_emit(ring, fb->pitches[0]);
10661 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10662 intel_ring_emit(ring, 0); /* aux display base address, unused */
10663
10664 intel_mark_page_flip_active(intel_crtc);
10665 __intel_ring_advance(ring);
10666 return 0;
10667 }
10668
10669 static int intel_gen3_queue_flip(struct drm_device *dev,
10670 struct drm_crtc *crtc,
10671 struct drm_framebuffer *fb,
10672 struct drm_i915_gem_object *obj,
10673 struct intel_engine_cs *ring,
10674 uint32_t flags)
10675 {
10676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10677 u32 flip_mask;
10678 int ret;
10679
10680 ret = intel_ring_begin(ring, 6);
10681 if (ret)
10682 return ret;
10683
10684 if (intel_crtc->plane)
10685 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10686 else
10687 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10688 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10689 intel_ring_emit(ring, MI_NOOP);
10690 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10691 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10692 intel_ring_emit(ring, fb->pitches[0]);
10693 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10694 intel_ring_emit(ring, MI_NOOP);
10695
10696 intel_mark_page_flip_active(intel_crtc);
10697 __intel_ring_advance(ring);
10698 return 0;
10699 }
10700
10701 static int intel_gen4_queue_flip(struct drm_device *dev,
10702 struct drm_crtc *crtc,
10703 struct drm_framebuffer *fb,
10704 struct drm_i915_gem_object *obj,
10705 struct intel_engine_cs *ring,
10706 uint32_t flags)
10707 {
10708 struct drm_i915_private *dev_priv = dev->dev_private;
10709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10710 uint32_t pf, pipesrc;
10711 int ret;
10712
10713 ret = intel_ring_begin(ring, 4);
10714 if (ret)
10715 return ret;
10716
10717 /* i965+ uses the linear or tiled offsets from the
10718 * Display Registers (which do not change across a page-flip)
10719 * so we need only reprogram the base address.
10720 */
10721 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10722 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10723 intel_ring_emit(ring, fb->pitches[0]);
10724 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10725 obj->tiling_mode);
10726
10727 /* XXX Enabling the panel-fitter across page-flip is so far
10728 * untested on non-native modes, so ignore it for now.
10729 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10730 */
10731 pf = 0;
10732 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10733 intel_ring_emit(ring, pf | pipesrc);
10734
10735 intel_mark_page_flip_active(intel_crtc);
10736 __intel_ring_advance(ring);
10737 return 0;
10738 }
10739
10740 static int intel_gen6_queue_flip(struct drm_device *dev,
10741 struct drm_crtc *crtc,
10742 struct drm_framebuffer *fb,
10743 struct drm_i915_gem_object *obj,
10744 struct intel_engine_cs *ring,
10745 uint32_t flags)
10746 {
10747 struct drm_i915_private *dev_priv = dev->dev_private;
10748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10749 uint32_t pf, pipesrc;
10750 int ret;
10751
10752 ret = intel_ring_begin(ring, 4);
10753 if (ret)
10754 return ret;
10755
10756 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10757 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10758 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10759 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10760
10761 /* Contrary to the suggestions in the documentation,
10762 * "Enable Panel Fitter" does not seem to be required when page
10763 * flipping with a non-native mode, and worse causes a normal
10764 * modeset to fail.
10765 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10766 */
10767 pf = 0;
10768 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10769 intel_ring_emit(ring, pf | pipesrc);
10770
10771 intel_mark_page_flip_active(intel_crtc);
10772 __intel_ring_advance(ring);
10773 return 0;
10774 }
10775
10776 static int intel_gen7_queue_flip(struct drm_device *dev,
10777 struct drm_crtc *crtc,
10778 struct drm_framebuffer *fb,
10779 struct drm_i915_gem_object *obj,
10780 struct intel_engine_cs *ring,
10781 uint32_t flags)
10782 {
10783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10784 uint32_t plane_bit = 0;
10785 int len, ret;
10786
10787 switch (intel_crtc->plane) {
10788 case PLANE_A:
10789 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10790 break;
10791 case PLANE_B:
10792 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10793 break;
10794 case PLANE_C:
10795 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10796 break;
10797 default:
10798 WARN_ONCE(1, "unknown plane in flip command\n");
10799 return -ENODEV;
10800 }
10801
10802 len = 4;
10803 if (ring->id == RCS) {
10804 len += 6;
10805 /*
10806 * On Gen 8, SRM is now taking an extra dword to accommodate
10807 * 48bits addresses, and we need a NOOP for the batch size to
10808 * stay even.
10809 */
10810 if (IS_GEN8(dev))
10811 len += 2;
10812 }
10813
10814 /*
10815 * BSpec MI_DISPLAY_FLIP for IVB:
10816 * "The full packet must be contained within the same cache line."
10817 *
10818 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10819 * cacheline, if we ever start emitting more commands before
10820 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10821 * then do the cacheline alignment, and finally emit the
10822 * MI_DISPLAY_FLIP.
10823 */
10824 ret = intel_ring_cacheline_align(ring);
10825 if (ret)
10826 return ret;
10827
10828 ret = intel_ring_begin(ring, len);
10829 if (ret)
10830 return ret;
10831
10832 /* Unmask the flip-done completion message. Note that the bspec says that
10833 * we should do this for both the BCS and RCS, and that we must not unmask
10834 * more than one flip event at any time (or ensure that one flip message
10835 * can be sent by waiting for flip-done prior to queueing new flips).
10836 * Experimentation says that BCS works despite DERRMR masking all
10837 * flip-done completion events and that unmasking all planes at once
10838 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10839 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10840 */
10841 if (ring->id == RCS) {
10842 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10843 intel_ring_emit(ring, DERRMR);
10844 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10845 DERRMR_PIPEB_PRI_FLIP_DONE |
10846 DERRMR_PIPEC_PRI_FLIP_DONE));
10847 if (IS_GEN8(dev))
10848 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10849 MI_SRM_LRM_GLOBAL_GTT);
10850 else
10851 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10852 MI_SRM_LRM_GLOBAL_GTT);
10853 intel_ring_emit(ring, DERRMR);
10854 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10855 if (IS_GEN8(dev)) {
10856 intel_ring_emit(ring, 0);
10857 intel_ring_emit(ring, MI_NOOP);
10858 }
10859 }
10860
10861 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10862 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10863 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10864 intel_ring_emit(ring, (MI_NOOP));
10865
10866 intel_mark_page_flip_active(intel_crtc);
10867 __intel_ring_advance(ring);
10868 return 0;
10869 }
10870
10871 static bool use_mmio_flip(struct intel_engine_cs *ring,
10872 struct drm_i915_gem_object *obj)
10873 {
10874 /*
10875 * This is not being used for older platforms, because
10876 * non-availability of flip done interrupt forces us to use
10877 * CS flips. Older platforms derive flip done using some clever
10878 * tricks involving the flip_pending status bits and vblank irqs.
10879 * So using MMIO flips there would disrupt this mechanism.
10880 */
10881
10882 if (ring == NULL)
10883 return true;
10884
10885 if (INTEL_INFO(ring->dev)->gen < 5)
10886 return false;
10887
10888 if (i915.use_mmio_flip < 0)
10889 return false;
10890 else if (i915.use_mmio_flip > 0)
10891 return true;
10892 else if (i915.enable_execlists)
10893 return true;
10894 else
10895 return ring != i915_gem_request_get_ring(obj->last_write_req);
10896 }
10897
10898 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10899 {
10900 struct drm_device *dev = intel_crtc->base.dev;
10901 struct drm_i915_private *dev_priv = dev->dev_private;
10902 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10903 const enum pipe pipe = intel_crtc->pipe;
10904 u32 ctl, stride;
10905
10906 ctl = I915_READ(PLANE_CTL(pipe, 0));
10907 ctl &= ~PLANE_CTL_TILED_MASK;
10908 switch (fb->modifier[0]) {
10909 case DRM_FORMAT_MOD_NONE:
10910 break;
10911 case I915_FORMAT_MOD_X_TILED:
10912 ctl |= PLANE_CTL_TILED_X;
10913 break;
10914 case I915_FORMAT_MOD_Y_TILED:
10915 ctl |= PLANE_CTL_TILED_Y;
10916 break;
10917 case I915_FORMAT_MOD_Yf_TILED:
10918 ctl |= PLANE_CTL_TILED_YF;
10919 break;
10920 default:
10921 MISSING_CASE(fb->modifier[0]);
10922 }
10923
10924 /*
10925 * The stride is either expressed as a multiple of 64 bytes chunks for
10926 * linear buffers or in number of tiles for tiled buffers.
10927 */
10928 stride = fb->pitches[0] /
10929 intel_fb_stride_alignment(dev, fb->modifier[0],
10930 fb->pixel_format);
10931
10932 /*
10933 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10934 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10935 */
10936 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10937 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10938
10939 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10940 POSTING_READ(PLANE_SURF(pipe, 0));
10941 }
10942
10943 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10944 {
10945 struct drm_device *dev = intel_crtc->base.dev;
10946 struct drm_i915_private *dev_priv = dev->dev_private;
10947 struct intel_framebuffer *intel_fb =
10948 to_intel_framebuffer(intel_crtc->base.primary->fb);
10949 struct drm_i915_gem_object *obj = intel_fb->obj;
10950 u32 dspcntr;
10951 u32 reg;
10952
10953 reg = DSPCNTR(intel_crtc->plane);
10954 dspcntr = I915_READ(reg);
10955
10956 if (obj->tiling_mode != I915_TILING_NONE)
10957 dspcntr |= DISPPLANE_TILED;
10958 else
10959 dspcntr &= ~DISPPLANE_TILED;
10960
10961 I915_WRITE(reg, dspcntr);
10962
10963 I915_WRITE(DSPSURF(intel_crtc->plane),
10964 intel_crtc->unpin_work->gtt_offset);
10965 POSTING_READ(DSPSURF(intel_crtc->plane));
10966
10967 }
10968
10969 /*
10970 * XXX: This is the temporary way to update the plane registers until we get
10971 * around to using the usual plane update functions for MMIO flips
10972 */
10973 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10974 {
10975 struct drm_device *dev = intel_crtc->base.dev;
10976 bool atomic_update;
10977 u32 start_vbl_count;
10978
10979 intel_mark_page_flip_active(intel_crtc);
10980
10981 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10982
10983 if (INTEL_INFO(dev)->gen >= 9)
10984 skl_do_mmio_flip(intel_crtc);
10985 else
10986 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10987 ilk_do_mmio_flip(intel_crtc);
10988
10989 if (atomic_update)
10990 intel_pipe_update_end(intel_crtc, start_vbl_count);
10991 }
10992
10993 static void intel_mmio_flip_work_func(struct work_struct *work)
10994 {
10995 struct intel_mmio_flip *mmio_flip =
10996 container_of(work, struct intel_mmio_flip, work);
10997
10998 if (mmio_flip->req)
10999 WARN_ON(__i915_wait_request(mmio_flip->req,
11000 mmio_flip->crtc->reset_counter,
11001 false, NULL,
11002 &mmio_flip->i915->rps.mmioflips));
11003
11004 intel_do_mmio_flip(mmio_flip->crtc);
11005
11006 i915_gem_request_unreference__unlocked(mmio_flip->req);
11007 kfree(mmio_flip);
11008 }
11009
11010 static int intel_queue_mmio_flip(struct drm_device *dev,
11011 struct drm_crtc *crtc,
11012 struct drm_framebuffer *fb,
11013 struct drm_i915_gem_object *obj,
11014 struct intel_engine_cs *ring,
11015 uint32_t flags)
11016 {
11017 struct intel_mmio_flip *mmio_flip;
11018
11019 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11020 if (mmio_flip == NULL)
11021 return -ENOMEM;
11022
11023 mmio_flip->i915 = to_i915(dev);
11024 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11025 mmio_flip->crtc = to_intel_crtc(crtc);
11026
11027 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11028 schedule_work(&mmio_flip->work);
11029
11030 return 0;
11031 }
11032
11033 static int intel_default_queue_flip(struct drm_device *dev,
11034 struct drm_crtc *crtc,
11035 struct drm_framebuffer *fb,
11036 struct drm_i915_gem_object *obj,
11037 struct intel_engine_cs *ring,
11038 uint32_t flags)
11039 {
11040 return -ENODEV;
11041 }
11042
11043 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11044 struct drm_crtc *crtc)
11045 {
11046 struct drm_i915_private *dev_priv = dev->dev_private;
11047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11048 struct intel_unpin_work *work = intel_crtc->unpin_work;
11049 u32 addr;
11050
11051 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11052 return true;
11053
11054 if (!work->enable_stall_check)
11055 return false;
11056
11057 if (work->flip_ready_vblank == 0) {
11058 if (work->flip_queued_req &&
11059 !i915_gem_request_completed(work->flip_queued_req, true))
11060 return false;
11061
11062 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11063 }
11064
11065 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11066 return false;
11067
11068 /* Potential stall - if we see that the flip has happened,
11069 * assume a missed interrupt. */
11070 if (INTEL_INFO(dev)->gen >= 4)
11071 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11072 else
11073 addr = I915_READ(DSPADDR(intel_crtc->plane));
11074
11075 /* There is a potential issue here with a false positive after a flip
11076 * to the same address. We could address this by checking for a
11077 * non-incrementing frame counter.
11078 */
11079 return addr == work->gtt_offset;
11080 }
11081
11082 void intel_check_page_flip(struct drm_device *dev, int pipe)
11083 {
11084 struct drm_i915_private *dev_priv = dev->dev_private;
11085 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11087 struct intel_unpin_work *work;
11088
11089 WARN_ON(!in_interrupt());
11090
11091 if (crtc == NULL)
11092 return;
11093
11094 spin_lock(&dev->event_lock);
11095 work = intel_crtc->unpin_work;
11096 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11097 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11098 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11099 page_flip_completed(intel_crtc);
11100 work = NULL;
11101 }
11102 if (work != NULL &&
11103 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11104 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11105 spin_unlock(&dev->event_lock);
11106 }
11107
11108 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11109 struct drm_framebuffer *fb,
11110 struct drm_pending_vblank_event *event,
11111 uint32_t page_flip_flags)
11112 {
11113 struct drm_device *dev = crtc->dev;
11114 struct drm_i915_private *dev_priv = dev->dev_private;
11115 struct drm_framebuffer *old_fb = crtc->primary->fb;
11116 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11118 struct drm_plane *primary = crtc->primary;
11119 enum pipe pipe = intel_crtc->pipe;
11120 struct intel_unpin_work *work;
11121 struct intel_engine_cs *ring;
11122 bool mmio_flip;
11123 int ret;
11124
11125 /*
11126 * drm_mode_page_flip_ioctl() should already catch this, but double
11127 * check to be safe. In the future we may enable pageflipping from
11128 * a disabled primary plane.
11129 */
11130 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11131 return -EBUSY;
11132
11133 /* Can't change pixel format via MI display flips. */
11134 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11135 return -EINVAL;
11136
11137 /*
11138 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11139 * Note that pitch changes could also affect these register.
11140 */
11141 if (INTEL_INFO(dev)->gen > 3 &&
11142 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11143 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11144 return -EINVAL;
11145
11146 if (i915_terminally_wedged(&dev_priv->gpu_error))
11147 goto out_hang;
11148
11149 work = kzalloc(sizeof(*work), GFP_KERNEL);
11150 if (work == NULL)
11151 return -ENOMEM;
11152
11153 work->event = event;
11154 work->crtc = crtc;
11155 work->old_fb = old_fb;
11156 INIT_WORK(&work->work, intel_unpin_work_fn);
11157
11158 ret = drm_crtc_vblank_get(crtc);
11159 if (ret)
11160 goto free_work;
11161
11162 /* We borrow the event spin lock for protecting unpin_work */
11163 spin_lock_irq(&dev->event_lock);
11164 if (intel_crtc->unpin_work) {
11165 /* Before declaring the flip queue wedged, check if
11166 * the hardware completed the operation behind our backs.
11167 */
11168 if (__intel_pageflip_stall_check(dev, crtc)) {
11169 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11170 page_flip_completed(intel_crtc);
11171 } else {
11172 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11173 spin_unlock_irq(&dev->event_lock);
11174
11175 drm_crtc_vblank_put(crtc);
11176 kfree(work);
11177 return -EBUSY;
11178 }
11179 }
11180 intel_crtc->unpin_work = work;
11181 spin_unlock_irq(&dev->event_lock);
11182
11183 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11184 flush_workqueue(dev_priv->wq);
11185
11186 /* Reference the objects for the scheduled work. */
11187 drm_framebuffer_reference(work->old_fb);
11188 drm_gem_object_reference(&obj->base);
11189
11190 crtc->primary->fb = fb;
11191 update_state_fb(crtc->primary);
11192
11193 work->pending_flip_obj = obj;
11194
11195 ret = i915_mutex_lock_interruptible(dev);
11196 if (ret)
11197 goto cleanup;
11198
11199 atomic_inc(&intel_crtc->unpin_work_count);
11200 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11201
11202 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11203 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11204
11205 if (IS_VALLEYVIEW(dev)) {
11206 ring = &dev_priv->ring[BCS];
11207 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11208 /* vlv: DISPLAY_FLIP fails to change tiling */
11209 ring = NULL;
11210 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11211 ring = &dev_priv->ring[BCS];
11212 } else if (INTEL_INFO(dev)->gen >= 7) {
11213 ring = i915_gem_request_get_ring(obj->last_write_req);
11214 if (ring == NULL || ring->id != RCS)
11215 ring = &dev_priv->ring[BCS];
11216 } else {
11217 ring = &dev_priv->ring[RCS];
11218 }
11219
11220 mmio_flip = use_mmio_flip(ring, obj);
11221
11222 /* When using CS flips, we want to emit semaphores between rings.
11223 * However, when using mmio flips we will create a task to do the
11224 * synchronisation, so all we want here is to pin the framebuffer
11225 * into the display plane and skip any waits.
11226 */
11227 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11228 crtc->primary->state,
11229 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11230 if (ret)
11231 goto cleanup_pending;
11232
11233 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11234 + intel_crtc->dspaddr_offset;
11235
11236 if (mmio_flip) {
11237 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11238 page_flip_flags);
11239 if (ret)
11240 goto cleanup_unpin;
11241
11242 i915_gem_request_assign(&work->flip_queued_req,
11243 obj->last_write_req);
11244 } else {
11245 if (obj->last_write_req) {
11246 ret = i915_gem_check_olr(obj->last_write_req);
11247 if (ret)
11248 goto cleanup_unpin;
11249 }
11250
11251 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11252 page_flip_flags);
11253 if (ret)
11254 goto cleanup_unpin;
11255
11256 i915_gem_request_assign(&work->flip_queued_req,
11257 intel_ring_get_request(ring));
11258 }
11259
11260 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11261 work->enable_stall_check = true;
11262
11263 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11264 INTEL_FRONTBUFFER_PRIMARY(pipe));
11265
11266 intel_fbc_disable(dev);
11267 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11268 mutex_unlock(&dev->struct_mutex);
11269
11270 trace_i915_flip_request(intel_crtc->plane, obj);
11271
11272 return 0;
11273
11274 cleanup_unpin:
11275 intel_unpin_fb_obj(fb, crtc->primary->state);
11276 cleanup_pending:
11277 atomic_dec(&intel_crtc->unpin_work_count);
11278 mutex_unlock(&dev->struct_mutex);
11279 cleanup:
11280 crtc->primary->fb = old_fb;
11281 update_state_fb(crtc->primary);
11282
11283 drm_gem_object_unreference_unlocked(&obj->base);
11284 drm_framebuffer_unreference(work->old_fb);
11285
11286 spin_lock_irq(&dev->event_lock);
11287 intel_crtc->unpin_work = NULL;
11288 spin_unlock_irq(&dev->event_lock);
11289
11290 drm_crtc_vblank_put(crtc);
11291 free_work:
11292 kfree(work);
11293
11294 if (ret == -EIO) {
11295 out_hang:
11296 ret = intel_plane_restore(primary);
11297 if (ret == 0 && event) {
11298 spin_lock_irq(&dev->event_lock);
11299 drm_send_vblank_event(dev, pipe, event);
11300 spin_unlock_irq(&dev->event_lock);
11301 }
11302 }
11303 return ret;
11304 }
11305
11306 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11307 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11308 .load_lut = intel_crtc_load_lut,
11309 .atomic_begin = intel_begin_crtc_commit,
11310 .atomic_flush = intel_finish_crtc_commit,
11311 };
11312
11313 /**
11314 * intel_modeset_update_staged_output_state
11315 *
11316 * Updates the staged output configuration state, e.g. after we've read out the
11317 * current hw state.
11318 */
11319 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11320 {
11321 struct intel_crtc *crtc;
11322 struct intel_encoder *encoder;
11323 struct intel_connector *connector;
11324
11325 for_each_intel_connector(dev, connector) {
11326 connector->new_encoder =
11327 to_intel_encoder(connector->base.encoder);
11328 }
11329
11330 for_each_intel_encoder(dev, encoder) {
11331 encoder->new_crtc =
11332 to_intel_crtc(encoder->base.crtc);
11333 }
11334
11335 for_each_intel_crtc(dev, crtc) {
11336 crtc->new_enabled = crtc->base.state->enable;
11337 }
11338 }
11339
11340 /* Transitional helper to copy current connector/encoder state to
11341 * connector->state. This is needed so that code that is partially
11342 * converted to atomic does the right thing.
11343 */
11344 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11345 {
11346 struct intel_connector *connector;
11347
11348 for_each_intel_connector(dev, connector) {
11349 if (connector->base.encoder) {
11350 connector->base.state->best_encoder =
11351 connector->base.encoder;
11352 connector->base.state->crtc =
11353 connector->base.encoder->crtc;
11354 } else {
11355 connector->base.state->best_encoder = NULL;
11356 connector->base.state->crtc = NULL;
11357 }
11358 }
11359 }
11360
11361 /* Fixup legacy state after an atomic state swap.
11362 */
11363 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11364 {
11365 struct intel_crtc *crtc;
11366 struct intel_encoder *encoder;
11367 struct intel_connector *connector;
11368
11369 for_each_intel_connector(state->dev, connector) {
11370 connector->base.encoder = connector->base.state->best_encoder;
11371 if (connector->base.encoder)
11372 connector->base.encoder->crtc =
11373 connector->base.state->crtc;
11374 }
11375
11376 /* Update crtc of disabled encoders */
11377 for_each_intel_encoder(state->dev, encoder) {
11378 int num_connectors = 0;
11379
11380 for_each_intel_connector(state->dev, connector)
11381 if (connector->base.encoder == &encoder->base)
11382 num_connectors++;
11383
11384 if (num_connectors == 0)
11385 encoder->base.crtc = NULL;
11386 }
11387
11388 for_each_intel_crtc(state->dev, crtc) {
11389 crtc->base.enabled = crtc->base.state->enable;
11390 crtc->config = to_intel_crtc_state(crtc->base.state);
11391 }
11392 }
11393
11394 static void
11395 connected_sink_compute_bpp(struct intel_connector *connector,
11396 struct intel_crtc_state *pipe_config)
11397 {
11398 int bpp = pipe_config->pipe_bpp;
11399
11400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11401 connector->base.base.id,
11402 connector->base.name);
11403
11404 /* Don't use an invalid EDID bpc value */
11405 if (connector->base.display_info.bpc &&
11406 connector->base.display_info.bpc * 3 < bpp) {
11407 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11408 bpp, connector->base.display_info.bpc*3);
11409 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11410 }
11411
11412 /* Clamp bpp to 8 on screens without EDID 1.4 */
11413 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11414 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11415 bpp);
11416 pipe_config->pipe_bpp = 24;
11417 }
11418 }
11419
11420 static int
11421 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11422 struct intel_crtc_state *pipe_config)
11423 {
11424 struct drm_device *dev = crtc->base.dev;
11425 struct drm_atomic_state *state;
11426 struct drm_connector *connector;
11427 struct drm_connector_state *connector_state;
11428 int bpp, i;
11429
11430 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11431 bpp = 10*3;
11432 else if (INTEL_INFO(dev)->gen >= 5)
11433 bpp = 12*3;
11434 else
11435 bpp = 8*3;
11436
11437
11438 pipe_config->pipe_bpp = bpp;
11439
11440 state = pipe_config->base.state;
11441
11442 /* Clamp display bpp to EDID value */
11443 for_each_connector_in_state(state, connector, connector_state, i) {
11444 if (connector_state->crtc != &crtc->base)
11445 continue;
11446
11447 connected_sink_compute_bpp(to_intel_connector(connector),
11448 pipe_config);
11449 }
11450
11451 return bpp;
11452 }
11453
11454 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11455 {
11456 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11457 "type: 0x%x flags: 0x%x\n",
11458 mode->crtc_clock,
11459 mode->crtc_hdisplay, mode->crtc_hsync_start,
11460 mode->crtc_hsync_end, mode->crtc_htotal,
11461 mode->crtc_vdisplay, mode->crtc_vsync_start,
11462 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11463 }
11464
11465 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11466 struct intel_crtc_state *pipe_config,
11467 const char *context)
11468 {
11469 struct drm_device *dev = crtc->base.dev;
11470 struct drm_plane *plane;
11471 struct intel_plane *intel_plane;
11472 struct intel_plane_state *state;
11473 struct drm_framebuffer *fb;
11474
11475 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11476 context, pipe_config, pipe_name(crtc->pipe));
11477
11478 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11479 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11480 pipe_config->pipe_bpp, pipe_config->dither);
11481 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11482 pipe_config->has_pch_encoder,
11483 pipe_config->fdi_lanes,
11484 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11485 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11486 pipe_config->fdi_m_n.tu);
11487 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11488 pipe_config->has_dp_encoder,
11489 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11490 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11491 pipe_config->dp_m_n.tu);
11492
11493 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11494 pipe_config->has_dp_encoder,
11495 pipe_config->dp_m2_n2.gmch_m,
11496 pipe_config->dp_m2_n2.gmch_n,
11497 pipe_config->dp_m2_n2.link_m,
11498 pipe_config->dp_m2_n2.link_n,
11499 pipe_config->dp_m2_n2.tu);
11500
11501 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11502 pipe_config->has_audio,
11503 pipe_config->has_infoframe);
11504
11505 DRM_DEBUG_KMS("requested mode:\n");
11506 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11507 DRM_DEBUG_KMS("adjusted mode:\n");
11508 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11509 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11510 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11511 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11512 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11513 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11514 crtc->num_scalers,
11515 pipe_config->scaler_state.scaler_users,
11516 pipe_config->scaler_state.scaler_id);
11517 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11518 pipe_config->gmch_pfit.control,
11519 pipe_config->gmch_pfit.pgm_ratios,
11520 pipe_config->gmch_pfit.lvds_border_bits);
11521 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11522 pipe_config->pch_pfit.pos,
11523 pipe_config->pch_pfit.size,
11524 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11525 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11526 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11527
11528 if (IS_BROXTON(dev)) {
11529 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11530 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11531 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11532 pipe_config->ddi_pll_sel,
11533 pipe_config->dpll_hw_state.ebb0,
11534 pipe_config->dpll_hw_state.pll0,
11535 pipe_config->dpll_hw_state.pll1,
11536 pipe_config->dpll_hw_state.pll2,
11537 pipe_config->dpll_hw_state.pll3,
11538 pipe_config->dpll_hw_state.pll6,
11539 pipe_config->dpll_hw_state.pll8,
11540 pipe_config->dpll_hw_state.pcsdw12);
11541 } else if (IS_SKYLAKE(dev)) {
11542 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11543 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11544 pipe_config->ddi_pll_sel,
11545 pipe_config->dpll_hw_state.ctrl1,
11546 pipe_config->dpll_hw_state.cfgcr1,
11547 pipe_config->dpll_hw_state.cfgcr2);
11548 } else if (HAS_DDI(dev)) {
11549 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11550 pipe_config->ddi_pll_sel,
11551 pipe_config->dpll_hw_state.wrpll);
11552 } else {
11553 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11554 "fp0: 0x%x, fp1: 0x%x\n",
11555 pipe_config->dpll_hw_state.dpll,
11556 pipe_config->dpll_hw_state.dpll_md,
11557 pipe_config->dpll_hw_state.fp0,
11558 pipe_config->dpll_hw_state.fp1);
11559 }
11560
11561 DRM_DEBUG_KMS("planes on this crtc\n");
11562 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11563 intel_plane = to_intel_plane(plane);
11564 if (intel_plane->pipe != crtc->pipe)
11565 continue;
11566
11567 state = to_intel_plane_state(plane->state);
11568 fb = state->base.fb;
11569 if (!fb) {
11570 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11571 "disabled, scaler_id = %d\n",
11572 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11573 plane->base.id, intel_plane->pipe,
11574 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11575 drm_plane_index(plane), state->scaler_id);
11576 continue;
11577 }
11578
11579 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11580 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11581 plane->base.id, intel_plane->pipe,
11582 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11583 drm_plane_index(plane));
11584 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11585 fb->base.id, fb->width, fb->height, fb->pixel_format);
11586 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11587 state->scaler_id,
11588 state->src.x1 >> 16, state->src.y1 >> 16,
11589 drm_rect_width(&state->src) >> 16,
11590 drm_rect_height(&state->src) >> 16,
11591 state->dst.x1, state->dst.y1,
11592 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11593 }
11594 }
11595
11596 static bool encoders_cloneable(const struct intel_encoder *a,
11597 const struct intel_encoder *b)
11598 {
11599 /* masks could be asymmetric, so check both ways */
11600 return a == b || (a->cloneable & (1 << b->type) &&
11601 b->cloneable & (1 << a->type));
11602 }
11603
11604 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11605 struct intel_crtc *crtc,
11606 struct intel_encoder *encoder)
11607 {
11608 struct intel_encoder *source_encoder;
11609 struct drm_connector *connector;
11610 struct drm_connector_state *connector_state;
11611 int i;
11612
11613 for_each_connector_in_state(state, connector, connector_state, i) {
11614 if (connector_state->crtc != &crtc->base)
11615 continue;
11616
11617 source_encoder =
11618 to_intel_encoder(connector_state->best_encoder);
11619 if (!encoders_cloneable(encoder, source_encoder))
11620 return false;
11621 }
11622
11623 return true;
11624 }
11625
11626 static bool check_encoder_cloning(struct drm_atomic_state *state,
11627 struct intel_crtc *crtc)
11628 {
11629 struct intel_encoder *encoder;
11630 struct drm_connector *connector;
11631 struct drm_connector_state *connector_state;
11632 int i;
11633
11634 for_each_connector_in_state(state, connector, connector_state, i) {
11635 if (connector_state->crtc != &crtc->base)
11636 continue;
11637
11638 encoder = to_intel_encoder(connector_state->best_encoder);
11639 if (!check_single_encoder_cloning(state, crtc, encoder))
11640 return false;
11641 }
11642
11643 return true;
11644 }
11645
11646 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11647 {
11648 struct drm_device *dev = state->dev;
11649 struct intel_encoder *encoder;
11650 struct drm_connector *connector;
11651 struct drm_connector_state *connector_state;
11652 unsigned int used_ports = 0;
11653 int i;
11654
11655 /*
11656 * Walk the connector list instead of the encoder
11657 * list to detect the problem on ddi platforms
11658 * where there's just one encoder per digital port.
11659 */
11660 for_each_connector_in_state(state, connector, connector_state, i) {
11661 if (!connector_state->best_encoder)
11662 continue;
11663
11664 encoder = to_intel_encoder(connector_state->best_encoder);
11665
11666 WARN_ON(!connector_state->crtc);
11667
11668 switch (encoder->type) {
11669 unsigned int port_mask;
11670 case INTEL_OUTPUT_UNKNOWN:
11671 if (WARN_ON(!HAS_DDI(dev)))
11672 break;
11673 case INTEL_OUTPUT_DISPLAYPORT:
11674 case INTEL_OUTPUT_HDMI:
11675 case INTEL_OUTPUT_EDP:
11676 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11677
11678 /* the same port mustn't appear more than once */
11679 if (used_ports & port_mask)
11680 return false;
11681
11682 used_ports |= port_mask;
11683 default:
11684 break;
11685 }
11686 }
11687
11688 return true;
11689 }
11690
11691 static void
11692 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11693 {
11694 struct drm_crtc_state tmp_state;
11695 struct intel_crtc_scaler_state scaler_state;
11696 struct intel_dpll_hw_state dpll_hw_state;
11697 enum intel_dpll_id shared_dpll;
11698 uint32_t ddi_pll_sel;
11699
11700 /* FIXME: before the switch to atomic started, a new pipe_config was
11701 * kzalloc'd. Code that depends on any field being zero should be
11702 * fixed, so that the crtc_state can be safely duplicated. For now,
11703 * only fields that are know to not cause problems are preserved. */
11704
11705 tmp_state = crtc_state->base;
11706 scaler_state = crtc_state->scaler_state;
11707 shared_dpll = crtc_state->shared_dpll;
11708 dpll_hw_state = crtc_state->dpll_hw_state;
11709 ddi_pll_sel = crtc_state->ddi_pll_sel;
11710
11711 memset(crtc_state, 0, sizeof *crtc_state);
11712
11713 crtc_state->base = tmp_state;
11714 crtc_state->scaler_state = scaler_state;
11715 crtc_state->shared_dpll = shared_dpll;
11716 crtc_state->dpll_hw_state = dpll_hw_state;
11717 crtc_state->ddi_pll_sel = ddi_pll_sel;
11718 }
11719
11720 static int
11721 intel_modeset_pipe_config(struct drm_crtc *crtc,
11722 struct drm_atomic_state *state,
11723 struct intel_crtc_state *pipe_config)
11724 {
11725 struct intel_encoder *encoder;
11726 struct drm_connector *connector;
11727 struct drm_connector_state *connector_state;
11728 int base_bpp, ret = -EINVAL;
11729 int i;
11730 bool retry = true;
11731
11732 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11733 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11734 return -EINVAL;
11735 }
11736
11737 if (!check_digital_port_conflicts(state)) {
11738 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11739 return -EINVAL;
11740 }
11741
11742 clear_intel_crtc_state(pipe_config);
11743
11744 pipe_config->cpu_transcoder =
11745 (enum transcoder) to_intel_crtc(crtc)->pipe;
11746
11747 /*
11748 * Sanitize sync polarity flags based on requested ones. If neither
11749 * positive or negative polarity is requested, treat this as meaning
11750 * negative polarity.
11751 */
11752 if (!(pipe_config->base.adjusted_mode.flags &
11753 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11754 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11755
11756 if (!(pipe_config->base.adjusted_mode.flags &
11757 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11758 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11759
11760 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11761 * plane pixel format and any sink constraints into account. Returns the
11762 * source plane bpp so that dithering can be selected on mismatches
11763 * after encoders and crtc also have had their say. */
11764 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11765 pipe_config);
11766 if (base_bpp < 0)
11767 goto fail;
11768
11769 /*
11770 * Determine the real pipe dimensions. Note that stereo modes can
11771 * increase the actual pipe size due to the frame doubling and
11772 * insertion of additional space for blanks between the frame. This
11773 * is stored in the crtc timings. We use the requested mode to do this
11774 * computation to clearly distinguish it from the adjusted mode, which
11775 * can be changed by the connectors in the below retry loop.
11776 */
11777 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11778 &pipe_config->pipe_src_w,
11779 &pipe_config->pipe_src_h);
11780
11781 encoder_retry:
11782 /* Ensure the port clock defaults are reset when retrying. */
11783 pipe_config->port_clock = 0;
11784 pipe_config->pixel_multiplier = 1;
11785
11786 /* Fill in default crtc timings, allow encoders to overwrite them. */
11787 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11788 CRTC_STEREO_DOUBLE);
11789
11790 /* Pass our mode to the connectors and the CRTC to give them a chance to
11791 * adjust it according to limitations or connector properties, and also
11792 * a chance to reject the mode entirely.
11793 */
11794 for_each_connector_in_state(state, connector, connector_state, i) {
11795 if (connector_state->crtc != crtc)
11796 continue;
11797
11798 encoder = to_intel_encoder(connector_state->best_encoder);
11799
11800 if (!(encoder->compute_config(encoder, pipe_config))) {
11801 DRM_DEBUG_KMS("Encoder config failure\n");
11802 goto fail;
11803 }
11804 }
11805
11806 /* Set default port clock if not overwritten by the encoder. Needs to be
11807 * done afterwards in case the encoder adjusts the mode. */
11808 if (!pipe_config->port_clock)
11809 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11810 * pipe_config->pixel_multiplier;
11811
11812 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11813 if (ret < 0) {
11814 DRM_DEBUG_KMS("CRTC fixup failed\n");
11815 goto fail;
11816 }
11817
11818 if (ret == RETRY) {
11819 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11820 ret = -EINVAL;
11821 goto fail;
11822 }
11823
11824 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11825 retry = false;
11826 goto encoder_retry;
11827 }
11828
11829 /* Dithering seems to not pass-through bits correctly when it should, so
11830 * only enable it on 6bpc panels. */
11831 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
11832 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11833 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11834
11835 return 0;
11836 fail:
11837 return ret;
11838 }
11839
11840 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11841 {
11842 struct drm_encoder *encoder;
11843 struct drm_device *dev = crtc->dev;
11844
11845 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11846 if (encoder->crtc == crtc)
11847 return true;
11848
11849 return false;
11850 }
11851
11852 static bool
11853 needs_modeset(struct drm_crtc_state *state)
11854 {
11855 return state->mode_changed || state->active_changed;
11856 }
11857
11858 static void
11859 intel_modeset_update_state(struct drm_atomic_state *state)
11860 {
11861 struct drm_device *dev = state->dev;
11862 struct drm_i915_private *dev_priv = dev->dev_private;
11863 struct intel_encoder *intel_encoder;
11864 struct drm_crtc *crtc;
11865 struct drm_crtc_state *crtc_state;
11866 struct drm_connector *connector;
11867 int i;
11868
11869 intel_shared_dpll_commit(dev_priv);
11870
11871 for_each_intel_encoder(dev, intel_encoder) {
11872 if (!intel_encoder->base.crtc)
11873 continue;
11874
11875 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11876 if (crtc != intel_encoder->base.crtc)
11877 continue;
11878
11879 if (crtc_state->enable && needs_modeset(crtc_state))
11880 intel_encoder->connectors_active = false;
11881
11882 break;
11883 }
11884 }
11885
11886 drm_atomic_helper_swap_state(state->dev, state);
11887 intel_modeset_fixup_state(state);
11888
11889 /* Double check state. */
11890 for_each_crtc(dev, crtc) {
11891 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11892 }
11893
11894 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11895 if (!connector->encoder || !connector->encoder->crtc)
11896 continue;
11897
11898 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11899 if (crtc != connector->encoder->crtc)
11900 continue;
11901
11902 if (crtc->state->enable && needs_modeset(crtc->state)) {
11903 struct drm_property *dpms_property =
11904 dev->mode_config.dpms_property;
11905
11906 connector->dpms = DRM_MODE_DPMS_ON;
11907 drm_object_property_set_value(&connector->base,
11908 dpms_property,
11909 DRM_MODE_DPMS_ON);
11910
11911 intel_encoder = to_intel_encoder(connector->encoder);
11912 intel_encoder->connectors_active = true;
11913 }
11914
11915 break;
11916 }
11917 }
11918
11919 }
11920
11921 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11922 {
11923 int diff;
11924
11925 if (clock1 == clock2)
11926 return true;
11927
11928 if (!clock1 || !clock2)
11929 return false;
11930
11931 diff = abs(clock1 - clock2);
11932
11933 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11934 return true;
11935
11936 return false;
11937 }
11938
11939 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11940 list_for_each_entry((intel_crtc), \
11941 &(dev)->mode_config.crtc_list, \
11942 base.head) \
11943 if (mask & (1 <<(intel_crtc)->pipe))
11944
11945 static bool
11946 intel_pipe_config_compare(struct drm_device *dev,
11947 struct intel_crtc_state *current_config,
11948 struct intel_crtc_state *pipe_config)
11949 {
11950 #define PIPE_CONF_CHECK_X(name) \
11951 if (current_config->name != pipe_config->name) { \
11952 DRM_ERROR("mismatch in " #name " " \
11953 "(expected 0x%08x, found 0x%08x)\n", \
11954 current_config->name, \
11955 pipe_config->name); \
11956 return false; \
11957 }
11958
11959 #define PIPE_CONF_CHECK_I(name) \
11960 if (current_config->name != pipe_config->name) { \
11961 DRM_ERROR("mismatch in " #name " " \
11962 "(expected %i, found %i)\n", \
11963 current_config->name, \
11964 pipe_config->name); \
11965 return false; \
11966 }
11967
11968 /* This is required for BDW+ where there is only one set of registers for
11969 * switching between high and low RR.
11970 * This macro can be used whenever a comparison has to be made between one
11971 * hw state and multiple sw state variables.
11972 */
11973 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11974 if ((current_config->name != pipe_config->name) && \
11975 (current_config->alt_name != pipe_config->name)) { \
11976 DRM_ERROR("mismatch in " #name " " \
11977 "(expected %i or %i, found %i)\n", \
11978 current_config->name, \
11979 current_config->alt_name, \
11980 pipe_config->name); \
11981 return false; \
11982 }
11983
11984 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11985 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11986 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11987 "(expected %i, found %i)\n", \
11988 current_config->name & (mask), \
11989 pipe_config->name & (mask)); \
11990 return false; \
11991 }
11992
11993 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11994 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11995 DRM_ERROR("mismatch in " #name " " \
11996 "(expected %i, found %i)\n", \
11997 current_config->name, \
11998 pipe_config->name); \
11999 return false; \
12000 }
12001
12002 #define PIPE_CONF_QUIRK(quirk) \
12003 ((current_config->quirks | pipe_config->quirks) & (quirk))
12004
12005 PIPE_CONF_CHECK_I(cpu_transcoder);
12006
12007 PIPE_CONF_CHECK_I(has_pch_encoder);
12008 PIPE_CONF_CHECK_I(fdi_lanes);
12009 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12010 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12011 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12012 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12013 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12014
12015 PIPE_CONF_CHECK_I(has_dp_encoder);
12016
12017 if (INTEL_INFO(dev)->gen < 8) {
12018 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12019 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12020 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12021 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12022 PIPE_CONF_CHECK_I(dp_m_n.tu);
12023
12024 if (current_config->has_drrs) {
12025 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12026 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12027 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12028 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12029 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12030 }
12031 } else {
12032 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12033 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12034 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12035 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12036 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12037 }
12038
12039 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12040 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12042 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12043 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12044 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12045
12046 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12047 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12048 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12049 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12050 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12051 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12052
12053 PIPE_CONF_CHECK_I(pixel_multiplier);
12054 PIPE_CONF_CHECK_I(has_hdmi_sink);
12055 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12056 IS_VALLEYVIEW(dev))
12057 PIPE_CONF_CHECK_I(limited_color_range);
12058 PIPE_CONF_CHECK_I(has_infoframe);
12059
12060 PIPE_CONF_CHECK_I(has_audio);
12061
12062 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12063 DRM_MODE_FLAG_INTERLACE);
12064
12065 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12066 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12067 DRM_MODE_FLAG_PHSYNC);
12068 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12069 DRM_MODE_FLAG_NHSYNC);
12070 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12071 DRM_MODE_FLAG_PVSYNC);
12072 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12073 DRM_MODE_FLAG_NVSYNC);
12074 }
12075
12076 PIPE_CONF_CHECK_I(pipe_src_w);
12077 PIPE_CONF_CHECK_I(pipe_src_h);
12078
12079 /*
12080 * FIXME: BIOS likes to set up a cloned config with lvds+external
12081 * screen. Since we don't yet re-compute the pipe config when moving
12082 * just the lvds port away to another pipe the sw tracking won't match.
12083 *
12084 * Proper atomic modesets with recomputed global state will fix this.
12085 * Until then just don't check gmch state for inherited modes.
12086 */
12087 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12088 PIPE_CONF_CHECK_I(gmch_pfit.control);
12089 /* pfit ratios are autocomputed by the hw on gen4+ */
12090 if (INTEL_INFO(dev)->gen < 4)
12091 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12092 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12093 }
12094
12095 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12096 if (current_config->pch_pfit.enabled) {
12097 PIPE_CONF_CHECK_I(pch_pfit.pos);
12098 PIPE_CONF_CHECK_I(pch_pfit.size);
12099 }
12100
12101 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12102
12103 /* BDW+ don't expose a synchronous way to read the state */
12104 if (IS_HASWELL(dev))
12105 PIPE_CONF_CHECK_I(ips_enabled);
12106
12107 PIPE_CONF_CHECK_I(double_wide);
12108
12109 PIPE_CONF_CHECK_X(ddi_pll_sel);
12110
12111 PIPE_CONF_CHECK_I(shared_dpll);
12112 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12113 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12114 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12115 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12116 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12117 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12118 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12119 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12120
12121 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12122 PIPE_CONF_CHECK_I(pipe_bpp);
12123
12124 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12125 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12126
12127 #undef PIPE_CONF_CHECK_X
12128 #undef PIPE_CONF_CHECK_I
12129 #undef PIPE_CONF_CHECK_I_ALT
12130 #undef PIPE_CONF_CHECK_FLAGS
12131 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12132 #undef PIPE_CONF_QUIRK
12133
12134 return true;
12135 }
12136
12137 static void check_wm_state(struct drm_device *dev)
12138 {
12139 struct drm_i915_private *dev_priv = dev->dev_private;
12140 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12141 struct intel_crtc *intel_crtc;
12142 int plane;
12143
12144 if (INTEL_INFO(dev)->gen < 9)
12145 return;
12146
12147 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12148 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12149
12150 for_each_intel_crtc(dev, intel_crtc) {
12151 struct skl_ddb_entry *hw_entry, *sw_entry;
12152 const enum pipe pipe = intel_crtc->pipe;
12153
12154 if (!intel_crtc->active)
12155 continue;
12156
12157 /* planes */
12158 for_each_plane(dev_priv, pipe, plane) {
12159 hw_entry = &hw_ddb.plane[pipe][plane];
12160 sw_entry = &sw_ddb->plane[pipe][plane];
12161
12162 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12163 continue;
12164
12165 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12166 "(expected (%u,%u), found (%u,%u))\n",
12167 pipe_name(pipe), plane + 1,
12168 sw_entry->start, sw_entry->end,
12169 hw_entry->start, hw_entry->end);
12170 }
12171
12172 /* cursor */
12173 hw_entry = &hw_ddb.cursor[pipe];
12174 sw_entry = &sw_ddb->cursor[pipe];
12175
12176 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12177 continue;
12178
12179 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12180 "(expected (%u,%u), found (%u,%u))\n",
12181 pipe_name(pipe),
12182 sw_entry->start, sw_entry->end,
12183 hw_entry->start, hw_entry->end);
12184 }
12185 }
12186
12187 static void
12188 check_connector_state(struct drm_device *dev)
12189 {
12190 struct intel_connector *connector;
12191
12192 for_each_intel_connector(dev, connector) {
12193 /* This also checks the encoder/connector hw state with the
12194 * ->get_hw_state callbacks. */
12195 intel_connector_check_state(connector);
12196
12197 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12198 "connector's staged encoder doesn't match current encoder\n");
12199 }
12200 }
12201
12202 static void
12203 check_encoder_state(struct drm_device *dev)
12204 {
12205 struct intel_encoder *encoder;
12206 struct intel_connector *connector;
12207
12208 for_each_intel_encoder(dev, encoder) {
12209 bool enabled = false;
12210 bool active = false;
12211 enum pipe pipe, tracked_pipe;
12212
12213 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12214 encoder->base.base.id,
12215 encoder->base.name);
12216
12217 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12218 "encoder's stage crtc doesn't match current crtc\n");
12219 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12220 "encoder's active_connectors set, but no crtc\n");
12221
12222 for_each_intel_connector(dev, connector) {
12223 if (connector->base.encoder != &encoder->base)
12224 continue;
12225 enabled = true;
12226 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12227 active = true;
12228 }
12229 /*
12230 * for MST connectors if we unplug the connector is gone
12231 * away but the encoder is still connected to a crtc
12232 * until a modeset happens in response to the hotplug.
12233 */
12234 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12235 continue;
12236
12237 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12238 "encoder's enabled state mismatch "
12239 "(expected %i, found %i)\n",
12240 !!encoder->base.crtc, enabled);
12241 I915_STATE_WARN(active && !encoder->base.crtc,
12242 "active encoder with no crtc\n");
12243
12244 I915_STATE_WARN(encoder->connectors_active != active,
12245 "encoder's computed active state doesn't match tracked active state "
12246 "(expected %i, found %i)\n", active, encoder->connectors_active);
12247
12248 active = encoder->get_hw_state(encoder, &pipe);
12249 I915_STATE_WARN(active != encoder->connectors_active,
12250 "encoder's hw state doesn't match sw tracking "
12251 "(expected %i, found %i)\n",
12252 encoder->connectors_active, active);
12253
12254 if (!encoder->base.crtc)
12255 continue;
12256
12257 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12258 I915_STATE_WARN(active && pipe != tracked_pipe,
12259 "active encoder's pipe doesn't match"
12260 "(expected %i, found %i)\n",
12261 tracked_pipe, pipe);
12262
12263 }
12264 }
12265
12266 static void
12267 check_crtc_state(struct drm_device *dev)
12268 {
12269 struct drm_i915_private *dev_priv = dev->dev_private;
12270 struct intel_crtc *crtc;
12271 struct intel_encoder *encoder;
12272 struct intel_crtc_state pipe_config;
12273
12274 for_each_intel_crtc(dev, crtc) {
12275 bool enabled = false;
12276 bool active = false;
12277
12278 memset(&pipe_config, 0, sizeof(pipe_config));
12279
12280 DRM_DEBUG_KMS("[CRTC:%d]\n",
12281 crtc->base.base.id);
12282
12283 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12284 "active crtc, but not enabled in sw tracking\n");
12285
12286 for_each_intel_encoder(dev, encoder) {
12287 if (encoder->base.crtc != &crtc->base)
12288 continue;
12289 enabled = true;
12290 if (encoder->connectors_active)
12291 active = true;
12292 }
12293
12294 I915_STATE_WARN(active != crtc->active,
12295 "crtc's computed active state doesn't match tracked active state "
12296 "(expected %i, found %i)\n", active, crtc->active);
12297 I915_STATE_WARN(enabled != crtc->base.state->enable,
12298 "crtc's computed enabled state doesn't match tracked enabled state "
12299 "(expected %i, found %i)\n", enabled,
12300 crtc->base.state->enable);
12301
12302 active = dev_priv->display.get_pipe_config(crtc,
12303 &pipe_config);
12304
12305 /* hw state is inconsistent with the pipe quirk */
12306 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12307 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12308 active = crtc->active;
12309
12310 for_each_intel_encoder(dev, encoder) {
12311 enum pipe pipe;
12312 if (encoder->base.crtc != &crtc->base)
12313 continue;
12314 if (encoder->get_hw_state(encoder, &pipe))
12315 encoder->get_config(encoder, &pipe_config);
12316 }
12317
12318 I915_STATE_WARN(crtc->active != active,
12319 "crtc active state doesn't match with hw state "
12320 "(expected %i, found %i)\n", crtc->active, active);
12321
12322 if (active &&
12323 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12324 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12325 intel_dump_pipe_config(crtc, &pipe_config,
12326 "[hw state]");
12327 intel_dump_pipe_config(crtc, crtc->config,
12328 "[sw state]");
12329 }
12330 }
12331 }
12332
12333 static void
12334 check_shared_dpll_state(struct drm_device *dev)
12335 {
12336 struct drm_i915_private *dev_priv = dev->dev_private;
12337 struct intel_crtc *crtc;
12338 struct intel_dpll_hw_state dpll_hw_state;
12339 int i;
12340
12341 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12342 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12343 int enabled_crtcs = 0, active_crtcs = 0;
12344 bool active;
12345
12346 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12347
12348 DRM_DEBUG_KMS("%s\n", pll->name);
12349
12350 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12351
12352 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12353 "more active pll users than references: %i vs %i\n",
12354 pll->active, hweight32(pll->config.crtc_mask));
12355 I915_STATE_WARN(pll->active && !pll->on,
12356 "pll in active use but not on in sw tracking\n");
12357 I915_STATE_WARN(pll->on && !pll->active,
12358 "pll in on but not on in use in sw tracking\n");
12359 I915_STATE_WARN(pll->on != active,
12360 "pll on state mismatch (expected %i, found %i)\n",
12361 pll->on, active);
12362
12363 for_each_intel_crtc(dev, crtc) {
12364 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12365 enabled_crtcs++;
12366 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12367 active_crtcs++;
12368 }
12369 I915_STATE_WARN(pll->active != active_crtcs,
12370 "pll active crtcs mismatch (expected %i, found %i)\n",
12371 pll->active, active_crtcs);
12372 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12373 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12374 hweight32(pll->config.crtc_mask), enabled_crtcs);
12375
12376 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12377 sizeof(dpll_hw_state)),
12378 "pll hw state mismatch\n");
12379 }
12380 }
12381
12382 void
12383 intel_modeset_check_state(struct drm_device *dev)
12384 {
12385 check_wm_state(dev);
12386 check_connector_state(dev);
12387 check_encoder_state(dev);
12388 check_crtc_state(dev);
12389 check_shared_dpll_state(dev);
12390 }
12391
12392 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12393 int dotclock)
12394 {
12395 /*
12396 * FDI already provided one idea for the dotclock.
12397 * Yell if the encoder disagrees.
12398 */
12399 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12400 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12401 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12402 }
12403
12404 static void update_scanline_offset(struct intel_crtc *crtc)
12405 {
12406 struct drm_device *dev = crtc->base.dev;
12407
12408 /*
12409 * The scanline counter increments at the leading edge of hsync.
12410 *
12411 * On most platforms it starts counting from vtotal-1 on the
12412 * first active line. That means the scanline counter value is
12413 * always one less than what we would expect. Ie. just after
12414 * start of vblank, which also occurs at start of hsync (on the
12415 * last active line), the scanline counter will read vblank_start-1.
12416 *
12417 * On gen2 the scanline counter starts counting from 1 instead
12418 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12419 * to keep the value positive), instead of adding one.
12420 *
12421 * On HSW+ the behaviour of the scanline counter depends on the output
12422 * type. For DP ports it behaves like most other platforms, but on HDMI
12423 * there's an extra 1 line difference. So we need to add two instead of
12424 * one to the value.
12425 */
12426 if (IS_GEN2(dev)) {
12427 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12428 int vtotal;
12429
12430 vtotal = mode->crtc_vtotal;
12431 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12432 vtotal /= 2;
12433
12434 crtc->scanline_offset = vtotal - 1;
12435 } else if (HAS_DDI(dev) &&
12436 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12437 crtc->scanline_offset = 2;
12438 } else
12439 crtc->scanline_offset = 1;
12440 }
12441
12442 static struct intel_crtc_state *
12443 intel_modeset_compute_config(struct drm_crtc *crtc,
12444 struct drm_atomic_state *state)
12445 {
12446 struct intel_crtc_state *pipe_config;
12447 int ret = 0;
12448
12449 ret = drm_atomic_add_affected_connectors(state, crtc);
12450 if (ret)
12451 return ERR_PTR(ret);
12452
12453 ret = drm_atomic_helper_check_modeset(state->dev, state);
12454 if (ret)
12455 return ERR_PTR(ret);
12456
12457 /*
12458 * Note this needs changes when we start tracking multiple modes
12459 * and crtcs. At that point we'll need to compute the whole config
12460 * (i.e. one pipe_config for each crtc) rather than just the one
12461 * for this crtc.
12462 */
12463 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12464 if (IS_ERR(pipe_config))
12465 return pipe_config;
12466
12467 if (!pipe_config->base.enable)
12468 return pipe_config;
12469
12470 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12471 if (ret)
12472 return ERR_PTR(ret);
12473
12474 /* Check things that can only be changed through modeset */
12475 if (pipe_config->has_audio !=
12476 to_intel_crtc(crtc)->config->has_audio)
12477 pipe_config->base.mode_changed = true;
12478
12479 /*
12480 * Note we have an issue here with infoframes: current code
12481 * only updates them on the full mode set path per hw
12482 * requirements. So here we should be checking for any
12483 * required changes and forcing a mode set.
12484 */
12485
12486 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12487
12488 ret = drm_atomic_helper_check_planes(state->dev, state);
12489 if (ret)
12490 return ERR_PTR(ret);
12491
12492 return pipe_config;
12493 }
12494
12495 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12496 {
12497 struct drm_device *dev = state->dev;
12498 struct drm_i915_private *dev_priv = to_i915(dev);
12499 unsigned clear_pipes = 0;
12500 struct intel_crtc *intel_crtc;
12501 struct intel_crtc_state *intel_crtc_state;
12502 struct drm_crtc *crtc;
12503 struct drm_crtc_state *crtc_state;
12504 int ret = 0;
12505 int i;
12506
12507 if (!dev_priv->display.crtc_compute_clock)
12508 return 0;
12509
12510 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12511 intel_crtc = to_intel_crtc(crtc);
12512 intel_crtc_state = to_intel_crtc_state(crtc_state);
12513
12514 if (needs_modeset(crtc_state)) {
12515 clear_pipes |= 1 << intel_crtc->pipe;
12516 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12517 }
12518 }
12519
12520 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12521 if (ret)
12522 goto done;
12523
12524 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12525 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12526 continue;
12527
12528 intel_crtc = to_intel_crtc(crtc);
12529 intel_crtc_state = to_intel_crtc_state(crtc_state);
12530
12531 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12532 intel_crtc_state);
12533 if (ret) {
12534 intel_shared_dpll_abort_config(dev_priv);
12535 goto done;
12536 }
12537 }
12538
12539 done:
12540 return ret;
12541 }
12542
12543 /* Code that should eventually be part of atomic_check() */
12544 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12545 {
12546 struct drm_device *dev = state->dev;
12547 int ret;
12548
12549 /*
12550 * See if the config requires any additional preparation, e.g.
12551 * to adjust global state with pipes off. We need to do this
12552 * here so we can get the modeset_pipe updated config for the new
12553 * mode set on this crtc. For other crtcs we need to use the
12554 * adjusted_mode bits in the crtc directly.
12555 */
12556 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12557 ret = valleyview_modeset_global_pipes(state);
12558 if (ret)
12559 return ret;
12560 }
12561
12562 ret = __intel_set_mode_setup_plls(state);
12563 if (ret)
12564 return ret;
12565
12566 return 0;
12567 }
12568
12569 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12570 struct intel_crtc_state *pipe_config)
12571 {
12572 struct drm_device *dev = modeset_crtc->dev;
12573 struct drm_i915_private *dev_priv = dev->dev_private;
12574 struct drm_atomic_state *state = pipe_config->base.state;
12575 struct drm_crtc *crtc;
12576 struct drm_crtc_state *crtc_state;
12577 int ret = 0;
12578 int i;
12579
12580 ret = __intel_set_mode_checks(state);
12581 if (ret < 0)
12582 return ret;
12583
12584 ret = drm_atomic_helper_prepare_planes(dev, state);
12585 if (ret)
12586 return ret;
12587
12588 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12589 if (!needs_modeset(crtc_state))
12590 continue;
12591
12592 if (!crtc_state->enable) {
12593 if (crtc->state->enable)
12594 intel_crtc_disable(crtc);
12595 } else if (crtc->state->enable) {
12596 intel_crtc_disable_planes(crtc);
12597 dev_priv->display.crtc_disable(crtc);
12598 }
12599 }
12600
12601 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12602 * to set it here already despite that we pass it down the callchain.
12603 *
12604 * Note we'll need to fix this up when we start tracking multiple
12605 * pipes; here we assume a single modeset_pipe and only track the
12606 * single crtc and mode.
12607 */
12608 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12609 modeset_crtc->mode = pipe_config->base.mode;
12610
12611 /*
12612 * Calculate and store various constants which
12613 * are later needed by vblank and swap-completion
12614 * timestamping. They are derived from true hwmode.
12615 */
12616 drm_calc_timestamping_constants(modeset_crtc,
12617 &pipe_config->base.adjusted_mode);
12618 }
12619
12620 /* Only after disabling all output pipelines that will be changed can we
12621 * update the the output configuration. */
12622 intel_modeset_update_state(state);
12623
12624 /* The state has been swaped above, so state actually contains the
12625 * old state now. */
12626
12627 modeset_update_crtc_power_domains(state);
12628
12629 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12630 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12631 if (!needs_modeset(crtc->state) || !crtc->state->enable) {
12632 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
12633 continue;
12634 }
12635
12636 update_scanline_offset(to_intel_crtc(crtc));
12637
12638 dev_priv->display.crtc_enable(crtc);
12639 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
12640 }
12641
12642 /* FIXME: add subpixel order */
12643
12644 drm_atomic_helper_cleanup_planes(dev, state);
12645
12646 drm_atomic_state_free(state);
12647
12648 return 0;
12649 }
12650
12651 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12652 struct intel_crtc_state *pipe_config,
12653 bool force_restore)
12654 {
12655 int ret;
12656
12657 ret = __intel_set_mode(crtc, pipe_config);
12658
12659 if (ret == 0 && force_restore) {
12660 intel_modeset_update_staged_output_state(crtc->dev);
12661 intel_modeset_check_state(crtc->dev);
12662 }
12663
12664 return ret;
12665 }
12666
12667 static int intel_set_mode(struct drm_crtc *crtc,
12668 struct drm_atomic_state *state,
12669 bool force_restore)
12670 {
12671 struct intel_crtc_state *pipe_config;
12672 int ret = 0;
12673
12674 pipe_config = intel_modeset_compute_config(crtc, state);
12675 if (IS_ERR(pipe_config)) {
12676 ret = PTR_ERR(pipe_config);
12677 goto out;
12678 }
12679
12680 ret = intel_set_mode_with_config(crtc, pipe_config, force_restore);
12681 if (ret)
12682 goto out;
12683
12684 out:
12685 return ret;
12686 }
12687
12688 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12689 {
12690 struct drm_device *dev = crtc->dev;
12691 struct drm_atomic_state *state;
12692 struct intel_encoder *encoder;
12693 struct intel_connector *connector;
12694 struct drm_connector_state *connector_state;
12695 struct intel_crtc_state *crtc_state;
12696 int ret;
12697
12698 state = drm_atomic_state_alloc(dev);
12699 if (!state) {
12700 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12701 crtc->base.id);
12702 return;
12703 }
12704
12705 state->acquire_ctx = dev->mode_config.acquire_ctx;
12706
12707 /* The force restore path in the HW readout code relies on the staged
12708 * config still keeping the user requested config while the actual
12709 * state has been overwritten by the configuration read from HW. We
12710 * need to copy the staged config to the atomic state, otherwise the
12711 * mode set will just reapply the state the HW is already in. */
12712 for_each_intel_encoder(dev, encoder) {
12713 if (&encoder->new_crtc->base != crtc)
12714 continue;
12715
12716 for_each_intel_connector(dev, connector) {
12717 if (connector->new_encoder != encoder)
12718 continue;
12719
12720 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12721 if (IS_ERR(connector_state)) {
12722 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12723 connector->base.base.id,
12724 connector->base.name,
12725 PTR_ERR(connector_state));
12726 continue;
12727 }
12728
12729 connector_state->crtc = crtc;
12730 connector_state->best_encoder = &encoder->base;
12731 }
12732 }
12733
12734 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12735 if (IS_ERR(crtc_state)) {
12736 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12737 crtc->base.id, PTR_ERR(crtc_state));
12738 drm_atomic_state_free(state);
12739 return;
12740 }
12741
12742 crtc_state->base.active = crtc_state->base.enable =
12743 to_intel_crtc(crtc)->new_enabled;
12744
12745 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12746
12747 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12748 crtc->primary->fb, crtc->x, crtc->y);
12749
12750 ret = intel_set_mode(crtc, state, false);
12751 if (ret)
12752 drm_atomic_state_free(state);
12753 }
12754
12755 #undef for_each_intel_crtc_masked
12756
12757 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12758 struct drm_mode_set *set)
12759 {
12760 int ro;
12761
12762 for (ro = 0; ro < set->num_connectors; ro++)
12763 if (set->connectors[ro] == &connector->base)
12764 return true;
12765
12766 return false;
12767 }
12768
12769 static int
12770 intel_modeset_stage_output_state(struct drm_device *dev,
12771 struct drm_mode_set *set,
12772 struct drm_atomic_state *state)
12773 {
12774 struct intel_connector *connector;
12775 struct drm_connector *drm_connector;
12776 struct drm_connector_state *connector_state;
12777 struct drm_crtc *crtc;
12778 struct drm_crtc_state *crtc_state;
12779 int i, ret;
12780
12781 /* The upper layers ensure that we either disable a crtc or have a list
12782 * of connectors. For paranoia, double-check this. */
12783 WARN_ON(!set->fb && (set->num_connectors != 0));
12784 WARN_ON(set->fb && (set->num_connectors == 0));
12785
12786 for_each_intel_connector(dev, connector) {
12787 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12788
12789 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12790 continue;
12791
12792 connector_state =
12793 drm_atomic_get_connector_state(state, &connector->base);
12794 if (IS_ERR(connector_state))
12795 return PTR_ERR(connector_state);
12796
12797 if (in_mode_set) {
12798 int pipe = to_intel_crtc(set->crtc)->pipe;
12799 connector_state->best_encoder =
12800 &intel_find_encoder(connector, pipe)->base;
12801 }
12802
12803 if (connector->base.state->crtc != set->crtc)
12804 continue;
12805
12806 /* If we disable the crtc, disable all its connectors. Also, if
12807 * the connector is on the changing crtc but not on the new
12808 * connector list, disable it. */
12809 if (!set->fb || !in_mode_set) {
12810 connector_state->best_encoder = NULL;
12811
12812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12813 connector->base.base.id,
12814 connector->base.name);
12815 }
12816 }
12817 /* connector->new_encoder is now updated for all connectors. */
12818
12819 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12820 connector = to_intel_connector(drm_connector);
12821
12822 if (!connector_state->best_encoder) {
12823 ret = drm_atomic_set_crtc_for_connector(connector_state,
12824 NULL);
12825 if (ret)
12826 return ret;
12827
12828 continue;
12829 }
12830
12831 if (intel_connector_in_mode_set(connector, set)) {
12832 struct drm_crtc *crtc = connector->base.state->crtc;
12833
12834 /* If this connector was in a previous crtc, add it
12835 * to the state. We might need to disable it. */
12836 if (crtc) {
12837 crtc_state =
12838 drm_atomic_get_crtc_state(state, crtc);
12839 if (IS_ERR(crtc_state))
12840 return PTR_ERR(crtc_state);
12841 }
12842
12843 ret = drm_atomic_set_crtc_for_connector(connector_state,
12844 set->crtc);
12845 if (ret)
12846 return ret;
12847 }
12848
12849 /* Make sure the new CRTC will work with the encoder */
12850 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12851 connector_state->crtc)) {
12852 return -EINVAL;
12853 }
12854
12855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12856 connector->base.base.id,
12857 connector->base.name,
12858 connector_state->crtc->base.id);
12859
12860 if (connector_state->best_encoder != &connector->encoder->base)
12861 connector->encoder =
12862 to_intel_encoder(connector_state->best_encoder);
12863 }
12864
12865 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12866 bool has_connectors;
12867
12868 ret = drm_atomic_add_affected_connectors(state, crtc);
12869 if (ret)
12870 return ret;
12871
12872 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12873 if (has_connectors != crtc_state->enable)
12874 crtc_state->enable =
12875 crtc_state->active = has_connectors;
12876 }
12877
12878 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12879 set->fb, set->x, set->y);
12880 if (ret)
12881 return ret;
12882
12883 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12884 if (IS_ERR(crtc_state))
12885 return PTR_ERR(crtc_state);
12886
12887 if (set->mode)
12888 drm_mode_copy(&crtc_state->mode, set->mode);
12889
12890 if (set->num_connectors)
12891 crtc_state->active = true;
12892
12893 return 0;
12894 }
12895
12896 static int intel_crtc_set_config(struct drm_mode_set *set)
12897 {
12898 struct drm_device *dev;
12899 struct drm_atomic_state *state = NULL;
12900 struct intel_crtc_state *pipe_config;
12901 int ret;
12902
12903 BUG_ON(!set);
12904 BUG_ON(!set->crtc);
12905 BUG_ON(!set->crtc->helper_private);
12906
12907 /* Enforce sane interface api - has been abused by the fb helper. */
12908 BUG_ON(!set->mode && set->fb);
12909 BUG_ON(set->fb && set->num_connectors == 0);
12910
12911 if (set->fb) {
12912 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12913 set->crtc->base.id, set->fb->base.id,
12914 (int)set->num_connectors, set->x, set->y);
12915 } else {
12916 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12917 }
12918
12919 dev = set->crtc->dev;
12920
12921 state = drm_atomic_state_alloc(dev);
12922 if (!state)
12923 return -ENOMEM;
12924
12925 state->acquire_ctx = dev->mode_config.acquire_ctx;
12926
12927 ret = intel_modeset_stage_output_state(dev, set, state);
12928 if (ret)
12929 goto out;
12930
12931 pipe_config = intel_modeset_compute_config(set->crtc, state);
12932 if (IS_ERR(pipe_config)) {
12933 ret = PTR_ERR(pipe_config);
12934 goto out;
12935 }
12936
12937 intel_update_pipe_size(to_intel_crtc(set->crtc));
12938
12939 ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
12940
12941 if (ret) {
12942 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12943 set->crtc->base.id, ret);
12944 }
12945
12946 out:
12947 if (ret)
12948 drm_atomic_state_free(state);
12949 return ret;
12950 }
12951
12952 static const struct drm_crtc_funcs intel_crtc_funcs = {
12953 .gamma_set = intel_crtc_gamma_set,
12954 .set_config = intel_crtc_set_config,
12955 .destroy = intel_crtc_destroy,
12956 .page_flip = intel_crtc_page_flip,
12957 .atomic_duplicate_state = intel_crtc_duplicate_state,
12958 .atomic_destroy_state = intel_crtc_destroy_state,
12959 };
12960
12961 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12962 struct intel_shared_dpll *pll,
12963 struct intel_dpll_hw_state *hw_state)
12964 {
12965 uint32_t val;
12966
12967 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12968 return false;
12969
12970 val = I915_READ(PCH_DPLL(pll->id));
12971 hw_state->dpll = val;
12972 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12973 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12974
12975 return val & DPLL_VCO_ENABLE;
12976 }
12977
12978 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12979 struct intel_shared_dpll *pll)
12980 {
12981 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12982 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12983 }
12984
12985 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12986 struct intel_shared_dpll *pll)
12987 {
12988 /* PCH refclock must be enabled first */
12989 ibx_assert_pch_refclk_enabled(dev_priv);
12990
12991 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12992
12993 /* Wait for the clocks to stabilize. */
12994 POSTING_READ(PCH_DPLL(pll->id));
12995 udelay(150);
12996
12997 /* The pixel multiplier can only be updated once the
12998 * DPLL is enabled and the clocks are stable.
12999 *
13000 * So write it again.
13001 */
13002 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13003 POSTING_READ(PCH_DPLL(pll->id));
13004 udelay(200);
13005 }
13006
13007 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13008 struct intel_shared_dpll *pll)
13009 {
13010 struct drm_device *dev = dev_priv->dev;
13011 struct intel_crtc *crtc;
13012
13013 /* Make sure no transcoder isn't still depending on us. */
13014 for_each_intel_crtc(dev, crtc) {
13015 if (intel_crtc_to_shared_dpll(crtc) == pll)
13016 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13017 }
13018
13019 I915_WRITE(PCH_DPLL(pll->id), 0);
13020 POSTING_READ(PCH_DPLL(pll->id));
13021 udelay(200);
13022 }
13023
13024 static char *ibx_pch_dpll_names[] = {
13025 "PCH DPLL A",
13026 "PCH DPLL B",
13027 };
13028
13029 static void ibx_pch_dpll_init(struct drm_device *dev)
13030 {
13031 struct drm_i915_private *dev_priv = dev->dev_private;
13032 int i;
13033
13034 dev_priv->num_shared_dpll = 2;
13035
13036 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13037 dev_priv->shared_dplls[i].id = i;
13038 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13039 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13040 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13041 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13042 dev_priv->shared_dplls[i].get_hw_state =
13043 ibx_pch_dpll_get_hw_state;
13044 }
13045 }
13046
13047 static void intel_shared_dpll_init(struct drm_device *dev)
13048 {
13049 struct drm_i915_private *dev_priv = dev->dev_private;
13050
13051 if (HAS_DDI(dev))
13052 intel_ddi_pll_init(dev);
13053 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13054 ibx_pch_dpll_init(dev);
13055 else
13056 dev_priv->num_shared_dpll = 0;
13057
13058 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13059 }
13060
13061 /**
13062 * intel_wm_need_update - Check whether watermarks need updating
13063 * @plane: drm plane
13064 * @state: new plane state
13065 *
13066 * Check current plane state versus the new one to determine whether
13067 * watermarks need to be recalculated.
13068 *
13069 * Returns true or false.
13070 */
13071 bool intel_wm_need_update(struct drm_plane *plane,
13072 struct drm_plane_state *state)
13073 {
13074 /* Update watermarks on tiling changes. */
13075 if (!plane->state->fb || !state->fb ||
13076 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13077 plane->state->rotation != state->rotation)
13078 return true;
13079
13080 return false;
13081 }
13082
13083 /**
13084 * intel_prepare_plane_fb - Prepare fb for usage on plane
13085 * @plane: drm plane to prepare for
13086 * @fb: framebuffer to prepare for presentation
13087 *
13088 * Prepares a framebuffer for usage on a display plane. Generally this
13089 * involves pinning the underlying object and updating the frontbuffer tracking
13090 * bits. Some older platforms need special physical address handling for
13091 * cursor planes.
13092 *
13093 * Returns 0 on success, negative error code on failure.
13094 */
13095 int
13096 intel_prepare_plane_fb(struct drm_plane *plane,
13097 struct drm_framebuffer *fb,
13098 const struct drm_plane_state *new_state)
13099 {
13100 struct drm_device *dev = plane->dev;
13101 struct intel_plane *intel_plane = to_intel_plane(plane);
13102 enum pipe pipe = intel_plane->pipe;
13103 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13104 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13105 unsigned frontbuffer_bits = 0;
13106 int ret = 0;
13107
13108 if (!obj)
13109 return 0;
13110
13111 switch (plane->type) {
13112 case DRM_PLANE_TYPE_PRIMARY:
13113 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13114 break;
13115 case DRM_PLANE_TYPE_CURSOR:
13116 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13117 break;
13118 case DRM_PLANE_TYPE_OVERLAY:
13119 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13120 break;
13121 }
13122
13123 mutex_lock(&dev->struct_mutex);
13124
13125 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13126 INTEL_INFO(dev)->cursor_needs_physical) {
13127 int align = IS_I830(dev) ? 16 * 1024 : 256;
13128 ret = i915_gem_object_attach_phys(obj, align);
13129 if (ret)
13130 DRM_DEBUG_KMS("failed to attach phys object\n");
13131 } else {
13132 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13133 }
13134
13135 if (ret == 0)
13136 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13137
13138 mutex_unlock(&dev->struct_mutex);
13139
13140 return ret;
13141 }
13142
13143 /**
13144 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13145 * @plane: drm plane to clean up for
13146 * @fb: old framebuffer that was on plane
13147 *
13148 * Cleans up a framebuffer that has just been removed from a plane.
13149 */
13150 void
13151 intel_cleanup_plane_fb(struct drm_plane *plane,
13152 struct drm_framebuffer *fb,
13153 const struct drm_plane_state *old_state)
13154 {
13155 struct drm_device *dev = plane->dev;
13156 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13157
13158 if (WARN_ON(!obj))
13159 return;
13160
13161 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13162 !INTEL_INFO(dev)->cursor_needs_physical) {
13163 mutex_lock(&dev->struct_mutex);
13164 intel_unpin_fb_obj(fb, old_state);
13165 mutex_unlock(&dev->struct_mutex);
13166 }
13167 }
13168
13169 int
13170 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13171 {
13172 int max_scale;
13173 struct drm_device *dev;
13174 struct drm_i915_private *dev_priv;
13175 int crtc_clock, cdclk;
13176
13177 if (!intel_crtc || !crtc_state)
13178 return DRM_PLANE_HELPER_NO_SCALING;
13179
13180 dev = intel_crtc->base.dev;
13181 dev_priv = dev->dev_private;
13182 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13183 cdclk = dev_priv->display.get_display_clock_speed(dev);
13184
13185 if (!crtc_clock || !cdclk)
13186 return DRM_PLANE_HELPER_NO_SCALING;
13187
13188 /*
13189 * skl max scale is lower of:
13190 * close to 3 but not 3, -1 is for that purpose
13191 * or
13192 * cdclk/crtc_clock
13193 */
13194 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13195
13196 return max_scale;
13197 }
13198
13199 static int
13200 intel_check_primary_plane(struct drm_plane *plane,
13201 struct intel_plane_state *state)
13202 {
13203 struct drm_device *dev = plane->dev;
13204 struct drm_i915_private *dev_priv = dev->dev_private;
13205 struct drm_crtc *crtc = state->base.crtc;
13206 struct intel_crtc *intel_crtc;
13207 struct intel_crtc_state *crtc_state;
13208 struct drm_framebuffer *fb = state->base.fb;
13209 struct drm_rect *dest = &state->dst;
13210 struct drm_rect *src = &state->src;
13211 const struct drm_rect *clip = &state->clip;
13212 bool can_position = false;
13213 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13214 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13215 int ret;
13216
13217 crtc = crtc ? crtc : plane->crtc;
13218 intel_crtc = to_intel_crtc(crtc);
13219 crtc_state = state->base.state ?
13220 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13221
13222 if (INTEL_INFO(dev)->gen >= 9) {
13223 /* use scaler when colorkey is not required */
13224 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13225 min_scale = 1;
13226 max_scale = skl_max_scale(intel_crtc, crtc_state);
13227 }
13228 can_position = true;
13229 }
13230
13231 ret = drm_plane_helper_check_update(plane, crtc, fb,
13232 src, dest, clip,
13233 min_scale,
13234 max_scale,
13235 can_position, true,
13236 &state->visible);
13237 if (ret)
13238 return ret;
13239
13240 if (crtc_state ? crtc_state->base.active : intel_crtc->active) {
13241 struct intel_plane_state *old_state =
13242 to_intel_plane_state(plane->state);
13243
13244 intel_crtc->atomic.wait_for_flips = true;
13245
13246 /*
13247 * FBC does not work on some platforms for rotated
13248 * planes, so disable it when rotation is not 0 and
13249 * update it when rotation is set back to 0.
13250 *
13251 * FIXME: This is redundant with the fbc update done in
13252 * the primary plane enable function except that that
13253 * one is done too late. We eventually need to unify
13254 * this.
13255 */
13256 if (state->visible &&
13257 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13258 dev_priv->fbc.crtc == intel_crtc &&
13259 state->base.rotation != BIT(DRM_ROTATE_0)) {
13260 intel_crtc->atomic.disable_fbc = true;
13261 }
13262
13263 if (state->visible && !old_state->visible) {
13264 /*
13265 * BDW signals flip done immediately if the plane
13266 * is disabled, even if the plane enable is already
13267 * armed to occur at the next vblank :(
13268 */
13269 if (IS_BROADWELL(dev))
13270 intel_crtc->atomic.wait_vblank = true;
13271
13272 if (crtc_state)
13273 intel_crtc->atomic.post_enable_primary = true;
13274 }
13275
13276 /*
13277 * FIXME: Actually if we will still have any other plane enabled
13278 * on the pipe we could let IPS enabled still, but for
13279 * now lets consider that when we make primary invisible
13280 * by setting DSPCNTR to 0 on update_primary_plane function
13281 * IPS needs to be disable.
13282 */
13283 if (!state->visible || !fb)
13284 intel_crtc->atomic.disable_ips = true;
13285
13286 if (!state->visible && old_state->visible &&
13287 crtc_state && !needs_modeset(&crtc_state->base))
13288 intel_crtc->atomic.pre_disable_primary = true;
13289
13290 intel_crtc->atomic.fb_bits |=
13291 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13292
13293 intel_crtc->atomic.update_fbc = true;
13294
13295 if (intel_wm_need_update(plane, &state->base))
13296 intel_crtc->atomic.update_wm = true;
13297 }
13298
13299 if (INTEL_INFO(dev)->gen >= 9) {
13300 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13301 to_intel_plane(plane), state, 0);
13302 if (ret)
13303 return ret;
13304 }
13305
13306 return 0;
13307 }
13308
13309 static void
13310 intel_commit_primary_plane(struct drm_plane *plane,
13311 struct intel_plane_state *state)
13312 {
13313 struct drm_crtc *crtc = state->base.crtc;
13314 struct drm_framebuffer *fb = state->base.fb;
13315 struct drm_device *dev = plane->dev;
13316 struct drm_i915_private *dev_priv = dev->dev_private;
13317 struct intel_crtc *intel_crtc;
13318 struct drm_rect *src = &state->src;
13319
13320 crtc = crtc ? crtc : plane->crtc;
13321 intel_crtc = to_intel_crtc(crtc);
13322
13323 plane->fb = fb;
13324 crtc->x = src->x1 >> 16;
13325 crtc->y = src->y1 >> 16;
13326
13327 if (intel_crtc->active) {
13328 if (state->visible)
13329 /* FIXME: kill this fastboot hack */
13330 intel_update_pipe_size(intel_crtc);
13331
13332 dev_priv->display.update_primary_plane(crtc, plane->fb,
13333 crtc->x, crtc->y);
13334 }
13335 }
13336
13337 static void
13338 intel_disable_primary_plane(struct drm_plane *plane,
13339 struct drm_crtc *crtc,
13340 bool force)
13341 {
13342 struct drm_device *dev = plane->dev;
13343 struct drm_i915_private *dev_priv = dev->dev_private;
13344
13345 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13346 }
13347
13348 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13349 {
13350 struct drm_device *dev = crtc->dev;
13351 struct drm_i915_private *dev_priv = dev->dev_private;
13352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13353 struct intel_plane *intel_plane;
13354 struct drm_plane *p;
13355 unsigned fb_bits = 0;
13356
13357 /* Track fb's for any planes being disabled */
13358 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13359 intel_plane = to_intel_plane(p);
13360
13361 if (intel_crtc->atomic.disabled_planes &
13362 (1 << drm_plane_index(p))) {
13363 switch (p->type) {
13364 case DRM_PLANE_TYPE_PRIMARY:
13365 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13366 break;
13367 case DRM_PLANE_TYPE_CURSOR:
13368 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13369 break;
13370 case DRM_PLANE_TYPE_OVERLAY:
13371 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13372 break;
13373 }
13374
13375 mutex_lock(&dev->struct_mutex);
13376 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13377 mutex_unlock(&dev->struct_mutex);
13378 }
13379 }
13380
13381 if (intel_crtc->atomic.wait_for_flips)
13382 intel_crtc_wait_for_pending_flips(crtc);
13383
13384 if (intel_crtc->atomic.disable_fbc)
13385 intel_fbc_disable(dev);
13386
13387 if (intel_crtc->atomic.disable_ips)
13388 hsw_disable_ips(intel_crtc);
13389
13390 if (intel_crtc->atomic.pre_disable_primary)
13391 intel_pre_disable_primary(crtc);
13392
13393 if (intel_crtc->atomic.update_wm)
13394 intel_update_watermarks(crtc);
13395
13396 intel_runtime_pm_get(dev_priv);
13397
13398 /* Perform vblank evasion around commit operation */
13399 if (intel_crtc->active)
13400 intel_crtc->atomic.evade =
13401 intel_pipe_update_start(intel_crtc,
13402 &intel_crtc->atomic.start_vbl_count);
13403 }
13404
13405 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13406 {
13407 struct drm_device *dev = crtc->dev;
13408 struct drm_i915_private *dev_priv = dev->dev_private;
13409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13410 struct drm_plane *p;
13411
13412 if (intel_crtc->atomic.evade)
13413 intel_pipe_update_end(intel_crtc,
13414 intel_crtc->atomic.start_vbl_count);
13415
13416 intel_runtime_pm_put(dev_priv);
13417
13418 if (intel_crtc->atomic.wait_vblank)
13419 intel_wait_for_vblank(dev, intel_crtc->pipe);
13420
13421 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13422
13423 if (intel_crtc->atomic.update_fbc) {
13424 mutex_lock(&dev->struct_mutex);
13425 intel_fbc_update(dev);
13426 mutex_unlock(&dev->struct_mutex);
13427 }
13428
13429 if (intel_crtc->atomic.post_enable_primary)
13430 intel_post_enable_primary(crtc);
13431
13432 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13433 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13434 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13435 false, false);
13436
13437 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13438 }
13439
13440 /**
13441 * intel_plane_destroy - destroy a plane
13442 * @plane: plane to destroy
13443 *
13444 * Common destruction function for all types of planes (primary, cursor,
13445 * sprite).
13446 */
13447 void intel_plane_destroy(struct drm_plane *plane)
13448 {
13449 struct intel_plane *intel_plane = to_intel_plane(plane);
13450 drm_plane_cleanup(plane);
13451 kfree(intel_plane);
13452 }
13453
13454 const struct drm_plane_funcs intel_plane_funcs = {
13455 .update_plane = drm_atomic_helper_update_plane,
13456 .disable_plane = drm_atomic_helper_disable_plane,
13457 .destroy = intel_plane_destroy,
13458 .set_property = drm_atomic_helper_plane_set_property,
13459 .atomic_get_property = intel_plane_atomic_get_property,
13460 .atomic_set_property = intel_plane_atomic_set_property,
13461 .atomic_duplicate_state = intel_plane_duplicate_state,
13462 .atomic_destroy_state = intel_plane_destroy_state,
13463
13464 };
13465
13466 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13467 int pipe)
13468 {
13469 struct intel_plane *primary;
13470 struct intel_plane_state *state;
13471 const uint32_t *intel_primary_formats;
13472 int num_formats;
13473
13474 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13475 if (primary == NULL)
13476 return NULL;
13477
13478 state = intel_create_plane_state(&primary->base);
13479 if (!state) {
13480 kfree(primary);
13481 return NULL;
13482 }
13483 primary->base.state = &state->base;
13484
13485 primary->can_scale = false;
13486 primary->max_downscale = 1;
13487 if (INTEL_INFO(dev)->gen >= 9) {
13488 primary->can_scale = true;
13489 state->scaler_id = -1;
13490 }
13491 primary->pipe = pipe;
13492 primary->plane = pipe;
13493 primary->check_plane = intel_check_primary_plane;
13494 primary->commit_plane = intel_commit_primary_plane;
13495 primary->disable_plane = intel_disable_primary_plane;
13496 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13497 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13498 primary->plane = !pipe;
13499
13500 if (INTEL_INFO(dev)->gen >= 9) {
13501 intel_primary_formats = skl_primary_formats;
13502 num_formats = ARRAY_SIZE(skl_primary_formats);
13503 } else if (INTEL_INFO(dev)->gen >= 4) {
13504 intel_primary_formats = i965_primary_formats;
13505 num_formats = ARRAY_SIZE(i965_primary_formats);
13506 } else {
13507 intel_primary_formats = i8xx_primary_formats;
13508 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13509 }
13510
13511 drm_universal_plane_init(dev, &primary->base, 0,
13512 &intel_plane_funcs,
13513 intel_primary_formats, num_formats,
13514 DRM_PLANE_TYPE_PRIMARY);
13515
13516 if (INTEL_INFO(dev)->gen >= 4)
13517 intel_create_rotation_property(dev, primary);
13518
13519 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13520
13521 return &primary->base;
13522 }
13523
13524 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13525 {
13526 if (!dev->mode_config.rotation_property) {
13527 unsigned long flags = BIT(DRM_ROTATE_0) |
13528 BIT(DRM_ROTATE_180);
13529
13530 if (INTEL_INFO(dev)->gen >= 9)
13531 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13532
13533 dev->mode_config.rotation_property =
13534 drm_mode_create_rotation_property(dev, flags);
13535 }
13536 if (dev->mode_config.rotation_property)
13537 drm_object_attach_property(&plane->base.base,
13538 dev->mode_config.rotation_property,
13539 plane->base.state->rotation);
13540 }
13541
13542 static int
13543 intel_check_cursor_plane(struct drm_plane *plane,
13544 struct intel_plane_state *state)
13545 {
13546 struct drm_crtc *crtc = state->base.crtc;
13547 struct drm_device *dev = plane->dev;
13548 struct drm_framebuffer *fb = state->base.fb;
13549 struct drm_rect *dest = &state->dst;
13550 struct drm_rect *src = &state->src;
13551 const struct drm_rect *clip = &state->clip;
13552 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13553 struct intel_crtc *intel_crtc;
13554 unsigned stride;
13555 int ret;
13556
13557 crtc = crtc ? crtc : plane->crtc;
13558 intel_crtc = to_intel_crtc(crtc);
13559
13560 ret = drm_plane_helper_check_update(plane, crtc, fb,
13561 src, dest, clip,
13562 DRM_PLANE_HELPER_NO_SCALING,
13563 DRM_PLANE_HELPER_NO_SCALING,
13564 true, true, &state->visible);
13565 if (ret)
13566 return ret;
13567
13568
13569 /* if we want to turn off the cursor ignore width and height */
13570 if (!obj)
13571 goto finish;
13572
13573 /* Check for which cursor types we support */
13574 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13575 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13576 state->base.crtc_w, state->base.crtc_h);
13577 return -EINVAL;
13578 }
13579
13580 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13581 if (obj->base.size < stride * state->base.crtc_h) {
13582 DRM_DEBUG_KMS("buffer is too small\n");
13583 return -ENOMEM;
13584 }
13585
13586 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13587 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13588 ret = -EINVAL;
13589 }
13590
13591 finish:
13592 if (intel_crtc->active) {
13593 if (plane->state->crtc_w != state->base.crtc_w)
13594 intel_crtc->atomic.update_wm = true;
13595
13596 intel_crtc->atomic.fb_bits |=
13597 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13598 }
13599
13600 return ret;
13601 }
13602
13603 static void
13604 intel_disable_cursor_plane(struct drm_plane *plane,
13605 struct drm_crtc *crtc,
13606 bool force)
13607 {
13608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13609
13610 if (!force) {
13611 plane->fb = NULL;
13612 intel_crtc->cursor_bo = NULL;
13613 intel_crtc->cursor_addr = 0;
13614 }
13615
13616 intel_crtc_update_cursor(crtc, false);
13617 }
13618
13619 static void
13620 intel_commit_cursor_plane(struct drm_plane *plane,
13621 struct intel_plane_state *state)
13622 {
13623 struct drm_crtc *crtc = state->base.crtc;
13624 struct drm_device *dev = plane->dev;
13625 struct intel_crtc *intel_crtc;
13626 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13627 uint32_t addr;
13628
13629 crtc = crtc ? crtc : plane->crtc;
13630 intel_crtc = to_intel_crtc(crtc);
13631
13632 plane->fb = state->base.fb;
13633 crtc->cursor_x = state->base.crtc_x;
13634 crtc->cursor_y = state->base.crtc_y;
13635
13636 if (intel_crtc->cursor_bo == obj)
13637 goto update;
13638
13639 if (!obj)
13640 addr = 0;
13641 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13642 addr = i915_gem_obj_ggtt_offset(obj);
13643 else
13644 addr = obj->phys_handle->busaddr;
13645
13646 intel_crtc->cursor_addr = addr;
13647 intel_crtc->cursor_bo = obj;
13648 update:
13649
13650 if (intel_crtc->active)
13651 intel_crtc_update_cursor(crtc, state->visible);
13652 }
13653
13654 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13655 int pipe)
13656 {
13657 struct intel_plane *cursor;
13658 struct intel_plane_state *state;
13659
13660 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13661 if (cursor == NULL)
13662 return NULL;
13663
13664 state = intel_create_plane_state(&cursor->base);
13665 if (!state) {
13666 kfree(cursor);
13667 return NULL;
13668 }
13669 cursor->base.state = &state->base;
13670
13671 cursor->can_scale = false;
13672 cursor->max_downscale = 1;
13673 cursor->pipe = pipe;
13674 cursor->plane = pipe;
13675 cursor->check_plane = intel_check_cursor_plane;
13676 cursor->commit_plane = intel_commit_cursor_plane;
13677 cursor->disable_plane = intel_disable_cursor_plane;
13678
13679 drm_universal_plane_init(dev, &cursor->base, 0,
13680 &intel_plane_funcs,
13681 intel_cursor_formats,
13682 ARRAY_SIZE(intel_cursor_formats),
13683 DRM_PLANE_TYPE_CURSOR);
13684
13685 if (INTEL_INFO(dev)->gen >= 4) {
13686 if (!dev->mode_config.rotation_property)
13687 dev->mode_config.rotation_property =
13688 drm_mode_create_rotation_property(dev,
13689 BIT(DRM_ROTATE_0) |
13690 BIT(DRM_ROTATE_180));
13691 if (dev->mode_config.rotation_property)
13692 drm_object_attach_property(&cursor->base.base,
13693 dev->mode_config.rotation_property,
13694 state->base.rotation);
13695 }
13696
13697 if (INTEL_INFO(dev)->gen >=9)
13698 state->scaler_id = -1;
13699
13700 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13701
13702 return &cursor->base;
13703 }
13704
13705 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13706 struct intel_crtc_state *crtc_state)
13707 {
13708 int i;
13709 struct intel_scaler *intel_scaler;
13710 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13711
13712 for (i = 0; i < intel_crtc->num_scalers; i++) {
13713 intel_scaler = &scaler_state->scalers[i];
13714 intel_scaler->in_use = 0;
13715 intel_scaler->id = i;
13716
13717 intel_scaler->mode = PS_SCALER_MODE_DYN;
13718 }
13719
13720 scaler_state->scaler_id = -1;
13721 }
13722
13723 static void intel_crtc_init(struct drm_device *dev, int pipe)
13724 {
13725 struct drm_i915_private *dev_priv = dev->dev_private;
13726 struct intel_crtc *intel_crtc;
13727 struct intel_crtc_state *crtc_state = NULL;
13728 struct drm_plane *primary = NULL;
13729 struct drm_plane *cursor = NULL;
13730 int i, ret;
13731
13732 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13733 if (intel_crtc == NULL)
13734 return;
13735
13736 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13737 if (!crtc_state)
13738 goto fail;
13739 intel_crtc->config = crtc_state;
13740 intel_crtc->base.state = &crtc_state->base;
13741 crtc_state->base.crtc = &intel_crtc->base;
13742
13743 /* initialize shared scalers */
13744 if (INTEL_INFO(dev)->gen >= 9) {
13745 if (pipe == PIPE_C)
13746 intel_crtc->num_scalers = 1;
13747 else
13748 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13749
13750 skl_init_scalers(dev, intel_crtc, crtc_state);
13751 }
13752
13753 primary = intel_primary_plane_create(dev, pipe);
13754 if (!primary)
13755 goto fail;
13756
13757 cursor = intel_cursor_plane_create(dev, pipe);
13758 if (!cursor)
13759 goto fail;
13760
13761 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13762 cursor, &intel_crtc_funcs);
13763 if (ret)
13764 goto fail;
13765
13766 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13767 for (i = 0; i < 256; i++) {
13768 intel_crtc->lut_r[i] = i;
13769 intel_crtc->lut_g[i] = i;
13770 intel_crtc->lut_b[i] = i;
13771 }
13772
13773 /*
13774 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13775 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13776 */
13777 intel_crtc->pipe = pipe;
13778 intel_crtc->plane = pipe;
13779 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13780 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13781 intel_crtc->plane = !pipe;
13782 }
13783
13784 intel_crtc->cursor_base = ~0;
13785 intel_crtc->cursor_cntl = ~0;
13786 intel_crtc->cursor_size = ~0;
13787
13788 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13789 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13790 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13791 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13792
13793 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13794
13795 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13796 return;
13797
13798 fail:
13799 if (primary)
13800 drm_plane_cleanup(primary);
13801 if (cursor)
13802 drm_plane_cleanup(cursor);
13803 kfree(crtc_state);
13804 kfree(intel_crtc);
13805 }
13806
13807 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13808 {
13809 struct drm_encoder *encoder = connector->base.encoder;
13810 struct drm_device *dev = connector->base.dev;
13811
13812 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13813
13814 if (!encoder || WARN_ON(!encoder->crtc))
13815 return INVALID_PIPE;
13816
13817 return to_intel_crtc(encoder->crtc)->pipe;
13818 }
13819
13820 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13821 struct drm_file *file)
13822 {
13823 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13824 struct drm_crtc *drmmode_crtc;
13825 struct intel_crtc *crtc;
13826
13827 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13828
13829 if (!drmmode_crtc) {
13830 DRM_ERROR("no such CRTC id\n");
13831 return -ENOENT;
13832 }
13833
13834 crtc = to_intel_crtc(drmmode_crtc);
13835 pipe_from_crtc_id->pipe = crtc->pipe;
13836
13837 return 0;
13838 }
13839
13840 static int intel_encoder_clones(struct intel_encoder *encoder)
13841 {
13842 struct drm_device *dev = encoder->base.dev;
13843 struct intel_encoder *source_encoder;
13844 int index_mask = 0;
13845 int entry = 0;
13846
13847 for_each_intel_encoder(dev, source_encoder) {
13848 if (encoders_cloneable(encoder, source_encoder))
13849 index_mask |= (1 << entry);
13850
13851 entry++;
13852 }
13853
13854 return index_mask;
13855 }
13856
13857 static bool has_edp_a(struct drm_device *dev)
13858 {
13859 struct drm_i915_private *dev_priv = dev->dev_private;
13860
13861 if (!IS_MOBILE(dev))
13862 return false;
13863
13864 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13865 return false;
13866
13867 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13868 return false;
13869
13870 return true;
13871 }
13872
13873 static bool intel_crt_present(struct drm_device *dev)
13874 {
13875 struct drm_i915_private *dev_priv = dev->dev_private;
13876
13877 if (INTEL_INFO(dev)->gen >= 9)
13878 return false;
13879
13880 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13881 return false;
13882
13883 if (IS_CHERRYVIEW(dev))
13884 return false;
13885
13886 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13887 return false;
13888
13889 return true;
13890 }
13891
13892 static void intel_setup_outputs(struct drm_device *dev)
13893 {
13894 struct drm_i915_private *dev_priv = dev->dev_private;
13895 struct intel_encoder *encoder;
13896 bool dpd_is_edp = false;
13897
13898 intel_lvds_init(dev);
13899
13900 if (intel_crt_present(dev))
13901 intel_crt_init(dev);
13902
13903 if (IS_BROXTON(dev)) {
13904 /*
13905 * FIXME: Broxton doesn't support port detection via the
13906 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13907 * detect the ports.
13908 */
13909 intel_ddi_init(dev, PORT_A);
13910 intel_ddi_init(dev, PORT_B);
13911 intel_ddi_init(dev, PORT_C);
13912 } else if (HAS_DDI(dev)) {
13913 int found;
13914
13915 /*
13916 * Haswell uses DDI functions to detect digital outputs.
13917 * On SKL pre-D0 the strap isn't connected, so we assume
13918 * it's there.
13919 */
13920 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13921 /* WaIgnoreDDIAStrap: skl */
13922 if (found ||
13923 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13924 intel_ddi_init(dev, PORT_A);
13925
13926 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13927 * register */
13928 found = I915_READ(SFUSE_STRAP);
13929
13930 if (found & SFUSE_STRAP_DDIB_DETECTED)
13931 intel_ddi_init(dev, PORT_B);
13932 if (found & SFUSE_STRAP_DDIC_DETECTED)
13933 intel_ddi_init(dev, PORT_C);
13934 if (found & SFUSE_STRAP_DDID_DETECTED)
13935 intel_ddi_init(dev, PORT_D);
13936 } else if (HAS_PCH_SPLIT(dev)) {
13937 int found;
13938 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13939
13940 if (has_edp_a(dev))
13941 intel_dp_init(dev, DP_A, PORT_A);
13942
13943 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13944 /* PCH SDVOB multiplex with HDMIB */
13945 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13946 if (!found)
13947 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13948 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13949 intel_dp_init(dev, PCH_DP_B, PORT_B);
13950 }
13951
13952 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13953 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13954
13955 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13956 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13957
13958 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13959 intel_dp_init(dev, PCH_DP_C, PORT_C);
13960
13961 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13962 intel_dp_init(dev, PCH_DP_D, PORT_D);
13963 } else if (IS_VALLEYVIEW(dev)) {
13964 /*
13965 * The DP_DETECTED bit is the latched state of the DDC
13966 * SDA pin at boot. However since eDP doesn't require DDC
13967 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13968 * eDP ports may have been muxed to an alternate function.
13969 * Thus we can't rely on the DP_DETECTED bit alone to detect
13970 * eDP ports. Consult the VBT as well as DP_DETECTED to
13971 * detect eDP ports.
13972 */
13973 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13974 !intel_dp_is_edp(dev, PORT_B))
13975 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13976 PORT_B);
13977 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13978 intel_dp_is_edp(dev, PORT_B))
13979 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13980
13981 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13982 !intel_dp_is_edp(dev, PORT_C))
13983 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13984 PORT_C);
13985 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13986 intel_dp_is_edp(dev, PORT_C))
13987 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13988
13989 if (IS_CHERRYVIEW(dev)) {
13990 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13991 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13992 PORT_D);
13993 /* eDP not supported on port D, so don't check VBT */
13994 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13995 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13996 }
13997
13998 intel_dsi_init(dev);
13999 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14000 bool found = false;
14001
14002 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14003 DRM_DEBUG_KMS("probing SDVOB\n");
14004 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14005 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14006 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14007 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14008 }
14009
14010 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14011 intel_dp_init(dev, DP_B, PORT_B);
14012 }
14013
14014 /* Before G4X SDVOC doesn't have its own detect register */
14015
14016 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14017 DRM_DEBUG_KMS("probing SDVOC\n");
14018 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14019 }
14020
14021 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14022
14023 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14024 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14025 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14026 }
14027 if (SUPPORTS_INTEGRATED_DP(dev))
14028 intel_dp_init(dev, DP_C, PORT_C);
14029 }
14030
14031 if (SUPPORTS_INTEGRATED_DP(dev) &&
14032 (I915_READ(DP_D) & DP_DETECTED))
14033 intel_dp_init(dev, DP_D, PORT_D);
14034 } else if (IS_GEN2(dev))
14035 intel_dvo_init(dev);
14036
14037 if (SUPPORTS_TV(dev))
14038 intel_tv_init(dev);
14039
14040 intel_psr_init(dev);
14041
14042 for_each_intel_encoder(dev, encoder) {
14043 encoder->base.possible_crtcs = encoder->crtc_mask;
14044 encoder->base.possible_clones =
14045 intel_encoder_clones(encoder);
14046 }
14047
14048 intel_init_pch_refclk(dev);
14049
14050 drm_helper_move_panel_connectors_to_head(dev);
14051 }
14052
14053 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14054 {
14055 struct drm_device *dev = fb->dev;
14056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14057
14058 drm_framebuffer_cleanup(fb);
14059 mutex_lock(&dev->struct_mutex);
14060 WARN_ON(!intel_fb->obj->framebuffer_references--);
14061 drm_gem_object_unreference(&intel_fb->obj->base);
14062 mutex_unlock(&dev->struct_mutex);
14063 kfree(intel_fb);
14064 }
14065
14066 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14067 struct drm_file *file,
14068 unsigned int *handle)
14069 {
14070 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14071 struct drm_i915_gem_object *obj = intel_fb->obj;
14072
14073 return drm_gem_handle_create(file, &obj->base, handle);
14074 }
14075
14076 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14077 .destroy = intel_user_framebuffer_destroy,
14078 .create_handle = intel_user_framebuffer_create_handle,
14079 };
14080
14081 static
14082 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14083 uint32_t pixel_format)
14084 {
14085 u32 gen = INTEL_INFO(dev)->gen;
14086
14087 if (gen >= 9) {
14088 /* "The stride in bytes must not exceed the of the size of 8K
14089 * pixels and 32K bytes."
14090 */
14091 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14092 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14093 return 32*1024;
14094 } else if (gen >= 4) {
14095 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14096 return 16*1024;
14097 else
14098 return 32*1024;
14099 } else if (gen >= 3) {
14100 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14101 return 8*1024;
14102 else
14103 return 16*1024;
14104 } else {
14105 /* XXX DSPC is limited to 4k tiled */
14106 return 8*1024;
14107 }
14108 }
14109
14110 static int intel_framebuffer_init(struct drm_device *dev,
14111 struct intel_framebuffer *intel_fb,
14112 struct drm_mode_fb_cmd2 *mode_cmd,
14113 struct drm_i915_gem_object *obj)
14114 {
14115 unsigned int aligned_height;
14116 int ret;
14117 u32 pitch_limit, stride_alignment;
14118
14119 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14120
14121 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14122 /* Enforce that fb modifier and tiling mode match, but only for
14123 * X-tiled. This is needed for FBC. */
14124 if (!!(obj->tiling_mode == I915_TILING_X) !=
14125 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14126 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14127 return -EINVAL;
14128 }
14129 } else {
14130 if (obj->tiling_mode == I915_TILING_X)
14131 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14132 else if (obj->tiling_mode == I915_TILING_Y) {
14133 DRM_DEBUG("No Y tiling for legacy addfb\n");
14134 return -EINVAL;
14135 }
14136 }
14137
14138 /* Passed in modifier sanity checking. */
14139 switch (mode_cmd->modifier[0]) {
14140 case I915_FORMAT_MOD_Y_TILED:
14141 case I915_FORMAT_MOD_Yf_TILED:
14142 if (INTEL_INFO(dev)->gen < 9) {
14143 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14144 mode_cmd->modifier[0]);
14145 return -EINVAL;
14146 }
14147 case DRM_FORMAT_MOD_NONE:
14148 case I915_FORMAT_MOD_X_TILED:
14149 break;
14150 default:
14151 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14152 mode_cmd->modifier[0]);
14153 return -EINVAL;
14154 }
14155
14156 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14157 mode_cmd->pixel_format);
14158 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14159 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14160 mode_cmd->pitches[0], stride_alignment);
14161 return -EINVAL;
14162 }
14163
14164 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14165 mode_cmd->pixel_format);
14166 if (mode_cmd->pitches[0] > pitch_limit) {
14167 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14168 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14169 "tiled" : "linear",
14170 mode_cmd->pitches[0], pitch_limit);
14171 return -EINVAL;
14172 }
14173
14174 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14175 mode_cmd->pitches[0] != obj->stride) {
14176 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14177 mode_cmd->pitches[0], obj->stride);
14178 return -EINVAL;
14179 }
14180
14181 /* Reject formats not supported by any plane early. */
14182 switch (mode_cmd->pixel_format) {
14183 case DRM_FORMAT_C8:
14184 case DRM_FORMAT_RGB565:
14185 case DRM_FORMAT_XRGB8888:
14186 case DRM_FORMAT_ARGB8888:
14187 break;
14188 case DRM_FORMAT_XRGB1555:
14189 if (INTEL_INFO(dev)->gen > 3) {
14190 DRM_DEBUG("unsupported pixel format: %s\n",
14191 drm_get_format_name(mode_cmd->pixel_format));
14192 return -EINVAL;
14193 }
14194 break;
14195 case DRM_FORMAT_ABGR8888:
14196 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14197 DRM_DEBUG("unsupported pixel format: %s\n",
14198 drm_get_format_name(mode_cmd->pixel_format));
14199 return -EINVAL;
14200 }
14201 break;
14202 case DRM_FORMAT_XBGR8888:
14203 case DRM_FORMAT_XRGB2101010:
14204 case DRM_FORMAT_XBGR2101010:
14205 if (INTEL_INFO(dev)->gen < 4) {
14206 DRM_DEBUG("unsupported pixel format: %s\n",
14207 drm_get_format_name(mode_cmd->pixel_format));
14208 return -EINVAL;
14209 }
14210 break;
14211 case DRM_FORMAT_ABGR2101010:
14212 if (!IS_VALLEYVIEW(dev)) {
14213 DRM_DEBUG("unsupported pixel format: %s\n",
14214 drm_get_format_name(mode_cmd->pixel_format));
14215 return -EINVAL;
14216 }
14217 break;
14218 case DRM_FORMAT_YUYV:
14219 case DRM_FORMAT_UYVY:
14220 case DRM_FORMAT_YVYU:
14221 case DRM_FORMAT_VYUY:
14222 if (INTEL_INFO(dev)->gen < 5) {
14223 DRM_DEBUG("unsupported pixel format: %s\n",
14224 drm_get_format_name(mode_cmd->pixel_format));
14225 return -EINVAL;
14226 }
14227 break;
14228 default:
14229 DRM_DEBUG("unsupported pixel format: %s\n",
14230 drm_get_format_name(mode_cmd->pixel_format));
14231 return -EINVAL;
14232 }
14233
14234 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14235 if (mode_cmd->offsets[0] != 0)
14236 return -EINVAL;
14237
14238 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14239 mode_cmd->pixel_format,
14240 mode_cmd->modifier[0]);
14241 /* FIXME drm helper for size checks (especially planar formats)? */
14242 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14243 return -EINVAL;
14244
14245 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14246 intel_fb->obj = obj;
14247 intel_fb->obj->framebuffer_references++;
14248
14249 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14250 if (ret) {
14251 DRM_ERROR("framebuffer init failed %d\n", ret);
14252 return ret;
14253 }
14254
14255 return 0;
14256 }
14257
14258 static struct drm_framebuffer *
14259 intel_user_framebuffer_create(struct drm_device *dev,
14260 struct drm_file *filp,
14261 struct drm_mode_fb_cmd2 *mode_cmd)
14262 {
14263 struct drm_i915_gem_object *obj;
14264
14265 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14266 mode_cmd->handles[0]));
14267 if (&obj->base == NULL)
14268 return ERR_PTR(-ENOENT);
14269
14270 return intel_framebuffer_create(dev, mode_cmd, obj);
14271 }
14272
14273 #ifndef CONFIG_DRM_I915_FBDEV
14274 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14275 {
14276 }
14277 #endif
14278
14279 static const struct drm_mode_config_funcs intel_mode_funcs = {
14280 .fb_create = intel_user_framebuffer_create,
14281 .output_poll_changed = intel_fbdev_output_poll_changed,
14282 .atomic_check = intel_atomic_check,
14283 .atomic_commit = intel_atomic_commit,
14284 };
14285
14286 /* Set up chip specific display functions */
14287 static void intel_init_display(struct drm_device *dev)
14288 {
14289 struct drm_i915_private *dev_priv = dev->dev_private;
14290
14291 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14292 dev_priv->display.find_dpll = g4x_find_best_dpll;
14293 else if (IS_CHERRYVIEW(dev))
14294 dev_priv->display.find_dpll = chv_find_best_dpll;
14295 else if (IS_VALLEYVIEW(dev))
14296 dev_priv->display.find_dpll = vlv_find_best_dpll;
14297 else if (IS_PINEVIEW(dev))
14298 dev_priv->display.find_dpll = pnv_find_best_dpll;
14299 else
14300 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14301
14302 if (INTEL_INFO(dev)->gen >= 9) {
14303 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14304 dev_priv->display.get_initial_plane_config =
14305 skylake_get_initial_plane_config;
14306 dev_priv->display.crtc_compute_clock =
14307 haswell_crtc_compute_clock;
14308 dev_priv->display.crtc_enable = haswell_crtc_enable;
14309 dev_priv->display.crtc_disable = haswell_crtc_disable;
14310 dev_priv->display.off = ironlake_crtc_off;
14311 dev_priv->display.update_primary_plane =
14312 skylake_update_primary_plane;
14313 } else if (HAS_DDI(dev)) {
14314 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14315 dev_priv->display.get_initial_plane_config =
14316 ironlake_get_initial_plane_config;
14317 dev_priv->display.crtc_compute_clock =
14318 haswell_crtc_compute_clock;
14319 dev_priv->display.crtc_enable = haswell_crtc_enable;
14320 dev_priv->display.crtc_disable = haswell_crtc_disable;
14321 dev_priv->display.off = ironlake_crtc_off;
14322 dev_priv->display.update_primary_plane =
14323 ironlake_update_primary_plane;
14324 } else if (HAS_PCH_SPLIT(dev)) {
14325 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14326 dev_priv->display.get_initial_plane_config =
14327 ironlake_get_initial_plane_config;
14328 dev_priv->display.crtc_compute_clock =
14329 ironlake_crtc_compute_clock;
14330 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14331 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14332 dev_priv->display.off = ironlake_crtc_off;
14333 dev_priv->display.update_primary_plane =
14334 ironlake_update_primary_plane;
14335 } else if (IS_VALLEYVIEW(dev)) {
14336 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14337 dev_priv->display.get_initial_plane_config =
14338 i9xx_get_initial_plane_config;
14339 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14340 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14341 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14342 dev_priv->display.off = i9xx_crtc_off;
14343 dev_priv->display.update_primary_plane =
14344 i9xx_update_primary_plane;
14345 } else {
14346 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14347 dev_priv->display.get_initial_plane_config =
14348 i9xx_get_initial_plane_config;
14349 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14350 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14351 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14352 dev_priv->display.off = i9xx_crtc_off;
14353 dev_priv->display.update_primary_plane =
14354 i9xx_update_primary_plane;
14355 }
14356
14357 /* Returns the core display clock speed */
14358 if (IS_SKYLAKE(dev))
14359 dev_priv->display.get_display_clock_speed =
14360 skylake_get_display_clock_speed;
14361 else if (IS_BROADWELL(dev))
14362 dev_priv->display.get_display_clock_speed =
14363 broadwell_get_display_clock_speed;
14364 else if (IS_HASWELL(dev))
14365 dev_priv->display.get_display_clock_speed =
14366 haswell_get_display_clock_speed;
14367 else if (IS_VALLEYVIEW(dev))
14368 dev_priv->display.get_display_clock_speed =
14369 valleyview_get_display_clock_speed;
14370 else if (IS_GEN5(dev))
14371 dev_priv->display.get_display_clock_speed =
14372 ilk_get_display_clock_speed;
14373 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14374 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14375 dev_priv->display.get_display_clock_speed =
14376 i945_get_display_clock_speed;
14377 else if (IS_I915G(dev))
14378 dev_priv->display.get_display_clock_speed =
14379 i915_get_display_clock_speed;
14380 else if (IS_I945GM(dev) || IS_845G(dev))
14381 dev_priv->display.get_display_clock_speed =
14382 i9xx_misc_get_display_clock_speed;
14383 else if (IS_PINEVIEW(dev))
14384 dev_priv->display.get_display_clock_speed =
14385 pnv_get_display_clock_speed;
14386 else if (IS_I915GM(dev))
14387 dev_priv->display.get_display_clock_speed =
14388 i915gm_get_display_clock_speed;
14389 else if (IS_I865G(dev))
14390 dev_priv->display.get_display_clock_speed =
14391 i865_get_display_clock_speed;
14392 else if (IS_I85X(dev))
14393 dev_priv->display.get_display_clock_speed =
14394 i855_get_display_clock_speed;
14395 else /* 852, 830 */
14396 dev_priv->display.get_display_clock_speed =
14397 i830_get_display_clock_speed;
14398
14399 if (IS_GEN5(dev)) {
14400 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14401 } else if (IS_GEN6(dev)) {
14402 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14403 } else if (IS_IVYBRIDGE(dev)) {
14404 /* FIXME: detect B0+ stepping and use auto training */
14405 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14406 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14407 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14408 } else if (IS_VALLEYVIEW(dev)) {
14409 dev_priv->display.modeset_global_resources =
14410 valleyview_modeset_global_resources;
14411 } else if (IS_BROXTON(dev)) {
14412 dev_priv->display.modeset_global_resources =
14413 broxton_modeset_global_resources;
14414 }
14415
14416 switch (INTEL_INFO(dev)->gen) {
14417 case 2:
14418 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14419 break;
14420
14421 case 3:
14422 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14423 break;
14424
14425 case 4:
14426 case 5:
14427 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14428 break;
14429
14430 case 6:
14431 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14432 break;
14433 case 7:
14434 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14435 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14436 break;
14437 case 9:
14438 /* Drop through - unsupported since execlist only. */
14439 default:
14440 /* Default just returns -ENODEV to indicate unsupported */
14441 dev_priv->display.queue_flip = intel_default_queue_flip;
14442 }
14443
14444 intel_panel_init_backlight_funcs(dev);
14445
14446 mutex_init(&dev_priv->pps_mutex);
14447 }
14448
14449 /*
14450 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14451 * resume, or other times. This quirk makes sure that's the case for
14452 * affected systems.
14453 */
14454 static void quirk_pipea_force(struct drm_device *dev)
14455 {
14456 struct drm_i915_private *dev_priv = dev->dev_private;
14457
14458 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14459 DRM_INFO("applying pipe a force quirk\n");
14460 }
14461
14462 static void quirk_pipeb_force(struct drm_device *dev)
14463 {
14464 struct drm_i915_private *dev_priv = dev->dev_private;
14465
14466 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14467 DRM_INFO("applying pipe b force quirk\n");
14468 }
14469
14470 /*
14471 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14472 */
14473 static void quirk_ssc_force_disable(struct drm_device *dev)
14474 {
14475 struct drm_i915_private *dev_priv = dev->dev_private;
14476 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14477 DRM_INFO("applying lvds SSC disable quirk\n");
14478 }
14479
14480 /*
14481 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14482 * brightness value
14483 */
14484 static void quirk_invert_brightness(struct drm_device *dev)
14485 {
14486 struct drm_i915_private *dev_priv = dev->dev_private;
14487 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14488 DRM_INFO("applying inverted panel brightness quirk\n");
14489 }
14490
14491 /* Some VBT's incorrectly indicate no backlight is present */
14492 static void quirk_backlight_present(struct drm_device *dev)
14493 {
14494 struct drm_i915_private *dev_priv = dev->dev_private;
14495 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14496 DRM_INFO("applying backlight present quirk\n");
14497 }
14498
14499 struct intel_quirk {
14500 int device;
14501 int subsystem_vendor;
14502 int subsystem_device;
14503 void (*hook)(struct drm_device *dev);
14504 };
14505
14506 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14507 struct intel_dmi_quirk {
14508 void (*hook)(struct drm_device *dev);
14509 const struct dmi_system_id (*dmi_id_list)[];
14510 };
14511
14512 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14513 {
14514 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14515 return 1;
14516 }
14517
14518 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14519 {
14520 .dmi_id_list = &(const struct dmi_system_id[]) {
14521 {
14522 .callback = intel_dmi_reverse_brightness,
14523 .ident = "NCR Corporation",
14524 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14525 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14526 },
14527 },
14528 { } /* terminating entry */
14529 },
14530 .hook = quirk_invert_brightness,
14531 },
14532 };
14533
14534 static struct intel_quirk intel_quirks[] = {
14535 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14536 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14537
14538 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14539 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14540
14541 /* 830 needs to leave pipe A & dpll A up */
14542 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14543
14544 /* 830 needs to leave pipe B & dpll B up */
14545 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14546
14547 /* Lenovo U160 cannot use SSC on LVDS */
14548 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14549
14550 /* Sony Vaio Y cannot use SSC on LVDS */
14551 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14552
14553 /* Acer Aspire 5734Z must invert backlight brightness */
14554 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14555
14556 /* Acer/eMachines G725 */
14557 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14558
14559 /* Acer/eMachines e725 */
14560 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14561
14562 /* Acer/Packard Bell NCL20 */
14563 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14564
14565 /* Acer Aspire 4736Z */
14566 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14567
14568 /* Acer Aspire 5336 */
14569 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14570
14571 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14572 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14573
14574 /* Acer C720 Chromebook (Core i3 4005U) */
14575 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14576
14577 /* Apple Macbook 2,1 (Core 2 T7400) */
14578 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14579
14580 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14581 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14582
14583 /* HP Chromebook 14 (Celeron 2955U) */
14584 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14585
14586 /* Dell Chromebook 11 */
14587 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14588 };
14589
14590 static void intel_init_quirks(struct drm_device *dev)
14591 {
14592 struct pci_dev *d = dev->pdev;
14593 int i;
14594
14595 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14596 struct intel_quirk *q = &intel_quirks[i];
14597
14598 if (d->device == q->device &&
14599 (d->subsystem_vendor == q->subsystem_vendor ||
14600 q->subsystem_vendor == PCI_ANY_ID) &&
14601 (d->subsystem_device == q->subsystem_device ||
14602 q->subsystem_device == PCI_ANY_ID))
14603 q->hook(dev);
14604 }
14605 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14606 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14607 intel_dmi_quirks[i].hook(dev);
14608 }
14609 }
14610
14611 /* Disable the VGA plane that we never use */
14612 static void i915_disable_vga(struct drm_device *dev)
14613 {
14614 struct drm_i915_private *dev_priv = dev->dev_private;
14615 u8 sr1;
14616 u32 vga_reg = i915_vgacntrl_reg(dev);
14617
14618 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14619 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14620 outb(SR01, VGA_SR_INDEX);
14621 sr1 = inb(VGA_SR_DATA);
14622 outb(sr1 | 1<<5, VGA_SR_DATA);
14623 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14624 udelay(300);
14625
14626 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14627 POSTING_READ(vga_reg);
14628 }
14629
14630 void intel_modeset_init_hw(struct drm_device *dev)
14631 {
14632 intel_prepare_ddi(dev);
14633
14634 if (IS_VALLEYVIEW(dev))
14635 vlv_update_cdclk(dev);
14636
14637 intel_init_clock_gating(dev);
14638
14639 intel_enable_gt_powersave(dev);
14640 }
14641
14642 void intel_modeset_init(struct drm_device *dev)
14643 {
14644 struct drm_i915_private *dev_priv = dev->dev_private;
14645 int sprite, ret;
14646 enum pipe pipe;
14647 struct intel_crtc *crtc;
14648
14649 drm_mode_config_init(dev);
14650
14651 dev->mode_config.min_width = 0;
14652 dev->mode_config.min_height = 0;
14653
14654 dev->mode_config.preferred_depth = 24;
14655 dev->mode_config.prefer_shadow = 1;
14656
14657 dev->mode_config.allow_fb_modifiers = true;
14658
14659 dev->mode_config.funcs = &intel_mode_funcs;
14660
14661 intel_init_quirks(dev);
14662
14663 intel_init_pm(dev);
14664
14665 if (INTEL_INFO(dev)->num_pipes == 0)
14666 return;
14667
14668 /*
14669 * There may be no VBT; and if the BIOS enabled SSC we can
14670 * just keep using it to avoid unnecessary flicker. Whereas if the
14671 * BIOS isn't using it, don't assume it will work even if the VBT
14672 * indicates as much.
14673 */
14674 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14675 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14676 DREF_SSC1_ENABLE);
14677
14678 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14679 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14680 bios_lvds_use_ssc ? "en" : "dis",
14681 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14682 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14683 }
14684 }
14685
14686 intel_init_display(dev);
14687 intel_init_audio(dev);
14688
14689 if (IS_GEN2(dev)) {
14690 dev->mode_config.max_width = 2048;
14691 dev->mode_config.max_height = 2048;
14692 } else if (IS_GEN3(dev)) {
14693 dev->mode_config.max_width = 4096;
14694 dev->mode_config.max_height = 4096;
14695 } else {
14696 dev->mode_config.max_width = 8192;
14697 dev->mode_config.max_height = 8192;
14698 }
14699
14700 if (IS_845G(dev) || IS_I865G(dev)) {
14701 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14702 dev->mode_config.cursor_height = 1023;
14703 } else if (IS_GEN2(dev)) {
14704 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14705 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14706 } else {
14707 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14708 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14709 }
14710
14711 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14712
14713 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14714 INTEL_INFO(dev)->num_pipes,
14715 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14716
14717 for_each_pipe(dev_priv, pipe) {
14718 intel_crtc_init(dev, pipe);
14719 for_each_sprite(dev_priv, pipe, sprite) {
14720 ret = intel_plane_init(dev, pipe, sprite);
14721 if (ret)
14722 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14723 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14724 }
14725 }
14726
14727 intel_init_dpio(dev);
14728
14729 intel_shared_dpll_init(dev);
14730
14731 /* Just disable it once at startup */
14732 i915_disable_vga(dev);
14733 intel_setup_outputs(dev);
14734
14735 /* Just in case the BIOS is doing something questionable. */
14736 intel_fbc_disable(dev);
14737
14738 drm_modeset_lock_all(dev);
14739 intel_modeset_setup_hw_state(dev, false);
14740 drm_modeset_unlock_all(dev);
14741
14742 for_each_intel_crtc(dev, crtc) {
14743 if (!crtc->active)
14744 continue;
14745
14746 /*
14747 * Note that reserving the BIOS fb up front prevents us
14748 * from stuffing other stolen allocations like the ring
14749 * on top. This prevents some ugliness at boot time, and
14750 * can even allow for smooth boot transitions if the BIOS
14751 * fb is large enough for the active pipe configuration.
14752 */
14753 if (dev_priv->display.get_initial_plane_config) {
14754 dev_priv->display.get_initial_plane_config(crtc,
14755 &crtc->plane_config);
14756 /*
14757 * If the fb is shared between multiple heads, we'll
14758 * just get the first one.
14759 */
14760 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14761 }
14762 }
14763 }
14764
14765 static void intel_enable_pipe_a(struct drm_device *dev)
14766 {
14767 struct intel_connector *connector;
14768 struct drm_connector *crt = NULL;
14769 struct intel_load_detect_pipe load_detect_temp;
14770 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14771
14772 /* We can't just switch on the pipe A, we need to set things up with a
14773 * proper mode and output configuration. As a gross hack, enable pipe A
14774 * by enabling the load detect pipe once. */
14775 for_each_intel_connector(dev, connector) {
14776 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14777 crt = &connector->base;
14778 break;
14779 }
14780 }
14781
14782 if (!crt)
14783 return;
14784
14785 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14786 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14787 }
14788
14789 static bool
14790 intel_check_plane_mapping(struct intel_crtc *crtc)
14791 {
14792 struct drm_device *dev = crtc->base.dev;
14793 struct drm_i915_private *dev_priv = dev->dev_private;
14794 u32 reg, val;
14795
14796 if (INTEL_INFO(dev)->num_pipes == 1)
14797 return true;
14798
14799 reg = DSPCNTR(!crtc->plane);
14800 val = I915_READ(reg);
14801
14802 if ((val & DISPLAY_PLANE_ENABLE) &&
14803 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14804 return false;
14805
14806 return true;
14807 }
14808
14809 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14810 {
14811 struct drm_device *dev = crtc->base.dev;
14812 struct drm_i915_private *dev_priv = dev->dev_private;
14813 u32 reg;
14814
14815 /* Clear any frame start delays used for debugging left by the BIOS */
14816 reg = PIPECONF(crtc->config->cpu_transcoder);
14817 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14818
14819 /* restore vblank interrupts to correct state */
14820 drm_crtc_vblank_reset(&crtc->base);
14821 if (crtc->active) {
14822 update_scanline_offset(crtc);
14823 drm_crtc_vblank_on(&crtc->base);
14824 }
14825
14826 /* We need to sanitize the plane -> pipe mapping first because this will
14827 * disable the crtc (and hence change the state) if it is wrong. Note
14828 * that gen4+ has a fixed plane -> pipe mapping. */
14829 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14830 struct intel_connector *connector;
14831 bool plane;
14832
14833 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14834 crtc->base.base.id);
14835
14836 /* Pipe has the wrong plane attached and the plane is active.
14837 * Temporarily change the plane mapping and disable everything
14838 * ... */
14839 plane = crtc->plane;
14840 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14841 crtc->plane = !plane;
14842 intel_crtc_disable_planes(&crtc->base);
14843 dev_priv->display.crtc_disable(&crtc->base);
14844 crtc->plane = plane;
14845
14846 /* ... and break all links. */
14847 for_each_intel_connector(dev, connector) {
14848 if (connector->encoder->base.crtc != &crtc->base)
14849 continue;
14850
14851 connector->base.dpms = DRM_MODE_DPMS_OFF;
14852 connector->base.encoder = NULL;
14853 }
14854 /* multiple connectors may have the same encoder:
14855 * handle them and break crtc link separately */
14856 for_each_intel_connector(dev, connector)
14857 if (connector->encoder->base.crtc == &crtc->base) {
14858 connector->encoder->base.crtc = NULL;
14859 connector->encoder->connectors_active = false;
14860 }
14861
14862 WARN_ON(crtc->active);
14863 crtc->base.state->enable = false;
14864 crtc->base.state->active = false;
14865 crtc->base.enabled = false;
14866 }
14867
14868 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14869 crtc->pipe == PIPE_A && !crtc->active) {
14870 /* BIOS forgot to enable pipe A, this mostly happens after
14871 * resume. Force-enable the pipe to fix this, the update_dpms
14872 * call below we restore the pipe to the right state, but leave
14873 * the required bits on. */
14874 intel_enable_pipe_a(dev);
14875 }
14876
14877 /* Adjust the state of the output pipe according to whether we
14878 * have active connectors/encoders. */
14879 intel_crtc_update_dpms(&crtc->base);
14880
14881 if (crtc->active != crtc->base.state->enable) {
14882 struct intel_encoder *encoder;
14883
14884 /* This can happen either due to bugs in the get_hw_state
14885 * functions or because the pipe is force-enabled due to the
14886 * pipe A quirk. */
14887 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14888 crtc->base.base.id,
14889 crtc->base.state->enable ? "enabled" : "disabled",
14890 crtc->active ? "enabled" : "disabled");
14891
14892 crtc->base.state->enable = crtc->active;
14893 crtc->base.state->active = crtc->active;
14894 crtc->base.enabled = crtc->active;
14895
14896 /* Because we only establish the connector -> encoder ->
14897 * crtc links if something is active, this means the
14898 * crtc is now deactivated. Break the links. connector
14899 * -> encoder links are only establish when things are
14900 * actually up, hence no need to break them. */
14901 WARN_ON(crtc->active);
14902
14903 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14904 WARN_ON(encoder->connectors_active);
14905 encoder->base.crtc = NULL;
14906 }
14907 }
14908
14909 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14910 /*
14911 * We start out with underrun reporting disabled to avoid races.
14912 * For correct bookkeeping mark this on active crtcs.
14913 *
14914 * Also on gmch platforms we dont have any hardware bits to
14915 * disable the underrun reporting. Which means we need to start
14916 * out with underrun reporting disabled also on inactive pipes,
14917 * since otherwise we'll complain about the garbage we read when
14918 * e.g. coming up after runtime pm.
14919 *
14920 * No protection against concurrent access is required - at
14921 * worst a fifo underrun happens which also sets this to false.
14922 */
14923 crtc->cpu_fifo_underrun_disabled = true;
14924 crtc->pch_fifo_underrun_disabled = true;
14925 }
14926 }
14927
14928 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14929 {
14930 struct intel_connector *connector;
14931 struct drm_device *dev = encoder->base.dev;
14932
14933 /* We need to check both for a crtc link (meaning that the
14934 * encoder is active and trying to read from a pipe) and the
14935 * pipe itself being active. */
14936 bool has_active_crtc = encoder->base.crtc &&
14937 to_intel_crtc(encoder->base.crtc)->active;
14938
14939 if (encoder->connectors_active && !has_active_crtc) {
14940 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14941 encoder->base.base.id,
14942 encoder->base.name);
14943
14944 /* Connector is active, but has no active pipe. This is
14945 * fallout from our resume register restoring. Disable
14946 * the encoder manually again. */
14947 if (encoder->base.crtc) {
14948 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14949 encoder->base.base.id,
14950 encoder->base.name);
14951 encoder->disable(encoder);
14952 if (encoder->post_disable)
14953 encoder->post_disable(encoder);
14954 }
14955 encoder->base.crtc = NULL;
14956 encoder->connectors_active = false;
14957
14958 /* Inconsistent output/port/pipe state happens presumably due to
14959 * a bug in one of the get_hw_state functions. Or someplace else
14960 * in our code, like the register restore mess on resume. Clamp
14961 * things to off as a safer default. */
14962 for_each_intel_connector(dev, connector) {
14963 if (connector->encoder != encoder)
14964 continue;
14965 connector->base.dpms = DRM_MODE_DPMS_OFF;
14966 connector->base.encoder = NULL;
14967 }
14968 }
14969 /* Enabled encoders without active connectors will be fixed in
14970 * the crtc fixup. */
14971 }
14972
14973 void i915_redisable_vga_power_on(struct drm_device *dev)
14974 {
14975 struct drm_i915_private *dev_priv = dev->dev_private;
14976 u32 vga_reg = i915_vgacntrl_reg(dev);
14977
14978 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14979 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14980 i915_disable_vga(dev);
14981 }
14982 }
14983
14984 void i915_redisable_vga(struct drm_device *dev)
14985 {
14986 struct drm_i915_private *dev_priv = dev->dev_private;
14987
14988 /* This function can be called both from intel_modeset_setup_hw_state or
14989 * at a very early point in our resume sequence, where the power well
14990 * structures are not yet restored. Since this function is at a very
14991 * paranoid "someone might have enabled VGA while we were not looking"
14992 * level, just check if the power well is enabled instead of trying to
14993 * follow the "don't touch the power well if we don't need it" policy
14994 * the rest of the driver uses. */
14995 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14996 return;
14997
14998 i915_redisable_vga_power_on(dev);
14999 }
15000
15001 static bool primary_get_hw_state(struct intel_crtc *crtc)
15002 {
15003 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15004
15005 if (!crtc->active)
15006 return false;
15007
15008 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15009 }
15010
15011 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15012 {
15013 struct drm_i915_private *dev_priv = dev->dev_private;
15014 enum pipe pipe;
15015 struct intel_crtc *crtc;
15016 struct intel_encoder *encoder;
15017 struct intel_connector *connector;
15018 int i;
15019
15020 for_each_intel_crtc(dev, crtc) {
15021 struct drm_plane *primary = crtc->base.primary;
15022 struct intel_plane_state *plane_state;
15023
15024 memset(crtc->config, 0, sizeof(*crtc->config));
15025 crtc->config->base.crtc = &crtc->base;
15026
15027 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15028
15029 crtc->active = dev_priv->display.get_pipe_config(crtc,
15030 crtc->config);
15031
15032 crtc->base.state->enable = crtc->active;
15033 crtc->base.state->active = crtc->active;
15034 crtc->base.enabled = crtc->active;
15035
15036 plane_state = to_intel_plane_state(primary->state);
15037 plane_state->visible = primary_get_hw_state(crtc);
15038
15039 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15040 crtc->base.base.id,
15041 crtc->active ? "enabled" : "disabled");
15042 }
15043
15044 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15045 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15046
15047 pll->on = pll->get_hw_state(dev_priv, pll,
15048 &pll->config.hw_state);
15049 pll->active = 0;
15050 pll->config.crtc_mask = 0;
15051 for_each_intel_crtc(dev, crtc) {
15052 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15053 pll->active++;
15054 pll->config.crtc_mask |= 1 << crtc->pipe;
15055 }
15056 }
15057
15058 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15059 pll->name, pll->config.crtc_mask, pll->on);
15060
15061 if (pll->config.crtc_mask)
15062 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15063 }
15064
15065 for_each_intel_encoder(dev, encoder) {
15066 pipe = 0;
15067
15068 if (encoder->get_hw_state(encoder, &pipe)) {
15069 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15070 encoder->base.crtc = &crtc->base;
15071 encoder->get_config(encoder, crtc->config);
15072 } else {
15073 encoder->base.crtc = NULL;
15074 }
15075
15076 encoder->connectors_active = false;
15077 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15078 encoder->base.base.id,
15079 encoder->base.name,
15080 encoder->base.crtc ? "enabled" : "disabled",
15081 pipe_name(pipe));
15082 }
15083
15084 for_each_intel_connector(dev, connector) {
15085 if (connector->get_hw_state(connector)) {
15086 connector->base.dpms = DRM_MODE_DPMS_ON;
15087 connector->encoder->connectors_active = true;
15088 connector->base.encoder = &connector->encoder->base;
15089 } else {
15090 connector->base.dpms = DRM_MODE_DPMS_OFF;
15091 connector->base.encoder = NULL;
15092 }
15093 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15094 connector->base.base.id,
15095 connector->base.name,
15096 connector->base.encoder ? "enabled" : "disabled");
15097 }
15098 }
15099
15100 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15101 * and i915 state tracking structures. */
15102 void intel_modeset_setup_hw_state(struct drm_device *dev,
15103 bool force_restore)
15104 {
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15106 enum pipe pipe;
15107 struct intel_crtc *crtc;
15108 struct intel_encoder *encoder;
15109 int i;
15110
15111 intel_modeset_readout_hw_state(dev);
15112
15113 /*
15114 * Now that we have the config, copy it to each CRTC struct
15115 * Note that this could go away if we move to using crtc_config
15116 * checking everywhere.
15117 */
15118 for_each_intel_crtc(dev, crtc) {
15119 if (crtc->active && i915.fastboot) {
15120 intel_mode_from_pipe_config(&crtc->base.mode,
15121 crtc->config);
15122 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15123 crtc->base.base.id);
15124 drm_mode_debug_printmodeline(&crtc->base.mode);
15125 }
15126 }
15127
15128 /* HW state is read out, now we need to sanitize this mess. */
15129 for_each_intel_encoder(dev, encoder) {
15130 intel_sanitize_encoder(encoder);
15131 }
15132
15133 for_each_pipe(dev_priv, pipe) {
15134 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15135 intel_sanitize_crtc(crtc);
15136 intel_dump_pipe_config(crtc, crtc->config,
15137 "[setup_hw_state]");
15138 }
15139
15140 intel_modeset_update_connector_atomic_state(dev);
15141
15142 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15143 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15144
15145 if (!pll->on || pll->active)
15146 continue;
15147
15148 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15149
15150 pll->disable(dev_priv, pll);
15151 pll->on = false;
15152 }
15153
15154 if (IS_GEN9(dev))
15155 skl_wm_get_hw_state(dev);
15156 else if (HAS_PCH_SPLIT(dev))
15157 ilk_wm_get_hw_state(dev);
15158
15159 if (force_restore) {
15160 i915_redisable_vga(dev);
15161
15162 /*
15163 * We need to use raw interfaces for restoring state to avoid
15164 * checking (bogus) intermediate states.
15165 */
15166 for_each_pipe(dev_priv, pipe) {
15167 struct drm_crtc *crtc =
15168 dev_priv->pipe_to_crtc_mapping[pipe];
15169
15170 intel_crtc_restore_mode(crtc);
15171 }
15172 } else {
15173 intel_modeset_update_staged_output_state(dev);
15174 }
15175
15176 intel_modeset_check_state(dev);
15177 }
15178
15179 void intel_modeset_gem_init(struct drm_device *dev)
15180 {
15181 struct drm_crtc *c;
15182 struct drm_i915_gem_object *obj;
15183 int ret;
15184
15185 mutex_lock(&dev->struct_mutex);
15186 intel_init_gt_powersave(dev);
15187 mutex_unlock(&dev->struct_mutex);
15188
15189 intel_modeset_init_hw(dev);
15190
15191 intel_setup_overlay(dev);
15192
15193 /*
15194 * Make sure any fbs we allocated at startup are properly
15195 * pinned & fenced. When we do the allocation it's too early
15196 * for this.
15197 */
15198 for_each_crtc(dev, c) {
15199 obj = intel_fb_obj(c->primary->fb);
15200 if (obj == NULL)
15201 continue;
15202
15203 mutex_lock(&dev->struct_mutex);
15204 ret = intel_pin_and_fence_fb_obj(c->primary,
15205 c->primary->fb,
15206 c->primary->state,
15207 NULL);
15208 mutex_unlock(&dev->struct_mutex);
15209 if (ret) {
15210 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15211 to_intel_crtc(c)->pipe);
15212 drm_framebuffer_unreference(c->primary->fb);
15213 c->primary->fb = NULL;
15214 update_state_fb(c->primary);
15215 }
15216 }
15217
15218 intel_backlight_register(dev);
15219 }
15220
15221 void intel_connector_unregister(struct intel_connector *intel_connector)
15222 {
15223 struct drm_connector *connector = &intel_connector->base;
15224
15225 intel_panel_destroy_backlight(connector);
15226 drm_connector_unregister(connector);
15227 }
15228
15229 void intel_modeset_cleanup(struct drm_device *dev)
15230 {
15231 struct drm_i915_private *dev_priv = dev->dev_private;
15232 struct drm_connector *connector;
15233
15234 intel_disable_gt_powersave(dev);
15235
15236 intel_backlight_unregister(dev);
15237
15238 /*
15239 * Interrupts and polling as the first thing to avoid creating havoc.
15240 * Too much stuff here (turning of connectors, ...) would
15241 * experience fancy races otherwise.
15242 */
15243 intel_irq_uninstall(dev_priv);
15244
15245 /*
15246 * Due to the hpd irq storm handling the hotplug work can re-arm the
15247 * poll handlers. Hence disable polling after hpd handling is shut down.
15248 */
15249 drm_kms_helper_poll_fini(dev);
15250
15251 mutex_lock(&dev->struct_mutex);
15252
15253 intel_unregister_dsm_handler();
15254
15255 intel_fbc_disable(dev);
15256
15257 mutex_unlock(&dev->struct_mutex);
15258
15259 /* flush any delayed tasks or pending work */
15260 flush_scheduled_work();
15261
15262 /* destroy the backlight and sysfs files before encoders/connectors */
15263 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15264 struct intel_connector *intel_connector;
15265
15266 intel_connector = to_intel_connector(connector);
15267 intel_connector->unregister(intel_connector);
15268 }
15269
15270 drm_mode_config_cleanup(dev);
15271
15272 intel_cleanup_overlay(dev);
15273
15274 mutex_lock(&dev->struct_mutex);
15275 intel_cleanup_gt_powersave(dev);
15276 mutex_unlock(&dev->struct_mutex);
15277 }
15278
15279 /*
15280 * Return which encoder is currently attached for connector.
15281 */
15282 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15283 {
15284 return &intel_attached_encoder(connector)->base;
15285 }
15286
15287 void intel_connector_attach_encoder(struct intel_connector *connector,
15288 struct intel_encoder *encoder)
15289 {
15290 connector->encoder = encoder;
15291 drm_mode_connector_attach_encoder(&connector->base,
15292 &encoder->base);
15293 }
15294
15295 /*
15296 * set vga decode state - true == enable VGA decode
15297 */
15298 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15299 {
15300 struct drm_i915_private *dev_priv = dev->dev_private;
15301 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15302 u16 gmch_ctrl;
15303
15304 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15305 DRM_ERROR("failed to read control word\n");
15306 return -EIO;
15307 }
15308
15309 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15310 return 0;
15311
15312 if (state)
15313 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15314 else
15315 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15316
15317 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15318 DRM_ERROR("failed to write control word\n");
15319 return -EIO;
15320 }
15321
15322 return 0;
15323 }
15324
15325 struct intel_display_error_state {
15326
15327 u32 power_well_driver;
15328
15329 int num_transcoders;
15330
15331 struct intel_cursor_error_state {
15332 u32 control;
15333 u32 position;
15334 u32 base;
15335 u32 size;
15336 } cursor[I915_MAX_PIPES];
15337
15338 struct intel_pipe_error_state {
15339 bool power_domain_on;
15340 u32 source;
15341 u32 stat;
15342 } pipe[I915_MAX_PIPES];
15343
15344 struct intel_plane_error_state {
15345 u32 control;
15346 u32 stride;
15347 u32 size;
15348 u32 pos;
15349 u32 addr;
15350 u32 surface;
15351 u32 tile_offset;
15352 } plane[I915_MAX_PIPES];
15353
15354 struct intel_transcoder_error_state {
15355 bool power_domain_on;
15356 enum transcoder cpu_transcoder;
15357
15358 u32 conf;
15359
15360 u32 htotal;
15361 u32 hblank;
15362 u32 hsync;
15363 u32 vtotal;
15364 u32 vblank;
15365 u32 vsync;
15366 } transcoder[4];
15367 };
15368
15369 struct intel_display_error_state *
15370 intel_display_capture_error_state(struct drm_device *dev)
15371 {
15372 struct drm_i915_private *dev_priv = dev->dev_private;
15373 struct intel_display_error_state *error;
15374 int transcoders[] = {
15375 TRANSCODER_A,
15376 TRANSCODER_B,
15377 TRANSCODER_C,
15378 TRANSCODER_EDP,
15379 };
15380 int i;
15381
15382 if (INTEL_INFO(dev)->num_pipes == 0)
15383 return NULL;
15384
15385 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15386 if (error == NULL)
15387 return NULL;
15388
15389 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15390 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15391
15392 for_each_pipe(dev_priv, i) {
15393 error->pipe[i].power_domain_on =
15394 __intel_display_power_is_enabled(dev_priv,
15395 POWER_DOMAIN_PIPE(i));
15396 if (!error->pipe[i].power_domain_on)
15397 continue;
15398
15399 error->cursor[i].control = I915_READ(CURCNTR(i));
15400 error->cursor[i].position = I915_READ(CURPOS(i));
15401 error->cursor[i].base = I915_READ(CURBASE(i));
15402
15403 error->plane[i].control = I915_READ(DSPCNTR(i));
15404 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15405 if (INTEL_INFO(dev)->gen <= 3) {
15406 error->plane[i].size = I915_READ(DSPSIZE(i));
15407 error->plane[i].pos = I915_READ(DSPPOS(i));
15408 }
15409 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15410 error->plane[i].addr = I915_READ(DSPADDR(i));
15411 if (INTEL_INFO(dev)->gen >= 4) {
15412 error->plane[i].surface = I915_READ(DSPSURF(i));
15413 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15414 }
15415
15416 error->pipe[i].source = I915_READ(PIPESRC(i));
15417
15418 if (HAS_GMCH_DISPLAY(dev))
15419 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15420 }
15421
15422 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15423 if (HAS_DDI(dev_priv->dev))
15424 error->num_transcoders++; /* Account for eDP. */
15425
15426 for (i = 0; i < error->num_transcoders; i++) {
15427 enum transcoder cpu_transcoder = transcoders[i];
15428
15429 error->transcoder[i].power_domain_on =
15430 __intel_display_power_is_enabled(dev_priv,
15431 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15432 if (!error->transcoder[i].power_domain_on)
15433 continue;
15434
15435 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15436
15437 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15438 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15439 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15440 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15441 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15442 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15443 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15444 }
15445
15446 return error;
15447 }
15448
15449 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15450
15451 void
15452 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15453 struct drm_device *dev,
15454 struct intel_display_error_state *error)
15455 {
15456 struct drm_i915_private *dev_priv = dev->dev_private;
15457 int i;
15458
15459 if (!error)
15460 return;
15461
15462 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15463 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15464 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15465 error->power_well_driver);
15466 for_each_pipe(dev_priv, i) {
15467 err_printf(m, "Pipe [%d]:\n", i);
15468 err_printf(m, " Power: %s\n",
15469 error->pipe[i].power_domain_on ? "on" : "off");
15470 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15471 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15472
15473 err_printf(m, "Plane [%d]:\n", i);
15474 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15475 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15476 if (INTEL_INFO(dev)->gen <= 3) {
15477 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15478 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15479 }
15480 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15481 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15482 if (INTEL_INFO(dev)->gen >= 4) {
15483 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15484 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15485 }
15486
15487 err_printf(m, "Cursor [%d]:\n", i);
15488 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15489 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15490 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15491 }
15492
15493 for (i = 0; i < error->num_transcoders; i++) {
15494 err_printf(m, "CPU transcoder: %c\n",
15495 transcoder_name(error->transcoder[i].cpu_transcoder));
15496 err_printf(m, " Power: %s\n",
15497 error->transcoder[i].power_domain_on ? "on" : "off");
15498 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15499 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15500 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15501 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15502 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15503 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15504 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15505 }
15506 }
15507
15508 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15509 {
15510 struct intel_crtc *crtc;
15511
15512 for_each_intel_crtc(dev, crtc) {
15513 struct intel_unpin_work *work;
15514
15515 spin_lock_irq(&dev->event_lock);
15516
15517 work = crtc->unpin_work;
15518
15519 if (work && work->event &&
15520 work->event->base.file_priv == file) {
15521 kfree(work->event);
15522 work->event = NULL;
15523 }
15524
15525 spin_unlock_irq(&dev->event_lock);
15526 }
15527 }
Linux with added FPC-III support