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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_drv.h
blob105928382e216239043faf4e651d10520c92b678
1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
39
40 /**
41 * _wait_for - magic (register) wait macro
42 *
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
47 */
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
50 int ret__ = 0; \
51 while (!(COND)) { \
52 if (time_after(jiffies, timeout__)) { \
53 if (!(COND)) \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
59 } else { \
60 cpu_relax(); \
61 } \
62 } \
63 ret__; \
64 })
65
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
70
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
73
74 /*
75 * Display related stuff
76 */
77
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
81 #define MAX_OUTPUTS 6
82 /* maximum connectors per crtcs in the mode set */
83
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
89
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
92
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_DVO = 2,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
108 };
109
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
114
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
117
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
121 };
122
123 struct intel_fbdev {
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
128 int preferred_bpp;
129 };
130
131 struct intel_encoder {
132 struct drm_encoder base;
133 /*
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
136 */
137 struct intel_crtc *new_crtc;
138
139 enum intel_output_type type;
140 unsigned int cloneable;
141 bool connectors_active;
142 void (*hot_plug)(struct intel_encoder *);
143 bool (*compute_config)(struct intel_encoder *,
144 struct intel_crtc_state *);
145 void (*pre_pll_enable)(struct intel_encoder *);
146 void (*pre_enable)(struct intel_encoder *);
147 void (*enable)(struct intel_encoder *);
148 void (*mode_set)(struct intel_encoder *intel_encoder);
149 void (*disable)(struct intel_encoder *);
150 void (*post_disable)(struct intel_encoder *);
151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
155 /* Reconstructs the equivalent mode flags for the current hardware
156 * state. This must be called _after_ display->get_pipe_config has
157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
159 void (*get_config)(struct intel_encoder *,
160 struct intel_crtc_state *pipe_config);
161 /*
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
165 */
166 void (*suspend)(struct intel_encoder *);
167 int crtc_mask;
168 enum hpd_pin hpd_pin;
169 };
170
171 struct intel_panel {
172 struct drm_display_mode *fixed_mode;
173 struct drm_display_mode *downclock_mode;
174 int fitting_mode;
175
176 /* backlight */
177 struct {
178 bool present;
179 u32 level;
180 u32 min;
181 u32 max;
182 bool enabled;
183 bool combination_mode; /* gen 2/4 only */
184 bool active_low_pwm;
185 struct backlight_device *device;
186 } backlight;
187
188 void (*backlight_power)(struct intel_connector *, bool enable);
189 };
190
191 struct intel_connector {
192 struct drm_connector base;
193 /*
194 * The fixed encoder this connector is connected to.
195 */
196 struct intel_encoder *encoder;
197
198 /*
199 * The new encoder this connector will be driven. Only differs from
200 * encoder while a modeset is in progress.
201 */
202 struct intel_encoder *new_encoder;
203
204 /* Reads out the current hw, returning true if the connector is enabled
205 * and active (i.e. dpms ON state). */
206 bool (*get_hw_state)(struct intel_connector *);
207
208 /*
209 * Removes all interfaces through which the connector is accessible
210 * - like sysfs, debugfs entries -, so that no new operations can be
211 * started on the connector. Also makes sure all currently pending
212 * operations finish before returing.
213 */
214 void (*unregister)(struct intel_connector *);
215
216 /* Panel info for eDP and LVDS */
217 struct intel_panel panel;
218
219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
220 struct edid *edid;
221 struct edid *detect_edid;
222
223 /* since POLL and HPD connectors may use the same HPD line keep the native
224 state of connector->polled in case hotplug storm detection changes it */
225 u8 polled;
226
227 void *port; /* store this opaque as its illegal to dereference it */
228
229 struct intel_dp *mst_port;
230 };
231
232 typedef struct dpll {
233 /* given values */
234 int n;
235 int m1, m2;
236 int p1, p2;
237 /* derived values */
238 int dot;
239 int vco;
240 int m;
241 int p;
242 } intel_clock_t;
243
244 struct intel_plane_state {
245 struct drm_plane_state base;
246 struct drm_rect src;
247 struct drm_rect dst;
248 struct drm_rect clip;
249 bool visible;
250
251 /*
252 * scaler_id
253 * = -1 : not using a scaler
254 * >= 0 : using a scalers
255 *
256 * plane requiring a scaler:
257 * - During check_plane, its bit is set in
258 * crtc_state->scaler_state.scaler_users by calling helper function
259 * update_scaler_users.
260 * - scaler_id indicates the scaler it got assigned.
261 *
262 * plane doesn't require a scaler:
263 * - this can happen when scaling is no more required or plane simply
264 * got disabled.
265 * - During check_plane, corresponding bit is reset in
266 * crtc_state->scaler_state.scaler_users by calling helper function
267 * update_scaler_users.
268 */
269 int scaler_id;
270 };
271
272 struct intel_initial_plane_config {
273 struct intel_framebuffer *fb;
274 unsigned int tiling;
275 int size;
276 u32 base;
277 };
278
279 #define SKL_MIN_SRC_W 8
280 #define SKL_MAX_SRC_W 4096
281 #define SKL_MIN_SRC_H 8
282 #define SKL_MAX_SRC_H 4096
283 #define SKL_MIN_DST_W 8
284 #define SKL_MAX_DST_W 4096
285 #define SKL_MIN_DST_H 8
286 #define SKL_MAX_DST_H 4096
287
288 struct intel_scaler {
289 int id;
290 int in_use;
291 uint32_t mode;
292 };
293
294 struct intel_crtc_scaler_state {
295 #define SKL_NUM_SCALERS 2
296 struct intel_scaler scalers[SKL_NUM_SCALERS];
297
298 /*
299 * scaler_users: keeps track of users requesting scalers on this crtc.
300 *
301 * If a bit is set, a user is using a scaler.
302 * Here user can be a plane or crtc as defined below:
303 * bits 0-30 - plane (bit position is index from drm_plane_index)
304 * bit 31 - crtc
305 *
306 * Instead of creating a new index to cover planes and crtc, using
307 * existing drm_plane_index for planes which is well less than 31
308 * planes and bit 31 for crtc. This should be fine to cover all
309 * our platforms.
310 *
311 * intel_atomic_setup_scalers will setup available scalers to users
312 * requesting scalers. It will gracefully fail if request exceeds
313 * avilability.
314 */
315 #define SKL_CRTC_INDEX 31
316 unsigned scaler_users;
317
318 /* scaler used by crtc for panel fitting purpose */
319 int scaler_id;
320 };
321
322 struct intel_crtc_state {
323 struct drm_crtc_state base;
324
325 /**
326 * quirks - bitfield with hw state readout quirks
327 *
328 * For various reasons the hw state readout code might not be able to
329 * completely faithfully read out the current state. These cases are
330 * tracked with quirk flags so that fastboot and state checker can act
331 * accordingly.
332 */
333 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
334 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
335 unsigned long quirks;
336
337 /* Pipe source size (ie. panel fitter input size)
338 * All planes will be positioned inside this space,
339 * and get clipped at the edges. */
340 int pipe_src_w, pipe_src_h;
341
342 /* Whether to set up the PCH/FDI. Note that we never allow sharing
343 * between pch encoders and cpu encoders. */
344 bool has_pch_encoder;
345
346 /* Are we sending infoframes on the attached port */
347 bool has_infoframe;
348
349 /* CPU Transcoder for the pipe. Currently this can only differ from the
350 * pipe on Haswell (where we have a special eDP transcoder). */
351 enum transcoder cpu_transcoder;
352
353 /*
354 * Use reduced/limited/broadcast rbg range, compressing from the full
355 * range fed into the crtcs.
356 */
357 bool limited_color_range;
358
359 /* DP has a bunch of special case unfortunately, so mark the pipe
360 * accordingly. */
361 bool has_dp_encoder;
362
363 /* Whether we should send NULL infoframes. Required for audio. */
364 bool has_hdmi_sink;
365
366 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
367 * has_dp_encoder is set. */
368 bool has_audio;
369
370 /*
371 * Enable dithering, used when the selected pipe bpp doesn't match the
372 * plane bpp.
373 */
374 bool dither;
375
376 /* Controls for the clock computation, to override various stages. */
377 bool clock_set;
378
379 /* SDVO TV has a bunch of special case. To make multifunction encoders
380 * work correctly, we need to track this at runtime.*/
381 bool sdvo_tv_clock;
382
383 /*
384 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
385 * required. This is set in the 2nd loop of calling encoder's
386 * ->compute_config if the first pick doesn't work out.
387 */
388 bool bw_constrained;
389
390 /* Settings for the intel dpll used on pretty much everything but
391 * haswell. */
392 struct dpll dpll;
393
394 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
395 enum intel_dpll_id shared_dpll;
396
397 /*
398 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
399 * - enum skl_dpll on SKL
400 */
401 uint32_t ddi_pll_sel;
402
403 /* Actual register state of the dpll, for shared dpll cross-checking. */
404 struct intel_dpll_hw_state dpll_hw_state;
405
406 int pipe_bpp;
407 struct intel_link_m_n dp_m_n;
408
409 /* m2_n2 for eDP downclock */
410 struct intel_link_m_n dp_m2_n2;
411 bool has_drrs;
412
413 /*
414 * Frequence the dpll for the port should run at. Differs from the
415 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
416 * already multiplied by pixel_multiplier.
417 */
418 int port_clock;
419
420 /* Used by SDVO (and if we ever fix it, HDMI). */
421 unsigned pixel_multiplier;
422
423 /* Panel fitter controls for gen2-gen4 + VLV */
424 struct {
425 u32 control;
426 u32 pgm_ratios;
427 u32 lvds_border_bits;
428 } gmch_pfit;
429
430 /* Panel fitter placement and size for Ironlake+ */
431 struct {
432 u32 pos;
433 u32 size;
434 bool enabled;
435 bool force_thru;
436 } pch_pfit;
437
438 /* FDI configuration, only valid if has_pch_encoder is set. */
439 int fdi_lanes;
440 struct intel_link_m_n fdi_m_n;
441
442 bool ips_enabled;
443
444 bool double_wide;
445
446 bool dp_encoder_is_mst;
447 int pbn;
448
449 struct intel_crtc_scaler_state scaler_state;
450 };
451
452 struct intel_pipe_wm {
453 struct intel_wm_level wm[5];
454 uint32_t linetime;
455 bool fbc_wm_enabled;
456 bool pipe_enabled;
457 bool sprites_enabled;
458 bool sprites_scaled;
459 };
460
461 struct intel_mmio_flip {
462 struct work_struct work;
463 struct drm_i915_private *i915;
464 struct drm_i915_gem_request *req;
465 struct intel_crtc *crtc;
466 };
467
468 struct skl_pipe_wm {
469 struct skl_wm_level wm[8];
470 struct skl_wm_level trans_wm;
471 uint32_t linetime;
472 };
473
474 /*
475 * Tracking of operations that need to be performed at the beginning/end of an
476 * atomic commit, outside the atomic section where interrupts are disabled.
477 * These are generally operations that grab mutexes or might otherwise sleep
478 * and thus can't be run with interrupts disabled.
479 */
480 struct intel_crtc_atomic_commit {
481 /* vblank evasion */
482 bool evade;
483 unsigned start_vbl_count;
484
485 /* Sleepable operations to perform before commit */
486 bool wait_for_flips;
487 bool disable_fbc;
488 bool disable_ips;
489 bool pre_disable_primary;
490 bool update_wm;
491 unsigned disabled_planes;
492
493 /* Sleepable operations to perform after commit */
494 unsigned fb_bits;
495 bool wait_vblank;
496 bool update_fbc;
497 bool post_enable_primary;
498 unsigned update_sprite_watermarks;
499 };
500
501 struct intel_crtc {
502 struct drm_crtc base;
503 enum pipe pipe;
504 enum plane plane;
505 u8 lut_r[256], lut_g[256], lut_b[256];
506 /*
507 * Whether the crtc and the connected output pipeline is active. Implies
508 * that crtc->enabled is set, i.e. the current mode configuration has
509 * some outputs connected to this crtc.
510 */
511 bool active;
512 unsigned long enabled_power_domains;
513 bool lowfreq_avail;
514 struct intel_overlay *overlay;
515 struct intel_unpin_work *unpin_work;
516
517 atomic_t unpin_work_count;
518
519 /* Display surface base address adjustement for pageflips. Note that on
520 * gen4+ this only adjusts up to a tile, offsets within a tile are
521 * handled in the hw itself (with the TILEOFF register). */
522 unsigned long dspaddr_offset;
523
524 struct drm_i915_gem_object *cursor_bo;
525 uint32_t cursor_addr;
526 uint32_t cursor_cntl;
527 uint32_t cursor_size;
528 uint32_t cursor_base;
529
530 struct intel_initial_plane_config plane_config;
531 struct intel_crtc_state *config;
532 bool new_enabled;
533
534 /* reset counter value when the last flip was submitted */
535 unsigned int reset_counter;
536
537 /* Access to these should be protected by dev_priv->irq_lock. */
538 bool cpu_fifo_underrun_disabled;
539 bool pch_fifo_underrun_disabled;
540
541 /* per-pipe watermark state */
542 struct {
543 /* watermarks currently being used */
544 struct intel_pipe_wm active;
545 /* SKL wm values currently in use */
546 struct skl_pipe_wm skl_active;
547 } wm;
548
549 int scanline_offset;
550
551 struct intel_crtc_atomic_commit atomic;
552
553 /* scalers available on this crtc */
554 int num_scalers;
555 };
556
557 struct intel_plane_wm_parameters {
558 uint32_t horiz_pixels;
559 uint32_t vert_pixels;
560 /*
561 * For packed pixel formats:
562 * bytes_per_pixel - holds bytes per pixel
563 * For planar pixel formats:
564 * bytes_per_pixel - holds bytes per pixel for uv-plane
565 * y_bytes_per_pixel - holds bytes per pixel for y-plane
566 */
567 uint8_t bytes_per_pixel;
568 uint8_t y_bytes_per_pixel;
569 bool enabled;
570 bool scaled;
571 u64 tiling;
572 unsigned int rotation;
573 };
574
575 struct intel_plane {
576 struct drm_plane base;
577 int plane;
578 enum pipe pipe;
579 bool can_scale;
580 int max_downscale;
581
582 /* FIXME convert to properties */
583 struct drm_intel_sprite_colorkey ckey;
584
585 /* Since we need to change the watermarks before/after
586 * enabling/disabling the planes, we need to store the parameters here
587 * as the other pieces of the struct may not reflect the values we want
588 * for the watermark calculations. Currently only Haswell uses this.
589 */
590 struct intel_plane_wm_parameters wm;
591
592 /*
593 * NOTE: Do not place new plane state fields here (e.g., when adding
594 * new plane properties). New runtime state should now be placed in
595 * the intel_plane_state structure and accessed via drm_plane->state.
596 */
597
598 void (*update_plane)(struct drm_plane *plane,
599 struct drm_crtc *crtc,
600 struct drm_framebuffer *fb,
601 int crtc_x, int crtc_y,
602 unsigned int crtc_w, unsigned int crtc_h,
603 uint32_t x, uint32_t y,
604 uint32_t src_w, uint32_t src_h);
605 void (*disable_plane)(struct drm_plane *plane,
606 struct drm_crtc *crtc, bool force);
607 int (*check_plane)(struct drm_plane *plane,
608 struct intel_plane_state *state);
609 void (*commit_plane)(struct drm_plane *plane,
610 struct intel_plane_state *state);
611 };
612
613 struct intel_watermark_params {
614 unsigned long fifo_size;
615 unsigned long max_wm;
616 unsigned long default_wm;
617 unsigned long guard_size;
618 unsigned long cacheline_size;
619 };
620
621 struct cxsr_latency {
622 int is_desktop;
623 int is_ddr3;
624 unsigned long fsb_freq;
625 unsigned long mem_freq;
626 unsigned long display_sr;
627 unsigned long display_hpll_disable;
628 unsigned long cursor_sr;
629 unsigned long cursor_hpll_disable;
630 };
631
632 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
633 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
634 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
635 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
636 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
637 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
638 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
639 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
640
641 struct intel_hdmi {
642 u32 hdmi_reg;
643 int ddc_bus;
644 uint32_t color_range;
645 bool color_range_auto;
646 bool has_hdmi_sink;
647 bool has_audio;
648 enum hdmi_force_audio force_audio;
649 bool rgb_quant_range_selectable;
650 enum hdmi_picture_aspect aspect_ratio;
651 void (*write_infoframe)(struct drm_encoder *encoder,
652 enum hdmi_infoframe_type type,
653 const void *frame, ssize_t len);
654 void (*set_infoframes)(struct drm_encoder *encoder,
655 bool enable,
656 struct drm_display_mode *adjusted_mode);
657 bool (*infoframe_enabled)(struct drm_encoder *encoder);
658 };
659
660 struct intel_dp_mst_encoder;
661 #define DP_MAX_DOWNSTREAM_PORTS 0x10
662
663 /*
664 * enum link_m_n_set:
665 * When platform provides two set of M_N registers for dp, we can
666 * program them and switch between them incase of DRRS.
667 * But When only one such register is provided, we have to program the
668 * required divider value on that registers itself based on the DRRS state.
669 *
670 * M1_N1 : Program dp_m_n on M1_N1 registers
671 * dp_m2_n2 on M2_N2 registers (If supported)
672 *
673 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
674 * M2_N2 registers are not supported
675 */
676
677 enum link_m_n_set {
678 /* Sets the m1_n1 and m2_n2 */
679 M1_N1 = 0,
680 M2_N2
681 };
682
683 struct intel_dp {
684 uint32_t output_reg;
685 uint32_t aux_ch_ctl_reg;
686 uint32_t DP;
687 bool has_audio;
688 enum hdmi_force_audio force_audio;
689 uint32_t color_range;
690 bool color_range_auto;
691 uint8_t link_bw;
692 uint8_t rate_select;
693 uint8_t lane_count;
694 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
695 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
696 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
697 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
698 uint8_t num_sink_rates;
699 int sink_rates[DP_MAX_SUPPORTED_RATES];
700 struct drm_dp_aux aux;
701 uint8_t train_set[4];
702 int panel_power_up_delay;
703 int panel_power_down_delay;
704 int panel_power_cycle_delay;
705 int backlight_on_delay;
706 int backlight_off_delay;
707 struct delayed_work panel_vdd_work;
708 bool want_panel_vdd;
709 unsigned long last_power_cycle;
710 unsigned long last_power_on;
711 unsigned long last_backlight_off;
712
713 struct notifier_block edp_notifier;
714
715 /*
716 * Pipe whose power sequencer is currently locked into
717 * this port. Only relevant on VLV/CHV.
718 */
719 enum pipe pps_pipe;
720 struct edp_power_seq pps_delays;
721
722 bool use_tps3;
723 bool can_mst; /* this port supports mst */
724 bool is_mst;
725 int active_mst_links;
726 /* connector directly attached - won't be use for modeset in mst world */
727 struct intel_connector *attached_connector;
728
729 /* mst connector list */
730 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
731 struct drm_dp_mst_topology_mgr mst_mgr;
732
733 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
734 /*
735 * This function returns the value we have to program the AUX_CTL
736 * register with to kick off an AUX transaction.
737 */
738 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
739 bool has_aux_irq,
740 int send_bytes,
741 uint32_t aux_clock_divider);
742 bool train_set_valid;
743
744 /* Displayport compliance testing */
745 unsigned long compliance_test_type;
746 unsigned long compliance_test_data;
747 bool compliance_test_active;
748 };
749
750 struct intel_digital_port {
751 struct intel_encoder base;
752 enum port port;
753 u32 saved_port_bits;
754 struct intel_dp dp;
755 struct intel_hdmi hdmi;
756 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
757 };
758
759 struct intel_dp_mst_encoder {
760 struct intel_encoder base;
761 enum pipe pipe;
762 struct intel_digital_port *primary;
763 void *port; /* store this opaque as its illegal to dereference it */
764 };
765
766 static inline int
767 vlv_dport_to_channel(struct intel_digital_port *dport)
768 {
769 switch (dport->port) {
770 case PORT_B:
771 case PORT_D:
772 return DPIO_CH0;
773 case PORT_C:
774 return DPIO_CH1;
775 default:
776 BUG();
777 }
778 }
779
780 static inline int
781 vlv_pipe_to_channel(enum pipe pipe)
782 {
783 switch (pipe) {
784 case PIPE_A:
785 case PIPE_C:
786 return DPIO_CH0;
787 case PIPE_B:
788 return DPIO_CH1;
789 default:
790 BUG();
791 }
792 }
793
794 static inline struct drm_crtc *
795 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
796 {
797 struct drm_i915_private *dev_priv = dev->dev_private;
798 return dev_priv->pipe_to_crtc_mapping[pipe];
799 }
800
801 static inline struct drm_crtc *
802 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
803 {
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 return dev_priv->plane_to_crtc_mapping[plane];
806 }
807
808 struct intel_unpin_work {
809 struct work_struct work;
810 struct drm_crtc *crtc;
811 struct drm_framebuffer *old_fb;
812 struct drm_i915_gem_object *pending_flip_obj;
813 struct drm_pending_vblank_event *event;
814 atomic_t pending;
815 #define INTEL_FLIP_INACTIVE 0
816 #define INTEL_FLIP_PENDING 1
817 #define INTEL_FLIP_COMPLETE 2
818 u32 flip_count;
819 u32 gtt_offset;
820 struct drm_i915_gem_request *flip_queued_req;
821 int flip_queued_vblank;
822 int flip_ready_vblank;
823 bool enable_stall_check;
824 };
825
826 struct intel_load_detect_pipe {
827 struct drm_framebuffer *release_fb;
828 bool load_detect_temp;
829 int dpms_mode;
830 };
831
832 static inline struct intel_encoder *
833 intel_attached_encoder(struct drm_connector *connector)
834 {
835 return to_intel_connector(connector)->encoder;
836 }
837
838 static inline struct intel_digital_port *
839 enc_to_dig_port(struct drm_encoder *encoder)
840 {
841 return container_of(encoder, struct intel_digital_port, base.base);
842 }
843
844 static inline struct intel_dp_mst_encoder *
845 enc_to_mst(struct drm_encoder *encoder)
846 {
847 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
848 }
849
850 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
851 {
852 return &enc_to_dig_port(encoder)->dp;
853 }
854
855 static inline struct intel_digital_port *
856 dp_to_dig_port(struct intel_dp *intel_dp)
857 {
858 return container_of(intel_dp, struct intel_digital_port, dp);
859 }
860
861 static inline struct intel_digital_port *
862 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
863 {
864 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
865 }
866
867 /*
868 * Returns the number of planes for this pipe, ie the number of sprites + 1
869 * (primary plane). This doesn't count the cursor plane then.
870 */
871 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
872 {
873 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
874 }
875
876 /* intel_fifo_underrun.c */
877 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
878 enum pipe pipe, bool enable);
879 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
880 enum transcoder pch_transcoder,
881 bool enable);
882 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
883 enum pipe pipe);
884 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
885 enum transcoder pch_transcoder);
886 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
887
888 /* i915_irq.c */
889 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
890 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
891 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
892 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
893 void gen6_reset_rps_interrupts(struct drm_device *dev);
894 void gen6_enable_rps_interrupts(struct drm_device *dev);
895 void gen6_disable_rps_interrupts(struct drm_device *dev);
896 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
897 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
898 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
899 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
900 {
901 /*
902 * We only use drm_irq_uninstall() at unload and VT switch, so
903 * this is the only thing we need to check.
904 */
905 return dev_priv->pm.irqs_enabled;
906 }
907
908 int intel_get_crtc_scanline(struct intel_crtc *crtc);
909 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
910 unsigned int pipe_mask);
911
912 /* intel_crt.c */
913 void intel_crt_init(struct drm_device *dev);
914
915
916 /* intel_ddi.c */
917 void intel_prepare_ddi(struct drm_device *dev);
918 void hsw_fdi_link_train(struct drm_crtc *crtc);
919 void intel_ddi_init(struct drm_device *dev, enum port port);
920 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
921 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
922 void intel_ddi_pll_init(struct drm_device *dev);
923 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
924 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
925 enum transcoder cpu_transcoder);
926 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
927 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
928 bool intel_ddi_pll_select(struct intel_crtc *crtc,
929 struct intel_crtc_state *crtc_state);
930 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
931 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
932 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
933 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
934 void intel_ddi_get_config(struct intel_encoder *encoder,
935 struct intel_crtc_state *pipe_config);
936 struct intel_encoder *
937 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
938
939 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
940 void intel_ddi_clock_get(struct intel_encoder *encoder,
941 struct intel_crtc_state *pipe_config);
942 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
943 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
944 enum port port, int type);
945
946 /* intel_frontbuffer.c */
947 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
948 struct intel_engine_cs *ring,
949 enum fb_op_origin origin);
950 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
951 unsigned frontbuffer_bits);
952 void intel_frontbuffer_flip_complete(struct drm_device *dev,
953 unsigned frontbuffer_bits);
954 void intel_frontbuffer_flush(struct drm_device *dev,
955 unsigned frontbuffer_bits);
956 /**
957 * intel_frontbuffer_flip - synchronous frontbuffer flip
958 * @dev: DRM device
959 * @frontbuffer_bits: frontbuffer plane tracking bits
960 *
961 * This function gets called after scheduling a flip on @obj. This is for
962 * synchronous plane updates which will happen on the next vblank and which will
963 * not get delayed by pending gpu rendering.
964 *
965 * Can be called without any locks held.
966 */
967 static inline
968 void intel_frontbuffer_flip(struct drm_device *dev,
969 unsigned frontbuffer_bits)
970 {
971 intel_frontbuffer_flush(dev, frontbuffer_bits);
972 }
973
974 unsigned int intel_fb_align_height(struct drm_device *dev,
975 unsigned int height,
976 uint32_t pixel_format,
977 uint64_t fb_format_modifier);
978 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
979
980 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
981 uint32_t pixel_format);
982
983 /* intel_audio.c */
984 void intel_init_audio(struct drm_device *dev);
985 void intel_audio_codec_enable(struct intel_encoder *encoder);
986 void intel_audio_codec_disable(struct intel_encoder *encoder);
987 void i915_audio_component_init(struct drm_i915_private *dev_priv);
988 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
989
990 /* intel_display.c */
991 extern const struct drm_plane_funcs intel_plane_funcs;
992 bool intel_has_pending_fb_unpin(struct drm_device *dev);
993 int intel_pch_rawclk(struct drm_device *dev);
994 void intel_mark_busy(struct drm_device *dev);
995 void intel_mark_idle(struct drm_device *dev);
996 void intel_crtc_restore_mode(struct drm_crtc *crtc);
997 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
998 void intel_crtc_reset(struct intel_crtc *crtc);
999 void intel_crtc_update_dpms(struct drm_crtc *crtc);
1000 void intel_encoder_destroy(struct drm_encoder *encoder);
1001 int intel_connector_init(struct intel_connector *);
1002 struct intel_connector *intel_connector_alloc(void);
1003 void intel_connector_dpms(struct drm_connector *, int mode);
1004 bool intel_connector_get_hw_state(struct intel_connector *connector);
1005 void intel_modeset_check_state(struct drm_device *dev);
1006 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1007 struct intel_digital_port *port);
1008 void intel_connector_attach_encoder(struct intel_connector *connector,
1009 struct intel_encoder *encoder);
1010 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1011 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1012 struct drm_crtc *crtc);
1013 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1014 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1015 struct drm_file *file_priv);
1016 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1017 enum pipe pipe);
1018 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1019 static inline void
1020 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1021 {
1022 drm_wait_one_vblank(dev, pipe);
1023 }
1024 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1025 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1026 struct intel_digital_port *dport,
1027 unsigned int expected_mask);
1028 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1029 struct drm_display_mode *mode,
1030 struct intel_load_detect_pipe *old,
1031 struct drm_modeset_acquire_ctx *ctx);
1032 void intel_release_load_detect_pipe(struct drm_connector *connector,
1033 struct intel_load_detect_pipe *old,
1034 struct drm_modeset_acquire_ctx *ctx);
1035 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1036 struct drm_framebuffer *fb,
1037 const struct drm_plane_state *plane_state,
1038 struct intel_engine_cs *pipelined);
1039 struct drm_framebuffer *
1040 __intel_framebuffer_create(struct drm_device *dev,
1041 struct drm_mode_fb_cmd2 *mode_cmd,
1042 struct drm_i915_gem_object *obj);
1043 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1044 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1045 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1046 void intel_check_page_flip(struct drm_device *dev, int pipe);
1047 int intel_prepare_plane_fb(struct drm_plane *plane,
1048 struct drm_framebuffer *fb,
1049 const struct drm_plane_state *new_state);
1050 void intel_cleanup_plane_fb(struct drm_plane *plane,
1051 struct drm_framebuffer *fb,
1052 const struct drm_plane_state *old_state);
1053 int intel_plane_atomic_get_property(struct drm_plane *plane,
1054 const struct drm_plane_state *state,
1055 struct drm_property *property,
1056 uint64_t *val);
1057 int intel_plane_atomic_set_property(struct drm_plane *plane,
1058 struct drm_plane_state *state,
1059 struct drm_property *property,
1060 uint64_t val);
1061
1062 unsigned int
1063 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1064 uint64_t fb_format_modifier);
1065
1066 static inline bool
1067 intel_rotation_90_or_270(unsigned int rotation)
1068 {
1069 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1070 }
1071
1072 void intel_create_rotation_property(struct drm_device *dev,
1073 struct intel_plane *plane);
1074
1075 bool intel_wm_need_update(struct drm_plane *plane,
1076 struct drm_plane_state *state);
1077
1078 /* shared dpll functions */
1079 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1080 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1081 struct intel_shared_dpll *pll,
1082 bool state);
1083 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1084 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1085 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1086 struct intel_crtc_state *state);
1087 void intel_put_shared_dpll(struct intel_crtc *crtc);
1088
1089 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1090 const struct dpll *dpll);
1091 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1092
1093 /* modesetting asserts */
1094 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1095 enum pipe pipe);
1096 void assert_pll(struct drm_i915_private *dev_priv,
1097 enum pipe pipe, bool state);
1098 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1099 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1100 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state);
1102 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1103 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1104 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1105 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1106 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1107 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1108 unsigned int tiling_mode,
1109 unsigned int bpp,
1110 unsigned int pitch);
1111 void intel_prepare_reset(struct drm_device *dev);
1112 void intel_finish_reset(struct drm_device *dev);
1113 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1114 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1115 void broxton_init_cdclk(struct drm_device *dev);
1116 void broxton_uninit_cdclk(struct drm_device *dev);
1117 void broxton_set_cdclk(struct drm_device *dev, int frequency);
1118 void broxton_ddi_phy_init(struct drm_device *dev);
1119 void broxton_ddi_phy_uninit(struct drm_device *dev);
1120 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1121 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1122 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1123 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1124 void intel_dp_get_m_n(struct intel_crtc *crtc,
1125 struct intel_crtc_state *pipe_config);
1126 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1127 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1128 void
1129 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1130 int dotclock);
1131 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1132 intel_clock_t *best_clock);
1133 bool intel_crtc_active(struct drm_crtc *crtc);
1134 void hsw_enable_ips(struct intel_crtc *crtc);
1135 void hsw_disable_ips(struct intel_crtc *crtc);
1136 enum intel_display_power_domain
1137 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1138 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1139 struct intel_crtc_state *pipe_config);
1140 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1141 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1142 void skl_detach_scalers(struct intel_crtc *intel_crtc);
1143 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1144 struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1145 struct intel_plane_state *plane_state, int force_detach);
1146 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1147
1148 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1149 struct drm_i915_gem_object *obj);
1150 u32 skl_plane_ctl_format(uint32_t pixel_format);
1151 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1152 u32 skl_plane_ctl_rotation(unsigned int rotation);
1153
1154 /* intel_csr.c */
1155 void intel_csr_ucode_init(struct drm_device *dev);
1156 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1157 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1158 enum csr_state state);
1159 void intel_csr_load_program(struct drm_device *dev);
1160 void intel_csr_ucode_fini(struct drm_device *dev);
1161 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1162
1163 /* intel_dp.c */
1164 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1165 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1166 struct intel_connector *intel_connector);
1167 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1168 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1169 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1170 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1171 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1172 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1173 bool intel_dp_compute_config(struct intel_encoder *encoder,
1174 struct intel_crtc_state *pipe_config);
1175 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1176 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1177 bool long_hpd);
1178 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1179 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1180 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1181 void intel_edp_panel_on(struct intel_dp *intel_dp);
1182 void intel_edp_panel_off(struct intel_dp *intel_dp);
1183 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1184 void intel_dp_mst_suspend(struct drm_device *dev);
1185 void intel_dp_mst_resume(struct drm_device *dev);
1186 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1187 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1188 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1189 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1190 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1191 void intel_plane_destroy(struct drm_plane *plane);
1192 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1193 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1194 void intel_edp_drrs_invalidate(struct drm_device *dev,
1195 unsigned frontbuffer_bits);
1196 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1197
1198 /* intel_dp_mst.c */
1199 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1200 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1201 /* intel_dsi.c */
1202 void intel_dsi_init(struct drm_device *dev);
1203
1204
1205 /* intel_dvo.c */
1206 void intel_dvo_init(struct drm_device *dev);
1207
1208
1209 /* legacy fbdev emulation in intel_fbdev.c */
1210 #ifdef CONFIG_DRM_I915_FBDEV
1211 extern int intel_fbdev_init(struct drm_device *dev);
1212 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1213 extern void intel_fbdev_fini(struct drm_device *dev);
1214 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1215 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1216 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1217 #else
1218 static inline int intel_fbdev_init(struct drm_device *dev)
1219 {
1220 return 0;
1221 }
1222
1223 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1224 {
1225 }
1226
1227 static inline void intel_fbdev_fini(struct drm_device *dev)
1228 {
1229 }
1230
1231 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1232 {
1233 }
1234
1235 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1236 {
1237 }
1238 #endif
1239
1240 /* intel_fbc.c */
1241 bool intel_fbc_enabled(struct drm_device *dev);
1242 void intel_fbc_update(struct drm_device *dev);
1243 void intel_fbc_init(struct drm_i915_private *dev_priv);
1244 void intel_fbc_disable(struct drm_device *dev);
1245 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1246 unsigned int frontbuffer_bits,
1247 enum fb_op_origin origin);
1248 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1249 unsigned int frontbuffer_bits);
1250
1251 /* intel_hdmi.c */
1252 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1253 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1254 struct intel_connector *intel_connector);
1255 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1256 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1257 struct intel_crtc_state *pipe_config);
1258
1259
1260 /* intel_lvds.c */
1261 void intel_lvds_init(struct drm_device *dev);
1262 bool intel_is_dual_link_lvds(struct drm_device *dev);
1263
1264
1265 /* intel_modes.c */
1266 int intel_connector_update_modes(struct drm_connector *connector,
1267 struct edid *edid);
1268 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1269 void intel_attach_force_audio_property(struct drm_connector *connector);
1270 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1271
1272
1273 /* intel_overlay.c */
1274 void intel_setup_overlay(struct drm_device *dev);
1275 void intel_cleanup_overlay(struct drm_device *dev);
1276 int intel_overlay_switch_off(struct intel_overlay *overlay);
1277 int intel_overlay_put_image(struct drm_device *dev, void *data,
1278 struct drm_file *file_priv);
1279 int intel_overlay_attrs(struct drm_device *dev, void *data,
1280 struct drm_file *file_priv);
1281 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1282
1283
1284 /* intel_panel.c */
1285 int intel_panel_init(struct intel_panel *panel,
1286 struct drm_display_mode *fixed_mode,
1287 struct drm_display_mode *downclock_mode);
1288 void intel_panel_fini(struct intel_panel *panel);
1289 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1290 struct drm_display_mode *adjusted_mode);
1291 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1292 struct intel_crtc_state *pipe_config,
1293 int fitting_mode);
1294 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1295 struct intel_crtc_state *pipe_config,
1296 int fitting_mode);
1297 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1298 u32 level, u32 max);
1299 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1300 void intel_panel_enable_backlight(struct intel_connector *connector);
1301 void intel_panel_disable_backlight(struct intel_connector *connector);
1302 void intel_panel_destroy_backlight(struct drm_connector *connector);
1303 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1304 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1305 extern struct drm_display_mode *intel_find_panel_downclock(
1306 struct drm_device *dev,
1307 struct drm_display_mode *fixed_mode,
1308 struct drm_connector *connector);
1309 void intel_backlight_register(struct drm_device *dev);
1310 void intel_backlight_unregister(struct drm_device *dev);
1311
1312
1313 /* intel_psr.c */
1314 void intel_psr_enable(struct intel_dp *intel_dp);
1315 void intel_psr_disable(struct intel_dp *intel_dp);
1316 void intel_psr_invalidate(struct drm_device *dev,
1317 unsigned frontbuffer_bits);
1318 void intel_psr_flush(struct drm_device *dev,
1319 unsigned frontbuffer_bits);
1320 void intel_psr_init(struct drm_device *dev);
1321 void intel_psr_single_frame_update(struct drm_device *dev);
1322
1323 /* intel_runtime_pm.c */
1324 int intel_power_domains_init(struct drm_i915_private *);
1325 void intel_power_domains_fini(struct drm_i915_private *);
1326 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1327 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1328
1329 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1330 enum intel_display_power_domain domain);
1331 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1332 enum intel_display_power_domain domain);
1333 void intel_display_power_get(struct drm_i915_private *dev_priv,
1334 enum intel_display_power_domain domain);
1335 void intel_display_power_put(struct drm_i915_private *dev_priv,
1336 enum intel_display_power_domain domain);
1337 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1338 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1339 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1340 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1341 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1342
1343 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1344
1345 /* intel_pm.c */
1346 void intel_init_clock_gating(struct drm_device *dev);
1347 void intel_suspend_hw(struct drm_device *dev);
1348 int ilk_wm_max_level(const struct drm_device *dev);
1349 void intel_update_watermarks(struct drm_crtc *crtc);
1350 void intel_update_sprite_watermarks(struct drm_plane *plane,
1351 struct drm_crtc *crtc,
1352 uint32_t sprite_width,
1353 uint32_t sprite_height,
1354 int pixel_size,
1355 bool enabled, bool scaled);
1356 void intel_init_pm(struct drm_device *dev);
1357 void intel_pm_setup(struct drm_device *dev);
1358 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1359 void intel_gpu_ips_teardown(void);
1360 void intel_init_gt_powersave(struct drm_device *dev);
1361 void intel_cleanup_gt_powersave(struct drm_device *dev);
1362 void intel_enable_gt_powersave(struct drm_device *dev);
1363 void intel_disable_gt_powersave(struct drm_device *dev);
1364 void intel_suspend_gt_powersave(struct drm_device *dev);
1365 void intel_reset_gt_powersave(struct drm_device *dev);
1366 void gen6_update_ring_freq(struct drm_device *dev);
1367 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1368 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1369 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1370 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1371 struct intel_rps_client *rps,
1372 unsigned long submitted);
1373 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1374 struct drm_i915_gem_request *req);
1375 void ilk_wm_get_hw_state(struct drm_device *dev);
1376 void skl_wm_get_hw_state(struct drm_device *dev);
1377 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1378 struct skl_ddb_allocation *ddb /* out */);
1379
1380
1381 /* intel_sdvo.c */
1382 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1383
1384
1385 /* intel_sprite.c */
1386 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1387 int intel_plane_restore(struct drm_plane *plane);
1388 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1389 struct drm_file *file_priv);
1390 bool intel_pipe_update_start(struct intel_crtc *crtc,
1391 uint32_t *start_vbl_count);
1392 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1393
1394 /* intel_tv.c */
1395 void intel_tv_init(struct drm_device *dev);
1396
1397 /* intel_atomic.c */
1398 int intel_atomic_check(struct drm_device *dev,
1399 struct drm_atomic_state *state);
1400 int intel_atomic_commit(struct drm_device *dev,
1401 struct drm_atomic_state *state,
1402 bool async);
1403 int intel_connector_atomic_get_property(struct drm_connector *connector,
1404 const struct drm_connector_state *state,
1405 struct drm_property *property,
1406 uint64_t *val);
1407 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1408 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1409 struct drm_crtc_state *state);
1410 static inline struct intel_crtc_state *
1411 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1412 struct intel_crtc *crtc)
1413 {
1414 struct drm_crtc_state *crtc_state;
1415 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1416 if (IS_ERR(crtc_state))
1417 return ERR_CAST(crtc_state);
1418
1419 return to_intel_crtc_state(crtc_state);
1420 }
1421 int intel_atomic_setup_scalers(struct drm_device *dev,
1422 struct intel_crtc *intel_crtc,
1423 struct intel_crtc_state *crtc_state);
1424
1425 /* intel_atomic_plane.c */
1426 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1427 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1428 void intel_plane_destroy_state(struct drm_plane *plane,
1429 struct drm_plane_state *state);
1430 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1431
1432 #endif /* __INTEL_DRV_H__ */
Linux with added FPC-III support