drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 struct gmbus_pin {
  38         const char *name;
  39         int reg;
  40 };
  41
  42 /* Map gmbus pin pairs to names and registers. */
  43 static const struct gmbus_pin gmbus_pins[] = {
  44         [GMBUS_PIN_SSC] = { "ssc", GPIOB },
  45         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  46         [GMBUS_PIN_PANEL] = { "panel", GPIOC },
  47         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  48         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  49         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  50 };
  51
  52 static const struct gmbus_pin gmbus_pins_bdw[] = {
  53         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  54         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  55         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  56         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  57 };
  58
  59 static const struct gmbus_pin gmbus_pins_skl[] = {
  60         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  61         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  62         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  63 };
  64
  65 static const struct gmbus_pin gmbus_pins_bxt[] = {
  66         [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
  67         [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
  68         [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
  69 };
  70
  71 /* pin is expected to be valid */
  72 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
  73                                              unsigned int pin)
  74 {
  75         if (IS_BROXTON(dev_priv))
  76                 return &gmbus_pins_bxt[pin];
  77         else if (IS_SKYLAKE(dev_priv))
  78                 return &gmbus_pins_skl[pin];
  79         else if (IS_BROADWELL(dev_priv))
  80                 return &gmbus_pins_bdw[pin];
  81         else
  82                 return &gmbus_pins[pin];
  83 }
  84
  85 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
  86                               unsigned int pin)
  87 {
  88         unsigned int size;
  89
  90         if (IS_BROXTON(dev_priv))
  91                 size = ARRAY_SIZE(gmbus_pins_bxt);
  92         else if (IS_SKYLAKE(dev_priv))
  93                 size = ARRAY_SIZE(gmbus_pins_skl);
  94         else if (IS_BROADWELL(dev_priv))
  95                 size = ARRAY_SIZE(gmbus_pins_bdw);
  96         else
  97                 size = ARRAY_SIZE(gmbus_pins);
  98
  99         return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
 100 }
 101
 102 /* Intel GPIO access functions */
 103
 104 #define I2C_RISEFALL_TIME 10
 105
 106 static inline struct intel_gmbus *
 107 to_intel_gmbus(struct i2c_adapter *i2c)
 108 {
 109         return container_of(i2c, struct intel_gmbus, adapter);
 110 }
 111
 112 void
 113 intel_i2c_reset(struct drm_device *dev)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
 118         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
 119 }
 120
 121 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
 122 {
 123         u32 val;
 124
 125         /* When using bit bashing for I2C, this bit needs to be set to 1 */
 126         if (!IS_PINEVIEW(dev_priv->dev))
 127                 return;
 128
 129         val = I915_READ(DSPCLK_GATE_D);
 130         if (enable)
 131                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
 132         else
 133                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 134         I915_WRITE(DSPCLK_GATE_D, val);
 135 }
 136
 137 static u32 get_reserved(struct intel_gmbus *bus)
 138 {
 139         struct drm_i915_private *dev_priv = bus->dev_priv;
 140         struct drm_device *dev = dev_priv->dev;
 141         u32 reserved = 0;
 142
 143         /* On most chips, these bits must be preserved in software. */
 144         if (!IS_I830(dev) && !IS_845G(dev))
 145                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
 146                                              (GPIO_DATA_PULLUP_DISABLE |
 147                                               GPIO_CLOCK_PULLUP_DISABLE);
 148
 149         return reserved;
 150 }
 151
 152 static int get_clock(void *data)
 153 {
 154         struct intel_gmbus *bus = data;
 155         struct drm_i915_private *dev_priv = bus->dev_priv;
 156         u32 reserved = get_reserved(bus);
 157         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 158         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 159         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 160 }
 161
 162 static int get_data(void *data)
 163 {
 164         struct intel_gmbus *bus = data;
 165         struct drm_i915_private *dev_priv = bus->dev_priv;
 166         u32 reserved = get_reserved(bus);
 167         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 168         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 169         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 170 }
 171
 172 static void set_clock(void *data, int state_high)
 173 {
 174         struct intel_gmbus *bus = data;
 175         struct drm_i915_private *dev_priv = bus->dev_priv;
 176         u32 reserved = get_reserved(bus);
 177         u32 clock_bits;
 178
 179         if (state_high)
 180                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 181         else
 182                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 183                         GPIO_CLOCK_VAL_MASK;
 184
 185         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 186         POSTING_READ(bus->gpio_reg);
 187 }
 188
 189 static void set_data(void *data, int state_high)
 190 {
 191         struct intel_gmbus *bus = data;
 192         struct drm_i915_private *dev_priv = bus->dev_priv;
 193         u32 reserved = get_reserved(bus);
 194         u32 data_bits;
 195
 196         if (state_high)
 197                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 198         else
 199                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 200                         GPIO_DATA_VAL_MASK;
 201
 202         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 203         POSTING_READ(bus->gpio_reg);
 204 }
 205
 206 static int
 207 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 208 {
 209         struct intel_gmbus *bus = container_of(adapter,
 210                                                struct intel_gmbus,
 211                                                adapter);
 212         struct drm_i915_private *dev_priv = bus->dev_priv;
 213
 214         intel_i2c_reset(dev_priv->dev);
 215         intel_i2c_quirk_set(dev_priv, true);
 216         set_data(bus, 1);
 217         set_clock(bus, 1);
 218         udelay(I2C_RISEFALL_TIME);
 219         return 0;
 220 }
 221
 222 static void
 223 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 224 {
 225         struct intel_gmbus *bus = container_of(adapter,
 226                                                struct intel_gmbus,
 227                                                adapter);
 228         struct drm_i915_private *dev_priv = bus->dev_priv;
 229
 230         set_data(bus, 1);
 231         set_clock(bus, 1);
 232         intel_i2c_quirk_set(dev_priv, false);
 233 }
 234
 235 static void
 236 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 237 {
 238         struct drm_i915_private *dev_priv = bus->dev_priv;
 239         struct i2c_algo_bit_data *algo;
 240
 241         algo = &bus->bit_algo;
 242
 243         bus->gpio_reg = dev_priv->gpio_mmio_base +
 244                 get_gmbus_pin(dev_priv, pin)->reg;
 245
 246         bus->adapter.algo_data = algo;
 247         algo->setsda = set_data;
 248         algo->setscl = set_clock;
 249         algo->getsda = get_data;
 250         algo->getscl = get_clock;
 251         algo->pre_xfer = intel_gpio_pre_xfer;
 252         algo->post_xfer = intel_gpio_post_xfer;
 253         algo->udelay = I2C_RISEFALL_TIME;
 254         algo->timeout = usecs_to_jiffies(2200);
 255         algo->data = bus;
 256 }
 257
 258 static int
 259 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 260                      u32 gmbus2_status,
 261                      u32 gmbus4_irq_en)
 262 {
 263         int i;
 264         int reg_offset = dev_priv->gpio_mmio_base;
 265         u32 gmbus2 = 0;
 266         DEFINE_WAIT(wait);
 267
 268         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 269                 gmbus4_irq_en = 0;
 270
 271         /* Important: The hw handles only the first bit, so set only one! Since
 272          * we also need to check for NAKs besides the hw ready/idle signal, we
 273          * need to wake up periodically and check that ourselves. */
 274         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 275
 276         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 277                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 278                                 TASK_UNINTERRUPTIBLE);
 279
 280                 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
 281                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 282                         break;
 283
 284                 schedule_timeout(1);
 285         }
 286         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 287
 288         I915_WRITE(GMBUS4 + reg_offset, 0);
 289
 290         if (gmbus2 & GMBUS_SATOER)
 291                 return -ENXIO;
 292         if (gmbus2 & gmbus2_status)
 293                 return 0;
 294         return -ETIMEDOUT;
 295 }
 296
 297 static int
 298 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 299 {
 300         int ret;
 301         int reg_offset = dev_priv->gpio_mmio_base;
 302
 303 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
 304
 305         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 306                 return wait_for(C, 10);
 307
 308         /* Important: The hw handles only the first bit, so set only one! */
 309         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
 310
 311         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 312                                  msecs_to_jiffies_timeout(10));
 313
 314         I915_WRITE(GMBUS4 + reg_offset, 0);
 315
 316         if (ret)
 317                 return 0;
 318         else
 319                 return -ETIMEDOUT;
 320 #undef C
 321 }
 322
 323 static int
 324 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 325                       unsigned short addr, u8 *buf, unsigned int len,
 326                       u32 gmbus1_index)
 327 {
 328         int reg_offset = dev_priv->gpio_mmio_base;
 329
 330         I915_WRITE(GMBUS1 + reg_offset,
 331                    gmbus1_index |
 332                    GMBUS_CYCLE_WAIT |
 333                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 334                    (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 335                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 336         while (len) {
 337                 int ret;
 338                 u32 val, loop = 0;
 339
 340                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 341                                            GMBUS_HW_RDY_EN);
 342                 if (ret)
 343                         return ret;
 344
 345                 val = I915_READ(GMBUS3 + reg_offset);
 346                 do {
 347                         *buf++ = val & 0xff;
 348                         val >>= 8;
 349                 } while (--len && ++loop < 4);
 350         }
 351
 352         return 0;
 353 }
 354
 355 static int
 356 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 357                 u32 gmbus1_index)
 358 {
 359         u8 *buf = msg->buf;
 360         unsigned int rx_size = msg->len;
 361         unsigned int len;
 362         int ret;
 363
 364         do {
 365                 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
 366
 367                 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
 368                                             buf, len, gmbus1_index);
 369                 if (ret)
 370                         return ret;
 371
 372                 rx_size -= len;
 373                 buf += len;
 374         } while (rx_size != 0);
 375
 376         return 0;
 377 }
 378
 379 static int
 380 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 381                        unsigned short addr, u8 *buf, unsigned int len)
 382 {
 383         int reg_offset = dev_priv->gpio_mmio_base;
 384         unsigned int chunk_size = len;
 385         u32 val, loop;
 386
 387         val = loop = 0;
 388         while (len && loop < 4) {
 389                 val |= *buf++ << (8 * loop++);
 390                 len -= 1;
 391         }
 392
 393         I915_WRITE(GMBUS3 + reg_offset, val);
 394         I915_WRITE(GMBUS1 + reg_offset,
 395                    GMBUS_CYCLE_WAIT |
 396                    (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
 397                    (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 398                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 399         while (len) {
 400                 int ret;
 401
 402                 val = loop = 0;
 403                 do {
 404                         val |= *buf++ << (8 * loop);
 405                 } while (--len && ++loop < 4);
 406
 407                 I915_WRITE(GMBUS3 + reg_offset, val);
 408
 409                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 410                                            GMBUS_HW_RDY_EN);
 411                 if (ret)
 412                         return ret;
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int
 419 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 420 {
 421         u8 *buf = msg->buf;
 422         unsigned int tx_size = msg->len;
 423         unsigned int len;
 424         int ret;
 425
 426         do {
 427                 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
 428
 429                 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
 430                 if (ret)
 431                         return ret;
 432
 433                 buf += len;
 434                 tx_size -= len;
 435         } while (tx_size != 0);
 436
 437         return 0;
 438 }
 439
 440 /*
 441  * The gmbus controller can combine a 1 or 2 byte write with a read that
 442  * immediately follows it by using an "INDEX" cycle.
 443  */
 444 static bool
 445 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 446 {
 447         return (i + 1 < num &&
 448                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
 449                 (msgs[i + 1].flags & I2C_M_RD));
 450 }
 451
 452 static int
 453 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 454 {
 455         int reg_offset = dev_priv->gpio_mmio_base;
 456         u32 gmbus1_index = 0;
 457         u32 gmbus5 = 0;
 458         int ret;
 459
 460         if (msgs[0].len == 2)
 461                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 462                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 463         if (msgs[0].len == 1)
 464                 gmbus1_index = GMBUS_CYCLE_INDEX |
 465                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 466
 467         /* GMBUS5 holds 16-bit index */
 468         if (gmbus5)
 469                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
 470
 471         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 472
 473         /* Clear GMBUS5 after each index transfer */
 474         if (gmbus5)
 475                 I915_WRITE(GMBUS5 + reg_offset, 0);
 476
 477         return ret;
 478 }
 479
 480 static int
 481 gmbus_xfer(struct i2c_adapter *adapter,
 482            struct i2c_msg *msgs,
 483            int num)
 484 {
 485         struct intel_gmbus *bus = container_of(adapter,
 486                                                struct intel_gmbus,
 487                                                adapter);
 488         struct drm_i915_private *dev_priv = bus->dev_priv;
 489         int i = 0, inc, try = 0, reg_offset;
 490         int ret = 0;
 491
 492         intel_aux_display_runtime_get(dev_priv);
 493         mutex_lock(&dev_priv->gmbus_mutex);
 494
 495         if (bus->force_bit) {
 496                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 497                 goto out;
 498         }
 499
 500         reg_offset = dev_priv->gpio_mmio_base;
 501
 502 retry:
 503         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 504
 505         for (; i < num; i += inc) {
 506                 inc = 1;
 507                 if (gmbus_is_index_read(msgs, i, num)) {
 508                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 509                         inc = 2; /* an index read is two msgs */
 510                 } else if (msgs[i].flags & I2C_M_RD) {
 511                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 512                 } else {
 513                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 514                 }
 515
 516                 if (ret == -ETIMEDOUT)
 517                         goto timeout;
 518                 if (ret == -ENXIO)
 519                         goto clear_err;
 520
 521                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
 522                                            GMBUS_HW_WAIT_EN);
 523                 if (ret == -ENXIO)
 524                         goto clear_err;
 525                 if (ret)
 526                         goto timeout;
 527         }
 528
 529         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 530          * a STOP on the very first cycle. To simplify the code we
 531          * unconditionally generate the STOP condition with an additional gmbus
 532          * cycle. */
 533         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 534
 535         /* Mark the GMBUS interface as disabled after waiting for idle.
 536          * We will re-enable it at the start of the next xfer,
 537          * till then let it sleep.
 538          */
 539         if (gmbus_wait_idle(dev_priv)) {
 540                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 541                          adapter->name);
 542                 ret = -ETIMEDOUT;
 543         }
 544         I915_WRITE(GMBUS0 + reg_offset, 0);
 545         ret = ret ?: i;
 546         goto out;
 547
 548 clear_err:
 549         /*
 550          * Wait for bus to IDLE before clearing NAK.
 551          * If we clear the NAK while bus is still active, then it will stay
 552          * active and the next transaction may fail.
 553          *
 554          * If no ACK is received during the address phase of a transaction, the
 555          * adapter must report -ENXIO. It is not clear what to return if no ACK
 556          * is received at other times. But we have to be careful to not return
 557          * spurious -ENXIO because that will prevent i2c and drm edid functions
 558          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 559          * timing out seems to happen when there _is_ a ddc chip present, but
 560          * it's slow responding and only answers on the 2nd retry.
 561          */
 562         ret = -ENXIO;
 563         if (gmbus_wait_idle(dev_priv)) {
 564                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 565                               adapter->name);
 566                 ret = -ETIMEDOUT;
 567         }
 568
 569         /* Toggle the Software Clear Interrupt bit. This has the effect
 570          * of resetting the GMBUS controller and so clearing the
 571          * BUS_ERROR raised by the slave's NAK.
 572          */
 573         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 574         I915_WRITE(GMBUS1 + reg_offset, 0);
 575         I915_WRITE(GMBUS0 + reg_offset, 0);
 576
 577         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 578                          adapter->name, msgs[i].addr,
 579                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 580
 581         /*
 582          * Passive adapters sometimes NAK the first probe. Retry the first
 583          * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
 584          * has retries internally. See also the retry loop in
 585          * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
 586          */
 587         if (ret == -ENXIO && i == 0 && try++ == 0) {
 588                 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
 589                               adapter->name);
 590                 goto retry;
 591         }
 592
 593         goto out;
 594
 595 timeout:
 596         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 597                  bus->adapter.name, bus->reg0 & 0xff);
 598         I915_WRITE(GMBUS0 + reg_offset, 0);
 599
 600         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 601         bus->force_bit = 1;
 602         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 603
 604 out:
 605         mutex_unlock(&dev_priv->gmbus_mutex);
 606         intel_aux_display_runtime_put(dev_priv);
 607         return ret;
 608 }
 609
 610 static u32 gmbus_func(struct i2c_adapter *adapter)
 611 {
 612         return i2c_bit_algo.functionality(adapter) &
 613                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 614                 /* I2C_FUNC_10BIT_ADDR | */
 615                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 616                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 617 }
 618
 619 static const struct i2c_algorithm gmbus_algorithm = {
 620         .master_xfer    = gmbus_xfer,
 621         .functionality  = gmbus_func
 622 };
 623
 624 /**
 625  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 626  * @dev: DRM device
 627  */
 628 int intel_setup_gmbus(struct drm_device *dev)
 629 {
 630         struct drm_i915_private *dev_priv = dev->dev_private;
 631         struct intel_gmbus *bus;
 632         unsigned int pin;
 633         int ret;
 634
 635         if (HAS_PCH_NOP(dev))
 636                 return 0;
 637         else if (HAS_PCH_SPLIT(dev))
 638                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 639         else if (IS_VALLEYVIEW(dev))
 640                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 641         else
 642                 dev_priv->gpio_mmio_base = 0;
 643
 644         mutex_init(&dev_priv->gmbus_mutex);
 645         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 646
 647         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 648                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 649                         continue;
 650
 651                 bus = &dev_priv->gmbus[pin];
 652
 653                 bus->adapter.owner = THIS_MODULE;
 654                 bus->adapter.class = I2C_CLASS_DDC;
 655                 snprintf(bus->adapter.name,
 656                          sizeof(bus->adapter.name),
 657                          "i915 gmbus %s",
 658                          get_gmbus_pin(dev_priv, pin)->name);
 659
 660                 bus->adapter.dev.parent = &dev->pdev->dev;
 661                 bus->dev_priv = dev_priv;
 662
 663                 bus->adapter.algo = &gmbus_algorithm;
 664
 665                 /* By default use a conservative clock rate */
 666                 bus->reg0 = pin | GMBUS_RATE_100KHZ;
 667
 668                 /* gmbus seems to be broken on i830 */
 669                 if (IS_I830(dev))
 670                         bus->force_bit = 1;
 671
 672                 intel_gpio_setup(bus, pin);
 673
 674                 ret = i2c_add_adapter(&bus->adapter);
 675                 if (ret)
 676                         goto err;
 677         }
 678
 679         intel_i2c_reset(dev_priv->dev);
 680
 681         return 0;
 682
 683 err:
 684         while (--pin) {
 685                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 686                         continue;
 687
 688                 bus = &dev_priv->gmbus[pin];
 689                 i2c_del_adapter(&bus->adapter);
 690         }
 691         return ret;
 692 }
 693
 694 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 695                                             unsigned int pin)
 696 {
 697         if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
 698                 return NULL;
 699
 700         return &dev_priv->gmbus[pin].adapter;
 701 }
 702
 703 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 704 {
 705         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 706
 707         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 708 }
 709
 710 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 711 {
 712         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 713
 714         bus->force_bit += force_bit ? 1 : -1;
 715         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
 716                       force_bit ? "en" : "dis", adapter->name,
 717                       bus->force_bit);
 718 }
 719
 720 void intel_teardown_gmbus(struct drm_device *dev)
 721 {
 722         struct drm_i915_private *dev_priv = dev->dev_private;
 723         struct intel_gmbus *bus;
 724         unsigned int pin;
 725
 726         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 727                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 728                         continue;
 729
 730                 bus = &dev_priv->gmbus[pin];
 731                 i2c_del_adapter(&bus->adapter);
 732         }
 733 }