drivers/gpu/drm/nouveau/dispnv04/disp.h

   1 #ifndef __NV04_DISPLAY_H__
   2 #define __NV04_DISPLAY_H__
   3
   4 #include <subdev/bios/pll.h>
   5
   6 #include "nouveau_display.h"
   7
   8 enum nv04_fp_display_regs {
   9         FP_DISPLAY_END,
  10         FP_TOTAL,
  11         FP_CRTC,
  12         FP_SYNC_START,
  13         FP_SYNC_END,
  14         FP_VALID_START,
  15         FP_VALID_END
  16 };
  17
  18 struct nv04_crtc_reg {
  19         unsigned char MiscOutReg;
  20         uint8_t CRTC[0xa0];
  21         uint8_t CR58[0x10];
  22         uint8_t Sequencer[5];
  23         uint8_t Graphics[9];
  24         uint8_t Attribute[21];
  25         unsigned char DAC[768];
  26
  27         /* PCRTC regs */
  28         uint32_t fb_start;
  29         uint32_t crtc_cfg;
  30         uint32_t cursor_cfg;
  31         uint32_t gpio_ext;
  32         uint32_t crtc_830;
  33         uint32_t crtc_834;
  34         uint32_t crtc_850;
  35         uint32_t crtc_eng_ctrl;
  36
  37         /* PRAMDAC regs */
  38         uint32_t nv10_cursync;
  39         struct nvkm_pll_vals pllvals;
  40         uint32_t ramdac_gen_ctrl;
  41         uint32_t ramdac_630;
  42         uint32_t ramdac_634;
  43         uint32_t tv_setup;
  44         uint32_t tv_vtotal;
  45         uint32_t tv_vskew;
  46         uint32_t tv_vsync_delay;
  47         uint32_t tv_htotal;
  48         uint32_t tv_hskew;
  49         uint32_t tv_hsync_delay;
  50         uint32_t tv_hsync_delay2;
  51         uint32_t fp_horiz_regs[7];
  52         uint32_t fp_vert_regs[7];
  53         uint32_t dither;
  54         uint32_t fp_control;
  55         uint32_t dither_regs[6];
  56         uint32_t fp_debug_0;
  57         uint32_t fp_debug_1;
  58         uint32_t fp_debug_2;
  59         uint32_t fp_margin_color;
  60         uint32_t ramdac_8c0;
  61         uint32_t ramdac_a20;
  62         uint32_t ramdac_a24;
  63         uint32_t ramdac_a34;
  64         uint32_t ctv_regs[38];
  65 };
  66
  67 struct nv04_output_reg {
  68         uint32_t output;
  69         int head;
  70 };
  71
  72 struct nv04_mode_state {
  73         struct nv04_crtc_reg crtc_reg[2];
  74         uint32_t pllsel;
  75         uint32_t sel_clk;
  76 };
  77
  78 struct nv04_display {
  79         struct nv04_mode_state mode_reg;
  80         struct nv04_mode_state saved_reg;
  81         uint32_t saved_vga_font[4][16384];
  82         uint32_t dac_users[4];
  83         struct nouveau_bo *image[2];
  84 };
  85
  86 static inline struct nv04_display *
  87 nv04_display(struct drm_device *dev)
  88 {
  89         return nouveau_display(dev)->priv;
  90 }
  91
  92 /* nv04_display.c */
  93 int nv04_display_create(struct drm_device *);
  94 void nv04_display_destroy(struct drm_device *);
  95 int nv04_display_init(struct drm_device *);
  96 void nv04_display_fini(struct drm_device *);
  97
  98 /* nv04_crtc.c */
  99 int nv04_crtc_create(struct drm_device *, int index);
 100
 101 /* nv04_dac.c */
 102 int nv04_dac_create(struct drm_connector *, struct dcb_output *);
 103 uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
 104 int nv04_dac_output_offset(struct drm_encoder *encoder);
 105 void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
 106 bool nv04_dac_in_use(struct drm_encoder *encoder);
 107
 108 /* nv04_dfp.c */
 109 int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
 110 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
 111 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
 112                                int head, bool dl);
 113 void nv04_dfp_disable(struct drm_device *dev, int head);
 114 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
 115
 116 /* nv04_tv.c */
 117 int nv04_tv_identify(struct drm_device *dev, int i2c_index);
 118 int nv04_tv_create(struct drm_connector *, struct dcb_output *);
 119
 120 /* nv17_tv.c */
 121 int nv17_tv_create(struct drm_connector *, struct dcb_output *);
 122
 123 /* overlay.c */
 124 void nouveau_overlay_init(struct drm_device *dev);
 125
 126 static inline bool
 127 nv_two_heads(struct drm_device *dev)
 128 {
 129         struct nouveau_drm *drm = nouveau_drm(dev);
 130         const int impl = dev->pdev->device & 0x0ff0;
 131
 132         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
 133             impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
 134                 return true;
 135
 136         return false;
 137 }
 138
 139 static inline bool
 140 nv_gf4_disp_arch(struct drm_device *dev)
 141 {
 142         return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
 143 }
 144
 145 static inline bool
 146 nv_two_reg_pll(struct drm_device *dev)
 147 {
 148         struct nouveau_drm *drm = nouveau_drm(dev);
 149         const int impl = dev->pdev->device & 0x0ff0;
 150
 151         if (impl == 0x0310 || impl == 0x0340 || drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE)
 152                 return true;
 153         return false;
 154 }
 155
 156 static inline bool
 157 nv_match_device(struct drm_device *dev, unsigned device,
 158                 unsigned sub_vendor, unsigned sub_device)
 159 {
 160         return dev->pdev->device == device &&
 161                 dev->pdev->subsystem_vendor == sub_vendor &&
 162                 dev->pdev->subsystem_device == sub_device;
 163 }
 164
 165 #include <subdev/bios.h>
 166 #include <subdev/bios/init.h>
 167
 168 static inline void
 169 nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
 170                             struct dcb_output *outp, int crtc)
 171 {
 172         struct nouveau_drm *drm = nouveau_drm(dev);
 173         struct nvkm_bios *bios = nvxx_bios(&drm->device);
 174         struct nvbios_init init = {
 175                 .subdev = nv_subdev(bios),
 176                 .bios = bios,
 177                 .offset = table,
 178                 .outp = outp,
 179                 .crtc = crtc,
 180                 .execute = 1,
 181         };
 182
 183         nvbios_exec(&init);
 184 }
 185
 186 #endif