| blob | 391ff9d5d70668326cea4ff4a078eeec673198bd |
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #ifndef CIK_H
25 #define CIK_H
27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define CIK_RB_BITMAP_WIDTH_PER_SH 2
31 #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
33 #define RADEON_NUM_OF_VMIDS 8
35 /* DIDT IND registers */
36 #define DIDT_SQ_CTRL0 0x0
37 # define DIDT_CTRL_EN (1 << 0)
38 #define DIDT_DB_CTRL0 0x20
39 #define DIDT_TD_CTRL0 0x40
40 #define DIDT_TCP_CTRL0 0x60
42 /* SMC IND registers */
43 #define DPM_TABLE_475 0x3F768
44 # define SamuBootLevel(x) ((x) << 0)
45 # define SamuBootLevel_MASK 0x000000ff
46 # define SamuBootLevel_SHIFT 0
47 # define AcpBootLevel(x) ((x) << 8)
48 # define AcpBootLevel_MASK 0x0000ff00
49 # define AcpBootLevel_SHIFT 8
50 # define VceBootLevel(x) ((x) << 16)
51 # define VceBootLevel_MASK 0x00ff0000
52 # define VceBootLevel_SHIFT 16
53 # define UvdBootLevel(x) ((x) << 24)
54 # define UvdBootLevel_MASK 0xff000000
55 # define UvdBootLevel_SHIFT 24
57 #define FIRMWARE_FLAGS 0x3F800
58 # define INTERRUPTS_ENABLED (1 << 0)
60 #define NB_DPM_CONFIG_1 0x3F9E8
61 # define Dpm0PgNbPsLo(x) ((x) << 0)
62 # define Dpm0PgNbPsLo_MASK 0x000000ff
63 # define Dpm0PgNbPsLo_SHIFT 0
64 # define Dpm0PgNbPsHi(x) ((x) << 8)
65 # define Dpm0PgNbPsHi_MASK 0x0000ff00
66 # define Dpm0PgNbPsHi_SHIFT 8
67 # define DpmXNbPsLo(x) ((x) << 16)
68 # define DpmXNbPsLo_MASK 0x00ff0000
69 # define DpmXNbPsLo_SHIFT 16
70 # define DpmXNbPsHi(x) ((x) << 24)
71 # define DpmXNbPsHi_MASK 0xff000000
72 # define DpmXNbPsHi_SHIFT 24
74 #define SMC_SYSCON_RESET_CNTL 0x80000000
75 # define RST_REG (1 << 0)
76 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
77 # define CK_DISABLE (1 << 0)
78 # define CKEN (1 << 24)
80 #define SMC_SYSCON_MISC_CNTL 0x80000010
82 #define SMC_SYSCON_MSG_ARG_0 0x80000068
84 #define SMC_PC_C 0x80000370
86 #define SMC_SCRATCH9 0x80000424
88 #define RCU_UC_EVENTS 0xC0000004
89 # define BOOT_SEQ_DONE (1 << 7)
91 #define GENERAL_PWRMGT 0xC0200000
92 # define GLOBAL_PWRMGT_EN (1 << 0)
93 # define STATIC_PM_EN (1 << 1)
94 # define THERMAL_PROTECTION_DIS (1 << 2)
95 # define THERMAL_PROTECTION_TYPE (1 << 3)
96 # define SW_SMIO_INDEX(x) ((x) << 6)
97 # define SW_SMIO_INDEX_MASK (1 << 6)
98 # define SW_SMIO_INDEX_SHIFT 6
99 # define VOLT_PWRMGT_EN (1 << 10)
100 # define GPU_COUNTER_CLK (1 << 15)
101 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
103 #define CNB_PWRMGT_CNTL 0xC0200004
104 # define GNB_SLOW_MODE(x) ((x) << 0)
105 # define GNB_SLOW_MODE_MASK (3 << 0)
106 # define GNB_SLOW_MODE_SHIFT 0
107 # define GNB_SLOW (1 << 2)
108 # define FORCE_NB_PS1 (1 << 3)
109 # define DPM_ENABLED (1 << 4)
111 #define SCLK_PWRMGT_CNTL 0xC0200008
112 # define SCLK_PWRMGT_OFF (1 << 0)
113 # define RESET_BUSY_CNT (1 << 4)
114 # define RESET_SCLK_CNT (1 << 5)
115 # define DYNAMIC_PM_EN (1 << 21)
117 #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014
118 # define CURRENT_STATE_MASK (0xf << 4)
119 # define CURRENT_STATE_SHIFT 4
120 # define CURR_MCLK_INDEX_MASK (0xf << 8)
121 # define CURR_MCLK_INDEX_SHIFT 8
122 # define CURR_SCLK_INDEX_MASK (0x1f << 16)
123 # define CURR_SCLK_INDEX_SHIFT 16
125 #define CG_SSP 0xC0200044
126 # define SST(x) ((x) << 0)
127 # define SST_MASK (0xffff << 0)
128 # define SSTU(x) ((x) << 16)
129 # define SSTU_MASK (0xf << 16)
131 #define CG_DISPLAY_GAP_CNTL 0xC0200060
132 # define DISP_GAP(x) ((x) << 0)
133 # define DISP_GAP_MASK (3 << 0)
134 # define VBI_TIMER_COUNT(x) ((x) << 4)
135 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
136 # define VBI_TIMER_UNIT(x) ((x) << 20)
137 # define VBI_TIMER_UNIT_MASK (7 << 20)
138 # define DISP_GAP_MCHG(x) ((x) << 24)
139 # define DISP_GAP_MCHG_MASK (3 << 24)
141 #define SMU_VOLTAGE_STATUS 0xC0200094
142 # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
143 # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
145 #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0
146 # define CURR_PCIE_INDEX_MASK (0xf << 24)
147 # define CURR_PCIE_INDEX_SHIFT 24
149 #define CG_ULV_PARAMETER 0xC0200158
151 #define CG_FTV_0 0xC02001A8
152 #define CG_FTV_1 0xC02001AC
153 #define CG_FTV_2 0xC02001B0
154 #define CG_FTV_3 0xC02001B4
155 #define CG_FTV_4 0xC02001B8
156 #define CG_FTV_5 0xC02001BC
157 #define CG_FTV_6 0xC02001C0
158 #define CG_FTV_7 0xC02001C4
160 #define CG_DISPLAY_GAP_CNTL2 0xC0200230
162 #define LCAC_SX0_OVR_SEL 0xC0400D04
163 #define LCAC_SX0_OVR_VAL 0xC0400D08
165 #define LCAC_MC0_CNTL 0xC0400D30
166 #define LCAC_MC0_OVR_SEL 0xC0400D34
167 #define LCAC_MC0_OVR_VAL 0xC0400D38
168 #define LCAC_MC1_CNTL 0xC0400D3C
169 #define LCAC_MC1_OVR_SEL 0xC0400D40
170 #define LCAC_MC1_OVR_VAL 0xC0400D44
172 #define LCAC_MC2_OVR_SEL 0xC0400D4C
173 #define LCAC_MC2_OVR_VAL 0xC0400D50
175 #define LCAC_MC3_OVR_SEL 0xC0400D58
176 #define LCAC_MC3_OVR_VAL 0xC0400D5C
178 #define LCAC_CPL_CNTL 0xC0400D80
179 #define LCAC_CPL_OVR_SEL 0xC0400D84
180 #define LCAC_CPL_OVR_VAL 0xC0400D88
182 /* dGPU */
183 #define CG_THERMAL_CTRL 0xC0300004
184 #define DPM_EVENT_SRC(x) ((x) << 0)
185 #define DPM_EVENT_SRC_MASK (7 << 0)
186 #define DIG_THERM_DPM(x) ((x) << 14)
187 #define DIG_THERM_DPM_MASK 0x003FC000
188 #define DIG_THERM_DPM_SHIFT 14
189 #define CG_THERMAL_STATUS 0xC0300008
190 #define FDO_PWM_DUTY(x) ((x) << 9)
191 #define FDO_PWM_DUTY_MASK (0xff << 9)
192 #define FDO_PWM_DUTY_SHIFT 9
193 #define CG_THERMAL_INT 0xC030000C
194 #define CI_DIG_THERM_INTH(x) ((x) << 8)
195 #define CI_DIG_THERM_INTH_MASK 0x0000FF00
196 #define CI_DIG_THERM_INTH_SHIFT 8
197 #define CI_DIG_THERM_INTL(x) ((x) << 16)
198 #define CI_DIG_THERM_INTL_MASK 0x00FF0000
199 #define CI_DIG_THERM_INTL_SHIFT 16
200 #define THERM_INT_MASK_HIGH (1 << 24)
201 #define THERM_INT_MASK_LOW (1 << 25)
202 #define CG_MULT_THERMAL_CTRL 0xC0300010
203 #define TEMP_SEL(x) ((x) << 20)
204 #define TEMP_SEL_MASK (0xff << 20)
205 #define TEMP_SEL_SHIFT 20
206 #define CG_MULT_THERMAL_STATUS 0xC0300014
207 #define ASIC_MAX_TEMP(x) ((x) << 0)
208 #define ASIC_MAX_TEMP_MASK 0x000001ff
209 #define ASIC_MAX_TEMP_SHIFT 0
210 #define CTF_TEMP(x) ((x) << 9)
211 #define CTF_TEMP_MASK 0x0003fe00
212 #define CTF_TEMP_SHIFT 9
214 #define CG_FDO_CTRL0 0xC0300064
215 #define FDO_STATIC_DUTY(x) ((x) << 0)
216 #define FDO_STATIC_DUTY_MASK 0x000000FF
217 #define FDO_STATIC_DUTY_SHIFT 0
218 #define CG_FDO_CTRL1 0xC0300068
219 #define FMAX_DUTY100(x) ((x) << 0)
220 #define FMAX_DUTY100_MASK 0x000000FF
221 #define FMAX_DUTY100_SHIFT 0
222 #define CG_FDO_CTRL2 0xC030006C
223 #define TMIN(x) ((x) << 0)
224 #define TMIN_MASK 0x000000FF
225 #define TMIN_SHIFT 0
226 #define FDO_PWM_MODE(x) ((x) << 11)
227 #define FDO_PWM_MODE_MASK (7 << 11)
228 #define FDO_PWM_MODE_SHIFT 11
229 #define TACH_PWM_RESP_RATE(x) ((x) << 25)
230 #define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
231 #define TACH_PWM_RESP_RATE_SHIFT 25
232 #define CG_TACH_CTRL 0xC0300070
233 # define EDGE_PER_REV(x) ((x) << 0)
234 # define EDGE_PER_REV_MASK (0x7 << 0)
235 # define EDGE_PER_REV_SHIFT 0
236 # define TARGET_PERIOD(x) ((x) << 3)
237 # define TARGET_PERIOD_MASK 0xfffffff8
238 # define TARGET_PERIOD_SHIFT 3
239 #define CG_TACH_STATUS 0xC0300074
240 # define TACH_PERIOD(x) ((x) << 0)
241 # define TACH_PERIOD_MASK 0xffffffff
242 # define TACH_PERIOD_SHIFT 0
244 #define CG_ECLK_CNTL 0xC05000AC
245 # define ECLK_DIVIDER_MASK 0x7f
246 # define ECLK_DIR_CNTL_EN (1 << 8)
247 #define CG_ECLK_STATUS 0xC05000B0
248 # define ECLK_STATUS (1 << 0)
250 #define CG_SPLL_FUNC_CNTL 0xC0500140
251 #define SPLL_RESET (1 << 0)
252 #define SPLL_PWRON (1 << 1)
253 #define SPLL_BYPASS_EN (1 << 3)
254 #define SPLL_REF_DIV(x) ((x) << 5)
255 #define SPLL_REF_DIV_MASK (0x3f << 5)
256 #define SPLL_PDIV_A(x) ((x) << 20)
257 #define SPLL_PDIV_A_MASK (0x7f << 20)
258 #define SPLL_PDIV_A_SHIFT 20
259 #define CG_SPLL_FUNC_CNTL_2 0xC0500144
260 #define SCLK_MUX_SEL(x) ((x) << 0)
261 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
262 #define CG_SPLL_FUNC_CNTL_3 0xC0500148
263 #define SPLL_FB_DIV(x) ((x) << 0)
264 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
265 #define SPLL_FB_DIV_SHIFT 0
266 #define SPLL_DITHEN (1 << 28)
267 #define CG_SPLL_FUNC_CNTL_4 0xC050014C
269 #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
270 #define SSEN (1 << 0)
271 #define CLK_S(x) ((x) << 4)
272 #define CLK_S_MASK (0xfff << 4)
273 #define CLK_S_SHIFT 4
274 #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
275 #define CLK_V(x) ((x) << 0)
276 #define CLK_V_MASK (0x3ffffff << 0)
277 #define CLK_V_SHIFT 0
279 #define MPLL_BYPASSCLK_SEL 0xC050019C
280 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
281 # define MPLL_CLKOUT_SEL_MASK 0xFF00
282 #define CG_CLKPIN_CNTL 0xC05001A0
283 # define XTALIN_DIVIDE (1 << 1)
284 # define BCLK_AS_XCLK (1 << 2)
285 #define CG_CLKPIN_CNTL_2 0xC05001A4
286 # define FORCE_BIF_REFCLK_EN (1 << 3)
287 # define MUX_TCLK_TO_XCLK (1 << 8)
288 #define THM_CLK_CNTL 0xC05001A8
289 # define CMON_CLK_SEL(x) ((x) << 0)
290 # define CMON_CLK_SEL_MASK 0xFF
291 # define TMON_CLK_SEL(x) ((x) << 8)
292 # define TMON_CLK_SEL_MASK 0xFF00
293 #define MISC_CLK_CTRL 0xC05001AC
294 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
295 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
296 # define ZCLK_SEL(x) ((x) << 8)
297 # define ZCLK_SEL_MASK 0xFF00
299 /* KV/KB */
300 #define CG_THERMAL_INT_CTRL 0xC2100028
301 #define DIG_THERM_INTH(x) ((x) << 0)
302 #define DIG_THERM_INTH_MASK 0x000000FF
303 #define DIG_THERM_INTH_SHIFT 0
304 #define DIG_THERM_INTL(x) ((x) << 8)
305 #define DIG_THERM_INTL_MASK 0x0000FF00
306 #define DIG_THERM_INTL_SHIFT 8
307 #define THERM_INTH_MASK (1 << 24)
308 #define THERM_INTL_MASK (1 << 25)
310 /* PCIE registers idx/data 0x38/0x3c */
312 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
313 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
314 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
315 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
316 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
317 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
318 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
319 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
320 # define PLL_RAMP_UP_TIME_0_SHIFT 24
322 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
323 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
324 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
325 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
326 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
327 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
328 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
329 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
330 # define PLL_RAMP_UP_TIME_1_SHIFT 24
333 # define SLV_MEM_LS_EN (1 << 16)
334 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
335 # define MST_MEM_LS_EN (1 << 18)
336 # define REPLAY_MEM_LS_EN (1 << 19)
339 # define LC_REVERSE_RCVR (1 << 0)
340 # define LC_REVERSE_XMIT (1 << 1)
341 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
342 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
343 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
344 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
347 # define P_IGNORE_EDB_ERR (1 << 6)
353 # define LC_L0S_INACTIVITY(x) ((x) << 8)
354 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
355 # define LC_L0S_INACTIVITY_SHIFT 8
356 # define LC_L1_INACTIVITY(x) ((x) << 12)
357 # define LC_L1_INACTIVITY_MASK (0xf << 12)
358 # define LC_L1_INACTIVITY_SHIFT 12
359 # define LC_PMI_TO_L1_DIS (1 << 16)
360 # define LC_ASPM_TO_L1_DIS (1 << 24)
363 # define LC_LINK_WIDTH_SHIFT 0
364 # define LC_LINK_WIDTH_MASK 0x7
365 # define LC_LINK_WIDTH_X0 0
366 # define LC_LINK_WIDTH_X1 1
367 # define LC_LINK_WIDTH_X2 2
368 # define LC_LINK_WIDTH_X4 3
369 # define LC_LINK_WIDTH_X8 4
370 # define LC_LINK_WIDTH_X16 6
371 # define LC_LINK_WIDTH_RD_SHIFT 4
372 # define LC_LINK_WIDTH_RD_MASK 0x70
373 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
374 # define LC_RECONFIG_NOW (1 << 8)
375 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
376 # define LC_RENEGOTIATE_EN (1 << 10)
377 # define LC_SHORT_RECONFIG_EN (1 << 11)
378 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
379 # define LC_UPCONFIGURE_DIS (1 << 13)
380 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
381 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
382 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
384 # define LC_XMIT_N_FTS(x) ((x) << 0)
385 # define LC_XMIT_N_FTS_MASK (0xff << 0)
386 # define LC_XMIT_N_FTS_SHIFT 0
387 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
388 # define LC_N_FTS_MASK (0xff << 24)
390 # define LC_GEN2_EN_STRAP (1 << 0)
391 # define LC_GEN3_EN_STRAP (1 << 1)
392 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
393 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
394 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
395 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
396 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
397 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
398 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
399 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
400 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
401 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
403 # define LC_CURRENT_DATA_RATE_SHIFT 13
404 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
405 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
406 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
407 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
408 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
411 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
412 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
415 # define LC_GO_TO_RECOVERY (1 << 30)
417 # define LC_REDO_EQ (1 << 5)
418 # define LC_SET_QUIESCE (1 << 13)
420 /* direct registers */
421 #define PCIE_INDEX 0x38
422 #define PCIE_DATA 0x3C
424 #define SMC_IND_INDEX_0 0x200
425 #define SMC_IND_DATA_0 0x204
427 #define SMC_IND_ACCESS_CNTL 0x240
428 #define AUTO_INCREMENT_IND_0 (1 << 0)
430 #define SMC_MESSAGE_0 0x250
431 #define SMC_MSG_MASK 0xffff
432 #define SMC_RESP_0 0x254
433 #define SMC_RESP_MASK 0xffff
435 #define SMC_MSG_ARG_0 0x290
437 #define VGA_HDP_CONTROL 0x328
438 #define VGA_MEMORY_DISABLE (1 << 4)
440 #define DMIF_ADDR_CALC 0xC00
442 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
443 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
444 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
446 #define SRBM_GFX_CNTL 0xE44
447 #define PIPEID(x) ((x) << 0)
448 #define MEID(x) ((x) << 2)
449 #define VMID(x) ((x) << 4)
450 #define QUEUEID(x) ((x) << 8)
452 #define SRBM_STATUS2 0xE4C
453 #define SDMA_BUSY (1 << 5)
454 #define SDMA1_BUSY (1 << 6)
455 #define SRBM_STATUS 0xE50
456 #define UVD_RQ_PENDING (1 << 1)
457 #define GRBM_RQ_PENDING (1 << 5)
458 #define VMC_BUSY (1 << 8)
459 #define MCB_BUSY (1 << 9)
460 #define MCB_NON_DISPLAY_BUSY (1 << 10)
461 #define MCC_BUSY (1 << 11)
462 #define MCD_BUSY (1 << 12)
463 #define SEM_BUSY (1 << 14)
464 #define IH_BUSY (1 << 17)
465 #define UVD_BUSY (1 << 19)
467 #define SRBM_SOFT_RESET 0xE60
468 #define SOFT_RESET_BIF (1 << 1)
469 #define SOFT_RESET_R0PLL (1 << 4)
470 #define SOFT_RESET_DC (1 << 5)
471 #define SOFT_RESET_SDMA1 (1 << 6)
472 #define SOFT_RESET_GRBM (1 << 8)
473 #define SOFT_RESET_HDP (1 << 9)
474 #define SOFT_RESET_IH (1 << 10)
475 #define SOFT_RESET_MC (1 << 11)
476 #define SOFT_RESET_ROM (1 << 14)
477 #define SOFT_RESET_SEM (1 << 15)
478 #define SOFT_RESET_VMC (1 << 17)
479 #define SOFT_RESET_SDMA (1 << 20)
480 #define SOFT_RESET_TST (1 << 21)
481 #define SOFT_RESET_REGBB (1 << 22)
482 #define SOFT_RESET_ORB (1 << 23)
483 #define SOFT_RESET_VCE (1 << 24)
485 #define SRBM_READ_ERROR 0xE98
486 #define SRBM_INT_CNTL 0xEA0
487 #define SRBM_INT_ACK 0xEA8
489 #define VM_L2_CNTL 0x1400
490 #define ENABLE_L2_CACHE (1 << 0)
491 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
492 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
493 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
494 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
495 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
496 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
497 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
498 #define VM_L2_CNTL2 0x1404
499 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
500 #define INVALIDATE_L2_CACHE (1 << 1)
501 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
502 #define INVALIDATE_PTE_AND_PDE_CACHES 0
503 #define INVALIDATE_ONLY_PTE_CACHES 1
504 #define INVALIDATE_ONLY_PDE_CACHES 2
505 #define VM_L2_CNTL3 0x1408
506 #define BANK_SELECT(x) ((x) << 0)
507 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
508 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
509 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
510 #define VM_L2_STATUS 0x140C
511 #define L2_BUSY (1 << 0)
512 #define VM_CONTEXT0_CNTL 0x1410
513 #define ENABLE_CONTEXT (1 << 0)
514 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
515 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
516 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
517 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
518 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
519 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
520 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
521 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
522 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
523 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
524 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
525 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
526 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
527 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
528 #define VM_CONTEXT1_CNTL 0x1414
529 #define VM_CONTEXT0_CNTL2 0x1430
530 #define VM_CONTEXT1_CNTL2 0x1434
531 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
532 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
533 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
534 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
535 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
536 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
537 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
538 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
540 #define VM_INVALIDATE_REQUEST 0x1478
541 #define VM_INVALIDATE_RESPONSE 0x147c
543 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
544 #define PROTECTIONS_MASK (0xf << 0)
545 #define PROTECTIONS_SHIFT 0
546 /* bit 0: range
547 * bit 1: pde0
548 * bit 2: valid
549 * bit 3: read
550 * bit 4: write
551 */
552 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
553 #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)
554 #define MEMORY_CLIENT_ID_SHIFT 12
555 #define MEMORY_CLIENT_RW_MASK (1 << 24)
556 #define MEMORY_CLIENT_RW_SHIFT 24
557 #define FAULT_VMID_MASK (0xf << 25)
558 #define FAULT_VMID_SHIFT 25
560 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
562 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
564 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
565 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
567 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
568 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
569 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
570 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
571 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
572 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
573 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
574 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
575 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
576 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
578 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
579 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
581 #define VM_L2_CG 0x15c0
582 #define MC_CG_ENABLE (1 << 18)
583 #define MC_LS_ENABLE (1 << 19)
585 #define MC_SHARED_CHMAP 0x2004
586 #define NOOFCHAN_SHIFT 12
587 #define NOOFCHAN_MASK 0x0000f000
588 #define MC_SHARED_CHREMAP 0x2008
590 #define CHUB_CONTROL 0x1864
591 #define BYPASS_VM (1 << 0)
593 #define MC_VM_FB_LOCATION 0x2024
594 #define MC_VM_AGP_TOP 0x2028
595 #define MC_VM_AGP_BOT 0x202C
596 #define MC_VM_AGP_BASE 0x2030
597 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
598 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
599 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
601 #define MC_VM_MX_L1_TLB_CNTL 0x2064
602 #define ENABLE_L1_TLB (1 << 0)
603 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
604 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
605 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
606 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
607 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
608 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
609 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
610 #define MC_VM_FB_OFFSET 0x2068
612 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
614 #define MC_HUB_MISC_HUB_CG 0x20b8
615 #define MC_HUB_MISC_VM_CG 0x20bc
617 #define MC_HUB_MISC_SIP_CG 0x20c0
619 #define MC_XPB_CLK_GAT 0x2478
621 #define MC_CITF_MISC_RD_CG 0x2648
622 #define MC_CITF_MISC_WR_CG 0x264c
623 #define MC_CITF_MISC_VM_CG 0x2650
625 #define MC_ARB_RAMCFG 0x2760
626 #define NOOFBANK_SHIFT 0
627 #define NOOFBANK_MASK 0x00000003
628 #define NOOFRANK_SHIFT 2
629 #define NOOFRANK_MASK 0x00000004
630 #define NOOFROWS_SHIFT 3
631 #define NOOFROWS_MASK 0x00000038
632 #define NOOFCOLS_SHIFT 6
633 #define NOOFCOLS_MASK 0x000000C0
634 #define CHANSIZE_SHIFT 8
635 #define CHANSIZE_MASK 0x00000100
636 #define NOOFGROUPS_SHIFT 12
637 #define NOOFGROUPS_MASK 0x00001000
639 #define MC_ARB_DRAM_TIMING 0x2774
640 #define MC_ARB_DRAM_TIMING2 0x2778
642 #define MC_ARB_BURST_TIME 0x2808
643 #define STATE0(x) ((x) << 0)
644 #define STATE0_MASK (0x1f << 0)
645 #define STATE0_SHIFT 0
646 #define STATE1(x) ((x) << 5)
647 #define STATE1_MASK (0x1f << 5)
648 #define STATE1_SHIFT 5
649 #define STATE2(x) ((x) << 10)
650 #define STATE2_MASK (0x1f << 10)
651 #define STATE2_SHIFT 10
652 #define STATE3(x) ((x) << 15)
653 #define STATE3_MASK (0x1f << 15)
654 #define STATE3_SHIFT 15
656 #define MC_SEQ_RAS_TIMING 0x28a0
657 #define MC_SEQ_CAS_TIMING 0x28a4
658 #define MC_SEQ_MISC_TIMING 0x28a8
659 #define MC_SEQ_MISC_TIMING2 0x28ac
660 #define MC_SEQ_PMG_TIMING 0x28b0
661 #define MC_SEQ_RD_CTL_D0 0x28b4
662 #define MC_SEQ_RD_CTL_D1 0x28b8
663 #define MC_SEQ_WR_CTL_D0 0x28bc
664 #define MC_SEQ_WR_CTL_D1 0x28c0
666 #define MC_SEQ_SUP_CNTL 0x28c8
667 #define RUN_MASK (1 << 0)
668 #define MC_SEQ_SUP_PGM 0x28cc
669 #define MC_PMG_AUTO_CMD 0x28d0
671 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
672 #define TRAIN_DONE_D0 (1 << 30)
673 #define TRAIN_DONE_D1 (1 << 31)
675 #define MC_IO_PAD_CNTL_D0 0x29d0
676 #define MEM_FALL_OUT_CMD (1 << 8)
678 #define MC_SEQ_MISC0 0x2a00
679 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
680 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
681 #define MC_SEQ_MISC0_VEN_ID_VALUE 3
682 #define MC_SEQ_MISC0_REV_ID_SHIFT 12
683 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
684 #define MC_SEQ_MISC0_REV_ID_VALUE 1
685 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
686 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
687 #define MC_SEQ_MISC0_GDDR5_VALUE 5
688 #define MC_SEQ_MISC1 0x2a04
689 #define MC_SEQ_RESERVE_M 0x2a08
690 #define MC_PMG_CMD_EMRS 0x2a0c
692 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
693 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
695 #define MC_SEQ_MISC5 0x2a54
696 #define MC_SEQ_MISC6 0x2a58
698 #define MC_SEQ_MISC7 0x2a64
700 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
701 #define MC_SEQ_CAS_TIMING_LP 0x2a70
702 #define MC_SEQ_MISC_TIMING_LP 0x2a74
703 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
704 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
705 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
706 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
707 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
709 #define MC_PMG_CMD_MRS 0x2aac
711 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
712 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
714 #define MC_PMG_CMD_MRS1 0x2b44
715 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
716 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
718 #define MC_SEQ_WR_CTL_2 0x2b54
719 #define MC_SEQ_WR_CTL_2_LP 0x2b58
720 #define MC_PMG_CMD_MRS2 0x2b5c
721 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
723 #define MCLK_PWRMGT_CNTL 0x2ba0
724 # define DLL_SPEED(x) ((x) << 0)
725 # define DLL_SPEED_MASK (0x1f << 0)
726 # define DLL_READY (1 << 6)
727 # define MC_INT_CNTL (1 << 7)
728 # define MRDCK0_PDNB (1 << 8)
729 # define MRDCK1_PDNB (1 << 9)
730 # define MRDCK0_RESET (1 << 16)
731 # define MRDCK1_RESET (1 << 17)
732 # define DLL_READY_READ (1 << 24)
733 #define DLL_CNTL 0x2ba4
734 # define MRDCK0_BYPASS (1 << 24)
735 # define MRDCK1_BYPASS (1 << 25)
737 #define MPLL_FUNC_CNTL 0x2bb4
738 #define BWCTRL(x) ((x) << 20)
739 #define BWCTRL_MASK (0xff << 20)
740 #define MPLL_FUNC_CNTL_1 0x2bb8
741 #define VCO_MODE(x) ((x) << 0)
742 #define VCO_MODE_MASK (3 << 0)
743 #define CLKFRAC(x) ((x) << 4)
744 #define CLKFRAC_MASK (0xfff << 4)
745 #define CLKF(x) ((x) << 16)
746 #define CLKF_MASK (0xfff << 16)
747 #define MPLL_FUNC_CNTL_2 0x2bbc
748 #define MPLL_AD_FUNC_CNTL 0x2bc0
749 #define YCLK_POST_DIV(x) ((x) << 0)
750 #define YCLK_POST_DIV_MASK (7 << 0)
751 #define MPLL_DQ_FUNC_CNTL 0x2bc4
752 #define YCLK_SEL(x) ((x) << 4)
753 #define YCLK_SEL_MASK (1 << 4)
755 #define MPLL_SS1 0x2bcc
756 #define CLKV(x) ((x) << 0)
757 #define CLKV_MASK (0x3ffffff << 0)
758 #define MPLL_SS2 0x2bd0
759 #define CLKS(x) ((x) << 0)
760 #define CLKS_MASK (0xfff << 0)
762 #define HDP_HOST_PATH_CNTL 0x2C00
763 #define CLOCK_GATING_DIS (1 << 23)
764 #define HDP_NONSURFACE_BASE 0x2C04
765 #define HDP_NONSURFACE_INFO 0x2C08
766 #define HDP_NONSURFACE_SIZE 0x2C0C
768 #define HDP_ADDR_CONFIG 0x2F48
769 #define HDP_MISC_CNTL 0x2F4C
770 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
771 #define HDP_MEM_POWER_LS 0x2F50
772 #define HDP_LS_ENABLE (1 << 0)
774 #define ATC_MISC_CG 0x3350
776 #define GMCON_RENG_EXECUTE 0x3508
777 #define RENG_EXECUTE_ON_PWR_UP (1 << 0)
778 #define GMCON_MISC 0x350c
779 #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
780 #define STCTRL_STUTTER_EN (1 << 16)
782 #define GMCON_PGFSM_CONFIG 0x3538
783 #define GMCON_PGFSM_WRITE 0x353c
784 #define GMCON_PGFSM_READ 0x3540
785 #define GMCON_MISC3 0x3544
787 #define MC_SEQ_CNTL_3 0x3600
788 # define CAC_EN (1 << 31)
789 #define MC_SEQ_G5PDX_CTRL 0x3604
790 #define MC_SEQ_G5PDX_CTRL_LP 0x3608
791 #define MC_SEQ_G5PDX_CMD0 0x360c
792 #define MC_SEQ_G5PDX_CMD0_LP 0x3610
793 #define MC_SEQ_G5PDX_CMD1 0x3614
794 #define MC_SEQ_G5PDX_CMD1_LP 0x3618
796 #define MC_SEQ_PMG_DVS_CTL 0x3628
797 #define MC_SEQ_PMG_DVS_CTL_LP 0x362c
798 #define MC_SEQ_PMG_DVS_CMD 0x3630
799 #define MC_SEQ_PMG_DVS_CMD_LP 0x3634
800 #define MC_SEQ_DLL_STBY 0x3638
801 #define MC_SEQ_DLL_STBY_LP 0x363c
803 #define IH_RB_CNTL 0x3e00
804 # define IH_RB_ENABLE (1 << 0)
806 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
807 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
809 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
810 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
811 #define IH_RB_BASE 0x3e04
812 #define IH_RB_RPTR 0x3e08
813 #define IH_RB_WPTR 0x3e0c
814 # define RB_OVERFLOW (1 << 0)
815 # define WPTR_OFFSET_MASK 0x3fffc
816 #define IH_RB_WPTR_ADDR_HI 0x3e10
817 #define IH_RB_WPTR_ADDR_LO 0x3e14
818 #define IH_CNTL 0x3e18
819 # define ENABLE_INTR (1 << 0)
820 # define IH_MC_SWAP(x) ((x) << 1)
821 # define IH_MC_SWAP_NONE 0
822 # define IH_MC_SWAP_16BIT 1
823 # define IH_MC_SWAP_32BIT 2
824 # define IH_MC_SWAP_64BIT 3
825 # define RPTR_REARM (1 << 4)
826 # define MC_WRREQ_CREDIT(x) ((x) << 15)
827 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
828 # define MC_VMID(x) ((x) << 25)
830 #define BIF_LNCNT_RESET 0x5220
831 # define RESET_LNCNT_EN (1 << 0)
833 #define CONFIG_MEMSIZE 0x5428
835 #define INTERRUPT_CNTL 0x5468
836 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
837 # define IH_DUMMY_RD_EN (1 << 1)
838 # define IH_REQ_NONSNOOP_EN (1 << 3)
839 # define GEN_IH_INT_EN (1 << 8)
840 #define INTERRUPT_CNTL2 0x546c
842 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
844 #define BIF_FB_EN 0x5490
845 #define FB_READ_EN (1 << 0)
846 #define FB_WRITE_EN (1 << 1)
848 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
850 #define GPU_HDP_FLUSH_REQ 0x54DC
851 #define GPU_HDP_FLUSH_DONE 0x54E0
852 #define CP0 (1 << 0)
853 #define CP1 (1 << 1)
854 #define CP2 (1 << 2)
855 #define CP3 (1 << 3)
856 #define CP4 (1 << 4)
857 #define CP5 (1 << 5)
858 #define CP6 (1 << 6)
859 #define CP7 (1 << 7)
860 #define CP8 (1 << 8)
861 #define CP9 (1 << 9)
862 #define SDMA0 (1 << 10)
863 #define SDMA1 (1 << 11)
865 /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
866 #define LB_MEMORY_CTRL 0x6b04
867 #define LB_MEMORY_SIZE(x) ((x) << 0)
868 #define LB_MEMORY_CONFIG(x) ((x) << 20)
870 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
871 # define LATENCY_WATERMARK_MASK(x) ((x) << 8)
872 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
873 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
874 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
876 /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
877 #define LB_VLINE_STATUS 0x6b24
878 # define VLINE_OCCURRED (1 << 0)
879 # define VLINE_ACK (1 << 4)
880 # define VLINE_STAT (1 << 12)
881 # define VLINE_INTERRUPT (1 << 16)
882 # define VLINE_INTERRUPT_TYPE (1 << 17)
883 /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
884 #define LB_VBLANK_STATUS 0x6b2c
885 # define VBLANK_OCCURRED (1 << 0)
886 # define VBLANK_ACK (1 << 4)
887 # define VBLANK_STAT (1 << 12)
888 # define VBLANK_INTERRUPT (1 << 16)
889 # define VBLANK_INTERRUPT_TYPE (1 << 17)
891 /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
892 #define LB_INTERRUPT_MASK 0x6b20
893 # define VBLANK_INTERRUPT_MASK (1 << 0)
894 # define VLINE_INTERRUPT_MASK (1 << 4)
895 # define VLINE2_INTERRUPT_MASK (1 << 8)
897 #define DISP_INTERRUPT_STATUS 0x60f4
898 # define LB_D1_VLINE_INTERRUPT (1 << 2)
899 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
900 # define DC_HPD1_INTERRUPT (1 << 17)
901 # define DC_HPD1_RX_INTERRUPT (1 << 18)
902 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
903 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
904 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
905 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
906 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
907 # define LB_D2_VLINE_INTERRUPT (1 << 2)
908 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
909 # define DC_HPD2_INTERRUPT (1 << 17)
910 # define DC_HPD2_RX_INTERRUPT (1 << 18)
911 # define DISP_TIMER_INTERRUPT (1 << 24)
912 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
913 # define LB_D3_VLINE_INTERRUPT (1 << 2)
914 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
915 # define DC_HPD3_INTERRUPT (1 << 17)
916 # define DC_HPD3_RX_INTERRUPT (1 << 18)
917 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
918 # define LB_D4_VLINE_INTERRUPT (1 << 2)
919 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
920 # define DC_HPD4_INTERRUPT (1 << 17)
921 # define DC_HPD4_RX_INTERRUPT (1 << 18)
922 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
923 # define LB_D5_VLINE_INTERRUPT (1 << 2)
924 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
925 # define DC_HPD5_INTERRUPT (1 << 17)
926 # define DC_HPD5_RX_INTERRUPT (1 << 18)
927 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
928 # define LB_D6_VLINE_INTERRUPT (1 << 2)
929 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
930 # define DC_HPD6_INTERRUPT (1 << 17)
931 # define DC_HPD6_RX_INTERRUPT (1 << 18)
932 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
934 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
935 #define GRPH_INT_STATUS 0x6858
936 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
937 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
938 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
939 #define GRPH_INT_CONTROL 0x685c
940 # define GRPH_PFLIP_INT_MASK (1 << 0)
941 # define GRPH_PFLIP_INT_TYPE (1 << 8)
943 #define DAC_AUTODETECT_INT_CONTROL 0x67c8
945 #define DC_HPD1_INT_STATUS 0x601c
946 #define DC_HPD2_INT_STATUS 0x6028
947 #define DC_HPD3_INT_STATUS 0x6034
948 #define DC_HPD4_INT_STATUS 0x6040
949 #define DC_HPD5_INT_STATUS 0x604c
950 #define DC_HPD6_INT_STATUS 0x6058
951 # define DC_HPDx_INT_STATUS (1 << 0)
952 # define DC_HPDx_SENSE (1 << 1)
953 # define DC_HPDx_SENSE_DELAYED (1 << 4)
954 # define DC_HPDx_RX_INT_STATUS (1 << 8)
956 #define DC_HPD1_INT_CONTROL 0x6020
957 #define DC_HPD2_INT_CONTROL 0x602c
958 #define DC_HPD3_INT_CONTROL 0x6038
959 #define DC_HPD4_INT_CONTROL 0x6044
960 #define DC_HPD5_INT_CONTROL 0x6050
961 #define DC_HPD6_INT_CONTROL 0x605c
962 # define DC_HPDx_INT_ACK (1 << 0)
963 # define DC_HPDx_INT_POLARITY (1 << 8)
964 # define DC_HPDx_INT_EN (1 << 16)
965 # define DC_HPDx_RX_INT_ACK (1 << 20)
966 # define DC_HPDx_RX_INT_EN (1 << 24)
968 #define DC_HPD1_CONTROL 0x6024
969 #define DC_HPD2_CONTROL 0x6030
970 #define DC_HPD3_CONTROL 0x603c
971 #define DC_HPD4_CONTROL 0x6048
972 #define DC_HPD5_CONTROL 0x6054
973 #define DC_HPD6_CONTROL 0x6060
974 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
975 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
976 # define DC_HPDx_EN (1 << 28)
978 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
979 # define STUTTER_ENABLE (1 << 0)
981 /* DCE8 FMT blocks */
982 #define FMT_DYNAMIC_EXP_CNTL 0x6fb4
983 # define FMT_DYNAMIC_EXP_EN (1 << 0)
984 # define FMT_DYNAMIC_EXP_MODE (1 << 4)
985 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
986 #define FMT_CONTROL 0x6fb8
987 # define FMT_PIXEL_ENCODING (1 << 16)
988 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
989 #define FMT_BIT_DEPTH_CONTROL 0x6fc8
990 # define FMT_TRUNCATE_EN (1 << 0)
991 # define FMT_TRUNCATE_MODE (1 << 1)
993 # define FMT_SPATIAL_DITHER_EN (1 << 8)
994 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
996 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
997 # define FMT_RGB_RANDOM_ENABLE (1 << 14)
998 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
999 # define FMT_TEMPORAL_DITHER_EN (1 << 16)
1001 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
1002 # define FMT_TEMPORAL_LEVEL (1 << 24)
1003 # define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1004 # define FMT_25FRC_SEL(x) ((x) << 26)
1005 # define FMT_50FRC_SEL(x) ((x) << 28)
1006 # define FMT_75FRC_SEL(x) ((x) << 30)
1007 #define FMT_CLAMP_CONTROL 0x6fe4
1008 # define FMT_CLAMP_DATA_EN (1 << 0)
1009 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
1010 # define FMT_CLAMP_6BPC 0
1011 # define FMT_CLAMP_8BPC 1
1012 # define FMT_CLAMP_10BPC 2
1014 #define GRBM_CNTL 0x8000
1015 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
1017 #define GRBM_STATUS2 0x8008
1018 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
1019 #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
1020 #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
1021 #define ME1PIPE0_RQ_PENDING (1 << 6)
1022 #define ME1PIPE1_RQ_PENDING (1 << 7)
1023 #define ME1PIPE2_RQ_PENDING (1 << 8)
1024 #define ME1PIPE3_RQ_PENDING (1 << 9)
1025 #define ME2PIPE0_RQ_PENDING (1 << 10)
1026 #define ME2PIPE1_RQ_PENDING (1 << 11)
1027 #define ME2PIPE2_RQ_PENDING (1 << 12)
1028 #define ME2PIPE3_RQ_PENDING (1 << 13)
1029 #define RLC_RQ_PENDING (1 << 14)
1030 #define RLC_BUSY (1 << 24)
1031 #define TC_BUSY (1 << 25)
1032 #define CPF_BUSY (1 << 28)
1033 #define CPC_BUSY (1 << 29)
1034 #define CPG_BUSY (1 << 30)
1036 #define GRBM_STATUS 0x8010
1037 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
1038 #define SRBM_RQ_PENDING (1 << 5)
1039 #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
1040 #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
1041 #define GDS_DMA_RQ_PENDING (1 << 9)
1042 #define DB_CLEAN (1 << 12)
1043 #define CB_CLEAN (1 << 13)
1044 #define TA_BUSY (1 << 14)
1045 #define GDS_BUSY (1 << 15)
1046 #define WD_BUSY_NO_DMA (1 << 16)
1047 #define VGT_BUSY (1 << 17)
1048 #define IA_BUSY_NO_DMA (1 << 18)
1049 #define IA_BUSY (1 << 19)
1050 #define SX_BUSY (1 << 20)
1051 #define WD_BUSY (1 << 21)
1052 #define SPI_BUSY (1 << 22)
1053 #define BCI_BUSY (1 << 23)
1054 #define SC_BUSY (1 << 24)
1055 #define PA_BUSY (1 << 25)
1056 #define DB_BUSY (1 << 26)
1057 #define CP_COHERENCY_BUSY (1 << 28)
1058 #define CP_BUSY (1 << 29)
1059 #define CB_BUSY (1 << 30)
1060 #define GUI_ACTIVE (1 << 31)
1061 #define GRBM_STATUS_SE0 0x8014
1062 #define GRBM_STATUS_SE1 0x8018
1063 #define GRBM_STATUS_SE2 0x8038
1064 #define GRBM_STATUS_SE3 0x803C
1065 #define SE_DB_CLEAN (1 << 1)
1066 #define SE_CB_CLEAN (1 << 2)
1067 #define SE_BCI_BUSY (1 << 22)
1068 #define SE_VGT_BUSY (1 << 23)
1069 #define SE_PA_BUSY (1 << 24)
1070 #define SE_TA_BUSY (1 << 25)
1071 #define SE_SX_BUSY (1 << 26)
1072 #define SE_SPI_BUSY (1 << 27)
1073 #define SE_SC_BUSY (1 << 29)
1074 #define SE_DB_BUSY (1 << 30)
1075 #define SE_CB_BUSY (1 << 31)
1077 #define GRBM_SOFT_RESET 0x8020
1085 #define GRBM_INT_CNTL 0x8060
1086 # define RDERR_INT_ENABLE (1 << 0)
1087 # define GUI_IDLE_INT_ENABLE (1 << 19)
1089 #define CP_CPC_STATUS 0x8210
1090 #define CP_CPC_BUSY_STAT 0x8214
1091 #define CP_CPC_STALLED_STAT1 0x8218
1092 #define CP_CPF_STATUS 0x821c
1093 #define CP_CPF_BUSY_STAT 0x8220
1094 #define CP_CPF_STALLED_STAT1 0x8224
1096 #define CP_MEC_CNTL 0x8234
1097 #define MEC_ME2_HALT (1 << 28)
1098 #define MEC_ME1_HALT (1 << 30)
1100 #define CP_MEC_CNTL 0x8234
1101 #define MEC_ME2_HALT (1 << 28)
1102 #define MEC_ME1_HALT (1 << 30)
1104 #define CP_STALLED_STAT3 0x8670
1105 #define CP_STALLED_STAT1 0x8674
1106 #define CP_STALLED_STAT2 0x8678
1108 #define CP_STAT 0x8680
1110 #define CP_ME_CNTL 0x86D8
1111 #define CP_CE_HALT (1 << 24)
1112 #define CP_PFP_HALT (1 << 26)
1113 #define CP_ME_HALT (1 << 28)
1115 #define CP_RB0_RPTR 0x8700
1116 #define CP_RB_WPTR_DELAY 0x8704
1117 #define CP_RB_WPTR_POLL_CNTL 0x8708
1118 #define IDLE_POLL_COUNT(x) ((x) << 16)
1119 #define IDLE_POLL_COUNT_MASK (0xffff << 16)
1121 #define CP_MEQ_THRESHOLDS 0x8764
1122 #define MEQ1_START(x) ((x) << 0)
1123 #define MEQ2_START(x) ((x) << 8)
1125 #define VGT_VTX_VECT_EJECT_REG 0x88B0
1127 #define VGT_CACHE_INVALIDATION 0x88C4
1128 #define CACHE_INVALIDATION(x) ((x) << 0)
1129 #define VC_ONLY 0
1130 #define TC_ONLY 1
1131 #define VC_AND_TC 2
1132 #define AUTO_INVLD_EN(x) ((x) << 6)
1133 #define NO_AUTO 0
1134 #define ES_AUTO 1
1135 #define GS_AUTO 2
1136 #define ES_AND_GS_AUTO 3
1138 #define VGT_GS_VERTEX_REUSE 0x88D4
1140 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1141 #define INACTIVE_CUS_MASK 0xFFFF0000
1142 #define INACTIVE_CUS_SHIFT 16
1143 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1145 #define PA_CL_ENHANCE 0x8A14
1146 #define CLIP_VTX_REORDER_ENA (1 << 0)
1147 #define NUM_CLIP_SEQ(x) ((x) << 1)
1149 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1150 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1151 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1153 #define PA_SC_FIFO_SIZE 0x8BCC
1154 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1155 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1156 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1157 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1159 #define PA_SC_ENHANCE 0x8BF0
1160 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
1161 #define DISABLE_PA_SC_GUIDANCE (1 << 13)
1163 #define SQ_CONFIG 0x8C00
1165 #define SH_MEM_BASES 0x8C28
1166 /* if PTR32, these are the bases for scratch and lds */
1169 #define SH_MEM_APE1_BASE 0x8C2C
1170 /* if PTR32, this is the base location of GPUVM */
1171 #define SH_MEM_APE1_LIMIT 0x8C30
1172 /* if PTR32, this is the upper limit of GPUVM */
1173 #define SH_MEM_CONFIG 0x8C34
1174 #define PTR32 (1 << 0)
1175 #define ALIGNMENT_MODE(x) ((x) << 2)
1176 #define SH_MEM_ALIGNMENT_MODE_DWORD 0
1177 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
1178 #define SH_MEM_ALIGNMENT_MODE_STRICT 2
1179 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
1180 #define DEFAULT_MTYPE(x) ((x) << 4)
1181 #define APE1_MTYPE(x) ((x) << 7)
1182 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */
1183 #define MTYPE_CACHED 0
1184 #define MTYPE_NONCACHED 3
1186 #define SX_DEBUG_1 0x9060
1188 #define SPI_CONFIG_CNTL 0x9100
1190 #define SPI_CONFIG_CNTL_1 0x913C
1191 #define VTX_DONE_DELAY(x) ((x) << 0)
1192 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1194 #define TA_CNTL_AUX 0x9508
1196 #define DB_DEBUG 0x9830
1197 #define DB_DEBUG2 0x9834
1198 #define DB_DEBUG3 0x9838
1200 #define CC_RB_BACKEND_DISABLE 0x98F4
1201 #define BACKEND_DISABLE(x) ((x) << 16)
1202 #define GB_ADDR_CONFIG 0x98F8
1203 #define NUM_PIPES(x) ((x) << 0)
1204 #define NUM_PIPES_MASK 0x00000007
1205 #define NUM_PIPES_SHIFT 0
1206 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1207 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1208 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
1209 #define NUM_SHADER_ENGINES(x) ((x) << 12)
1210 #define NUM_SHADER_ENGINES_MASK 0x00003000
1211 #define NUM_SHADER_ENGINES_SHIFT 12
1212 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1213 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1214 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1215 #define ROW_SIZE(x) ((x) << 28)
1216 #define ROW_SIZE_MASK 0x30000000
1217 #define ROW_SIZE_SHIFT 28
1219 #define GB_TILE_MODE0 0x9910
1220 # define ARRAY_MODE(x) ((x) << 2)
1221 # define ARRAY_LINEAR_GENERAL 0
1222 # define ARRAY_LINEAR_ALIGNED 1
1223 # define ARRAY_1D_TILED_THIN1 2
1224 # define ARRAY_2D_TILED_THIN1 4
1225 # define ARRAY_PRT_TILED_THIN1 5
1226 # define ARRAY_PRT_2D_TILED_THIN1 6
1227 # define PIPE_CONFIG(x) ((x) << 6)
1228 # define ADDR_SURF_P2 0
1229 # define ADDR_SURF_P4_8x16 4
1230 # define ADDR_SURF_P4_16x16 5
1231 # define ADDR_SURF_P4_16x32 6
1232 # define ADDR_SURF_P4_32x32 7
1233 # define ADDR_SURF_P8_16x16_8x16 8
1234 # define ADDR_SURF_P8_16x32_8x16 9
1235 # define ADDR_SURF_P8_32x32_8x16 10
1236 # define ADDR_SURF_P8_16x32_16x16 11
1237 # define ADDR_SURF_P8_32x32_16x16 12
1238 # define ADDR_SURF_P8_32x32_16x32 13
1239 # define ADDR_SURF_P8_32x64_32x32 14
1240 # define ADDR_SURF_P16_32x32_8x16 16
1241 # define ADDR_SURF_P16_32x32_16x16 17
1242 # define TILE_SPLIT(x) ((x) << 11)
1243 # define ADDR_SURF_TILE_SPLIT_64B 0
1244 # define ADDR_SURF_TILE_SPLIT_128B 1
1245 # define ADDR_SURF_TILE_SPLIT_256B 2
1246 # define ADDR_SURF_TILE_SPLIT_512B 3
1247 # define ADDR_SURF_TILE_SPLIT_1KB 4
1248 # define ADDR_SURF_TILE_SPLIT_2KB 5
1249 # define ADDR_SURF_TILE_SPLIT_4KB 6
1250 # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
1251 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
1252 # define ADDR_SURF_THIN_MICRO_TILING 1
1253 # define ADDR_SURF_DEPTH_MICRO_TILING 2
1254 # define ADDR_SURF_ROTATED_MICRO_TILING 3
1255 # define SAMPLE_SPLIT(x) ((x) << 25)
1256 # define ADDR_SURF_SAMPLE_SPLIT_1 0
1257 # define ADDR_SURF_SAMPLE_SPLIT_2 1
1258 # define ADDR_SURF_SAMPLE_SPLIT_4 2
1259 # define ADDR_SURF_SAMPLE_SPLIT_8 3
1261 #define GB_MACROTILE_MODE0 0x9990
1262 # define BANK_WIDTH(x) ((x) << 0)
1263 # define ADDR_SURF_BANK_WIDTH_1 0
1264 # define ADDR_SURF_BANK_WIDTH_2 1
1265 # define ADDR_SURF_BANK_WIDTH_4 2
1266 # define ADDR_SURF_BANK_WIDTH_8 3
1267 # define BANK_HEIGHT(x) ((x) << 2)
1268 # define ADDR_SURF_BANK_HEIGHT_1 0
1269 # define ADDR_SURF_BANK_HEIGHT_2 1
1270 # define ADDR_SURF_BANK_HEIGHT_4 2
1271 # define ADDR_SURF_BANK_HEIGHT_8 3
1272 # define MACRO_TILE_ASPECT(x) ((x) << 4)
1273 # define ADDR_SURF_MACRO_ASPECT_1 0
1274 # define ADDR_SURF_MACRO_ASPECT_2 1
1275 # define ADDR_SURF_MACRO_ASPECT_4 2
1276 # define ADDR_SURF_MACRO_ASPECT_8 3
1277 # define NUM_BANKS(x) ((x) << 6)
1278 # define ADDR_SURF_2_BANK 0
1279 # define ADDR_SURF_4_BANK 1
1280 # define ADDR_SURF_8_BANK 2
1281 # define ADDR_SURF_16_BANK 3
1283 #define CB_HW_CONTROL 0x9A10
1285 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1286 #define BACKEND_DISABLE_MASK 0x00FF0000
1287 #define BACKEND_DISABLE_SHIFT 16
1289 #define TCP_CHAN_STEER_LO 0xac0c
1290 #define TCP_CHAN_STEER_HI 0xac10
1292 #define TC_CFG_L1_LOAD_POLICY0 0xAC68
1293 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C
1294 #define TC_CFG_L1_STORE_POLICY 0xAC70
1295 #define TC_CFG_L2_LOAD_POLICY0 0xAC74
1296 #define TC_CFG_L2_LOAD_POLICY1 0xAC78
1297 #define TC_CFG_L2_STORE_POLICY0 0xAC7C
1298 #define TC_CFG_L2_STORE_POLICY1 0xAC80
1299 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84
1300 #define TC_CFG_L1_VOLATILE 0xAC88
1301 #define TC_CFG_L2_VOLATILE 0xAC8C
1303 #define CP_RB0_BASE 0xC100
1304 #define CP_RB0_CNTL 0xC104
1305 #define RB_BUFSZ(x) ((x) << 0)
1306 #define RB_BLKSZ(x) ((x) << 8)
1307 #define BUF_SWAP_32BIT (2 << 16)
1308 #define RB_NO_UPDATE (1 << 27)
1309 #define RB_RPTR_WR_ENA (1 << 31)
1311 #define CP_RB0_RPTR_ADDR 0xC10C
1312 #define RB_RPTR_SWAP_32BIT (2 << 0)
1313 #define CP_RB0_RPTR_ADDR_HI 0xC110
1314 #define CP_RB0_WPTR 0xC114
1316 #define CP_DEVICE_ID 0xC12C
1317 #define CP_ENDIAN_SWAP 0xC140
1318 #define CP_RB_VMID 0xC144
1320 #define CP_PFP_UCODE_ADDR 0xC150
1321 #define CP_PFP_UCODE_DATA 0xC154
1322 #define CP_ME_RAM_RADDR 0xC158
1323 #define CP_ME_RAM_WADDR 0xC15C
1324 #define CP_ME_RAM_DATA 0xC160
1326 #define CP_CE_UCODE_ADDR 0xC168
1327 #define CP_CE_UCODE_DATA 0xC16C
1328 #define CP_MEC_ME1_UCODE_ADDR 0xC170
1329 #define CP_MEC_ME1_UCODE_DATA 0xC174
1330 #define CP_MEC_ME2_UCODE_ADDR 0xC178
1331 #define CP_MEC_ME2_UCODE_DATA 0xC17C
1333 #define CP_INT_CNTL_RING0 0xC1A8
1334 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1335 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1336 # define PRIV_INSTR_INT_ENABLE (1 << 22)
1337 # define PRIV_REG_INT_ENABLE (1 << 23)
1338 # define OPCODE_ERROR_INT_ENABLE (1 << 24)
1339 # define TIME_STAMP_INT_ENABLE (1 << 26)
1340 # define CP_RINGID2_INT_ENABLE (1 << 29)
1341 # define CP_RINGID1_INT_ENABLE (1 << 30)
1342 # define CP_RINGID0_INT_ENABLE (1 << 31)
1344 #define CP_INT_STATUS_RING0 0xC1B4
1345 # define PRIV_INSTR_INT_STAT (1 << 22)
1346 # define PRIV_REG_INT_STAT (1 << 23)
1347 # define TIME_STAMP_INT_STAT (1 << 26)
1348 # define CP_RINGID2_INT_STAT (1 << 29)
1349 # define CP_RINGID1_INT_STAT (1 << 30)
1350 # define CP_RINGID0_INT_STAT (1 << 31)
1352 #define CP_MEM_SLP_CNTL 0xC1E4
1353 # define CP_MEM_LS_EN (1 << 0)
1355 #define CP_CPF_DEBUG 0xC200
1357 #define CP_PQ_WPTR_POLL_CNTL 0xC20C
1358 #define WPTR_POLL_EN (1 << 31)
1360 #define CP_ME1_PIPE0_INT_CNTL 0xC214
1361 #define CP_ME1_PIPE1_INT_CNTL 0xC218
1362 #define CP_ME1_PIPE2_INT_CNTL 0xC21C
1363 #define CP_ME1_PIPE3_INT_CNTL 0xC220
1364 #define CP_ME2_PIPE0_INT_CNTL 0xC224
1365 #define CP_ME2_PIPE1_INT_CNTL 0xC228
1366 #define CP_ME2_PIPE2_INT_CNTL 0xC22C
1367 #define CP_ME2_PIPE3_INT_CNTL 0xC230
1368 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
1369 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
1370 # define PRIV_REG_INT_ENABLE (1 << 23)
1371 # define TIME_STAMP_INT_ENABLE (1 << 26)
1372 # define GENERIC2_INT_ENABLE (1 << 29)
1373 # define GENERIC1_INT_ENABLE (1 << 30)
1374 # define GENERIC0_INT_ENABLE (1 << 31)
1375 #define CP_ME1_PIPE0_INT_STATUS 0xC214
1376 #define CP_ME1_PIPE1_INT_STATUS 0xC218
1377 #define CP_ME1_PIPE2_INT_STATUS 0xC21C
1378 #define CP_ME1_PIPE3_INT_STATUS 0xC220
1379 #define CP_ME2_PIPE0_INT_STATUS 0xC224
1380 #define CP_ME2_PIPE1_INT_STATUS 0xC228
1381 #define CP_ME2_PIPE2_INT_STATUS 0xC22C
1382 #define CP_ME2_PIPE3_INT_STATUS 0xC230
1383 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
1384 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
1385 # define PRIV_REG_INT_STATUS (1 << 23)
1386 # define TIME_STAMP_INT_STATUS (1 << 26)
1387 # define GENERIC2_INT_STATUS (1 << 29)
1388 # define GENERIC1_INT_STATUS (1 << 30)
1389 # define GENERIC0_INT_STATUS (1 << 31)
1391 #define CP_MAX_CONTEXT 0xC2B8
1393 #define CP_RB0_BASE_HI 0xC2C4
1395 #define RLC_CNTL 0xC300
1396 # define RLC_ENABLE (1 << 0)
1398 #define RLC_MC_CNTL 0xC30C
1400 #define RLC_MEM_SLP_CNTL 0xC318
1401 # define RLC_MEM_LS_EN (1 << 0)
1403 #define RLC_LB_CNTR_MAX 0xC348
1405 #define RLC_LB_CNTL 0xC364
1406 # define LOAD_BALANCE_ENABLE (1 << 0)
1408 #define RLC_LB_CNTR_INIT 0xC36C
1410 #define RLC_SAVE_AND_RESTORE_BASE 0xC374
1413 #define RLC_PG_DELAY_2 0xC37C
1415 #define RLC_GPM_UCODE_ADDR 0xC388
1416 #define RLC_GPM_UCODE_DATA 0xC38C
1417 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390
1418 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394
1419 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
1420 #define RLC_UCODE_CNTL 0xC39C
1422 #define RLC_GPM_STAT 0xC400
1423 # define RLC_GPM_BUSY (1 << 0)
1424 # define GFX_POWER_STATUS (1 << 1)
1425 # define GFX_CLOCK_STATUS (1 << 2)
1427 #define RLC_PG_CNTL 0xC40C
1428 # define GFX_PG_ENABLE (1 << 0)
1429 # define GFX_PG_SRC (1 << 1)
1430 # define DYN_PER_CU_PG_ENABLE (1 << 2)
1431 # define STATIC_PER_CU_PG_ENABLE (1 << 3)
1432 # define DISABLE_GDS_PG (1 << 13)
1433 # define DISABLE_CP_PG (1 << 15)
1434 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
1435 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
1437 #define RLC_CGTT_MGCG_OVERRIDE 0xC420
1438 #define RLC_CGCG_CGLS_CTRL 0xC424
1439 # define CGCG_EN (1 << 0)
1440 # define CGLS_EN (1 << 1)
1442 #define RLC_PG_DELAY 0xC434
1444 #define RLC_LB_INIT_CU_MASK 0xC43C
1446 #define RLC_LB_PARAMS 0xC444
1448 #define RLC_PG_AO_CU_MASK 0xC44C
1450 #define RLC_MAX_PG_CU 0xC450
1451 # define MAX_PU_CU(x) ((x) << 0)
1452 # define MAX_PU_CU_MASK (0xff << 0)
1453 #define RLC_AUTO_PG_CTRL 0xC454
1454 # define AUTO_PG_EN (1 << 0)
1455 # define GRBM_REG_SGIT(x) ((x) << 3)
1456 # define GRBM_REG_SGIT_MASK (0xffff << 3)
1458 #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
1459 #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
1460 #define RLC_SERDES_WR_CTRL 0xC47C
1461 #define BPM_ADDR(x) ((x) << 0)
1462 #define BPM_ADDR_MASK (0xff << 0)
1463 #define CGLS_ENABLE (1 << 16)
1464 #define CGCG_OVERRIDE_0 (1 << 20)
1465 #define MGCG_OVERRIDE_0 (1 << 22)
1466 #define MGCG_OVERRIDE_1 (1 << 23)
1468 #define RLC_SERDES_CU_MASTER_BUSY 0xC484
1469 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
1470 # define SE_MASTER_BUSY_MASK 0x0000ffff
1471 # define GC_MASTER_BUSY (1 << 16)
1472 # define TC0_MASTER_BUSY (1 << 17)
1473 # define TC1_MASTER_BUSY (1 << 18)
1475 #define RLC_GPM_SCRATCH_ADDR 0xC4B0
1476 #define RLC_GPM_SCRATCH_DATA 0xC4B4
1478 #define RLC_GPR_REG2 0xC4E8
1479 #define REQ 0x00000001
1480 #define MESSAGE(x) ((x) << 1)
1481 #define MESSAGE_MASK 0x0000001e
1482 #define MSG_ENTER_RLC_SAFE_MODE 1
1483 #define MSG_EXIT_RLC_SAFE_MODE 0
1485 #define CP_HPD_EOP_BASE_ADDR 0xC904
1486 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1487 #define CP_HPD_EOP_VMID 0xC90C
1488 #define CP_HPD_EOP_CONTROL 0xC910
1489 #define EOP_SIZE(x) ((x) << 0)
1490 #define EOP_SIZE_MASK (0x3f << 0)
1491 #define CP_MQD_BASE_ADDR 0xC914
1492 #define CP_MQD_BASE_ADDR_HI 0xC918
1493 #define CP_HQD_ACTIVE 0xC91C
1494 #define CP_HQD_VMID 0xC920
1496 #define CP_HQD_PERSISTENT_STATE 0xC924u
1497 #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)
1499 #define CP_HQD_PIPE_PRIORITY 0xC928u
1500 #define CP_HQD_QUEUE_PRIORITY 0xC92Cu
1501 #define CP_HQD_QUANTUM 0xC930u
1502 #define QUANTUM_EN 1U
1503 #define QUANTUM_SCALE_1MS (1U << 4)
1504 #define QUANTUM_DURATION(x) ((x) << 8)
1506 #define CP_HQD_PQ_BASE 0xC934
1507 #define CP_HQD_PQ_BASE_HI 0xC938
1508 #define CP_HQD_PQ_RPTR 0xC93C
1509 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
1510 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
1511 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
1512 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
1513 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
1514 #define DOORBELL_OFFSET(x) ((x) << 2)
1515 #define DOORBELL_OFFSET_MASK (0x1fffff << 2)
1516 #define DOORBELL_SOURCE (1 << 28)
1517 #define DOORBELL_SCHD_HIT (1 << 29)
1518 #define DOORBELL_EN (1 << 30)
1519 #define DOORBELL_HIT (1 << 31)
1520 #define CP_HQD_PQ_WPTR 0xC954
1521 #define CP_HQD_PQ_CONTROL 0xC958
1522 #define QUEUE_SIZE(x) ((x) << 0)
1523 #define QUEUE_SIZE_MASK (0x3f << 0)
1524 #define RPTR_BLOCK_SIZE(x) ((x) << 8)
1525 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
1526 #define PQ_VOLATILE (1 << 26)
1527 #define NO_UPDATE_RPTR (1 << 27)
1528 #define UNORD_DISPATCH (1 << 28)
1529 #define ROQ_PQ_IB_FLIP (1 << 29)
1530 #define PRIV_STATE (1 << 30)
1531 #define KMD_QUEUE (1 << 31)
1533 #define CP_HQD_IB_BASE_ADDR 0xC95Cu
1534 #define CP_HQD_IB_BASE_ADDR_HI 0xC960u
1535 #define CP_HQD_IB_RPTR 0xC964u
1536 #define CP_HQD_IB_CONTROL 0xC968u
1537 #define IB_ATC_EN (1U << 23)
1538 #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
1540 #define CP_HQD_DEQUEUE_REQUEST 0xC974
1541 #define DEQUEUE_REQUEST_DRAIN 1
1542 #define DEQUEUE_REQUEST_RESET 2
1544 #define CP_MQD_CONTROL 0xC99C
1545 #define MQD_VMID(x) ((x) << 0)
1546 #define MQD_VMID_MASK (0xf << 0)
1548 #define CP_HQD_SEMA_CMD 0xC97Cu
1549 #define CP_HQD_MSG_TYPE 0xC980u
1550 #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u
1551 #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u
1552 #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu
1553 #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u
1554 #define CP_HQD_HQ_SCHEDULER0 0xC994u
1555 #define CP_HQD_HQ_SCHEDULER1 0xC998u
1557 #define SH_STATIC_MEM_CONFIG 0x9604u
1559 #define DB_RENDER_CONTROL 0x28000
1561 #define PA_SC_RASTER_CONFIG 0x28350
1562 # define RASTER_CONFIG_RB_MAP_0 0
1563 # define RASTER_CONFIG_RB_MAP_1 1
1564 # define RASTER_CONFIG_RB_MAP_2 2
1565 # define RASTER_CONFIG_RB_MAP_3 3
1566 #define PKR_MAP(x) ((x) << 8)
1568 #define VGT_EVENT_INITIATOR 0x28a90
1569 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1570 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1571 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1572 # define CACHE_FLUSH_TS (4 << 0)
1573 # define CACHE_FLUSH (6 << 0)
1574 # define CS_PARTIAL_FLUSH (7 << 0)
1575 # define VGT_STREAMOUT_RESET (10 << 0)
1576 # define END_OF_PIPE_INCR_DE (11 << 0)
1577 # define END_OF_PIPE_IB_END (12 << 0)
1578 # define RST_PIX_CNT (13 << 0)
1579 # define VS_PARTIAL_FLUSH (15 << 0)
1580 # define PS_PARTIAL_FLUSH (16 << 0)
1581 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1582 # define ZPASS_DONE (21 << 0)
1583 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1584 # define PERFCOUNTER_START (23 << 0)
1585 # define PERFCOUNTER_STOP (24 << 0)
1586 # define PIPELINESTAT_START (25 << 0)
1587 # define PIPELINESTAT_STOP (26 << 0)
1588 # define PERFCOUNTER_SAMPLE (27 << 0)
1589 # define SAMPLE_PIPELINESTAT (30 << 0)
1590 # define SO_VGT_STREAMOUT_FLUSH (31 << 0)
1591 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1592 # define RESET_VTX_CNT (33 << 0)
1593 # define VGT_FLUSH (36 << 0)
1594 # define BOTTOM_OF_PIPE_TS (40 << 0)
1595 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1596 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1597 # define FLUSH_AND_INV_DB_META (44 << 0)
1598 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1599 # define FLUSH_AND_INV_CB_META (46 << 0)
1600 # define CS_DONE (47 << 0)
1601 # define PS_DONE (48 << 0)
1602 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1603 # define THREAD_TRACE_START (51 << 0)
1604 # define THREAD_TRACE_STOP (52 << 0)
1605 # define THREAD_TRACE_FLUSH (54 << 0)
1606 # define THREAD_TRACE_FINISH (55 << 0)
1607 # define PIXEL_PIPE_STAT_CONTROL (56 << 0)
1608 # define PIXEL_PIPE_STAT_DUMP (57 << 0)
1609 # define PIXEL_PIPE_STAT_RESET (58 << 0)
1611 #define SCRATCH_REG0 0x30100
1612 #define SCRATCH_REG1 0x30104
1613 #define SCRATCH_REG2 0x30108
1614 #define SCRATCH_REG3 0x3010C
1615 #define SCRATCH_REG4 0x30110
1616 #define SCRATCH_REG5 0x30114
1617 #define SCRATCH_REG6 0x30118
1618 #define SCRATCH_REG7 0x3011C
1620 #define SCRATCH_UMSK 0x30140
1621 #define SCRATCH_ADDR 0x30144
1623 #define CP_SEM_WAIT_TIMER 0x301BC
1625 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
1627 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
1629 #define GRBM_GFX_INDEX 0x30800
1630 #define INSTANCE_INDEX(x) ((x) << 0)
1631 #define SH_INDEX(x) ((x) << 8)
1632 #define SE_INDEX(x) ((x) << 16)
1633 #define SH_BROADCAST_WRITES (1 << 29)
1634 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1635 #define SE_BROADCAST_WRITES (1 << 31)
1637 #define VGT_ESGS_RING_SIZE 0x30900
1638 #define VGT_GSVS_RING_SIZE 0x30904
1639 #define VGT_PRIMITIVE_TYPE 0x30908
1640 #define VGT_INDEX_TYPE 0x3090C
1642 #define VGT_NUM_INDICES 0x30930
1643 #define VGT_NUM_INSTANCES 0x30934
1644 #define VGT_TF_RING_SIZE 0x30938
1645 #define VGT_HS_OFFCHIP_PARAM 0x3093C
1646 #define VGT_TF_MEMORY_BASE 0x30940
1648 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00
1649 #define PA_SC_LINE_STIPPLE_STATE 0x30a04
1651 #define SQC_CACHES 0x30d20
1653 #define CP_PERFMON_CNTL 0x36020
1655 #define CGTS_SM_CTRL_REG 0x3c000
1656 #define SM_MODE(x) ((x) << 17)
1657 #define SM_MODE_MASK (0x7 << 17)
1658 #define SM_MODE_ENABLE (1 << 20)
1659 #define CGTS_OVERRIDE (1 << 21)
1660 #define CGTS_LS_OVERRIDE (1 << 22)
1661 #define ON_MONITOR_ADD_EN (1 << 23)
1662 #define ON_MONITOR_ADD(x) ((x) << 24)
1663 #define ON_MONITOR_ADD_MASK (0xff << 24)
1665 #define CGTS_TCC_DISABLE 0x3c00c
1666 #define CGTS_USER_TCC_DISABLE 0x3c010
1667 #define TCC_DISABLE_MASK 0xFFFF0000
1668 #define TCC_DISABLE_SHIFT 16
1670 #define CB_CGTT_SCLK_CTRL 0x3c2a0
1672 /*
1673 * PM4
1674 */
1675 #define PACKET_TYPE0 0
1676 #define PACKET_TYPE1 1
1677 #define PACKET_TYPE2 2
1678 #define PACKET_TYPE3 3
1680 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1681 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1682 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1683 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1684 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1685 (((reg) >> 2) & 0xFFFF) | \
1686 ((n) & 0x3FFF) << 16)
1687 #define CP_PACKET2 0x80000000
1688 #define PACKET2_PAD_SHIFT 0
1689 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1691 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1693 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1694 (((op) & 0xFF) << 8) | \
1695 ((n) & 0x3FFF) << 16)
1697 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1699 /* Packet 3 types */
1700 #define PACKET3_NOP 0x10
1701 #define PACKET3_SET_BASE 0x11
1702 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1703 #define CE_PARTITION_BASE 3
1704 #define PACKET3_CLEAR_STATE 0x12
1705 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1706 #define PACKET3_DISPATCH_DIRECT 0x15
1707 #define PACKET3_DISPATCH_INDIRECT 0x16
1708 #define PACKET3_ATOMIC_GDS 0x1D
1709 #define PACKET3_ATOMIC_MEM 0x1E
1710 #define PACKET3_OCCLUSION_QUERY 0x1F
1711 #define PACKET3_SET_PREDICATION 0x20
1712 #define PACKET3_REG_RMW 0x21
1713 #define PACKET3_COND_EXEC 0x22
1714 #define PACKET3_PRED_EXEC 0x23
1715 #define PACKET3_DRAW_INDIRECT 0x24
1716 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1717 #define PACKET3_INDEX_BASE 0x26
1718 #define PACKET3_DRAW_INDEX_2 0x27
1719 #define PACKET3_CONTEXT_CONTROL 0x28
1720 #define PACKET3_INDEX_TYPE 0x2A
1721 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1722 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1723 #define PACKET3_NUM_INSTANCES 0x2F
1724 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1725 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
1726 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1727 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1728 #define PACKET3_DRAW_PREAMBLE 0x36
1729 #define PACKET3_WRITE_DATA 0x37
1730 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1731 /* 0 - register
1732 * 1 - memory (sync - via GRBM)
1733 * 2 - gl2
1734 * 3 - gds
1735 * 4 - reserved
1736 * 5 - memory (async - direct)
1737 */
1738 #define WR_ONE_ADDR (1 << 16)
1739 #define WR_CONFIRM (1 << 20)
1740 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
1741 /* 0 - LRU
1742 * 1 - Stream
1743 */
1744 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1745 /* 0 - me
1746 * 1 - pfp
1747 * 2 - ce
1748 */
1749 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1750 #define PACKET3_MEM_SEMAPHORE 0x39
1751 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
1754 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1755 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1756 #define PACKET3_COPY_DW 0x3B
1757 #define PACKET3_WAIT_REG_MEM 0x3C
1758 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1759 /* 0 - always
1760 * 1 - <
1761 * 2 - <=
1762 * 3 - ==
1763 * 4 - !=
1764 * 5 - >=
1765 * 6 - >
1766 */
1767 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1768 /* 0 - reg
1769 * 1 - mem
1770 */
1771 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
1772 /* 0 - wait_reg_mem
1773 * 1 - wr_wait_wr_reg
1774 */
1775 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1776 /* 0 - me
1777 * 1 - pfp
1778 */
1779 #define PACKET3_INDIRECT_BUFFER 0x3F
1780 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1781 #define INDIRECT_BUFFER_VALID (1 << 23)
1782 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
1783 /* 0 - LRU
1784 * 1 - Stream
1785 * 2 - Bypass
1786 */
1787 #define PACKET3_COPY_DATA 0x40
1788 #define PACKET3_PFP_SYNC_ME 0x42
1789 #define PACKET3_SURFACE_SYNC 0x43
1790 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1791 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1792 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1793 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1794 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1795 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1796 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1797 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1798 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1799 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1800 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1801 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1804 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1805 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1806 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1808 # define PACKET3_CB_ACTION_ENA (1 << 25)
1809 # define PACKET3_DB_ACTION_ENA (1 << 26)
1810 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1811 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1812 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1813 #define PACKET3_COND_WRITE 0x45
1814 #define PACKET3_EVENT_WRITE 0x46
1815 #define EVENT_TYPE(x) ((x) << 0)
1816 #define EVENT_INDEX(x) ((x) << 8)
1817 /* 0 - any non-TS event
1818 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1819 * 2 - SAMPLE_PIPELINESTAT
1820 * 3 - SAMPLE_STREAMOUTSTAT*
1821 * 4 - *S_PARTIAL_FLUSH
1822 * 5 - EOP events
1823 * 6 - EOS events
1824 */
1825 #define PACKET3_EVENT_WRITE_EOP 0x47
1826 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1829 #define EOP_TCL1_ACTION_EN (1 << 16)
1831 #define EOP_TCL2_VOLATILE (1 << 24)
1832 #define EOP_CACHE_POLICY(x) ((x) << 25)
1833 /* 0 - LRU
1834 * 1 - Stream
1835 * 2 - Bypass
1836 */
1837 #define DATA_SEL(x) ((x) << 29)
1838 /* 0 - discard
1839 * 1 - send low 32bit data
1840 * 2 - send 64bit data
1841 * 3 - send 64bit GPU counter value
1842 * 4 - send 64bit sys counter value
1843 */
1844 #define INT_SEL(x) ((x) << 24)
1845 /* 0 - none
1846 * 1 - interrupt only (DATA_SEL = 0)
1847 * 2 - interrupt when data write is confirmed
1848 */
1849 #define DST_SEL(x) ((x) << 16)
1850 /* 0 - MC
1851 * 1 - TC/L2
1852 */
1853 #define PACKET3_EVENT_WRITE_EOS 0x48
1854 #define PACKET3_RELEASE_MEM 0x49
1855 #define PACKET3_PREAMBLE_CNTL 0x4A
1856 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1857 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1858 #define PACKET3_DMA_DATA 0x50
1859 /* 1. header
1860 * 2. CONTROL
1861 * 3. SRC_ADDR_LO or DATA [31:0]
1862 * 4. SRC_ADDR_HI [31:0]
1863 * 5. DST_ADDR_LO [31:0]
1864 * 6. DST_ADDR_HI [7:0]
1865 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
1866 */
1867 /* CONTROL */
1868 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
1869 /* 0 - ME
1870 * 1 - PFP
1871 */
1872 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
1873 /* 0 - LRU
1874 * 1 - Stream
1875 * 2 - Bypass
1876 */
1877 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
1878 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
1879 /* 0 - DST_ADDR using DAS
1880 * 1 - GDS
1881 * 3 - DST_ADDR using L2
1882 */
1883 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
1884 /* 0 - LRU
1885 * 1 - Stream
1886 * 2 - Bypass
1887 */
1888 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
1889 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
1890 /* 0 - SRC_ADDR using SAS
1891 * 1 - GDS
1892 * 2 - DATA
1893 * 3 - SRC_ADDR using L2
1894 */
1895 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
1896 /* COMMAND */
1897 # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
1898 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
1899 /* 0 - none
1900 * 1 - 8 in 16
1901 * 2 - 8 in 32
1902 * 3 - 8 in 64
1903 */
1904 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
1905 /* 0 - none
1906 * 1 - 8 in 16
1907 * 2 - 8 in 32
1908 * 3 - 8 in 64
1909 */
1910 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
1911 /* 0 - memory
1912 * 1 - register
1913 */
1914 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
1915 /* 0 - memory
1916 * 1 - register
1917 */
1918 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
1919 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
1920 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
1921 #define PACKET3_AQUIRE_MEM 0x58
1922 #define PACKET3_REWIND 0x59
1923 #define PACKET3_LOAD_UCONFIG_REG 0x5E
1924 #define PACKET3_LOAD_SH_REG 0x5F
1925 #define PACKET3_LOAD_CONFIG_REG 0x60
1926 #define PACKET3_LOAD_CONTEXT_REG 0x61
1927 #define PACKET3_SET_CONFIG_REG 0x68
1928 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1929 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1930 #define PACKET3_SET_CONTEXT_REG 0x69
1931 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1932 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1933 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1934 #define PACKET3_SET_SH_REG 0x76
1935 #define PACKET3_SET_SH_REG_START 0x0000b000
1936 #define PACKET3_SET_SH_REG_END 0x0000c000
1937 #define PACKET3_SET_SH_REG_OFFSET 0x77
1938 #define PACKET3_SET_QUEUE_REG 0x78
1939 #define PACKET3_SET_UCONFIG_REG 0x79
1940 #define PACKET3_SET_UCONFIG_REG_START 0x00030000
1941 #define PACKET3_SET_UCONFIG_REG_END 0x00031000
1942 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1943 #define PACKET3_SCRATCH_RAM_READ 0x7E
1944 #define PACKET3_LOAD_CONST_RAM 0x80
1945 #define PACKET3_WRITE_CONST_RAM 0x81
1946 #define PACKET3_DUMP_CONST_RAM 0x83
1947 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1948 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1949 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1950 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1951 #define PACKET3_SWITCH_BUFFER 0x8B
1953 /* SDMA - first instance at 0xd000, second at 0xd800 */
1957 #define SDMA0_UCODE_ADDR 0xD000
1958 #define SDMA0_UCODE_DATA 0xD004
1959 #define SDMA0_POWER_CNTL 0xD008
1960 #define SDMA0_CLK_CTRL 0xD00C
1962 #define SDMA0_CNTL 0xD010
1963 # define TRAP_ENABLE (1 << 0)
1964 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1965 # define SEM_WAIT_INT_ENABLE (1 << 2)
1966 # define DATA_SWAP_ENABLE (1 << 3)
1967 # define FENCE_SWAP_ENABLE (1 << 4)
1968 # define AUTO_CTXSW_ENABLE (1 << 18)
1969 # define CTXEMPTY_INT_ENABLE (1 << 28)
1971 #define SDMA0_TILING_CONFIG 0xD018
1973 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
1974 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
1976 #define SDMA0_STATUS_REG 0xd034
1977 # define SDMA_IDLE (1 << 0)
1979 #define SDMA0_ME_CNTL 0xD048
1980 # define SDMA_HALT (1 << 0)
1982 #define SDMA0_GFX_RB_CNTL 0xD200
1983 # define SDMA_RB_ENABLE (1 << 0)
1986 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1989 #define SDMA0_GFX_RB_BASE 0xD204
1990 #define SDMA0_GFX_RB_BASE_HI 0xD208
1991 #define SDMA0_GFX_RB_RPTR 0xD20C
1992 #define SDMA0_GFX_RB_WPTR 0xD210
1994 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
1995 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
1996 #define SDMA0_GFX_IB_CNTL 0xD228
1997 # define SDMA_IB_ENABLE (1 << 0)
1998 # define SDMA_IB_SWAP_ENABLE (1 << 4)
1999 # define SDMA_SWITCH_INSIDE_IB (1 << 8)
2000 # define SDMA_CMD_VMID(x) ((x) << 16)
2002 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
2003 #define SDMA0_GFX_APE1_CNTL 0xD2A0
2005 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
2006 (((sub_op) & 0xFF) << 8) | \
2007 (((op) & 0xFF) << 0))
2008 /* sDMA opcodes */
2009 #define SDMA_OPCODE_NOP 0
2010 #define SDMA_OPCODE_COPY 1
2011 # define SDMA_COPY_SUB_OPCODE_LINEAR 0
2012 # define SDMA_COPY_SUB_OPCODE_TILED 1
2013 # define SDMA_COPY_SUB_OPCODE_SOA 3
2014 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
2015 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
2016 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
2017 #define SDMA_OPCODE_WRITE 2
2018 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
2019 # define SDMA_WRTIE_SUB_OPCODE_TILED 1
2020 #define SDMA_OPCODE_INDIRECT_BUFFER 4
2021 #define SDMA_OPCODE_FENCE 5
2022 #define SDMA_OPCODE_TRAP 6
2023 #define SDMA_OPCODE_SEMAPHORE 7
2024 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
2025 /* 0 - increment
2026 * 1 - write 1
2027 */
2028 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
2029 /* 0 - wait
2030 * 1 - signal
2031 */
2032 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
2033 /* mailbox */
2034 #define SDMA_OPCODE_POLL_REG_MEM 8
2035 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
2036 /* 0 - wait_reg_mem
2037 * 1 - wr_wait_wr_reg
2038 */
2039 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
2040 /* 0 - always
2041 * 1 - <
2042 * 2 - <=
2043 * 3 - ==
2044 * 4 - !=
2045 * 5 - >=
2046 * 6 - >
2047 */
2048 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
2049 /* 0 = register
2050 * 1 = memory
2051 */
2052 #define SDMA_OPCODE_COND_EXEC 9
2053 #define SDMA_OPCODE_CONSTANT_FILL 11
2054 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
2055 /* 0 = byte fill
2056 * 2 = DW fill
2057 */
2058 #define SDMA_OPCODE_GENERATE_PTE_PDE 12
2059 #define SDMA_OPCODE_TIMESTAMP 13
2060 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
2061 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
2062 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
2063 #define SDMA_OPCODE_SRBM_WRITE 14
2064 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
2065 /* byte mask */
2067 /* UVD */
2069 #define UVD_UDEC_ADDR_CONFIG 0xef4c
2070 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
2071 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
2073 #define UVD_LMI_EXT40_ADDR 0xf498
2074 #define UVD_LMI_ADDR_EXT 0xf594
2075 #define UVD_VCPU_CACHE_OFFSET0 0xf608
2076 #define UVD_VCPU_CACHE_SIZE0 0xf60c
2077 #define UVD_VCPU_CACHE_OFFSET1 0xf610
2078 #define UVD_VCPU_CACHE_SIZE1 0xf614
2079 #define UVD_VCPU_CACHE_OFFSET2 0xf618
2080 #define UVD_VCPU_CACHE_SIZE2 0xf61c
2082 #define UVD_RBC_RB_RPTR 0xf690
2083 #define UVD_RBC_RB_WPTR 0xf694
2085 #define UVD_CGC_CTRL 0xF4B0
2086 # define DCM (1 << 0)
2087 # define CG_DT(x) ((x) << 2)
2088 # define CG_DT_MASK (0xf << 2)
2089 # define CLK_OD(x) ((x) << 6)
2090 # define CLK_OD_MASK (0x1f << 6)
2092 #define UVD_STATUS 0xf6bc
2094 /* UVD clocks */
2096 #define CG_DCLK_CNTL 0xC050009C
2097 # define DCLK_DIVIDER_MASK 0x7f
2098 # define DCLK_DIR_CNTL_EN (1 << 8)
2099 #define CG_DCLK_STATUS 0xC05000A0
2100 # define DCLK_STATUS (1 << 0)
2101 #define CG_VCLK_CNTL 0xC05000A4
2102 #define CG_VCLK_STATUS 0xC05000A8
2104 /* UVD CTX indirect */
2105 #define UVD_CGC_MEM_CTRL 0xC0
2107 /* VCE */
2109 #define VCE_VCPU_CACHE_OFFSET0 0x20024
2110 #define VCE_VCPU_CACHE_SIZE0 0x20028
2111 #define VCE_VCPU_CACHE_OFFSET1 0x2002c
2112 #define VCE_VCPU_CACHE_SIZE1 0x20030
2113 #define VCE_VCPU_CACHE_OFFSET2 0x20034
2114 #define VCE_VCPU_CACHE_SIZE2 0x20038
2115 #define VCE_RB_RPTR2 0x20178
2116 #define VCE_RB_WPTR2 0x2017c
2117 #define VCE_RB_RPTR 0x2018c
2118 #define VCE_RB_WPTR 0x20190
2119 #define VCE_CLOCK_GATING_A 0x202f8
2120 # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0)
2121 # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0)
2122 # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4)
2123 # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4)
2124 # define CGC_UENC_WAIT_AWAKE (1 << 18)
2125 #define VCE_CLOCK_GATING_B 0x202fc
2126 #define VCE_CGTT_CLK_OVERRIDE 0x207a0
2127 #define VCE_UENC_CLOCK_GATING 0x207bc
2128 # define CLOCK_ON_DELAY_MASK (0xf << 0)
2129 # define CLOCK_ON_DELAY(x) ((x) << 0)
2130 # define CLOCK_OFF_DELAY_MASK (0xff << 4)
2131 # define CLOCK_OFF_DELAY(x) ((x) << 4)
2132 #define VCE_UENC_REG_CLOCK_GATING 0x207c0
2133 #define VCE_SYS_INT_EN 0x21300
2134 # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
2135 #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
2136 #define VCE_LMI_CTRL2 0x21474
2137 #define VCE_LMI_CTRL 0x21498
2138 #define VCE_LMI_VM_CTRL 0x214a0
2139 #define VCE_LMI_SWAP_CNTL 0x214b4
2140 #define VCE_LMI_SWAP_CNTL1 0x214b8
2141 #define VCE_LMI_CACHE_CTRL 0x214f4
2143 #define VCE_CMD_NO_OP 0x00000000
2144 #define VCE_CMD_END 0x00000001
2145 #define VCE_CMD_IB 0x00000002
2146 #define VCE_CMD_FENCE 0x00000003
2147 #define VCE_CMD_TRAP 0x00000004
2148 #define VCE_CMD_IB_AUTO 0x00000005
2149 #define VCE_CMD_SEMAPHORE 0x00000006
2151 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u
2152 #define ATC_VMID0_PASID_MAPPING 0x339Cu
2153 #define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF)
2154 #define ATC_VMID_PASID_MAPPING_PASID_SHIFT 0
2155 #define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31)
2156 #define ATC_VMID_PASID_MAPPING_VALID_SHIFT 31
2158 #define ATC_VM_APERTURE0_CNTL 0x3310u
2159 #define ATS_ACCESS_MODE_NEVER 0
2160 #define ATS_ACCESS_MODE_ALWAYS 1
2162 #define ATC_VM_APERTURE0_CNTL2 0x3318u
2163 #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u
2164 #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u
2165 #define ATC_VM_APERTURE1_CNTL 0x3314u
2166 #define ATC_VM_APERTURE1_CNTL2 0x331Cu
2167 #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu
2168 #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u
2170 #define IH_VMID_0_LUT 0x3D40u
2172 #endif