1 /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002.
4 * Copyright (C) 2004 Nicolai Haehnle.
7 * The Weather Channel (TM) funded Tungsten Graphics to develop the
8 * initial release of the Radeon 8500 driver under the XFree86 license.
9 * This notice must be preserved.
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 * Nicolai Haehnle <prefect_@gmx.net>
33 * ------------------------ This file is DEPRECATED! -------------------------
37 #include <drm/radeon_drm.h>
38 #include "radeon_drv.h"
40 #include "drm_buffer.h"
42 #include <asm/unaligned.h>
44 #define R300_SIMULTANEOUS_CLIPRECTS 4
46 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
48 static const int r300_cliprect_cntl
[4] = {
56 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
57 * buffer, starting with index n.
59 static int r300_emit_cliprects(drm_radeon_private_t
*dev_priv
,
60 drm_radeon_kcmd_buffer_t
*cmdbuf
, int n
)
62 struct drm_clip_rect box
;
67 nr
= cmdbuf
->nbox
- n
;
68 if (nr
> R300_SIMULTANEOUS_CLIPRECTS
)
69 nr
= R300_SIMULTANEOUS_CLIPRECTS
;
71 DRM_DEBUG("%i cliprects\n", nr
);
74 BEGIN_RING(6 + nr
* 2);
75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0
, nr
* 2 - 1));
77 for (i
= 0; i
< nr
; ++i
) {
79 (&box
, &cmdbuf
->boxes
[n
+ i
], sizeof(box
))) {
80 DRM_ERROR("copy cliprect faulted\n");
84 box
.x2
--; /* Hardware expects inclusive bottom-right corner */
87 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV515
) {
97 box
.x1
= (box
.x1
+ R300_CLIPRECT_OFFSET
) &
99 box
.y1
= (box
.y1
+ R300_CLIPRECT_OFFSET
) &
101 box
.x2
= (box
.x2
+ R300_CLIPRECT_OFFSET
) &
103 box
.y2
= (box
.y2
+ R300_CLIPRECT_OFFSET
) &
107 OUT_RING((box
.x1
<< R300_CLIPRECT_X_SHIFT
) |
108 (box
.y1
<< R300_CLIPRECT_Y_SHIFT
));
109 OUT_RING((box
.x2
<< R300_CLIPRECT_X_SHIFT
) |
110 (box
.y2
<< R300_CLIPRECT_Y_SHIFT
));
114 OUT_RING_REG(R300_RE_CLIPRECT_CNTL
, r300_cliprect_cntl
[nr
- 1]);
116 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
117 * client might be able to trample over memory.
118 * The impact should be very limited, but I'd rather be safe than
121 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL
, 1));
123 OUT_RING(R300_SCISSORS_X_MASK
| R300_SCISSORS_Y_MASK
);
126 /* Why we allow zero cliprect rendering:
127 * There are some commands in a command buffer that must be submitted
128 * even when there are no cliprects, e.g. DMA buffer discard
129 * or state setting (though state setting could be avoided by
130 * simulating a loss of context).
132 * Now since the cmdbuf interface is so chaotic right now (and is
133 * bound to remain that way for a bit until things settle down),
134 * it is basically impossible to filter out the commands that are
135 * necessary and those that aren't.
137 * So I choose the safe way and don't do any filtering at all;
138 * instead, I simply set up the engine so that all rendering
139 * can't produce any fragments.
142 OUT_RING_REG(R300_RE_CLIPRECT_CNTL
, 0);
146 /* flus cache and wait idle clean after cliprect change */
148 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
149 OUT_RING(R300_RB3D_DC_FLUSH
);
152 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
153 OUT_RING(RADEON_WAIT_3D_IDLECLEAN
);
156 dev_priv
->track_flush
|= RADEON_FLUSH_EMITED
;
161 static u8 r300_reg_flags
[0x10000 >> 2];
163 void r300_init_reg_flags(struct drm_device
*dev
)
166 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
168 memset(r300_reg_flags
, 0, 0x10000 >> 2);
169 #define ADD_RANGE_MARK(reg, count,mark) \
170 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
171 r300_reg_flags[i]|=(mark);
174 #define MARK_CHECK_OFFSET 2
176 #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
178 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
179 ADD_RANGE(R300_SE_VPORT_XSCALE
, 6);
180 ADD_RANGE(R300_VAP_CNTL
, 1);
181 ADD_RANGE(R300_SE_VTE_CNTL
, 2);
182 ADD_RANGE(0x2134, 2);
183 ADD_RANGE(R300_VAP_CNTL_STATUS
, 1);
184 ADD_RANGE(R300_VAP_INPUT_CNTL_0
, 2);
185 ADD_RANGE(0x21DC, 1);
186 ADD_RANGE(R300_VAP_UNKNOWN_221C
, 1);
187 ADD_RANGE(R300_VAP_CLIP_X_0
, 4);
188 ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG
, 1);
189 ADD_RANGE(R300_VAP_UNKNOWN_2288
, 1);
190 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
191 ADD_RANGE(R300_VAP_PVS_CNTL_1
, 3);
192 ADD_RANGE(R300_GB_ENABLE
, 1);
193 ADD_RANGE(R300_GB_MSPOS0
, 5);
194 ADD_RANGE(R300_TX_INVALTAGS
, 1);
195 ADD_RANGE(R300_TX_ENABLE
, 1);
196 ADD_RANGE(0x4200, 4);
197 ADD_RANGE(0x4214, 1);
198 ADD_RANGE(R300_RE_POINTSIZE
, 1);
199 ADD_RANGE(0x4230, 3);
200 ADD_RANGE(R300_RE_LINE_CNT
, 1);
201 ADD_RANGE(R300_RE_UNK4238
, 1);
202 ADD_RANGE(0x4260, 3);
203 ADD_RANGE(R300_RE_SHADE
, 4);
204 ADD_RANGE(R300_RE_POLYGON_MODE
, 5);
205 ADD_RANGE(R300_RE_ZBIAS_CNTL
, 1);
206 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR
, 4);
207 ADD_RANGE(R300_RE_OCCLUSION_CNTL
, 1);
208 ADD_RANGE(R300_RE_CULL_CNTL
, 1);
209 ADD_RANGE(0x42C0, 2);
210 ADD_RANGE(R300_RS_CNTL_0
, 2);
212 ADD_RANGE(R300_SU_REG_DEST
, 1);
213 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV530
)
214 ADD_RANGE(RV530_FG_ZBREG_DEST
, 1);
216 ADD_RANGE(R300_SC_HYPERZ
, 2);
217 ADD_RANGE(0x43E8, 1);
219 ADD_RANGE(0x46A4, 5);
221 ADD_RANGE(R300_RE_FOG_STATE
, 1);
222 ADD_RANGE(R300_FOG_COLOR_R
, 3);
223 ADD_RANGE(R300_PP_ALPHA_TEST
, 2);
224 ADD_RANGE(0x4BD8, 1);
225 ADD_RANGE(R300_PFS_PARAM_0_X
, 64);
226 ADD_RANGE(0x4E00, 1);
227 ADD_RANGE(R300_RB3D_CBLEND
, 2);
228 ADD_RANGE(R300_RB3D_COLORMASK
, 1);
229 ADD_RANGE(R300_RB3D_BLEND_COLOR
, 3);
230 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0
, 1, MARK_CHECK_OFFSET
); /* check offset */
231 ADD_RANGE(R300_RB3D_COLORPITCH0
, 1);
232 ADD_RANGE(0x4E50, 9);
233 ADD_RANGE(0x4E88, 1);
234 ADD_RANGE(0x4EA0, 2);
235 ADD_RANGE(R300_ZB_CNTL
, 3);
236 ADD_RANGE(R300_ZB_FORMAT
, 4);
237 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET
, 1, MARK_CHECK_OFFSET
); /* check offset */
238 ADD_RANGE(R300_ZB_DEPTHPITCH
, 1);
239 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE
, 1);
240 ADD_RANGE(R300_ZB_ZMASK_OFFSET
, 13);
241 ADD_RANGE(R300_ZB_ZPASS_DATA
, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */
243 ADD_RANGE(R300_TX_FILTER_0
, 16);
244 ADD_RANGE(R300_TX_FILTER1_0
, 16);
245 ADD_RANGE(R300_TX_SIZE_0
, 16);
246 ADD_RANGE(R300_TX_FORMAT_0
, 16);
247 ADD_RANGE(R300_TX_PITCH_0
, 16);
248 /* Texture offset is dangerous and needs more checking */
249 ADD_RANGE_MARK(R300_TX_OFFSET_0
, 16, MARK_CHECK_OFFSET
);
250 ADD_RANGE(R300_TX_CHROMA_KEY_0
, 16);
251 ADD_RANGE(R300_TX_BORDER_COLOR_0
, 16);
253 /* Sporadic registers used as primitives are emitted */
254 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT
, 1);
255 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT
, 1);
256 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0
, 8);
257 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0
, 8);
259 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV515
) {
260 ADD_RANGE(R500_VAP_INDEX_OFFSET
, 1);
261 ADD_RANGE(R500_US_CONFIG
, 2);
262 ADD_RANGE(R500_US_CODE_ADDR
, 3);
263 ADD_RANGE(R500_US_FC_CTRL
, 1);
264 ADD_RANGE(R500_RS_IP_0
, 16);
265 ADD_RANGE(R500_RS_INST_0
, 16);
266 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR
, 2);
267 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR
, 2);
268 ADD_RANGE(R500_ZB_FIFO_SIZE
, 2);
270 ADD_RANGE(R300_PFS_CNTL_0
, 3);
271 ADD_RANGE(R300_PFS_NODE_0
, 4);
272 ADD_RANGE(R300_PFS_TEXI_0
, 64);
273 ADD_RANGE(R300_PFS_INSTR0_0
, 64);
274 ADD_RANGE(R300_PFS_INSTR1_0
, 64);
275 ADD_RANGE(R300_PFS_INSTR2_0
, 64);
276 ADD_RANGE(R300_PFS_INSTR3_0
, 64);
277 ADD_RANGE(R300_RS_INTERP_0
, 8);
278 ADD_RANGE(R300_RS_ROUTE_0
, 8);
283 static __inline__
int r300_check_range(unsigned reg
, int count
)
288 for (i
= (reg
>> 2); i
< (reg
>> 2) + count
; i
++)
289 if (r300_reg_flags
[i
] != MARK_SAFE
)
294 static __inline__
int r300_emit_carefully_checked_packet0(drm_radeon_private_t
*
296 drm_radeon_kcmd_buffer_t
298 drm_r300_cmd_header_t
307 sz
= header
.packet0
.count
;
308 reg
= (header
.packet0
.reghi
<< 8) | header
.packet0
.reglo
;
310 if ((sz
> 64) || (sz
< 0)) {
311 DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
316 for (i
= 0; i
< sz
; i
++) {
317 switch (r300_reg_flags
[(reg
>> 2) + i
]) {
320 case MARK_CHECK_OFFSET
:
321 value
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, i
);
322 if (!radeon_check_offset(dev_priv
, *value
)) {
323 DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n",
329 DRM_ERROR("Register %04x failed check as flag=%02x\n",
330 reg
+ i
* 4, r300_reg_flags
[(reg
>> 2) + i
]);
336 OUT_RING(CP_PACKET0(reg
, sz
- 1));
337 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, sz
);
344 * Emits a packet0 setting arbitrary registers.
345 * Called by r300_do_cp_cmdbuf.
347 * Note that checks are performed on contents and addresses of the registers
349 static __inline__
int r300_emit_packet0(drm_radeon_private_t
*dev_priv
,
350 drm_radeon_kcmd_buffer_t
*cmdbuf
,
351 drm_r300_cmd_header_t header
)
357 sz
= header
.packet0
.count
;
358 reg
= (header
.packet0
.reghi
<< 8) | header
.packet0
.reglo
;
363 if (sz
* 4 > drm_buffer_unprocessed(cmdbuf
->buffer
))
366 if (reg
+ sz
* 4 >= 0x10000) {
367 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg
,
372 if (r300_check_range(reg
, sz
)) {
373 /* go and check everything */
374 return r300_emit_carefully_checked_packet0(dev_priv
, cmdbuf
,
377 /* the rest of the data is safe to emit, whatever the values the user passed */
380 OUT_RING(CP_PACKET0(reg
, sz
- 1));
381 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, sz
);
388 * Uploads user-supplied vertex program instructions or parameters onto
390 * Called by r300_do_cp_cmdbuf.
392 static __inline__
int r300_emit_vpu(drm_radeon_private_t
*dev_priv
,
393 drm_radeon_kcmd_buffer_t
*cmdbuf
,
394 drm_r300_cmd_header_t header
)
400 sz
= header
.vpu
.count
;
401 addr
= (header
.vpu
.adrhi
<< 8) | header
.vpu
.adrlo
;
405 if (sz
* 16 > drm_buffer_unprocessed(cmdbuf
->buffer
))
408 /* VAP is very sensitive so we purge cache before we program it
409 * and we also flush its state before & after */
411 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
412 OUT_RING(R300_RB3D_DC_FLUSH
);
413 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
414 OUT_RING(RADEON_WAIT_3D_IDLECLEAN
);
415 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG
, 0));
419 dev_priv
->track_flush
|= RADEON_FLUSH_EMITED
;
421 BEGIN_RING(3 + sz
* 4);
422 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS
, addr
);
423 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA
, sz
* 4 - 1));
424 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, sz
* 4);
428 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG
, 0));
436 * Emit a clear packet from userspace.
437 * Called by r300_emit_packet3.
439 static __inline__
int r300_emit_clear(drm_radeon_private_t
*dev_priv
,
440 drm_radeon_kcmd_buffer_t
*cmdbuf
)
444 if (8 * 4 > drm_buffer_unprocessed(cmdbuf
->buffer
))
448 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2
, 8));
449 OUT_RING(R300_PRIM_TYPE_POINT
| R300_PRIM_WALK_RING
|
450 (1 << R300_PRIM_NUM_VERTICES_SHIFT
));
451 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, 8);
455 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
456 OUT_RING(R300_RB3D_DC_FLUSH
);
457 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
458 OUT_RING(RADEON_WAIT_3D_IDLECLEAN
);
461 dev_priv
->track_flush
|= RADEON_FLUSH_EMITED
;
466 static __inline__
int r300_emit_3d_load_vbpntr(drm_radeon_private_t
*dev_priv
,
467 drm_radeon_kcmd_buffer_t
*cmdbuf
,
471 #define MAX_ARRAY_PACKET 64
476 count
= (header
& RADEON_CP_PACKET_COUNT_MASK
) >> 16;
478 if ((count
+ 1) > MAX_ARRAY_PACKET
) {
479 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
483 /* carefully check packet contents */
485 /* We have already read the header so advance the buffer. */
486 drm_buffer_advance(cmdbuf
->buffer
, 4);
488 narrays
= *(u32
*)drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 0);
491 while ((k
< narrays
) && (i
< (count
+ 1))) {
492 i
++; /* skip attribute field */
493 data
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, i
);
494 if (!radeon_check_offset(dev_priv
, *data
)) {
496 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
504 /* have one more to process, they come in pairs */
505 data
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, i
);
506 if (!radeon_check_offset(dev_priv
, *data
)) {
508 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
515 /* do the counts match what we expect ? */
516 if ((k
!= narrays
) || (i
!= (count
+ 1))) {
518 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
519 k
, i
, narrays
, count
+ 1);
523 /* all clear, output packet */
525 BEGIN_RING(count
+ 2);
527 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, count
+ 1);
533 static __inline__
int r300_emit_bitblt_multi(drm_radeon_private_t
*dev_priv
,
534 drm_radeon_kcmd_buffer_t
*cmdbuf
)
536 u32
*cmd
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 0);
541 count
= (*cmd
& RADEON_CP_PACKET_COUNT_MASK
) >> 16;
545 u32
*cmd1
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 1);
546 if (*cmd1
& (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
547 | RADEON_GMC_DST_PITCH_OFFSET_CNTL
)) {
549 u32
*cmd2
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 2);
550 offset
= *cmd2
<< 10;
551 ret
= !radeon_check_offset(dev_priv
, offset
);
553 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset
);
558 if ((*cmd1
& RADEON_GMC_SRC_PITCH_OFFSET_CNTL
) &&
559 (*cmd1
& RADEON_GMC_DST_PITCH_OFFSET_CNTL
)) {
560 u32
*cmd3
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 3);
561 offset
= *cmd3
<< 10;
562 ret
= !radeon_check_offset(dev_priv
, offset
);
564 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset
);
572 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, count
+ 2);
578 static __inline__
int r300_emit_draw_indx_2(drm_radeon_private_t
*dev_priv
,
579 drm_radeon_kcmd_buffer_t
*cmdbuf
)
581 u32
*cmd
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 0);
582 u32
*cmd1
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 1);
587 count
= (*cmd
& RADEON_CP_PACKET_COUNT_MASK
) >> 16;
589 expected_count
= *cmd1
>> 16;
590 if (!(*cmd1
& R300_VAP_VF_CNTL__INDEX_SIZE_32bit
))
591 expected_count
= (expected_count
+1)/2;
593 if (count
&& count
!= expected_count
) {
594 DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n",
595 count
, expected_count
);
600 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, count
+ 2);
604 drm_r300_cmd_header_t stack_header
, *header
;
605 u32
*cmd1
, *cmd2
, *cmd3
;
607 if (drm_buffer_unprocessed(cmdbuf
->buffer
)
608 < 4*4 + sizeof(stack_header
)) {
609 DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n");
613 header
= drm_buffer_read_object(cmdbuf
->buffer
,
614 sizeof(stack_header
), &stack_header
);
616 cmd
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 0);
617 cmd1
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 1);
618 cmd2
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 2);
619 cmd3
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 3);
621 if (header
->header
.cmd_type
!= R300_CMD_PACKET3
||
622 header
->packet3
.packet
!= R300_CMD_PACKET3_RAW
||
623 *cmd
!= CP_PACKET3(RADEON_CP_INDX_BUFFER
, 2)) {
624 DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n");
628 if ((*cmd1
& 0x8000ffff) != 0x80000810) {
629 DRM_ERROR("Invalid indx_buffer reg address %08X\n",
633 if (!radeon_check_offset(dev_priv
, *cmd2
)) {
634 DRM_ERROR("Invalid indx_buffer offset is %08X\n",
638 if (*cmd3
!= expected_count
) {
639 DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n",
640 *cmd3
, expected_count
);
645 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, 4);
652 static __inline__
int r300_emit_raw_packet3(drm_radeon_private_t
*dev_priv
,
653 drm_radeon_kcmd_buffer_t
*cmdbuf
)
659 if (4 > drm_buffer_unprocessed(cmdbuf
->buffer
))
662 /* Fixme !! This simply emits a packet without much checking.
663 We need to be smarter. */
665 /* obtain first word - actual packet3 header */
666 header
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 0);
668 /* Is it packet 3 ? */
669 if ((*header
>> 30) != 0x3) {
670 DRM_ERROR("Not a packet3 header (0x%08x)\n", *header
);
674 count
= (*header
>> 16) & 0x3fff;
676 /* Check again now that we know how much data to expect */
677 if ((count
+ 2) * 4 > drm_buffer_unprocessed(cmdbuf
->buffer
)) {
679 ("Expected packet3 of length %d but have only %d bytes left\n",
680 (count
+ 2) * 4, drm_buffer_unprocessed(cmdbuf
->buffer
));
684 /* Is it a packet type we know about ? */
685 switch (*header
& 0xff00) {
686 case RADEON_3D_LOAD_VBPNTR
: /* load vertex array pointers */
687 return r300_emit_3d_load_vbpntr(dev_priv
, cmdbuf
, *header
);
689 case RADEON_CNTL_BITBLT_MULTI
:
690 return r300_emit_bitblt_multi(dev_priv
, cmdbuf
);
692 case RADEON_CP_INDX_BUFFER
:
693 DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n");
695 case RADEON_CP_3D_DRAW_IMMD_2
:
696 /* triggers drawing using in-packet vertex data */
697 case RADEON_CP_3D_DRAW_VBUF_2
:
698 /* triggers drawing of vertex buffers setup elsewhere */
699 dev_priv
->track_flush
&= ~(RADEON_FLUSH_EMITED
|
700 RADEON_PURGE_EMITED
);
702 case RADEON_CP_3D_DRAW_INDX_2
:
703 /* triggers drawing using indices to vertex buffer */
704 /* whenever we send vertex we clear flush & purge */
705 dev_priv
->track_flush
&= ~(RADEON_FLUSH_EMITED
|
706 RADEON_PURGE_EMITED
);
707 return r300_emit_draw_indx_2(dev_priv
, cmdbuf
);
708 case RADEON_WAIT_FOR_IDLE
:
710 /* these packets are safe */
713 DRM_ERROR("Unknown packet3 header (0x%08x)\n", *header
);
717 BEGIN_RING(count
+ 2);
718 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, count
+ 2);
725 * Emit a rendering packet3 from userspace.
726 * Called by r300_do_cp_cmdbuf.
728 static __inline__
int r300_emit_packet3(drm_radeon_private_t
*dev_priv
,
729 drm_radeon_kcmd_buffer_t
*cmdbuf
,
730 drm_r300_cmd_header_t header
)
734 int orig_iter
= cmdbuf
->buffer
->iterator
;
736 /* This is a do-while-loop so that we run the interior at least once,
737 * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
741 if (cmdbuf
->nbox
> R300_SIMULTANEOUS_CLIPRECTS
) {
742 ret
= r300_emit_cliprects(dev_priv
, cmdbuf
, n
);
746 cmdbuf
->buffer
->iterator
= orig_iter
;
749 switch (header
.packet3
.packet
) {
750 case R300_CMD_PACKET3_CLEAR
:
751 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
752 ret
= r300_emit_clear(dev_priv
, cmdbuf
);
754 DRM_ERROR("r300_emit_clear failed\n");
759 case R300_CMD_PACKET3_RAW
:
760 DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
761 ret
= r300_emit_raw_packet3(dev_priv
, cmdbuf
);
763 DRM_ERROR("r300_emit_raw_packet3 failed\n");
769 DRM_ERROR("bad packet3 type %i at byte %d\n",
770 header
.packet3
.packet
,
771 cmdbuf
->buffer
->iterator
- (int)sizeof(header
));
775 n
+= R300_SIMULTANEOUS_CLIPRECTS
;
776 } while (n
< cmdbuf
->nbox
);
781 /* Some of the R300 chips seem to be extremely touchy about the two registers
782 * that are configured in r300_pacify.
783 * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
784 * sends a command buffer that contains only state setting commands and a
785 * vertex program/parameter upload sequence, this will eventually lead to a
786 * lockup, unless the sequence is bracketed by calls to r300_pacify.
787 * So we should take great care to *always* call r300_pacify before
788 * *anything* 3D related, and again afterwards. This is what the
789 * call bracket in r300_do_cp_cmdbuf is for.
793 * Emit the sequence to pacify R300.
795 static void r300_pacify(drm_radeon_private_t
*dev_priv
)
797 uint32_t cache_z
, cache_3d
, cache_2d
;
800 cache_z
= R300_ZC_FLUSH
;
801 cache_2d
= R300_RB2D_DC_FLUSH
;
802 cache_3d
= R300_RB3D_DC_FLUSH
;
803 if (!(dev_priv
->track_flush
& RADEON_PURGE_EMITED
)) {
804 /* we can purge, primitive where draw since last purge */
805 cache_z
|= R300_ZC_FREE
;
806 cache_2d
|= R300_RB2D_DC_FREE
;
807 cache_3d
|= R300_RB3D_DC_FREE
;
810 /* flush & purge zbuffer */
812 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT
, 0));
815 /* flush & purge 3d */
817 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
820 /* flush & purge texture */
822 OUT_RING(CP_PACKET0(R300_TX_INVALTAGS
, 0));
825 /* FIXME: is this one really needed ? */
827 OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL
, 0));
831 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
832 OUT_RING(RADEON_WAIT_3D_IDLECLEAN
);
834 /* flush & purge 2d through E2 as RB2D will trigger lockup */
836 OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT
, 0));
838 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
839 OUT_RING(RADEON_WAIT_2D_IDLECLEAN
|
840 RADEON_WAIT_HOST_IDLECLEAN
);
842 /* set flush & purge flags */
843 dev_priv
->track_flush
|= RADEON_FLUSH_EMITED
| RADEON_PURGE_EMITED
;
847 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
848 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
849 * be careful about how this function is called.
851 static void r300_discard_buffer(struct drm_device
*dev
, struct drm_master
*master
, struct drm_buf
*buf
)
853 drm_radeon_buf_priv_t
*buf_priv
= buf
->dev_private
;
854 struct drm_radeon_master_private
*master_priv
= master
->driver_priv
;
856 buf_priv
->age
= ++master_priv
->sarea_priv
->last_dispatch
;
861 static void r300_cmd_wait(drm_radeon_private_t
* dev_priv
,
862 drm_r300_cmd_header_t header
)
867 if (!header
.wait
.flags
)
872 switch(header
.wait
.flags
) {
874 wait_until
= RADEON_WAIT_2D_IDLE
;
877 wait_until
= RADEON_WAIT_3D_IDLE
;
879 case R300_NEW_WAIT_2D_3D
:
880 wait_until
= RADEON_WAIT_2D_IDLE
|RADEON_WAIT_3D_IDLE
;
882 case R300_NEW_WAIT_2D_2D_CLEAN
:
883 wait_until
= RADEON_WAIT_2D_IDLE
|RADEON_WAIT_2D_IDLECLEAN
;
885 case R300_NEW_WAIT_3D_3D_CLEAN
:
886 wait_until
= RADEON_WAIT_3D_IDLE
|RADEON_WAIT_3D_IDLECLEAN
;
888 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN
:
889 wait_until
= RADEON_WAIT_2D_IDLE
|RADEON_WAIT_2D_IDLECLEAN
;
890 wait_until
|= RADEON_WAIT_3D_IDLE
|RADEON_WAIT_3D_IDLECLEAN
;
897 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL
, 0));
898 OUT_RING(wait_until
);
902 static int r300_scratch(drm_radeon_private_t
*dev_priv
,
903 drm_radeon_kcmd_buffer_t
*cmdbuf
,
904 drm_r300_cmd_header_t header
)
907 u32 i
, *buf_idx
, h_pending
;
912 if (drm_buffer_unprocessed(cmdbuf
->buffer
) <
913 (sizeof(u64
) + header
.scratch
.n_bufs
* sizeof(*buf_idx
))) {
917 if (header
.scratch
.reg
>= 5) {
921 dev_priv
->scratch_ages
[header
.scratch
.reg
]++;
923 ptr_addr
= drm_buffer_read_object(cmdbuf
->buffer
,
924 sizeof(stack_ptr_addr
), &stack_ptr_addr
);
925 ref_age_base
= (u32
*)(unsigned long)get_unaligned(ptr_addr
);
927 for (i
=0; i
< header
.scratch
.n_bufs
; i
++) {
928 buf_idx
= drm_buffer_pointer_to_dword(cmdbuf
->buffer
, 0);
929 *buf_idx
*= 2; /* 8 bytes per buf */
931 if (copy_to_user(ref_age_base
+ *buf_idx
,
932 &dev_priv
->scratch_ages
[header
.scratch
.reg
],
936 if (copy_from_user(&h_pending
,
937 ref_age_base
+ *buf_idx
+ 1,
946 if (copy_to_user(ref_age_base
+ *buf_idx
+ 1,
951 drm_buffer_advance(cmdbuf
->buffer
, sizeof(*buf_idx
));
955 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0
+ header
.scratch
.reg
* 4, 0 ) );
956 OUT_RING( dev_priv
->scratch_ages
[header
.scratch
.reg
] );
963 * Uploads user-supplied vertex program instructions or parameters onto
965 * Called by r300_do_cp_cmdbuf.
967 static inline int r300_emit_r500fp(drm_radeon_private_t
*dev_priv
,
968 drm_radeon_kcmd_buffer_t
*cmdbuf
,
969 drm_r300_cmd_header_t header
)
978 sz
= header
.r500fp
.count
;
979 /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
980 addr
= ((header
.r500fp
.adrhi_flags
& 1) << 8) | header
.r500fp
.adrlo
;
982 type
= !!(header
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
983 isclamp
= !!(header
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
985 addr
|= (type
<< 16);
986 addr
|= (isclamp
<< 17);
988 stride
= type
? 4 : 6;
990 DRM_DEBUG("r500fp %d %d type: %d\n", sz
, addr
, type
);
993 if (sz
* stride
* 4 > drm_buffer_unprocessed(cmdbuf
->buffer
))
996 BEGIN_RING(3 + sz
* stride
);
997 OUT_RING_REG(R500_GA_US_VECTOR_INDEX
, addr
);
998 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA
, sz
* stride
- 1));
999 OUT_RING_DRM_BUFFER(cmdbuf
->buffer
, sz
* stride
);
1008 * Parses and validates a user-supplied command buffer and emits appropriate
1009 * commands on the DMA ring buffer.
1010 * Called by the ioctl handler function radeon_cp_cmdbuf.
1012 int r300_do_cp_cmdbuf(struct drm_device
*dev
,
1013 struct drm_file
*file_priv
,
1014 drm_radeon_kcmd_buffer_t
*cmdbuf
)
1016 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1017 struct drm_radeon_master_private
*master_priv
= file_priv
->master
->driver_priv
;
1018 struct drm_device_dma
*dma
= dev
->dma
;
1019 struct drm_buf
*buf
= NULL
;
1020 int emit_dispatch_age
= 0;
1026 r300_pacify(dev_priv
);
1028 if (cmdbuf
->nbox
<= R300_SIMULTANEOUS_CLIPRECTS
) {
1029 ret
= r300_emit_cliprects(dev_priv
, cmdbuf
, 0);
1034 while (drm_buffer_unprocessed(cmdbuf
->buffer
)
1035 >= sizeof(drm_r300_cmd_header_t
)) {
1037 drm_r300_cmd_header_t
*header
, stack_header
;
1039 header
= drm_buffer_read_object(cmdbuf
->buffer
,
1040 sizeof(stack_header
), &stack_header
);
1042 switch (header
->header
.cmd_type
) {
1043 case R300_CMD_PACKET0
:
1044 DRM_DEBUG("R300_CMD_PACKET0\n");
1045 ret
= r300_emit_packet0(dev_priv
, cmdbuf
, *header
);
1047 DRM_ERROR("r300_emit_packet0 failed\n");
1053 DRM_DEBUG("R300_CMD_VPU\n");
1054 ret
= r300_emit_vpu(dev_priv
, cmdbuf
, *header
);
1056 DRM_ERROR("r300_emit_vpu failed\n");
1061 case R300_CMD_PACKET3
:
1062 DRM_DEBUG("R300_CMD_PACKET3\n");
1063 ret
= r300_emit_packet3(dev_priv
, cmdbuf
, *header
);
1065 DRM_ERROR("r300_emit_packet3 failed\n");
1070 case R300_CMD_END3D
:
1071 DRM_DEBUG("R300_CMD_END3D\n");
1073 Ideally userspace driver should not need to issue this call,
1074 i.e. the drm driver should issue it automatically and prevent
1077 In practice, we do not understand why this call is needed and what
1078 it does (except for some vague guesses that it has to do with cache
1079 coherence) and so the user space driver does it.
1081 Once we are sure which uses prevent lockups the code could be moved
1082 into the kernel and the userspace driver will not
1083 need to use this command.
1085 Note that issuing this command does not hurt anything
1086 except, possibly, performance */
1087 r300_pacify(dev_priv
);
1090 case R300_CMD_CP_DELAY
:
1091 /* simple enough, we can do it here */
1092 DRM_DEBUG("R300_CMD_CP_DELAY\n");
1097 BEGIN_RING(header
->delay
.count
);
1098 for (i
= 0; i
< header
->delay
.count
; i
++)
1099 OUT_RING(RADEON_CP_PACKET2
);
1104 case R300_CMD_DMA_DISCARD
:
1105 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
1106 idx
= header
->dma
.buf_idx
;
1107 if (idx
< 0 || idx
>= dma
->buf_count
) {
1108 DRM_ERROR("buffer index %d (of %d max)\n",
1109 idx
, dma
->buf_count
- 1);
1114 buf
= dma
->buflist
[idx
];
1115 if (buf
->file_priv
!= file_priv
|| buf
->pending
) {
1116 DRM_ERROR("bad buffer %p %p %d\n",
1117 buf
->file_priv
, file_priv
,
1123 emit_dispatch_age
= 1;
1124 r300_discard_buffer(dev
, file_priv
->master
, buf
);
1128 DRM_DEBUG("R300_CMD_WAIT\n");
1129 r300_cmd_wait(dev_priv
, *header
);
1132 case R300_CMD_SCRATCH
:
1133 DRM_DEBUG("R300_CMD_SCRATCH\n");
1134 ret
= r300_scratch(dev_priv
, cmdbuf
, *header
);
1136 DRM_ERROR("r300_scratch failed\n");
1141 case R300_CMD_R500FP
:
1142 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) < CHIP_RV515
) {
1143 DRM_ERROR("Calling r500 command on r300 card\n");
1147 DRM_DEBUG("R300_CMD_R500FP\n");
1148 ret
= r300_emit_r500fp(dev_priv
, cmdbuf
, *header
);
1150 DRM_ERROR("r300_emit_r500fp failed\n");
1155 DRM_ERROR("bad cmd_type %i at byte %d\n",
1156 header
->header
.cmd_type
,
1157 cmdbuf
->buffer
->iterator
- (int)sizeof(*header
));
1166 r300_pacify(dev_priv
);
1168 /* We emit the vertex buffer age here, outside the pacifier "brackets"
1170 * (1) This may coalesce multiple age emissions into a single one and
1171 * (2) more importantly, some chips lock up hard when scratch registers
1172 * are written inside the pacifier bracket.
1174 if (emit_dispatch_age
) {
1177 /* Emit the vertex buffer age */
1179 RADEON_DISPATCH_AGE(master_priv
->sarea_priv
->last_dispatch
);