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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / si_dpm.c
blob787cd8fd897faf52e5874cb0183a07bc36594fdc
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "radeon_asic.h"
27 #include "sid.h"
28 #include "r600_dpm.h"
29 #include "si_dpm.h"
30 #include "atom.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
33
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
38
39 #define SMC_RAM_END 0x20000
40
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
42
43 static const struct si_cac_config_reg cac_weights_tahiti[] =
44 {
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 { 0xFFFFFFFF }
106 };
107
108 static const struct si_cac_config_reg lcac_tahiti[] =
109 {
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0xFFFFFFFF }
197
198 };
199
200 static const struct si_cac_config_reg cac_override_tahiti[] =
201 {
202 { 0xFFFFFFFF }
203 };
204
205 static const struct si_powertune_data powertune_data_tahiti =
206 {
207 ((1 << 16) | 27027),
208 6,
209 0,
210 4,
211 95,
212 {
213 0UL,
214 0UL,
215 4521550UL,
216 309631529UL,
217 -1270850L,
218 4513710L,
219 40
220 },
221 595000000UL,
222 12,
223 {
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0
232 },
233 true
234 };
235
236 static const struct si_dte_data dte_data_tahiti =
237 {
238 { 1159409, 0, 0, 0, 0 },
239 { 777, 0, 0, 0, 0 },
240 2,
241 54000,
242 127000,
243 25,
244 2,
245 10,
246 13,
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 85,
251 false
252 };
253
254 static const struct si_dte_data dte_data_tahiti_le =
255 {
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 0x5,
259 0xAFC8,
260 0x64,
261 0x32,
262 1,
263 0,
264 0x10,
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 85,
269 true
270 };
271
272 static const struct si_dte_data dte_data_tahiti_pro =
273 {
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
276 5,
277 45000,
278 100,
279 0xA,
280 1,
281 0,
282 0x10,
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 90,
287 true
288 };
289
290 static const struct si_dte_data dte_data_new_zealand =
291 {
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 0x5,
295 0xAFC8,
296 0x69,
297 0x32,
298 1,
299 0,
300 0x10,
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 85,
305 true
306 };
307
308 static const struct si_dte_data dte_data_aruba_pro =
309 {
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 5,
313 45000,
314 100,
315 0xA,
316 1,
317 0,
318 0x10,
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 90,
323 true
324 };
325
326 static const struct si_dte_data dte_data_malta =
327 {
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
330 5,
331 45000,
332 100,
333 0xA,
334 1,
335 0,
336 0x10,
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 90,
341 true
342 };
343
344 struct si_cac_config_reg cac_weights_pitcairn[] =
345 {
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 { 0xFFFFFFFF }
407 };
408
409 static const struct si_cac_config_reg lcac_pitcairn[] =
410 {
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498 };
499
500 static const struct si_cac_config_reg cac_override_pitcairn[] =
501 {
502 { 0xFFFFFFFF }
503 };
504
505 static const struct si_powertune_data powertune_data_pitcairn =
506 {
507 ((1 << 16) | 27027),
508 5,
509 0,
510 6,
511 100,
512 {
513 51600000UL,
514 1800000UL,
515 7194395UL,
516 309631529UL,
517 -1270850L,
518 4513710L,
519 100
520 },
521 117830498UL,
522 12,
523 {
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 true
534 };
535
536 static const struct si_dte_data dte_data_pitcairn =
537 {
538 { 0, 0, 0, 0, 0 },
539 { 0, 0, 0, 0, 0 },
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 0,
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 0,
551 false
552 };
553
554 static const struct si_dte_data dte_data_curacao_xt =
555 {
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
558 5,
559 45000,
560 100,
561 0xA,
562 1,
563 0,
564 0x10,
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 90,
569 true
570 };
571
572 static const struct si_dte_data dte_data_curacao_pro =
573 {
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
576 5,
577 45000,
578 100,
579 0xA,
580 1,
581 0,
582 0x10,
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 90,
587 true
588 };
589
590 static const struct si_dte_data dte_data_neptune_xt =
591 {
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
594 5,
595 45000,
596 100,
597 0xA,
598 1,
599 0,
600 0x10,
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 90,
605 true
606 };
607
608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609 {
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 { 0xFFFFFFFF }
671 };
672
673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674 {
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 { 0xFFFFFFFF }
736 };
737
738 static const struct si_cac_config_reg cac_weights_heathrow[] =
739 {
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 { 0xFFFFFFFF }
801 };
802
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804 {
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 { 0xFFFFFFFF }
866 };
867
868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
869 {
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 { 0xFFFFFFFF }
931 };
932
933 static const struct si_cac_config_reg lcac_cape_verde[] =
934 {
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 { 0xFFFFFFFF }
990 };
991
992 static const struct si_cac_config_reg cac_override_cape_verde[] =
993 {
994 { 0xFFFFFFFF }
995 };
996
997 static const struct si_powertune_data powertune_data_cape_verde =
998 {
999 ((1 << 16) | 0x6993),
1000 5,
1001 0,
1002 7,
1003 105,
1004 {
1005 0UL,
1006 0UL,
1007 7194395UL,
1008 309631529UL,
1009 -1270850L,
1010 4513710L,
1011 100
1012 },
1013 117830498UL,
1014 12,
1015 {
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0,
1023 0
1024 },
1025 true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030 { 0, 0, 0, 0, 0 },
1031 { 0, 0, 0, 0, 0 },
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 0,
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 0,
1043 false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 5,
1051 55000,
1052 0x69,
1053 0xA,
1054 1,
1055 0,
1056 0x3,
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 90,
1061 true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 5,
1069 55000,
1070 0x69,
1071 0xA,
1072 1,
1073 0,
1074 0x3,
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 90,
1079 true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 5,
1087 55000,
1088 0x69,
1089 0xA,
1090 1,
1091 0,
1092 0x3,
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 90,
1097 true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521 { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526 ((1 << 16) | 0x6993),
1527 5,
1528 0,
1529 7,
1530 105,
1531 {
1532 0UL,
1533 0UL,
1534 7194395UL,
1535 309631529UL,
1536 -1270850L,
1537 4513710L,
1538 100
1539 },
1540 117830498UL,
1541 12,
1542 {
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0,
1550 0
1551 },
1552 true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557 ((1 << 16) | 0x6993),
1558 5,
1559 0,
1560 7,
1561 105,
1562 {
1563 0UL,
1564 0UL,
1565 7194395UL,
1566 309631529UL,
1567 -1270850L,
1568 4513710L,
1569 100
1570 },
1571 117830498UL,
1572 12,
1573 {
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0
1582 },
1583 true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588 { 0, 0, 0, 0, 0 },
1589 { 0, 0, 0, 0, 0 },
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 0,
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 0,
1601 false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 5,
1609 55000,
1610 105,
1611 0xA,
1612 1,
1613 0,
1614 0x10,
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 90,
1619 true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 5,
1627 55000,
1628 105,
1629 0xA,
1630 1,
1631 0,
1632 0x10,
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 90,
1637 true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708 ((1 << 16) | 0x6993),
1709 5,
1710 0,
1711 9,
1712 105,
1713 {
1714 0UL,
1715 0UL,
1716 7194395UL,
1717 309631529UL,
1718 -1270850L,
1719 4513710L,
1720 100
1721 },
1722 117830498UL,
1723 12,
1724 {
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0,
1732 0
1733 },
1734 true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 u32 engine_clock,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767 return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775 s64 tmp;
1776
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1786
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1799 u16 v,
1800 s32 t,
1801 u32 i_leakage,
1802 u32 *leakage)
1803 {
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1810 {
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1827 const u32 fixed_kt,
1828 u16 v,
1829 u32 i_leakage,
1830 u32 *leakage)
1831 {
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1838 {
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1845 u32 i;
1846
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1849
1850 for (i = 0; i < k; i++) {
1851 dte_data->r[i] =
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1854 }
1855
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1860 }
1861 } else {
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863 }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1871
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1878
1879 switch (rdev->pdev->device) {
1880 case 0x6798:
1881 si_pi->dte_data.enable_dte_by_default = true;
1882 break;
1883 case 0x6799:
1884 si_pi->dte_data = dte_data_new_zealand;
1885 break;
1886 case 0x6790:
1887 case 0x6791:
1888 case 0x6792:
1889 case 0x679E:
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1892 break;
1893 case 0x679B:
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1896 break;
1897 case 0x679A:
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1900 break;
1901 default:
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1904 break;
1905 }
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1908 case 0x6810:
1909 case 0x6818:
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1916 break;
1917 case 0x6819:
1918 case 0x6811:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1925 break;
1926 case 0x6800:
1927 case 0x6806:
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1934 break;
1935 default:
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1941 break;
1942 }
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948 switch (rdev->pdev->device) {
1949 case 0x683B:
1950 case 0x683F:
1951 case 0x6829:
1952 case 0x6835:
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x682C:
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1959 break;
1960 case 0x6825:
1961 case 0x6827:
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x6824:
1966 case 0x682D:
1967 si_pi->cac_weights = cac_weights_chelsea_xt;
1968 si_pi->dte_data = dte_data_cape_verde;
1969 break;
1970 case 0x682F:
1971 si_pi->cac_weights = cac_weights_chelsea_pro;
1972 si_pi->dte_data = dte_data_cape_verde;
1973 break;
1974 case 0x6820:
1975 si_pi->cac_weights = cac_weights_heathrow;
1976 si_pi->dte_data = dte_data_venus_xtx;
1977 break;
1978 case 0x6821:
1979 si_pi->cac_weights = cac_weights_heathrow;
1980 si_pi->dte_data = dte_data_venus_xt;
1981 break;
1982 case 0x6823:
1983 case 0x682B:
1984 case 0x6822:
1985 case 0x682A:
1986 si_pi->cac_weights = cac_weights_chelsea_pro;
1987 si_pi->dte_data = dte_data_venus_pro;
1988 break;
1989 default:
1990 si_pi->cac_weights = cac_weights_cape_verde;
1991 si_pi->dte_data = dte_data_cape_verde;
1992 break;
1993 }
1994 } else if (rdev->family == CHIP_OLAND) {
1995 switch (rdev->pdev->device) {
1996 case 0x6601:
1997 case 0x6621:
1998 case 0x6603:
1999 case 0x6605:
2000 si_pi->cac_weights = cac_weights_mars_pro;
2001 si_pi->lcac_config = lcac_mars_pro;
2002 si_pi->cac_override = cac_override_oland;
2003 si_pi->powertune_data = &powertune_data_mars_pro;
2004 si_pi->dte_data = dte_data_mars_pro;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x6600:
2008 case 0x6606:
2009 case 0x6620:
2010 case 0x6604:
2011 si_pi->cac_weights = cac_weights_mars_xt;
2012 si_pi->lcac_config = lcac_mars_pro;
2013 si_pi->cac_override = cac_override_oland;
2014 si_pi->powertune_data = &powertune_data_mars_pro;
2015 si_pi->dte_data = dte_data_mars_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x6611:
2019 case 0x6613:
2020 case 0x6608:
2021 si_pi->cac_weights = cac_weights_oland_pro;
2022 si_pi->lcac_config = lcac_mars_pro;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_mars_pro;
2025 si_pi->dte_data = dte_data_mars_pro;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6610:
2029 si_pi->cac_weights = cac_weights_oland_xt;
2030 si_pi->lcac_config = lcac_mars_pro;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_mars_pro;
2033 si_pi->dte_data = dte_data_mars_pro;
2034 update_dte_from_pl2 = true;
2035 break;
2036 default:
2037 si_pi->cac_weights = cac_weights_oland;
2038 si_pi->lcac_config = lcac_oland;
2039 si_pi->cac_override = cac_override_oland;
2040 si_pi->powertune_data = &powertune_data_oland;
2041 si_pi->dte_data = dte_data_oland;
2042 break;
2043 }
2044 } else if (rdev->family == CHIP_HAINAN) {
2045 si_pi->cac_weights = cac_weights_hainan;
2046 si_pi->lcac_config = lcac_oland;
2047 si_pi->cac_override = cac_override_oland;
2048 si_pi->powertune_data = &powertune_data_hainan;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2051 } else {
2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053 return;
2054 }
2055
2056 ni_pi->enable_power_containment = false;
2057 ni_pi->enable_cac = false;
2058 ni_pi->enable_sq_ramping = false;
2059 si_pi->enable_dte = false;
2060
2061 if (si_pi->powertune_data->enable_powertune_by_default) {
2062 ni_pi->enable_power_containment= true;
2063 ni_pi->enable_cac = true;
2064 if (si_pi->dte_data.enable_dte_by_default) {
2065 si_pi->enable_dte = true;
2066 if (update_dte_from_pl2)
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069 }
2070 ni_pi->enable_sq_ramping = true;
2071 }
2072
2073 ni_pi->driver_calculate_cac_leakage = true;
2074 ni_pi->cac_configuration_required = true;
2075
2076 if (ni_pi->cac_configuration_required) {
2077 ni_pi->support_cac_long_term_average = true;
2078 si_pi->dyn_powertune_data.l2_lta_window_size =
2079 si_pi->powertune_data->l2_lta_window_size_default;
2080 si_pi->dyn_powertune_data.lts_truncate =
2081 si_pi->powertune_data->lts_truncate_default;
2082 } else {
2083 ni_pi->support_cac_long_term_average = false;
2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 si_pi->dyn_powertune_data.lts_truncate = 0;
2086 }
2087
2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 }
2090
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 {
2093 return 1;
2094 }
2095
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 {
2098 u32 xclk;
2099 u32 wintime;
2100 u32 cac_window;
2101 u32 cac_window_size;
2102
2103 xclk = radeon_get_xclk(rdev);
2104
2105 if (xclk == 0)
2106 return 0;
2107
2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111 wintime = (cac_window_size * 100) / xclk;
2112
2113 return wintime;
2114 }
2115
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 {
2118 return power_in_watts;
2119 }
2120
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 bool adjust_polarity,
2123 u32 tdp_adjustment,
2124 u32 *tdp_limit,
2125 u32 *near_tdp_limit)
2126 {
2127 u32 adjustment_delta, max_tdp_limit;
2128
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130 return -EINVAL;
2131
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134 if (adjust_polarity) {
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 } else {
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 else
2143 *near_tdp_limit = 0;
2144 }
2145
2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 return -EINVAL;
2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149 return -EINVAL;
2150
2151 return 0;
2152 }
2153
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 struct radeon_ps *radeon_state)
2156 {
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160 if (ni_pi->enable_power_containment) {
2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 PP_SIslands_PAPMParameters *papm_parm;
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165 u32 tdp_limit;
2166 u32 near_tdp_limit;
2167 int ret;
2168
2169 if (scaling_factor == 0)
2170 return -EINVAL;
2171
2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174 ret = si_calculate_adjusted_tdp_limits(rdev,
2175 false, /* ??? */
2176 rdev->pm.dpm.tdp_adjustment,
2177 &tdp_limit,
2178 &near_tdp_limit);
2179 if (ret)
2180 return ret;
2181
2182 smc_table->dpm2Params.TDPLimit =
2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 smc_table->dpm2Params.NearTDPLimit =
2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 smc_table->dpm2Params.SafePowerLimit =
2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189 ret = si_copy_bytes_to_smc(rdev,
2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193 sizeof(u32) * 3,
2194 si_pi->sram_end);
2195 if (ret)
2196 return ret;
2197
2198 if (si_pi->enable_ppm) {
2199 papm_parm = &si_pi->papm_parm;
2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 papm_parm->PlatformPowerLimit = 0xffffffff;
2206 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 (u8 *)papm_parm,
2210 sizeof(PP_SIslands_PAPMParameters),
2211 si_pi->sram_end);
2212 if (ret)
2213 return ret;
2214 }
2215 }
2216 return 0;
2217 }
2218
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 struct radeon_ps *radeon_state)
2221 {
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225 if (ni_pi->enable_power_containment) {
2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228 int ret;
2229
2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232 smc_table->dpm2Params.NearTDPLimit =
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 smc_table->dpm2Params.SafePowerLimit =
2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237 ret = si_copy_bytes_to_smc(rdev,
2238 (si_pi->state_table_start +
2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242 sizeof(u32) * 2,
2243 si_pi->sram_end);
2244 if (ret)
2245 return ret;
2246 }
2247
2248 return 0;
2249 }
2250
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 const u16 prev_std_vddc,
2253 const u16 curr_std_vddc)
2254 {
2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 u64 prev_vddc = (u64)prev_std_vddc;
2257 u64 curr_vddc = (u64)curr_std_vddc;
2258 u64 pwr_efficiency_ratio, n, d;
2259
2260 if ((prev_vddc == 0) || (curr_vddc == 0))
2261 return 0;
2262
2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 d = prev_vddc * prev_vddc;
2265 pwr_efficiency_ratio = div64_u64(n, d);
2266
2267 if (pwr_efficiency_ratio > (u64)0xFFFF)
2268 return 0;
2269
2270 return (u16)pwr_efficiency_ratio;
2271 }
2272
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state)
2275 {
2276 struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 radeon_state->vclk && radeon_state->dclk)
2280 return true;
2281
2282 return false;
2283 }
2284
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 struct radeon_ps *radeon_state,
2287 SISLANDS_SMC_SWSTATE *smc_state)
2288 {
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 struct ni_ps *state = ni_get_ps(radeon_state);
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293 u32 prev_sclk;
2294 u32 max_sclk;
2295 u32 min_sclk;
2296 u16 prev_std_vddc;
2297 u16 curr_std_vddc;
2298 int i;
2299 u16 pwr_efficiency_ratio;
2300 u8 max_ps_percent;
2301 bool disable_uvd_power_tune;
2302 int ret;
2303
2304 if (ni_pi->enable_power_containment == false)
2305 return 0;
2306
2307 if (state->performance_level_count == 0)
2308 return -EINVAL;
2309
2310 if (smc_state->levelCount != state->performance_level_count)
2311 return -EINVAL;
2312
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315 smc_state->levels[0].dpm2.MaxPS = 0;
2316 smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321 for (i = 1; i < state->performance_level_count; i++) {
2322 prev_sclk = state->performance_levels[i-1].sclk;
2323 max_sclk = state->performance_levels[i].sclk;
2324 if (i == 1)
2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 else
2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329 if (prev_sclk > max_sclk)
2330 return -EINVAL;
2331
2332 if ((max_ps_percent == 0) ||
2333 (prev_sclk == max_sclk) ||
2334 disable_uvd_power_tune) {
2335 min_sclk = max_sclk;
2336 } else if (i == 1) {
2337 min_sclk = prev_sclk;
2338 } else {
2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340 }
2341
2342 if (min_sclk < state->performance_levels[0].sclk)
2343 min_sclk = state->performance_levels[0].sclk;
2344
2345 if (min_sclk == 0)
2346 return -EINVAL;
2347
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 state->performance_levels[i-1].vddc, &vddc);
2350 if (ret)
2351 return ret;
2352
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354 if (ret)
2355 return ret;
2356
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 state->performance_levels[i].vddc, &vddc);
2359 if (ret)
2360 return ret;
2361
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363 if (ret)
2364 return ret;
2365
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 prev_std_vddc, curr_std_vddc);
2368
2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374 }
2375
2376 return 0;
2377 }
2378
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 struct radeon_ps *radeon_state,
2381 SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 struct ni_ps *state = ni_get_ps(radeon_state);
2385 u32 sq_power_throttle, sq_power_throttle2;
2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387 int i;
2388
2389 if (state->performance_level_count == 0)
2390 return -EINVAL;
2391
2392 if (smc_state->levelCount != state->performance_level_count)
2393 return -EINVAL;
2394
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396 return -EINVAL;
2397
2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 enable_sq_ramping = false;
2400
2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 enable_sq_ramping = false;
2403
2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 enable_sq_ramping = false;
2406
2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 enable_sq_ramping = false;
2409
2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 enable_sq_ramping = false;
2412
2413 for (i = 0; i < state->performance_level_count; i++) {
2414 sq_power_throttle = 0;
2415 sq_power_throttle2 = 0;
2416
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 enable_sq_ramping) {
2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 } else {
2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427 }
2428
2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431 }
2432
2433 return 0;
2434 }
2435
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437 struct radeon_ps *radeon_new_state,
2438 bool enable)
2439 {
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 PPSMC_Result smc_result;
2442 int ret = 0;
2443
2444 if (ni_pi->enable_power_containment) {
2445 if (enable) {
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 if (smc_result != PPSMC_Result_OK) {
2449 ret = -EINVAL;
2450 ni_pi->pc_enabled = false;
2451 } else {
2452 ni_pi->pc_enabled = true;
2453 }
2454 }
2455 } else {
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 if (smc_result != PPSMC_Result_OK)
2458 ret = -EINVAL;
2459 ni_pi->pc_enabled = false;
2460 }
2461 }
2462
2463 return ret;
2464 }
2465
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 {
2468 struct si_power_info *si_pi = si_get_pi(rdev);
2469 int ret = 0;
2470 struct si_dte_data *dte_data = &si_pi->dte_data;
2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472 u32 table_size;
2473 u8 tdep_count;
2474 u32 i;
2475
2476 if (dte_data == NULL)
2477 si_pi->enable_dte = false;
2478
2479 if (si_pi->enable_dte == false)
2480 return 0;
2481
2482 if (dte_data->k <= 0)
2483 return -EINVAL;
2484
2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 if (dte_tables == NULL) {
2487 si_pi->enable_dte = false;
2488 return -ENOMEM;
2489 }
2490
2491 table_size = dte_data->k;
2492
2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496 tdep_count = dte_data->tdep_count;
2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500 dte_tables->K = cpu_to_be32(table_size);
2501 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 dte_tables->WindowSize = dte_data->window_size;
2504 dte_tables->temp_select = dte_data->temp_select;
2505 dte_tables->DTE_mode = dte_data->dte_mode;
2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508 if (tdep_count > 0)
2509 table_size--;
2510
2511 for (i = 0; i < table_size; i++) {
2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2514 }
2515
2516 dte_tables->Tdep_count = tdep_count;
2517
2518 for (i = 0; i < (u32)tdep_count; i++) {
2519 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522 }
2523
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526 kfree(dte_tables);
2527
2528 return ret;
2529 }
2530
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532 u16 *max, u16 *min)
2533 {
2534 struct si_power_info *si_pi = si_get_pi(rdev);
2535 struct radeon_cac_leakage_table *table =
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537 u32 i;
2538 u32 v0_loadline;
2539
2540
2541 if (table == NULL)
2542 return -EINVAL;
2543
2544 *max = 0;
2545 *min = 0xFFFF;
2546
2547 for (i = 0; i < table->count; i++) {
2548 if (table->entries[i].vddc > *max)
2549 *max = table->entries[i].vddc;
2550 if (table->entries[i].vddc < *min)
2551 *min = table->entries[i].vddc;
2552 }
2553
2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555 return -EINVAL;
2556
2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559 if (v0_loadline > 0xFFFFUL)
2560 return -EINVAL;
2561
2562 *min = (u16)v0_loadline;
2563
2564 if ((*min > *max) || (*max == 0) || (*min == 0))
2565 return -EINVAL;
2566
2567 return 0;
2568 }
2569
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 {
2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 }
2575
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 PP_SIslands_CacConfig *cac_tables,
2578 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579 u16 t0, u16 t_step)
2580 {
2581 struct si_power_info *si_pi = si_get_pi(rdev);
2582 u32 leakage;
2583 unsigned int i, j;
2584 s32 t;
2585 u32 smc_leakage;
2586 u32 scaling_factor;
2587 u16 voltage;
2588
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 t = (1000 * (i * t_step + t0));
2593
2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 voltage = vddc_max - (vddc_step * j);
2596
2597 si_calculate_leakage_for_v_and_t(rdev,
2598 &si_pi->powertune_data->leakage_coefficients,
2599 voltage,
2600 t,
2601 si_pi->dyn_powertune_data.cac_leakage,
2602 &leakage);
2603
2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606 if (smc_leakage > 0xFFFF)
2607 smc_leakage = 0xFFFF;
2608
2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 cpu_to_be16((u16)smc_leakage);
2611 }
2612 }
2613 return 0;
2614 }
2615
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 PP_SIslands_CacConfig *cac_tables,
2618 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 {
2620 struct si_power_info *si_pi = si_get_pi(rdev);
2621 u32 leakage;
2622 unsigned int i, j;
2623 u32 smc_leakage;
2624 u32 scaling_factor;
2625 u16 voltage;
2626
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 voltage = vddc_max - (vddc_step * j);
2631
2632 si_calculate_leakage_for_v(rdev,
2633 &si_pi->powertune_data->leakage_coefficients,
2634 si_pi->powertune_data->fixed_kt,
2635 voltage,
2636 si_pi->dyn_powertune_data.cac_leakage,
2637 &leakage);
2638
2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641 if (smc_leakage > 0xFFFF)
2642 smc_leakage = 0xFFFF;
2643
2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 cpu_to_be16((u16)smc_leakage);
2647 }
2648 return 0;
2649 }
2650
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 {
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 struct si_power_info *si_pi = si_get_pi(rdev);
2655 PP_SIslands_CacConfig *cac_tables = NULL;
2656 u16 vddc_max, vddc_min, vddc_step;
2657 u16 t0, t_step;
2658 u32 load_line_slope, reg;
2659 int ret = 0;
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662 if (ni_pi->enable_cac == false)
2663 return 0;
2664
2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666 if (!cac_tables)
2667 return -ENOMEM;
2668
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 WREG32(CG_CAC_CTRL, reg);
2672
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 si_pi->dyn_powertune_data.dc_pwr_value =
2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682 if (ret)
2683 goto done_free;
2684
2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687 t_step = 4;
2688 t0 = 60;
2689
2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 vddc_max, vddc_min, vddc_step,
2693 t0, t_step);
2694 else
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 vddc_max, vddc_min, vddc_step);
2697 if (ret)
2698 goto done_free;
2699
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 cac_tables->calculation_repeats = cpu_to_be32(2);
2710 cac_tables->dc_cac = cpu_to_be32(0);
2711 cac_tables->log2_PG_LKG_SCALE = 12;
2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719 if (ret)
2720 goto done_free;
2721
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724 done_free:
2725 if (ret) {
2726 ni_pi->enable_cac = false;
2727 ni_pi->enable_power_containment = false;
2728 }
2729
2730 kfree(cac_tables);
2731
2732 return 0;
2733 }
2734
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 const struct si_cac_config_reg *cac_config_regs)
2737 {
2738 const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 u32 data = 0, offset;
2740
2741 if (!config_regs)
2742 return -EINVAL;
2743
2744 while (config_regs->offset != 0xFFFFFFFF) {
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 data = RREG32_SMC(offset);
2750 break;
2751 default:
2752 data = RREG32(config_regs->offset << 2);
2753 break;
2754 }
2755
2756 data &= ~config_regs->mask;
2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759 switch (config_regs->type) {
2760 case SISLANDS_CACCONFIG_CGIND:
2761 offset = SMC_CG_IND_START + config_regs->offset;
2762 if (offset < SMC_CG_IND_END)
2763 WREG32_SMC(offset, data);
2764 break;
2765 default:
2766 WREG32(config_regs->offset << 2, data);
2767 break;
2768 }
2769 config_regs++;
2770 }
2771 return 0;
2772 }
2773
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 {
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 struct si_power_info *si_pi = si_get_pi(rdev);
2778 int ret;
2779
2780 if ((ni_pi->enable_cac == false) ||
2781 (ni_pi->cac_configuration_required == false))
2782 return 0;
2783
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785 if (ret)
2786 return ret;
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788 if (ret)
2789 return ret;
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791 if (ret)
2792 return ret;
2793
2794 return 0;
2795 }
2796
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798 struct radeon_ps *radeon_new_state,
2799 bool enable)
2800 {
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 struct si_power_info *si_pi = si_get_pi(rdev);
2803 PPSMC_Result smc_result;
2804 int ret = 0;
2805
2806 if (ni_pi->enable_cac) {
2807 if (enable) {
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 if (ni_pi->support_cac_long_term_average) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 if (smc_result != PPSMC_Result_OK)
2812 ni_pi->support_cac_long_term_average = false;
2813 }
2814
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 if (smc_result != PPSMC_Result_OK) {
2817 ret = -EINVAL;
2818 ni_pi->cac_enabled = false;
2819 } else {
2820 ni_pi->cac_enabled = true;
2821 }
2822
2823 if (si_pi->enable_dte) {
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 if (smc_result != PPSMC_Result_OK)
2826 ret = -EINVAL;
2827 }
2828 }
2829 } else if (ni_pi->cac_enabled) {
2830 if (si_pi->enable_dte)
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835 ni_pi->cac_enabled = false;
2836
2837 if (ni_pi->support_cac_long_term_average)
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839 }
2840 }
2841 return ret;
2842 }
2843
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 {
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 struct si_power_info *si_pi = si_get_pi(rdev);
2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 SISLANDS_SMC_SCLK_VALUE sclk_params;
2850 u32 fb_div, p_div;
2851 u32 clk_s, clk_v;
2852 u32 sclk = 0;
2853 int ret = 0;
2854 u32 tmp;
2855 int i;
2856
2857 if (si_pi->spll_table_start == 0)
2858 return -EINVAL;
2859
2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 if (spll_table == NULL)
2862 return -ENOMEM;
2863
2864 for (i = 0; i < 256; i++) {
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866 if (ret)
2867 break;
2868
2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874 fb_div &= ~0x00001FFF;
2875 fb_div >>= 1;
2876 clk_v >>= 6;
2877
2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 ret = -EINVAL;
2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 ret = -EINVAL;
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 ret = -EINVAL;
2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885 ret = -EINVAL;
2886
2887 if (ret)
2888 break;
2889
2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898 sclk += 512;
2899 }
2900
2901
2902 if (!ret)
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905 si_pi->sram_end);
2906
2907 if (ret)
2908 ni_pi->enable_power_containment = false;
2909
2910 kfree(spll_table);
2911
2912 return ret;
2913 }
2914
2915 struct si_dpm_quirk {
2916 u32 chip_vendor;
2917 u32 chip_device;
2918 u32 subsys_vendor;
2919 u32 subsys_device;
2920 u32 max_sclk;
2921 u32 max_mclk;
2922 };
2923
2924 /* cards with dpm stability problems */
2925 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2930 { 0, 0, 0, 0 },
2931 };
2932
2933 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2934 u16 vce_voltage)
2935 {
2936 u16 highest_leakage = 0;
2937 struct si_power_info *si_pi = si_get_pi(rdev);
2938 int i;
2939
2940 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2941 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2942 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2943 }
2944
2945 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2946 return highest_leakage;
2947
2948 return vce_voltage;
2949 }
2950
2951 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2952 u32 evclk, u32 ecclk, u16 *voltage)
2953 {
2954 u32 i;
2955 int ret = -EINVAL;
2956 struct radeon_vce_clock_voltage_dependency_table *table =
2957 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2958
2959 if (((evclk == 0) && (ecclk == 0)) ||
2960 (table && (table->count == 0))) {
2961 *voltage = 0;
2962 return 0;
2963 }
2964
2965 for (i = 0; i < table->count; i++) {
2966 if ((evclk <= table->entries[i].evclk) &&
2967 (ecclk <= table->entries[i].ecclk)) {
2968 *voltage = table->entries[i].v;
2969 ret = 0;
2970 break;
2971 }
2972 }
2973
2974 /* if no match return the highest voltage */
2975 if (ret)
2976 *voltage = table->entries[table->count - 1].v;
2977
2978 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2979
2980 return ret;
2981 }
2982
2983 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2984 struct radeon_ps *rps)
2985 {
2986 struct ni_ps *ps = ni_get_ps(rps);
2987 struct radeon_clock_and_voltage_limits *max_limits;
2988 bool disable_mclk_switching = false;
2989 bool disable_sclk_switching = false;
2990 u32 mclk, sclk;
2991 u16 vddc, vddci, min_vce_voltage = 0;
2992 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2993 u32 max_sclk = 0, max_mclk = 0;
2994 int i;
2995 struct si_dpm_quirk *p = si_dpm_quirk_list;
2996
2997 /* Apply dpm quirks */
2998 while (p && p->chip_device != 0) {
2999 if (rdev->pdev->vendor == p->chip_vendor &&
3000 rdev->pdev->device == p->chip_device &&
3001 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3002 rdev->pdev->subsystem_device == p->subsys_device) {
3003 max_sclk = p->max_sclk;
3004 max_mclk = p->max_mclk;
3005 break;
3006 }
3007 ++p;
3008 }
3009
3010 if (rps->vce_active) {
3011 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3012 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3013 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3014 &min_vce_voltage);
3015 } else {
3016 rps->evclk = 0;
3017 rps->ecclk = 0;
3018 }
3019
3020 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3021 ni_dpm_vblank_too_short(rdev))
3022 disable_mclk_switching = true;
3023
3024 if (rps->vclk || rps->dclk) {
3025 disable_mclk_switching = true;
3026 disable_sclk_switching = true;
3027 }
3028
3029 if (rdev->pm.dpm.ac_power)
3030 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3031 else
3032 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3033
3034 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3035 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3036 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3037 }
3038 if (rdev->pm.dpm.ac_power == false) {
3039 for (i = 0; i < ps->performance_level_count; i++) {
3040 if (ps->performance_levels[i].mclk > max_limits->mclk)
3041 ps->performance_levels[i].mclk = max_limits->mclk;
3042 if (ps->performance_levels[i].sclk > max_limits->sclk)
3043 ps->performance_levels[i].sclk = max_limits->sclk;
3044 if (ps->performance_levels[i].vddc > max_limits->vddc)
3045 ps->performance_levels[i].vddc = max_limits->vddc;
3046 if (ps->performance_levels[i].vddci > max_limits->vddci)
3047 ps->performance_levels[i].vddci = max_limits->vddci;
3048 }
3049 }
3050
3051 /* limit clocks to max supported clocks based on voltage dependency tables */
3052 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3053 &max_sclk_vddc);
3054 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3055 &max_mclk_vddci);
3056 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3057 &max_mclk_vddc);
3058
3059 for (i = 0; i < ps->performance_level_count; i++) {
3060 if (max_sclk_vddc) {
3061 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3062 ps->performance_levels[i].sclk = max_sclk_vddc;
3063 }
3064 if (max_mclk_vddci) {
3065 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3066 ps->performance_levels[i].mclk = max_mclk_vddci;
3067 }
3068 if (max_mclk_vddc) {
3069 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3070 ps->performance_levels[i].mclk = max_mclk_vddc;
3071 }
3072 if (max_mclk) {
3073 if (ps->performance_levels[i].mclk > max_mclk)
3074 ps->performance_levels[i].mclk = max_mclk;
3075 }
3076 if (max_sclk) {
3077 if (ps->performance_levels[i].sclk > max_sclk)
3078 ps->performance_levels[i].sclk = max_sclk;
3079 }
3080 }
3081
3082 /* XXX validate the min clocks required for display */
3083
3084 if (disable_mclk_switching) {
3085 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3086 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3087 } else {
3088 mclk = ps->performance_levels[0].mclk;
3089 vddci = ps->performance_levels[0].vddci;
3090 }
3091
3092 if (disable_sclk_switching) {
3093 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3094 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3095 } else {
3096 sclk = ps->performance_levels[0].sclk;
3097 vddc = ps->performance_levels[0].vddc;
3098 }
3099
3100 if (rps->vce_active) {
3101 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3102 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3103 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3104 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3105 }
3106
3107 /* adjusted low state */
3108 ps->performance_levels[0].sclk = sclk;
3109 ps->performance_levels[0].mclk = mclk;
3110 ps->performance_levels[0].vddc = vddc;
3111 ps->performance_levels[0].vddci = vddci;
3112
3113 if (disable_sclk_switching) {
3114 sclk = ps->performance_levels[0].sclk;
3115 for (i = 1; i < ps->performance_level_count; i++) {
3116 if (sclk < ps->performance_levels[i].sclk)
3117 sclk = ps->performance_levels[i].sclk;
3118 }
3119 for (i = 0; i < ps->performance_level_count; i++) {
3120 ps->performance_levels[i].sclk = sclk;
3121 ps->performance_levels[i].vddc = vddc;
3122 }
3123 } else {
3124 for (i = 1; i < ps->performance_level_count; i++) {
3125 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3126 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3127 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3128 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3129 }
3130 }
3131
3132 if (disable_mclk_switching) {
3133 mclk = ps->performance_levels[0].mclk;
3134 for (i = 1; i < ps->performance_level_count; i++) {
3135 if (mclk < ps->performance_levels[i].mclk)
3136 mclk = ps->performance_levels[i].mclk;
3137 }
3138 for (i = 0; i < ps->performance_level_count; i++) {
3139 ps->performance_levels[i].mclk = mclk;
3140 ps->performance_levels[i].vddci = vddci;
3141 }
3142 } else {
3143 for (i = 1; i < ps->performance_level_count; i++) {
3144 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3145 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3146 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3147 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3148 }
3149 }
3150
3151 for (i = 0; i < ps->performance_level_count; i++)
3152 btc_adjust_clock_combinations(rdev, max_limits,
3153 &ps->performance_levels[i]);
3154
3155 for (i = 0; i < ps->performance_level_count; i++) {
3156 if (ps->performance_levels[i].vddc < min_vce_voltage)
3157 ps->performance_levels[i].vddc = min_vce_voltage;
3158 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3159 ps->performance_levels[i].sclk,
3160 max_limits->vddc, &ps->performance_levels[i].vddc);
3161 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3162 ps->performance_levels[i].mclk,
3163 max_limits->vddci, &ps->performance_levels[i].vddci);
3164 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3165 ps->performance_levels[i].mclk,
3166 max_limits->vddc, &ps->performance_levels[i].vddc);
3167 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3168 rdev->clock.current_dispclk,
3169 max_limits->vddc, &ps->performance_levels[i].vddc);
3170 }
3171
3172 for (i = 0; i < ps->performance_level_count; i++) {
3173 btc_apply_voltage_delta_rules(rdev,
3174 max_limits->vddc, max_limits->vddci,
3175 &ps->performance_levels[i].vddc,
3176 &ps->performance_levels[i].vddci);
3177 }
3178
3179 ps->dc_compatible = true;
3180 for (i = 0; i < ps->performance_level_count; i++) {
3181 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3182 ps->dc_compatible = false;
3183 }
3184 }
3185
3186 #if 0
3187 static int si_read_smc_soft_register(struct radeon_device *rdev,
3188 u16 reg_offset, u32 *value)
3189 {
3190 struct si_power_info *si_pi = si_get_pi(rdev);
3191
3192 return si_read_smc_sram_dword(rdev,
3193 si_pi->soft_regs_start + reg_offset, value,
3194 si_pi->sram_end);
3195 }
3196 #endif
3197
3198 static int si_write_smc_soft_register(struct radeon_device *rdev,
3199 u16 reg_offset, u32 value)
3200 {
3201 struct si_power_info *si_pi = si_get_pi(rdev);
3202
3203 return si_write_smc_sram_dword(rdev,
3204 si_pi->soft_regs_start + reg_offset,
3205 value, si_pi->sram_end);
3206 }
3207
3208 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3209 {
3210 bool ret = false;
3211 u32 tmp, width, row, column, bank, density;
3212 bool is_memory_gddr5, is_special;
3213
3214 tmp = RREG32(MC_SEQ_MISC0);
3215 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3216 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3217 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3218
3219 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3220 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3221
3222 tmp = RREG32(MC_ARB_RAMCFG);
3223 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3224 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3225 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3226
3227 density = (1 << (row + column - 20 + bank)) * width;
3228
3229 if ((rdev->pdev->device == 0x6819) &&
3230 is_memory_gddr5 && is_special && (density == 0x400))
3231 ret = true;
3232
3233 return ret;
3234 }
3235
3236 static void si_get_leakage_vddc(struct radeon_device *rdev)
3237 {
3238 struct si_power_info *si_pi = si_get_pi(rdev);
3239 u16 vddc, count = 0;
3240 int i, ret;
3241
3242 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3243 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3244
3245 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3246 si_pi->leakage_voltage.entries[count].voltage = vddc;
3247 si_pi->leakage_voltage.entries[count].leakage_index =
3248 SISLANDS_LEAKAGE_INDEX0 + i;
3249 count++;
3250 }
3251 }
3252 si_pi->leakage_voltage.count = count;
3253 }
3254
3255 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3256 u32 index, u16 *leakage_voltage)
3257 {
3258 struct si_power_info *si_pi = si_get_pi(rdev);
3259 int i;
3260
3261 if (leakage_voltage == NULL)
3262 return -EINVAL;
3263
3264 if ((index & 0xff00) != 0xff00)
3265 return -EINVAL;
3266
3267 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3268 return -EINVAL;
3269
3270 if (index < SISLANDS_LEAKAGE_INDEX0)
3271 return -EINVAL;
3272
3273 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3274 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3275 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3276 return 0;
3277 }
3278 }
3279 return -EAGAIN;
3280 }
3281
3282 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3283 {
3284 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3285 bool want_thermal_protection;
3286 enum radeon_dpm_event_src dpm_event_src;
3287
3288 switch (sources) {
3289 case 0:
3290 default:
3291 want_thermal_protection = false;
3292 break;
3293 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3294 want_thermal_protection = true;
3295 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3296 break;
3297 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3298 want_thermal_protection = true;
3299 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3300 break;
3301 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3302 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3303 want_thermal_protection = true;
3304 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3305 break;
3306 }
3307
3308 if (want_thermal_protection) {
3309 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3310 if (pi->thermal_protection)
3311 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3312 } else {
3313 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3314 }
3315 }
3316
3317 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3318 enum radeon_dpm_auto_throttle_src source,
3319 bool enable)
3320 {
3321 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3322
3323 if (enable) {
3324 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3325 pi->active_auto_throttle_sources |= 1 << source;
3326 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3327 }
3328 } else {
3329 if (pi->active_auto_throttle_sources & (1 << source)) {
3330 pi->active_auto_throttle_sources &= ~(1 << source);
3331 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3332 }
3333 }
3334 }
3335
3336 static void si_start_dpm(struct radeon_device *rdev)
3337 {
3338 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3339 }
3340
3341 static void si_stop_dpm(struct radeon_device *rdev)
3342 {
3343 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3344 }
3345
3346 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3347 {
3348 if (enable)
3349 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3350 else
3351 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3352
3353 }
3354
3355 #if 0
3356 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3357 u32 thermal_level)
3358 {
3359 PPSMC_Result ret;
3360
3361 if (thermal_level == 0) {
3362 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3363 if (ret == PPSMC_Result_OK)
3364 return 0;
3365 else
3366 return -EINVAL;
3367 }
3368 return 0;
3369 }
3370
3371 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3372 {
3373 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3374 }
3375 #endif
3376
3377 #if 0
3378 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3379 {
3380 if (ac_power)
3381 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3382 0 : -EINVAL;
3383
3384 return 0;
3385 }
3386 #endif
3387
3388 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3389 PPSMC_Msg msg, u32 parameter)
3390 {
3391 WREG32(SMC_SCRATCH0, parameter);
3392 return si_send_msg_to_smc(rdev, msg);
3393 }
3394
3395 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3396 {
3397 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3398 return -EINVAL;
3399
3400 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3401 0 : -EINVAL;
3402 }
3403
3404 int si_dpm_force_performance_level(struct radeon_device *rdev,
3405 enum radeon_dpm_forced_level level)
3406 {
3407 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3408 struct ni_ps *ps = ni_get_ps(rps);
3409 u32 levels = ps->performance_level_count;
3410
3411 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3412 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3413 return -EINVAL;
3414
3415 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3416 return -EINVAL;
3417 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3418 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3419 return -EINVAL;
3420
3421 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3422 return -EINVAL;
3423 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3424 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3425 return -EINVAL;
3426
3427 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3428 return -EINVAL;
3429 }
3430
3431 rdev->pm.dpm.forced_level = level;
3432
3433 return 0;
3434 }
3435
3436 #if 0
3437 static int si_set_boot_state(struct radeon_device *rdev)
3438 {
3439 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3440 0 : -EINVAL;
3441 }
3442 #endif
3443
3444 static int si_set_sw_state(struct radeon_device *rdev)
3445 {
3446 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3447 0 : -EINVAL;
3448 }
3449
3450 static int si_halt_smc(struct radeon_device *rdev)
3451 {
3452 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3453 return -EINVAL;
3454
3455 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3456 0 : -EINVAL;
3457 }
3458
3459 static int si_resume_smc(struct radeon_device *rdev)
3460 {
3461 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3462 return -EINVAL;
3463
3464 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3465 0 : -EINVAL;
3466 }
3467
3468 static void si_dpm_start_smc(struct radeon_device *rdev)
3469 {
3470 si_program_jump_on_start(rdev);
3471 si_start_smc(rdev);
3472 si_start_smc_clock(rdev);
3473 }
3474
3475 static void si_dpm_stop_smc(struct radeon_device *rdev)
3476 {
3477 si_reset_smc(rdev);
3478 si_stop_smc_clock(rdev);
3479 }
3480
3481 static int si_process_firmware_header(struct radeon_device *rdev)
3482 {
3483 struct si_power_info *si_pi = si_get_pi(rdev);
3484 u32 tmp;
3485 int ret;
3486
3487 ret = si_read_smc_sram_dword(rdev,
3488 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3489 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3490 &tmp, si_pi->sram_end);
3491 if (ret)
3492 return ret;
3493
3494 si_pi->state_table_start = tmp;
3495
3496 ret = si_read_smc_sram_dword(rdev,
3497 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3498 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3499 &tmp, si_pi->sram_end);
3500 if (ret)
3501 return ret;
3502
3503 si_pi->soft_regs_start = tmp;
3504
3505 ret = si_read_smc_sram_dword(rdev,
3506 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3507 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3508 &tmp, si_pi->sram_end);
3509 if (ret)
3510 return ret;
3511
3512 si_pi->mc_reg_table_start = tmp;
3513
3514 ret = si_read_smc_sram_dword(rdev,
3515 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3516 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3517 &tmp, si_pi->sram_end);
3518 if (ret)
3519 return ret;
3520
3521 si_pi->fan_table_start = tmp;
3522
3523 ret = si_read_smc_sram_dword(rdev,
3524 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3525 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3526 &tmp, si_pi->sram_end);
3527 if (ret)
3528 return ret;
3529
3530 si_pi->arb_table_start = tmp;
3531
3532 ret = si_read_smc_sram_dword(rdev,
3533 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3534 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3535 &tmp, si_pi->sram_end);
3536 if (ret)
3537 return ret;
3538
3539 si_pi->cac_table_start = tmp;
3540
3541 ret = si_read_smc_sram_dword(rdev,
3542 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3543 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3544 &tmp, si_pi->sram_end);
3545 if (ret)
3546 return ret;
3547
3548 si_pi->dte_table_start = tmp;
3549
3550 ret = si_read_smc_sram_dword(rdev,
3551 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3552 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3553 &tmp, si_pi->sram_end);
3554 if (ret)
3555 return ret;
3556
3557 si_pi->spll_table_start = tmp;
3558
3559 ret = si_read_smc_sram_dword(rdev,
3560 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3561 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3562 &tmp, si_pi->sram_end);
3563 if (ret)
3564 return ret;
3565
3566 si_pi->papm_cfg_table_start = tmp;
3567
3568 return ret;
3569 }
3570
3571 static void si_read_clock_registers(struct radeon_device *rdev)
3572 {
3573 struct si_power_info *si_pi = si_get_pi(rdev);
3574
3575 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3576 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3577 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3578 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3579 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3580 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3581 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3582 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3583 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3584 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3585 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3586 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3587 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3588 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3589 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3590 }
3591
3592 static void si_enable_thermal_protection(struct radeon_device *rdev,
3593 bool enable)
3594 {
3595 if (enable)
3596 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3597 else
3598 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3599 }
3600
3601 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3602 {
3603 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3604 }
3605
3606 #if 0
3607 static int si_enter_ulp_state(struct radeon_device *rdev)
3608 {
3609 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3610
3611 udelay(25000);
3612
3613 return 0;
3614 }
3615
3616 static int si_exit_ulp_state(struct radeon_device *rdev)
3617 {
3618 int i;
3619
3620 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3621
3622 udelay(7000);
3623
3624 for (i = 0; i < rdev->usec_timeout; i++) {
3625 if (RREG32(SMC_RESP_0) == 1)
3626 break;
3627 udelay(1000);
3628 }
3629
3630 return 0;
3631 }
3632 #endif
3633
3634 static int si_notify_smc_display_change(struct radeon_device *rdev,
3635 bool has_display)
3636 {
3637 PPSMC_Msg msg = has_display ?
3638 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3639
3640 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3641 0 : -EINVAL;
3642 }
3643
3644 static void si_program_response_times(struct radeon_device *rdev)
3645 {
3646 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3647 u32 vddc_dly, acpi_dly, vbi_dly;
3648 u32 reference_clock;
3649
3650 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3651
3652 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3653 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3654
3655 if (voltage_response_time == 0)
3656 voltage_response_time = 1000;
3657
3658 acpi_delay_time = 15000;
3659 vbi_time_out = 100000;
3660
3661 reference_clock = radeon_get_xclk(rdev);
3662
3663 vddc_dly = (voltage_response_time * reference_clock) / 100;
3664 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3665 vbi_dly = (vbi_time_out * reference_clock) / 100;
3666
3667 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3668 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3669 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3670 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3671 }
3672
3673 static void si_program_ds_registers(struct radeon_device *rdev)
3674 {
3675 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3676 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3677
3678 if (eg_pi->sclk_deep_sleep) {
3679 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3680 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3681 ~AUTOSCALE_ON_SS_CLEAR);
3682 }
3683 }
3684
3685 static void si_program_display_gap(struct radeon_device *rdev)
3686 {
3687 u32 tmp, pipe;
3688 int i;
3689
3690 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3691 if (rdev->pm.dpm.new_active_crtc_count > 0)
3692 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3693 else
3694 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3695
3696 if (rdev->pm.dpm.new_active_crtc_count > 1)
3697 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3698 else
3699 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3700
3701 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3702
3703 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3704 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3705
3706 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3707 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3708 /* find the first active crtc */
3709 for (i = 0; i < rdev->num_crtc; i++) {
3710 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3711 break;
3712 }
3713 if (i == rdev->num_crtc)
3714 pipe = 0;
3715 else
3716 pipe = i;
3717
3718 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3719 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3720 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3721 }
3722
3723 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3724 * This can be a problem on PowerXpress systems or if you want to use the card
3725 * for offscreen rendering or compute if there are no crtcs enabled.
3726 */
3727 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3728 }
3729
3730 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3731 {
3732 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3733
3734 if (enable) {
3735 if (pi->sclk_ss)
3736 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3737 } else {
3738 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3739 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3740 }
3741 }
3742
3743 static void si_setup_bsp(struct radeon_device *rdev)
3744 {
3745 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3746 u32 xclk = radeon_get_xclk(rdev);
3747
3748 r600_calculate_u_and_p(pi->asi,
3749 xclk,
3750 16,
3751 &pi->bsp,
3752 &pi->bsu);
3753
3754 r600_calculate_u_and_p(pi->pasi,
3755 xclk,
3756 16,
3757 &pi->pbsp,
3758 &pi->pbsu);
3759
3760
3761 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3762 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3763
3764 WREG32(CG_BSP, pi->dsp);
3765 }
3766
3767 static void si_program_git(struct radeon_device *rdev)
3768 {
3769 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3770 }
3771
3772 static void si_program_tp(struct radeon_device *rdev)
3773 {
3774 int i;
3775 enum r600_td td = R600_TD_DFLT;
3776
3777 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3778 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3779
3780 if (td == R600_TD_AUTO)
3781 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3782 else
3783 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3784
3785 if (td == R600_TD_UP)
3786 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3787
3788 if (td == R600_TD_DOWN)
3789 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3790 }
3791
3792 static void si_program_tpp(struct radeon_device *rdev)
3793 {
3794 WREG32(CG_TPC, R600_TPC_DFLT);
3795 }
3796
3797 static void si_program_sstp(struct radeon_device *rdev)
3798 {
3799 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3800 }
3801
3802 static void si_enable_display_gap(struct radeon_device *rdev)
3803 {
3804 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3805
3806 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3807 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3808 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3809
3810 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3811 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3812 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3813 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3814 }
3815
3816 static void si_program_vc(struct radeon_device *rdev)
3817 {
3818 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3819
3820 WREG32(CG_FTV, pi->vrc);
3821 }
3822
3823 static void si_clear_vc(struct radeon_device *rdev)
3824 {
3825 WREG32(CG_FTV, 0);
3826 }
3827
3828 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3829 {
3830 u8 mc_para_index;
3831
3832 if (memory_clock < 10000)
3833 mc_para_index = 0;
3834 else if (memory_clock >= 80000)
3835 mc_para_index = 0x0f;
3836 else
3837 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3838 return mc_para_index;
3839 }
3840
3841 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3842 {
3843 u8 mc_para_index;
3844
3845 if (strobe_mode) {
3846 if (memory_clock < 12500)
3847 mc_para_index = 0x00;
3848 else if (memory_clock > 47500)
3849 mc_para_index = 0x0f;
3850 else
3851 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3852 } else {
3853 if (memory_clock < 65000)
3854 mc_para_index = 0x00;
3855 else if (memory_clock > 135000)
3856 mc_para_index = 0x0f;
3857 else
3858 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3859 }
3860 return mc_para_index;
3861 }
3862
3863 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3864 {
3865 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3866 bool strobe_mode = false;
3867 u8 result = 0;
3868
3869 if (mclk <= pi->mclk_strobe_mode_threshold)
3870 strobe_mode = true;
3871
3872 if (pi->mem_gddr5)
3873 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3874 else
3875 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3876
3877 if (strobe_mode)
3878 result |= SISLANDS_SMC_STROBE_ENABLE;
3879
3880 return result;
3881 }
3882
3883 static int si_upload_firmware(struct radeon_device *rdev)
3884 {
3885 struct si_power_info *si_pi = si_get_pi(rdev);
3886 int ret;
3887
3888 si_reset_smc(rdev);
3889 si_stop_smc_clock(rdev);
3890
3891 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3892
3893 return ret;
3894 }
3895
3896 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3897 const struct atom_voltage_table *table,
3898 const struct radeon_phase_shedding_limits_table *limits)
3899 {
3900 u32 data, num_bits, num_levels;
3901
3902 if ((table == NULL) || (limits == NULL))
3903 return false;
3904
3905 data = table->mask_low;
3906
3907 num_bits = hweight32(data);
3908
3909 if (num_bits == 0)
3910 return false;
3911
3912 num_levels = (1 << num_bits);
3913
3914 if (table->count != num_levels)
3915 return false;
3916
3917 if (limits->count != (num_levels - 1))
3918 return false;
3919
3920 return true;
3921 }
3922
3923 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3924 u32 max_voltage_steps,
3925 struct atom_voltage_table *voltage_table)
3926 {
3927 unsigned int i, diff;
3928
3929 if (voltage_table->count <= max_voltage_steps)
3930 return;
3931
3932 diff = voltage_table->count - max_voltage_steps;
3933
3934 for (i= 0; i < max_voltage_steps; i++)
3935 voltage_table->entries[i] = voltage_table->entries[i + diff];
3936
3937 voltage_table->count = max_voltage_steps;
3938 }
3939
3940 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3941 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3942 struct atom_voltage_table *voltage_table)
3943 {
3944 u32 i;
3945
3946 if (voltage_dependency_table == NULL)
3947 return -EINVAL;
3948
3949 voltage_table->mask_low = 0;
3950 voltage_table->phase_delay = 0;
3951
3952 voltage_table->count = voltage_dependency_table->count;
3953 for (i = 0; i < voltage_table->count; i++) {
3954 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3955 voltage_table->entries[i].smio_low = 0;
3956 }
3957
3958 return 0;
3959 }
3960
3961 static int si_construct_voltage_tables(struct radeon_device *rdev)
3962 {
3963 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3965 struct si_power_info *si_pi = si_get_pi(rdev);
3966 int ret;
3967
3968 if (pi->voltage_control) {
3969 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3970 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3971 if (ret)
3972 return ret;
3973
3974 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3975 si_trim_voltage_table_to_fit_state_table(rdev,
3976 SISLANDS_MAX_NO_VREG_STEPS,
3977 &eg_pi->vddc_voltage_table);
3978 } else if (si_pi->voltage_control_svi2) {
3979 ret = si_get_svi2_voltage_table(rdev,
3980 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3981 &eg_pi->vddc_voltage_table);
3982 if (ret)
3983 return ret;
3984 } else {
3985 return -EINVAL;
3986 }
3987
3988 if (eg_pi->vddci_control) {
3989 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3990 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3991 if (ret)
3992 return ret;
3993
3994 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3995 si_trim_voltage_table_to_fit_state_table(rdev,
3996 SISLANDS_MAX_NO_VREG_STEPS,
3997 &eg_pi->vddci_voltage_table);
3998 }
3999 if (si_pi->vddci_control_svi2) {
4000 ret = si_get_svi2_voltage_table(rdev,
4001 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4002 &eg_pi->vddci_voltage_table);
4003 if (ret)
4004 return ret;
4005 }
4006
4007 if (pi->mvdd_control) {
4008 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4009 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4010
4011 if (ret) {
4012 pi->mvdd_control = false;
4013 return ret;
4014 }
4015
4016 if (si_pi->mvdd_voltage_table.count == 0) {
4017 pi->mvdd_control = false;
4018 return -EINVAL;
4019 }
4020
4021 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4022 si_trim_voltage_table_to_fit_state_table(rdev,
4023 SISLANDS_MAX_NO_VREG_STEPS,
4024 &si_pi->mvdd_voltage_table);
4025 }
4026
4027 if (si_pi->vddc_phase_shed_control) {
4028 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4029 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4030 if (ret)
4031 si_pi->vddc_phase_shed_control = false;
4032
4033 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4034 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4035 si_pi->vddc_phase_shed_control = false;
4036 }
4037
4038 return 0;
4039 }
4040
4041 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4042 const struct atom_voltage_table *voltage_table,
4043 SISLANDS_SMC_STATETABLE *table)
4044 {
4045 unsigned int i;
4046
4047 for (i = 0; i < voltage_table->count; i++)
4048 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4049 }
4050
4051 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4052 SISLANDS_SMC_STATETABLE *table)
4053 {
4054 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4055 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4056 struct si_power_info *si_pi = si_get_pi(rdev);
4057 u8 i;
4058
4059 if (si_pi->voltage_control_svi2) {
4060 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4061 si_pi->svc_gpio_id);
4062 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4063 si_pi->svd_gpio_id);
4064 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4065 2);
4066 } else {
4067 if (eg_pi->vddc_voltage_table.count) {
4068 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4069 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4070 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4071
4072 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4073 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4074 table->maxVDDCIndexInPPTable = i;
4075 break;
4076 }
4077 }
4078 }
4079
4080 if (eg_pi->vddci_voltage_table.count) {
4081 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4082
4083 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4084 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4085 }
4086
4087
4088 if (si_pi->mvdd_voltage_table.count) {
4089 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4090
4091 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4092 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4093 }
4094
4095 if (si_pi->vddc_phase_shed_control) {
4096 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4097 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4098 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4099
4100 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4101 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4102
4103 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4104 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4105 } else {
4106 si_pi->vddc_phase_shed_control = false;
4107 }
4108 }
4109 }
4110
4111 return 0;
4112 }
4113
4114 static int si_populate_voltage_value(struct radeon_device *rdev,
4115 const struct atom_voltage_table *table,
4116 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4117 {
4118 unsigned int i;
4119
4120 for (i = 0; i < table->count; i++) {
4121 if (value <= table->entries[i].value) {
4122 voltage->index = (u8)i;
4123 voltage->value = cpu_to_be16(table->entries[i].value);
4124 break;
4125 }
4126 }
4127
4128 if (i >= table->count)
4129 return -EINVAL;
4130
4131 return 0;
4132 }
4133
4134 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4135 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4136 {
4137 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4138 struct si_power_info *si_pi = si_get_pi(rdev);
4139
4140 if (pi->mvdd_control) {
4141 if (mclk <= pi->mvdd_split_frequency)
4142 voltage->index = 0;
4143 else
4144 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4145
4146 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4147 }
4148 return 0;
4149 }
4150
4151 static int si_get_std_voltage_value(struct radeon_device *rdev,
4152 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4153 u16 *std_voltage)
4154 {
4155 u16 v_index;
4156 bool voltage_found = false;
4157 *std_voltage = be16_to_cpu(voltage->value);
4158
4159 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4160 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4161 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4162 return -EINVAL;
4163
4164 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4165 if (be16_to_cpu(voltage->value) ==
4166 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4167 voltage_found = true;
4168 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4169 *std_voltage =
4170 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4171 else
4172 *std_voltage =
4173 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4174 break;
4175 }
4176 }
4177
4178 if (!voltage_found) {
4179 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4180 if (be16_to_cpu(voltage->value) <=
4181 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4182 voltage_found = true;
4183 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4184 *std_voltage =
4185 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4186 else
4187 *std_voltage =
4188 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4189 break;
4190 }
4191 }
4192 }
4193 } else {
4194 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4195 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4196 }
4197 }
4198
4199 return 0;
4200 }
4201
4202 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4203 u16 value, u8 index,
4204 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4205 {
4206 voltage->index = index;
4207 voltage->value = cpu_to_be16(value);
4208
4209 return 0;
4210 }
4211
4212 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4213 const struct radeon_phase_shedding_limits_table *limits,
4214 u16 voltage, u32 sclk, u32 mclk,
4215 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4216 {
4217 unsigned int i;
4218
4219 for (i = 0; i < limits->count; i++) {
4220 if ((voltage <= limits->entries[i].voltage) &&
4221 (sclk <= limits->entries[i].sclk) &&
4222 (mclk <= limits->entries[i].mclk))
4223 break;
4224 }
4225
4226 smc_voltage->phase_settings = (u8)i;
4227
4228 return 0;
4229 }
4230
4231 static int si_init_arb_table_index(struct radeon_device *rdev)
4232 {
4233 struct si_power_info *si_pi = si_get_pi(rdev);
4234 u32 tmp;
4235 int ret;
4236
4237 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4238 if (ret)
4239 return ret;
4240
4241 tmp &= 0x00FFFFFF;
4242 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4243
4244 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4245 }
4246
4247 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4248 {
4249 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4250 }
4251
4252 static int si_reset_to_default(struct radeon_device *rdev)
4253 {
4254 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4255 0 : -EINVAL;
4256 }
4257
4258 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4259 {
4260 struct si_power_info *si_pi = si_get_pi(rdev);
4261 u32 tmp;
4262 int ret;
4263
4264 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4265 &tmp, si_pi->sram_end);
4266 if (ret)
4267 return ret;
4268
4269 tmp = (tmp >> 24) & 0xff;
4270
4271 if (tmp == MC_CG_ARB_FREQ_F0)
4272 return 0;
4273
4274 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4275 }
4276
4277 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4278 u32 engine_clock)
4279 {
4280 u32 dram_rows;
4281 u32 dram_refresh_rate;
4282 u32 mc_arb_rfsh_rate;
4283 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4284
4285 if (tmp >= 4)
4286 dram_rows = 16384;
4287 else
4288 dram_rows = 1 << (tmp + 10);
4289
4290 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4291 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4292
4293 return mc_arb_rfsh_rate;
4294 }
4295
4296 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4297 struct rv7xx_pl *pl,
4298 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4299 {
4300 u32 dram_timing;
4301 u32 dram_timing2;
4302 u32 burst_time;
4303
4304 arb_regs->mc_arb_rfsh_rate =
4305 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4306
4307 radeon_atom_set_engine_dram_timings(rdev,
4308 pl->sclk,
4309 pl->mclk);
4310
4311 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4312 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4313 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4314
4315 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4316 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4317 arb_regs->mc_arb_burst_time = (u8)burst_time;
4318
4319 return 0;
4320 }
4321
4322 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4323 struct radeon_ps *radeon_state,
4324 unsigned int first_arb_set)
4325 {
4326 struct si_power_info *si_pi = si_get_pi(rdev);
4327 struct ni_ps *state = ni_get_ps(radeon_state);
4328 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4329 int i, ret = 0;
4330
4331 for (i = 0; i < state->performance_level_count; i++) {
4332 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4333 if (ret)
4334 break;
4335 ret = si_copy_bytes_to_smc(rdev,
4336 si_pi->arb_table_start +
4337 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4338 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4339 (u8 *)&arb_regs,
4340 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4341 si_pi->sram_end);
4342 if (ret)
4343 break;
4344 }
4345
4346 return ret;
4347 }
4348
4349 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4350 struct radeon_ps *radeon_new_state)
4351 {
4352 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4353 SISLANDS_DRIVER_STATE_ARB_INDEX);
4354 }
4355
4356 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4357 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4358 {
4359 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4360 struct si_power_info *si_pi = si_get_pi(rdev);
4361
4362 if (pi->mvdd_control)
4363 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4364 si_pi->mvdd_bootup_value, voltage);
4365
4366 return 0;
4367 }
4368
4369 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4370 struct radeon_ps *radeon_initial_state,
4371 SISLANDS_SMC_STATETABLE *table)
4372 {
4373 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4374 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4375 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4376 struct si_power_info *si_pi = si_get_pi(rdev);
4377 u32 reg;
4378 int ret;
4379
4380 table->initialState.levels[0].mclk.vDLL_CNTL =
4381 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4382 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4383 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4384 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4385 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4386 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4387 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4388 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4389 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4390 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4391 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4392 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4393 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4394 table->initialState.levels[0].mclk.vMPLL_SS =
4395 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4396 table->initialState.levels[0].mclk.vMPLL_SS2 =
4397 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4398
4399 table->initialState.levels[0].mclk.mclk_value =
4400 cpu_to_be32(initial_state->performance_levels[0].mclk);
4401
4402 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4403 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4404 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4405 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4406 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4407 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4408 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4409 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4410 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4411 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4412 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4413 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4414
4415 table->initialState.levels[0].sclk.sclk_value =
4416 cpu_to_be32(initial_state->performance_levels[0].sclk);
4417
4418 table->initialState.levels[0].arbRefreshState =
4419 SISLANDS_INITIAL_STATE_ARB_INDEX;
4420
4421 table->initialState.levels[0].ACIndex = 0;
4422
4423 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4424 initial_state->performance_levels[0].vddc,
4425 &table->initialState.levels[0].vddc);
4426
4427 if (!ret) {
4428 u16 std_vddc;
4429
4430 ret = si_get_std_voltage_value(rdev,
4431 &table->initialState.levels[0].vddc,
4432 &std_vddc);
4433 if (!ret)
4434 si_populate_std_voltage_value(rdev, std_vddc,
4435 table->initialState.levels[0].vddc.index,
4436 &table->initialState.levels[0].std_vddc);
4437 }
4438
4439 if (eg_pi->vddci_control)
4440 si_populate_voltage_value(rdev,
4441 &eg_pi->vddci_voltage_table,
4442 initial_state->performance_levels[0].vddci,
4443 &table->initialState.levels[0].vddci);
4444
4445 if (si_pi->vddc_phase_shed_control)
4446 si_populate_phase_shedding_value(rdev,
4447 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4448 initial_state->performance_levels[0].vddc,
4449 initial_state->performance_levels[0].sclk,
4450 initial_state->performance_levels[0].mclk,
4451 &table->initialState.levels[0].vddc);
4452
4453 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4454
4455 reg = CG_R(0xffff) | CG_L(0);
4456 table->initialState.levels[0].aT = cpu_to_be32(reg);
4457
4458 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4459
4460 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4461
4462 if (pi->mem_gddr5) {
4463 table->initialState.levels[0].strobeMode =
4464 si_get_strobe_mode_settings(rdev,
4465 initial_state->performance_levels[0].mclk);
4466
4467 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4468 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4469 else
4470 table->initialState.levels[0].mcFlags = 0;
4471 }
4472
4473 table->initialState.levelCount = 1;
4474
4475 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4476
4477 table->initialState.levels[0].dpm2.MaxPS = 0;
4478 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4479 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4480 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4481 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4482
4483 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4484 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4485
4486 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4487 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4488
4489 return 0;
4490 }
4491
4492 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4493 SISLANDS_SMC_STATETABLE *table)
4494 {
4495 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4496 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4497 struct si_power_info *si_pi = si_get_pi(rdev);
4498 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4499 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4500 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4501 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4502 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4503 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4504 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4505 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4506 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4507 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4508 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4509 u32 reg;
4510 int ret;
4511
4512 table->ACPIState = table->initialState;
4513
4514 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4515
4516 if (pi->acpi_vddc) {
4517 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4518 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4519 if (!ret) {
4520 u16 std_vddc;
4521
4522 ret = si_get_std_voltage_value(rdev,
4523 &table->ACPIState.levels[0].vddc, &std_vddc);
4524 if (!ret)
4525 si_populate_std_voltage_value(rdev, std_vddc,
4526 table->ACPIState.levels[0].vddc.index,
4527 &table->ACPIState.levels[0].std_vddc);
4528 }
4529 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4530
4531 if (si_pi->vddc_phase_shed_control) {
4532 si_populate_phase_shedding_value(rdev,
4533 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4534 pi->acpi_vddc,
4535 0,
4536 0,
4537 &table->ACPIState.levels[0].vddc);
4538 }
4539 } else {
4540 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4541 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4542 if (!ret) {
4543 u16 std_vddc;
4544
4545 ret = si_get_std_voltage_value(rdev,
4546 &table->ACPIState.levels[0].vddc, &std_vddc);
4547
4548 if (!ret)
4549 si_populate_std_voltage_value(rdev, std_vddc,
4550 table->ACPIState.levels[0].vddc.index,
4551 &table->ACPIState.levels[0].std_vddc);
4552 }
4553 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4554 si_pi->sys_pcie_mask,
4555 si_pi->boot_pcie_gen,
4556 RADEON_PCIE_GEN1);
4557
4558 if (si_pi->vddc_phase_shed_control)
4559 si_populate_phase_shedding_value(rdev,
4560 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4561 pi->min_vddc_in_table,
4562 0,
4563 0,
4564 &table->ACPIState.levels[0].vddc);
4565 }
4566
4567 if (pi->acpi_vddc) {
4568 if (eg_pi->acpi_vddci)
4569 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4570 eg_pi->acpi_vddci,
4571 &table->ACPIState.levels[0].vddci);
4572 }
4573
4574 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4575 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4576
4577 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4578
4579 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4580 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4581
4582 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4583 cpu_to_be32(dll_cntl);
4584 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4585 cpu_to_be32(mclk_pwrmgt_cntl);
4586 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4587 cpu_to_be32(mpll_ad_func_cntl);
4588 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4589 cpu_to_be32(mpll_dq_func_cntl);
4590 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4591 cpu_to_be32(mpll_func_cntl);
4592 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4593 cpu_to_be32(mpll_func_cntl_1);
4594 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4595 cpu_to_be32(mpll_func_cntl_2);
4596 table->ACPIState.levels[0].mclk.vMPLL_SS =
4597 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4598 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4599 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4600
4601 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4602 cpu_to_be32(spll_func_cntl);
4603 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4604 cpu_to_be32(spll_func_cntl_2);
4605 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4606 cpu_to_be32(spll_func_cntl_3);
4607 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4608 cpu_to_be32(spll_func_cntl_4);
4609
4610 table->ACPIState.levels[0].mclk.mclk_value = 0;
4611 table->ACPIState.levels[0].sclk.sclk_value = 0;
4612
4613 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4614
4615 if (eg_pi->dynamic_ac_timing)
4616 table->ACPIState.levels[0].ACIndex = 0;
4617
4618 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4619 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4620 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4621 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4622 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4623
4624 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4625 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4626
4627 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4628 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4629
4630 return 0;
4631 }
4632
4633 static int si_populate_ulv_state(struct radeon_device *rdev,
4634 SISLANDS_SMC_SWSTATE *state)
4635 {
4636 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4637 struct si_power_info *si_pi = si_get_pi(rdev);
4638 struct si_ulv_param *ulv = &si_pi->ulv;
4639 u32 sclk_in_sr = 1350; /* ??? */
4640 int ret;
4641
4642 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4643 &state->levels[0]);
4644 if (!ret) {
4645 if (eg_pi->sclk_deep_sleep) {
4646 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4647 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4648 else
4649 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4650 }
4651 if (ulv->one_pcie_lane_in_ulv)
4652 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4653 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4654 state->levels[0].ACIndex = 1;
4655 state->levels[0].std_vddc = state->levels[0].vddc;
4656 state->levelCount = 1;
4657
4658 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4659 }
4660
4661 return ret;
4662 }
4663
4664 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4665 {
4666 struct si_power_info *si_pi = si_get_pi(rdev);
4667 struct si_ulv_param *ulv = &si_pi->ulv;
4668 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4669 int ret;
4670
4671 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4672 &arb_regs);
4673 if (ret)
4674 return ret;
4675
4676 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4677 ulv->volt_change_delay);
4678
4679 ret = si_copy_bytes_to_smc(rdev,
4680 si_pi->arb_table_start +
4681 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4682 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4683 (u8 *)&arb_regs,
4684 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4685 si_pi->sram_end);
4686
4687 return ret;
4688 }
4689
4690 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4691 {
4692 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4693
4694 pi->mvdd_split_frequency = 30000;
4695 }
4696
4697 static int si_init_smc_table(struct radeon_device *rdev)
4698 {
4699 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4700 struct si_power_info *si_pi = si_get_pi(rdev);
4701 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4702 const struct si_ulv_param *ulv = &si_pi->ulv;
4703 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4704 int ret;
4705 u32 lane_width;
4706 u32 vr_hot_gpio;
4707
4708 si_populate_smc_voltage_tables(rdev, table);
4709
4710 switch (rdev->pm.int_thermal_type) {
4711 case THERMAL_TYPE_SI:
4712 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4713 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4714 break;
4715 case THERMAL_TYPE_NONE:
4716 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4717 break;
4718 default:
4719 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4720 break;
4721 }
4722
4723 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4724 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4725
4726 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4727 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4728 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4729 }
4730
4731 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4732 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4733
4734 if (pi->mem_gddr5)
4735 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4736
4737 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4738 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4739
4740 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4741 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4742 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4743 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4744 vr_hot_gpio);
4745 }
4746
4747 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4748 if (ret)
4749 return ret;
4750
4751 ret = si_populate_smc_acpi_state(rdev, table);
4752 if (ret)
4753 return ret;
4754
4755 table->driverState = table->initialState;
4756
4757 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4758 SISLANDS_INITIAL_STATE_ARB_INDEX);
4759 if (ret)
4760 return ret;
4761
4762 if (ulv->supported && ulv->pl.vddc) {
4763 ret = si_populate_ulv_state(rdev, &table->ULVState);
4764 if (ret)
4765 return ret;
4766
4767 ret = si_program_ulv_memory_timing_parameters(rdev);
4768 if (ret)
4769 return ret;
4770
4771 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4772 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4773
4774 lane_width = radeon_get_pcie_lanes(rdev);
4775 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4776 } else {
4777 table->ULVState = table->initialState;
4778 }
4779
4780 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4781 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4782 si_pi->sram_end);
4783 }
4784
4785 static int si_calculate_sclk_params(struct radeon_device *rdev,
4786 u32 engine_clock,
4787 SISLANDS_SMC_SCLK_VALUE *sclk)
4788 {
4789 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4790 struct si_power_info *si_pi = si_get_pi(rdev);
4791 struct atom_clock_dividers dividers;
4792 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4793 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4794 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4795 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4796 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4797 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4798 u64 tmp;
4799 u32 reference_clock = rdev->clock.spll.reference_freq;
4800 u32 reference_divider;
4801 u32 fbdiv;
4802 int ret;
4803
4804 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4805 engine_clock, false, &dividers);
4806 if (ret)
4807 return ret;
4808
4809 reference_divider = 1 + dividers.ref_div;
4810
4811 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4812 do_div(tmp, reference_clock);
4813 fbdiv = (u32) tmp;
4814
4815 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4816 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4817 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4818
4819 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4820 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4821
4822 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4823 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4824 spll_func_cntl_3 |= SPLL_DITHEN;
4825
4826 if (pi->sclk_ss) {
4827 struct radeon_atom_ss ss;
4828 u32 vco_freq = engine_clock * dividers.post_div;
4829
4830 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4831 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4832 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4833 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4834
4835 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4836 cg_spll_spread_spectrum |= CLK_S(clk_s);
4837 cg_spll_spread_spectrum |= SSEN;
4838
4839 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4840 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4841 }
4842 }
4843
4844 sclk->sclk_value = engine_clock;
4845 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4846 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4847 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4848 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4849 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4850 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4851
4852 return 0;
4853 }
4854
4855 static int si_populate_sclk_value(struct radeon_device *rdev,
4856 u32 engine_clock,
4857 SISLANDS_SMC_SCLK_VALUE *sclk)
4858 {
4859 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4860 int ret;
4861
4862 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4863 if (!ret) {
4864 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4865 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4866 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4867 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4868 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4869 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4870 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4871 }
4872
4873 return ret;
4874 }
4875
4876 static int si_populate_mclk_value(struct radeon_device *rdev,
4877 u32 engine_clock,
4878 u32 memory_clock,
4879 SISLANDS_SMC_MCLK_VALUE *mclk,
4880 bool strobe_mode,
4881 bool dll_state_on)
4882 {
4883 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4884 struct si_power_info *si_pi = si_get_pi(rdev);
4885 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4886 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4887 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4888 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4889 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4890 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4891 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4892 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4893 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4894 struct atom_mpll_param mpll_param;
4895 int ret;
4896
4897 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4898 if (ret)
4899 return ret;
4900
4901 mpll_func_cntl &= ~BWCTRL_MASK;
4902 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4903
4904 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4905 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4906 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4907
4908 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4909 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4910
4911 if (pi->mem_gddr5) {
4912 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4913 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4914 YCLK_POST_DIV(mpll_param.post_div);
4915 }
4916
4917 if (pi->mclk_ss) {
4918 struct radeon_atom_ss ss;
4919 u32 freq_nom;
4920 u32 tmp;
4921 u32 reference_clock = rdev->clock.mpll.reference_freq;
4922
4923 if (pi->mem_gddr5)
4924 freq_nom = memory_clock * 4;
4925 else
4926 freq_nom = memory_clock * 2;
4927
4928 tmp = freq_nom / reference_clock;
4929 tmp = tmp * tmp;
4930 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4931 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4932 u32 clks = reference_clock * 5 / ss.rate;
4933 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4934
4935 mpll_ss1 &= ~CLKV_MASK;
4936 mpll_ss1 |= CLKV(clkv);
4937
4938 mpll_ss2 &= ~CLKS_MASK;
4939 mpll_ss2 |= CLKS(clks);
4940 }
4941 }
4942
4943 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4944 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4945
4946 if (dll_state_on)
4947 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4948 else
4949 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4950
4951 mclk->mclk_value = cpu_to_be32(memory_clock);
4952 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4953 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4954 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4955 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4956 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4957 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4958 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4959 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4960 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4961
4962 return 0;
4963 }
4964
4965 static void si_populate_smc_sp(struct radeon_device *rdev,
4966 struct radeon_ps *radeon_state,
4967 SISLANDS_SMC_SWSTATE *smc_state)
4968 {
4969 struct ni_ps *ps = ni_get_ps(radeon_state);
4970 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4971 int i;
4972
4973 for (i = 0; i < ps->performance_level_count - 1; i++)
4974 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4975
4976 smc_state->levels[ps->performance_level_count - 1].bSP =
4977 cpu_to_be32(pi->psp);
4978 }
4979
4980 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4981 struct rv7xx_pl *pl,
4982 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4983 {
4984 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4985 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4986 struct si_power_info *si_pi = si_get_pi(rdev);
4987 int ret;
4988 bool dll_state_on;
4989 u16 std_vddc;
4990 bool gmc_pg = false;
4991
4992 if (eg_pi->pcie_performance_request &&
4993 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4994 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4995 else
4996 level->gen2PCIE = (u8)pl->pcie_gen;
4997
4998 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4999 if (ret)
5000 return ret;
5001
5002 level->mcFlags = 0;
5003
5004 if (pi->mclk_stutter_mode_threshold &&
5005 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5006 !eg_pi->uvd_enabled &&
5007 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5008 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5009 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5010
5011 if (gmc_pg)
5012 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5013 }
5014
5015 if (pi->mem_gddr5) {
5016 if (pl->mclk > pi->mclk_edc_enable_threshold)
5017 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5018
5019 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5020 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5021
5022 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5023
5024 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5025 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5026 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5027 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5028 else
5029 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5030 } else {
5031 dll_state_on = false;
5032 }
5033 } else {
5034 level->strobeMode = si_get_strobe_mode_settings(rdev,
5035 pl->mclk);
5036
5037 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5038 }
5039
5040 ret = si_populate_mclk_value(rdev,
5041 pl->sclk,
5042 pl->mclk,
5043 &level->mclk,
5044 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5045 if (ret)
5046 return ret;
5047
5048 ret = si_populate_voltage_value(rdev,
5049 &eg_pi->vddc_voltage_table,
5050 pl->vddc, &level->vddc);
5051 if (ret)
5052 return ret;
5053
5054
5055 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5056 if (ret)
5057 return ret;
5058
5059 ret = si_populate_std_voltage_value(rdev, std_vddc,
5060 level->vddc.index, &level->std_vddc);
5061 if (ret)
5062 return ret;
5063
5064 if (eg_pi->vddci_control) {
5065 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5066 pl->vddci, &level->vddci);
5067 if (ret)
5068 return ret;
5069 }
5070
5071 if (si_pi->vddc_phase_shed_control) {
5072 ret = si_populate_phase_shedding_value(rdev,
5073 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5074 pl->vddc,
5075 pl->sclk,
5076 pl->mclk,
5077 &level->vddc);
5078 if (ret)
5079 return ret;
5080 }
5081
5082 level->MaxPoweredUpCU = si_pi->max_cu;
5083
5084 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5085
5086 return ret;
5087 }
5088
5089 static int si_populate_smc_t(struct radeon_device *rdev,
5090 struct radeon_ps *radeon_state,
5091 SISLANDS_SMC_SWSTATE *smc_state)
5092 {
5093 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5094 struct ni_ps *state = ni_get_ps(radeon_state);
5095 u32 a_t;
5096 u32 t_l, t_h;
5097 u32 high_bsp;
5098 int i, ret;
5099
5100 if (state->performance_level_count >= 9)
5101 return -EINVAL;
5102
5103 if (state->performance_level_count < 2) {
5104 a_t = CG_R(0xffff) | CG_L(0);
5105 smc_state->levels[0].aT = cpu_to_be32(a_t);
5106 return 0;
5107 }
5108
5109 smc_state->levels[0].aT = cpu_to_be32(0);
5110
5111 for (i = 0; i <= state->performance_level_count - 2; i++) {
5112 ret = r600_calculate_at(
5113 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5114 100 * R600_AH_DFLT,
5115 state->performance_levels[i + 1].sclk,
5116 state->performance_levels[i].sclk,
5117 &t_l,
5118 &t_h);
5119
5120 if (ret) {
5121 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5122 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5123 }
5124
5125 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5126 a_t |= CG_R(t_l * pi->bsp / 20000);
5127 smc_state->levels[i].aT = cpu_to_be32(a_t);
5128
5129 high_bsp = (i == state->performance_level_count - 2) ?
5130 pi->pbsp : pi->bsp;
5131 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5132 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5133 }
5134
5135 return 0;
5136 }
5137
5138 static int si_disable_ulv(struct radeon_device *rdev)
5139 {
5140 struct si_power_info *si_pi = si_get_pi(rdev);
5141 struct si_ulv_param *ulv = &si_pi->ulv;
5142
5143 if (ulv->supported)
5144 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5145 0 : -EINVAL;
5146
5147 return 0;
5148 }
5149
5150 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5151 struct radeon_ps *radeon_state)
5152 {
5153 const struct si_power_info *si_pi = si_get_pi(rdev);
5154 const struct si_ulv_param *ulv = &si_pi->ulv;
5155 const struct ni_ps *state = ni_get_ps(radeon_state);
5156 int i;
5157
5158 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5159 return false;
5160
5161 /* XXX validate against display requirements! */
5162
5163 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5164 if (rdev->clock.current_dispclk <=
5165 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5166 if (ulv->pl.vddc <
5167 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5168 return false;
5169 }
5170 }
5171
5172 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5173 return false;
5174
5175 return true;
5176 }
5177
5178 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5179 struct radeon_ps *radeon_new_state)
5180 {
5181 const struct si_power_info *si_pi = si_get_pi(rdev);
5182 const struct si_ulv_param *ulv = &si_pi->ulv;
5183
5184 if (ulv->supported) {
5185 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5186 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5187 0 : -EINVAL;
5188 }
5189 return 0;
5190 }
5191
5192 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5193 struct radeon_ps *radeon_state,
5194 SISLANDS_SMC_SWSTATE *smc_state)
5195 {
5196 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5197 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5198 struct si_power_info *si_pi = si_get_pi(rdev);
5199 struct ni_ps *state = ni_get_ps(radeon_state);
5200 int i, ret;
5201 u32 threshold;
5202 u32 sclk_in_sr = 1350; /* ??? */
5203
5204 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5205 return -EINVAL;
5206
5207 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5208
5209 if (radeon_state->vclk && radeon_state->dclk) {
5210 eg_pi->uvd_enabled = true;
5211 if (eg_pi->smu_uvd_hs)
5212 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5213 } else {
5214 eg_pi->uvd_enabled = false;
5215 }
5216
5217 if (state->dc_compatible)
5218 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5219
5220 smc_state->levelCount = 0;
5221 for (i = 0; i < state->performance_level_count; i++) {
5222 if (eg_pi->sclk_deep_sleep) {
5223 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5224 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5225 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5226 else
5227 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5228 }
5229 }
5230
5231 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5232 &smc_state->levels[i]);
5233 smc_state->levels[i].arbRefreshState =
5234 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5235
5236 if (ret)
5237 return ret;
5238
5239 if (ni_pi->enable_power_containment)
5240 smc_state->levels[i].displayWatermark =
5241 (state->performance_levels[i].sclk < threshold) ?
5242 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5243 else
5244 smc_state->levels[i].displayWatermark = (i < 2) ?
5245 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5246
5247 if (eg_pi->dynamic_ac_timing)
5248 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5249 else
5250 smc_state->levels[i].ACIndex = 0;
5251
5252 smc_state->levelCount++;
5253 }
5254
5255 si_write_smc_soft_register(rdev,
5256 SI_SMC_SOFT_REGISTER_watermark_threshold,
5257 threshold / 512);
5258
5259 si_populate_smc_sp(rdev, radeon_state, smc_state);
5260
5261 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5262 if (ret)
5263 ni_pi->enable_power_containment = false;
5264
5265 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5266 if (ret)
5267 ni_pi->enable_sq_ramping = false;
5268
5269 return si_populate_smc_t(rdev, radeon_state, smc_state);
5270 }
5271
5272 static int si_upload_sw_state(struct radeon_device *rdev,
5273 struct radeon_ps *radeon_new_state)
5274 {
5275 struct si_power_info *si_pi = si_get_pi(rdev);
5276 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5277 int ret;
5278 u32 address = si_pi->state_table_start +
5279 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5280 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5281 ((new_state->performance_level_count - 1) *
5282 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5283 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5284
5285 memset(smc_state, 0, state_size);
5286
5287 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5288 if (ret)
5289 return ret;
5290
5291 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5292 state_size, si_pi->sram_end);
5293
5294 return ret;
5295 }
5296
5297 static int si_upload_ulv_state(struct radeon_device *rdev)
5298 {
5299 struct si_power_info *si_pi = si_get_pi(rdev);
5300 struct si_ulv_param *ulv = &si_pi->ulv;
5301 int ret = 0;
5302
5303 if (ulv->supported && ulv->pl.vddc) {
5304 u32 address = si_pi->state_table_start +
5305 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5306 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5307 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5308
5309 memset(smc_state, 0, state_size);
5310
5311 ret = si_populate_ulv_state(rdev, smc_state);
5312 if (!ret)
5313 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5314 state_size, si_pi->sram_end);
5315 }
5316
5317 return ret;
5318 }
5319
5320 static int si_upload_smc_data(struct radeon_device *rdev)
5321 {
5322 struct radeon_crtc *radeon_crtc = NULL;
5323 int i;
5324
5325 if (rdev->pm.dpm.new_active_crtc_count == 0)
5326 return 0;
5327
5328 for (i = 0; i < rdev->num_crtc; i++) {
5329 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5330 radeon_crtc = rdev->mode_info.crtcs[i];
5331 break;
5332 }
5333 }
5334
5335 if (radeon_crtc == NULL)
5336 return 0;
5337
5338 if (radeon_crtc->line_time <= 0)
5339 return 0;
5340
5341 if (si_write_smc_soft_register(rdev,
5342 SI_SMC_SOFT_REGISTER_crtc_index,
5343 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5344 return 0;
5345
5346 if (si_write_smc_soft_register(rdev,
5347 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5348 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5349 return 0;
5350
5351 if (si_write_smc_soft_register(rdev,
5352 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5353 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5354 return 0;
5355
5356 return 0;
5357 }
5358
5359 static int si_set_mc_special_registers(struct radeon_device *rdev,
5360 struct si_mc_reg_table *table)
5361 {
5362 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5363 u8 i, j, k;
5364 u32 temp_reg;
5365
5366 for (i = 0, j = table->last; i < table->last; i++) {
5367 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5368 return -EINVAL;
5369 switch (table->mc_reg_address[i].s1 << 2) {
5370 case MC_SEQ_MISC1:
5371 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5372 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5373 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5374 for (k = 0; k < table->num_entries; k++)
5375 table->mc_reg_table_entry[k].mc_data[j] =
5376 ((temp_reg & 0xffff0000)) |
5377 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5378 j++;
5379 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5380 return -EINVAL;
5381
5382 temp_reg = RREG32(MC_PMG_CMD_MRS);
5383 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5384 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5385 for (k = 0; k < table->num_entries; k++) {
5386 table->mc_reg_table_entry[k].mc_data[j] =
5387 (temp_reg & 0xffff0000) |
5388 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5389 if (!pi->mem_gddr5)
5390 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5391 }
5392 j++;
5393 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5394 return -EINVAL;
5395
5396 if (!pi->mem_gddr5) {
5397 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5398 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5399 for (k = 0; k < table->num_entries; k++)
5400 table->mc_reg_table_entry[k].mc_data[j] =
5401 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5402 j++;
5403 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5404 return -EINVAL;
5405 }
5406 break;
5407 case MC_SEQ_RESERVE_M:
5408 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5409 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5410 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5411 for(k = 0; k < table->num_entries; k++)
5412 table->mc_reg_table_entry[k].mc_data[j] =
5413 (temp_reg & 0xffff0000) |
5414 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5415 j++;
5416 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5417 return -EINVAL;
5418 break;
5419 default:
5420 break;
5421 }
5422 }
5423
5424 table->last = j;
5425
5426 return 0;
5427 }
5428
5429 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5430 {
5431 bool result = true;
5432
5433 switch (in_reg) {
5434 case MC_SEQ_RAS_TIMING >> 2:
5435 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5436 break;
5437 case MC_SEQ_CAS_TIMING >> 2:
5438 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5439 break;
5440 case MC_SEQ_MISC_TIMING >> 2:
5441 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5442 break;
5443 case MC_SEQ_MISC_TIMING2 >> 2:
5444 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5445 break;
5446 case MC_SEQ_RD_CTL_D0 >> 2:
5447 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5448 break;
5449 case MC_SEQ_RD_CTL_D1 >> 2:
5450 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5451 break;
5452 case MC_SEQ_WR_CTL_D0 >> 2:
5453 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5454 break;
5455 case MC_SEQ_WR_CTL_D1 >> 2:
5456 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5457 break;
5458 case MC_PMG_CMD_EMRS >> 2:
5459 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5460 break;
5461 case MC_PMG_CMD_MRS >> 2:
5462 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5463 break;
5464 case MC_PMG_CMD_MRS1 >> 2:
5465 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5466 break;
5467 case MC_SEQ_PMG_TIMING >> 2:
5468 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5469 break;
5470 case MC_PMG_CMD_MRS2 >> 2:
5471 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5472 break;
5473 case MC_SEQ_WR_CTL_2 >> 2:
5474 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5475 break;
5476 default:
5477 result = false;
5478 break;
5479 }
5480
5481 return result;
5482 }
5483
5484 static void si_set_valid_flag(struct si_mc_reg_table *table)
5485 {
5486 u8 i, j;
5487
5488 for (i = 0; i < table->last; i++) {
5489 for (j = 1; j < table->num_entries; j++) {
5490 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5491 table->valid_flag |= 1 << i;
5492 break;
5493 }
5494 }
5495 }
5496 }
5497
5498 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5499 {
5500 u32 i;
5501 u16 address;
5502
5503 for (i = 0; i < table->last; i++)
5504 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5505 address : table->mc_reg_address[i].s1;
5506
5507 }
5508
5509 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5510 struct si_mc_reg_table *si_table)
5511 {
5512 u8 i, j;
5513
5514 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5515 return -EINVAL;
5516 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5517 return -EINVAL;
5518
5519 for (i = 0; i < table->last; i++)
5520 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5521 si_table->last = table->last;
5522
5523 for (i = 0; i < table->num_entries; i++) {
5524 si_table->mc_reg_table_entry[i].mclk_max =
5525 table->mc_reg_table_entry[i].mclk_max;
5526 for (j = 0; j < table->last; j++) {
5527 si_table->mc_reg_table_entry[i].mc_data[j] =
5528 table->mc_reg_table_entry[i].mc_data[j];
5529 }
5530 }
5531 si_table->num_entries = table->num_entries;
5532
5533 return 0;
5534 }
5535
5536 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5537 {
5538 struct si_power_info *si_pi = si_get_pi(rdev);
5539 struct atom_mc_reg_table *table;
5540 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5541 u8 module_index = rv770_get_memory_module_index(rdev);
5542 int ret;
5543
5544 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5545 if (!table)
5546 return -ENOMEM;
5547
5548 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5549 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5550 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5551 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5552 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5553 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5554 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5555 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5556 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5557 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5558 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5559 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5560 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5561 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5562
5563 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5564 if (ret)
5565 goto init_mc_done;
5566
5567 ret = si_copy_vbios_mc_reg_table(table, si_table);
5568 if (ret)
5569 goto init_mc_done;
5570
5571 si_set_s0_mc_reg_index(si_table);
5572
5573 ret = si_set_mc_special_registers(rdev, si_table);
5574 if (ret)
5575 goto init_mc_done;
5576
5577 si_set_valid_flag(si_table);
5578
5579 init_mc_done:
5580 kfree(table);
5581
5582 return ret;
5583
5584 }
5585
5586 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5587 SMC_SIslands_MCRegisters *mc_reg_table)
5588 {
5589 struct si_power_info *si_pi = si_get_pi(rdev);
5590 u32 i, j;
5591
5592 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5593 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5594 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5595 break;
5596 mc_reg_table->address[i].s0 =
5597 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5598 mc_reg_table->address[i].s1 =
5599 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5600 i++;
5601 }
5602 }
5603 mc_reg_table->last = (u8)i;
5604 }
5605
5606 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5607 SMC_SIslands_MCRegisterSet *data,
5608 u32 num_entries, u32 valid_flag)
5609 {
5610 u32 i, j;
5611
5612 for(i = 0, j = 0; j < num_entries; j++) {
5613 if (valid_flag & (1 << j)) {
5614 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5615 i++;
5616 }
5617 }
5618 }
5619
5620 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5621 struct rv7xx_pl *pl,
5622 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5623 {
5624 struct si_power_info *si_pi = si_get_pi(rdev);
5625 u32 i = 0;
5626
5627 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5628 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5629 break;
5630 }
5631
5632 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5633 --i;
5634
5635 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5636 mc_reg_table_data, si_pi->mc_reg_table.last,
5637 si_pi->mc_reg_table.valid_flag);
5638 }
5639
5640 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5641 struct radeon_ps *radeon_state,
5642 SMC_SIslands_MCRegisters *mc_reg_table)
5643 {
5644 struct ni_ps *state = ni_get_ps(radeon_state);
5645 int i;
5646
5647 for (i = 0; i < state->performance_level_count; i++) {
5648 si_convert_mc_reg_table_entry_to_smc(rdev,
5649 &state->performance_levels[i],
5650 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5651 }
5652 }
5653
5654 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5655 struct radeon_ps *radeon_boot_state)
5656 {
5657 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5658 struct si_power_info *si_pi = si_get_pi(rdev);
5659 struct si_ulv_param *ulv = &si_pi->ulv;
5660 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5661
5662 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5663
5664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5665
5666 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5667
5668 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5669 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5670
5671 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5672 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5673 si_pi->mc_reg_table.last,
5674 si_pi->mc_reg_table.valid_flag);
5675
5676 if (ulv->supported && ulv->pl.vddc != 0)
5677 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5678 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5679 else
5680 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5681 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5682 si_pi->mc_reg_table.last,
5683 si_pi->mc_reg_table.valid_flag);
5684
5685 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5686
5687 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5688 (u8 *)smc_mc_reg_table,
5689 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5690 }
5691
5692 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5693 struct radeon_ps *radeon_new_state)
5694 {
5695 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5696 struct si_power_info *si_pi = si_get_pi(rdev);
5697 u32 address = si_pi->mc_reg_table_start +
5698 offsetof(SMC_SIslands_MCRegisters,
5699 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5700 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5701
5702 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5703
5704 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5705
5706
5707 return si_copy_bytes_to_smc(rdev, address,
5708 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5709 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5710 si_pi->sram_end);
5711
5712 }
5713
5714 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5715 {
5716 if (enable)
5717 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5718 else
5719 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5720 }
5721
5722 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5723 struct radeon_ps *radeon_state)
5724 {
5725 struct ni_ps *state = ni_get_ps(radeon_state);
5726 int i;
5727 u16 pcie_speed, max_speed = 0;
5728
5729 for (i = 0; i < state->performance_level_count; i++) {
5730 pcie_speed = state->performance_levels[i].pcie_gen;
5731 if (max_speed < pcie_speed)
5732 max_speed = pcie_speed;
5733 }
5734 return max_speed;
5735 }
5736
5737 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5738 {
5739 u32 speed_cntl;
5740
5741 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5742 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5743
5744 return (u16)speed_cntl;
5745 }
5746
5747 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5748 struct radeon_ps *radeon_new_state,
5749 struct radeon_ps *radeon_current_state)
5750 {
5751 struct si_power_info *si_pi = si_get_pi(rdev);
5752 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5753 enum radeon_pcie_gen current_link_speed;
5754
5755 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5756 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5757 else
5758 current_link_speed = si_pi->force_pcie_gen;
5759
5760 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5761 si_pi->pspp_notify_required = false;
5762 if (target_link_speed > current_link_speed) {
5763 switch (target_link_speed) {
5764 #if defined(CONFIG_ACPI)
5765 case RADEON_PCIE_GEN3:
5766 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5767 break;
5768 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5769 if (current_link_speed == RADEON_PCIE_GEN2)
5770 break;
5771 case RADEON_PCIE_GEN2:
5772 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5773 break;
5774 #endif
5775 default:
5776 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5777 break;
5778 }
5779 } else {
5780 if (target_link_speed < current_link_speed)
5781 si_pi->pspp_notify_required = true;
5782 }
5783 }
5784
5785 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5786 struct radeon_ps *radeon_new_state,
5787 struct radeon_ps *radeon_current_state)
5788 {
5789 struct si_power_info *si_pi = si_get_pi(rdev);
5790 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5791 u8 request;
5792
5793 if (si_pi->pspp_notify_required) {
5794 if (target_link_speed == RADEON_PCIE_GEN3)
5795 request = PCIE_PERF_REQ_PECI_GEN3;
5796 else if (target_link_speed == RADEON_PCIE_GEN2)
5797 request = PCIE_PERF_REQ_PECI_GEN2;
5798 else
5799 request = PCIE_PERF_REQ_PECI_GEN1;
5800
5801 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5802 (si_get_current_pcie_speed(rdev) > 0))
5803 return;
5804
5805 #if defined(CONFIG_ACPI)
5806 radeon_acpi_pcie_performance_request(rdev, request, false);
5807 #endif
5808 }
5809 }
5810
5811 #if 0
5812 static int si_ds_request(struct radeon_device *rdev,
5813 bool ds_status_on, u32 count_write)
5814 {
5815 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5816
5817 if (eg_pi->sclk_deep_sleep) {
5818 if (ds_status_on)
5819 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5820 PPSMC_Result_OK) ?
5821 0 : -EINVAL;
5822 else
5823 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5824 PPSMC_Result_OK) ? 0 : -EINVAL;
5825 }
5826 return 0;
5827 }
5828 #endif
5829
5830 static void si_set_max_cu_value(struct radeon_device *rdev)
5831 {
5832 struct si_power_info *si_pi = si_get_pi(rdev);
5833
5834 if (rdev->family == CHIP_VERDE) {
5835 switch (rdev->pdev->device) {
5836 case 0x6820:
5837 case 0x6825:
5838 case 0x6821:
5839 case 0x6823:
5840 case 0x6827:
5841 si_pi->max_cu = 10;
5842 break;
5843 case 0x682D:
5844 case 0x6824:
5845 case 0x682F:
5846 case 0x6826:
5847 si_pi->max_cu = 8;
5848 break;
5849 case 0x6828:
5850 case 0x6830:
5851 case 0x6831:
5852 case 0x6838:
5853 case 0x6839:
5854 case 0x683D:
5855 si_pi->max_cu = 10;
5856 break;
5857 case 0x683B:
5858 case 0x683F:
5859 case 0x6829:
5860 si_pi->max_cu = 8;
5861 break;
5862 default:
5863 si_pi->max_cu = 0;
5864 break;
5865 }
5866 } else {
5867 si_pi->max_cu = 0;
5868 }
5869 }
5870
5871 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5872 struct radeon_clock_voltage_dependency_table *table)
5873 {
5874 u32 i;
5875 int j;
5876 u16 leakage_voltage;
5877
5878 if (table) {
5879 for (i = 0; i < table->count; i++) {
5880 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5881 table->entries[i].v,
5882 &leakage_voltage)) {
5883 case 0:
5884 table->entries[i].v = leakage_voltage;
5885 break;
5886 case -EAGAIN:
5887 return -EINVAL;
5888 case -EINVAL:
5889 default:
5890 break;
5891 }
5892 }
5893
5894 for (j = (table->count - 2); j >= 0; j--) {
5895 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5896 table->entries[j].v : table->entries[j + 1].v;
5897 }
5898 }
5899 return 0;
5900 }
5901
5902 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5903 {
5904 int ret = 0;
5905
5906 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5907 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5908 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5909 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5910 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5911 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5912 return ret;
5913 }
5914
5915 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5916 struct radeon_ps *radeon_new_state,
5917 struct radeon_ps *radeon_current_state)
5918 {
5919 u32 lane_width;
5920 u32 new_lane_width =
5921 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5922 u32 current_lane_width =
5923 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5924
5925 if (new_lane_width != current_lane_width) {
5926 radeon_set_pcie_lanes(rdev, new_lane_width);
5927 lane_width = radeon_get_pcie_lanes(rdev);
5928 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5929 }
5930 }
5931
5932 static void si_set_vce_clock(struct radeon_device *rdev,
5933 struct radeon_ps *new_rps,
5934 struct radeon_ps *old_rps)
5935 {
5936 if ((old_rps->evclk != new_rps->evclk) ||
5937 (old_rps->ecclk != new_rps->ecclk)) {
5938 /* turn the clocks on when encoding, off otherwise */
5939 if (new_rps->evclk || new_rps->ecclk)
5940 vce_v1_0_enable_mgcg(rdev, false);
5941 else
5942 vce_v1_0_enable_mgcg(rdev, true);
5943 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5944 }
5945 }
5946
5947 void si_dpm_setup_asic(struct radeon_device *rdev)
5948 {
5949 int r;
5950
5951 r = si_mc_load_microcode(rdev);
5952 if (r)
5953 DRM_ERROR("Failed to load MC firmware!\n");
5954 rv770_get_memory_type(rdev);
5955 si_read_clock_registers(rdev);
5956 si_enable_acpi_power_management(rdev);
5957 }
5958
5959 static int si_thermal_enable_alert(struct radeon_device *rdev,
5960 bool enable)
5961 {
5962 u32 thermal_int = RREG32(CG_THERMAL_INT);
5963
5964 if (enable) {
5965 PPSMC_Result result;
5966
5967 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5968 WREG32(CG_THERMAL_INT, thermal_int);
5969 rdev->irq.dpm_thermal = false;
5970 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5971 if (result != PPSMC_Result_OK) {
5972 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5973 return -EINVAL;
5974 }
5975 } else {
5976 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5977 WREG32(CG_THERMAL_INT, thermal_int);
5978 rdev->irq.dpm_thermal = true;
5979 }
5980
5981 return 0;
5982 }
5983
5984 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5985 int min_temp, int max_temp)
5986 {
5987 int low_temp = 0 * 1000;
5988 int high_temp = 255 * 1000;
5989
5990 if (low_temp < min_temp)
5991 low_temp = min_temp;
5992 if (high_temp > max_temp)
5993 high_temp = max_temp;
5994 if (high_temp < low_temp) {
5995 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5996 return -EINVAL;
5997 }
5998
5999 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6000 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6001 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6002
6003 rdev->pm.dpm.thermal.min_temp = low_temp;
6004 rdev->pm.dpm.thermal.max_temp = high_temp;
6005
6006 return 0;
6007 }
6008
6009 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6010 {
6011 struct si_power_info *si_pi = si_get_pi(rdev);
6012 u32 tmp;
6013
6014 if (si_pi->fan_ctrl_is_in_default_mode) {
6015 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6016 si_pi->fan_ctrl_default_mode = tmp;
6017 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6018 si_pi->t_min = tmp;
6019 si_pi->fan_ctrl_is_in_default_mode = false;
6020 }
6021
6022 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6023 tmp |= TMIN(0);
6024 WREG32(CG_FDO_CTRL2, tmp);
6025
6026 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6027 tmp |= FDO_PWM_MODE(mode);
6028 WREG32(CG_FDO_CTRL2, tmp);
6029 }
6030
6031 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6032 {
6033 struct si_power_info *si_pi = si_get_pi(rdev);
6034 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6035 u32 duty100;
6036 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6037 u16 fdo_min, slope1, slope2;
6038 u32 reference_clock, tmp;
6039 int ret;
6040 u64 tmp64;
6041
6042 if (!si_pi->fan_table_start) {
6043 rdev->pm.dpm.fan.ucode_fan_control = false;
6044 return 0;
6045 }
6046
6047 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6048
6049 if (duty100 == 0) {
6050 rdev->pm.dpm.fan.ucode_fan_control = false;
6051 return 0;
6052 }
6053
6054 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6055 do_div(tmp64, 10000);
6056 fdo_min = (u16)tmp64;
6057
6058 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6059 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6060
6061 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6062 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6063
6064 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6065 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6066
6067 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6068 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6069 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6070
6071 fan_table.slope1 = cpu_to_be16(slope1);
6072 fan_table.slope2 = cpu_to_be16(slope2);
6073
6074 fan_table.fdo_min = cpu_to_be16(fdo_min);
6075
6076 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6077
6078 fan_table.hys_up = cpu_to_be16(1);
6079
6080 fan_table.hys_slope = cpu_to_be16(1);
6081
6082 fan_table.temp_resp_lim = cpu_to_be16(5);
6083
6084 reference_clock = radeon_get_xclk(rdev);
6085
6086 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6087 reference_clock) / 1600);
6088
6089 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6090
6091 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6092 fan_table.temp_src = (uint8_t)tmp;
6093
6094 ret = si_copy_bytes_to_smc(rdev,
6095 si_pi->fan_table_start,
6096 (u8 *)(&fan_table),
6097 sizeof(fan_table),
6098 si_pi->sram_end);
6099
6100 if (ret) {
6101 DRM_ERROR("Failed to load fan table to the SMC.");
6102 rdev->pm.dpm.fan.ucode_fan_control = false;
6103 }
6104
6105 return 0;
6106 }
6107
6108 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6109 {
6110 struct si_power_info *si_pi = si_get_pi(rdev);
6111 PPSMC_Result ret;
6112
6113 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6114 if (ret == PPSMC_Result_OK) {
6115 si_pi->fan_is_controlled_by_smc = true;
6116 return 0;
6117 } else {
6118 return -EINVAL;
6119 }
6120 }
6121
6122 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6123 {
6124 struct si_power_info *si_pi = si_get_pi(rdev);
6125 PPSMC_Result ret;
6126
6127 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6128
6129 if (ret == PPSMC_Result_OK) {
6130 si_pi->fan_is_controlled_by_smc = false;
6131 return 0;
6132 } else {
6133 return -EINVAL;
6134 }
6135 }
6136
6137 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6138 u32 *speed)
6139 {
6140 u32 duty, duty100;
6141 u64 tmp64;
6142
6143 if (rdev->pm.no_fan)
6144 return -ENOENT;
6145
6146 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6147 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6148
6149 if (duty100 == 0)
6150 return -EINVAL;
6151
6152 tmp64 = (u64)duty * 100;
6153 do_div(tmp64, duty100);
6154 *speed = (u32)tmp64;
6155
6156 if (*speed > 100)
6157 *speed = 100;
6158
6159 return 0;
6160 }
6161
6162 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6163 u32 speed)
6164 {
6165 struct si_power_info *si_pi = si_get_pi(rdev);
6166 u32 tmp;
6167 u32 duty, duty100;
6168 u64 tmp64;
6169
6170 if (rdev->pm.no_fan)
6171 return -ENOENT;
6172
6173 if (si_pi->fan_is_controlled_by_smc)
6174 return -EINVAL;
6175
6176 if (speed > 100)
6177 return -EINVAL;
6178
6179 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6180
6181 if (duty100 == 0)
6182 return -EINVAL;
6183
6184 tmp64 = (u64)speed * duty100;
6185 do_div(tmp64, 100);
6186 duty = (u32)tmp64;
6187
6188 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6189 tmp |= FDO_STATIC_DUTY(duty);
6190 WREG32(CG_FDO_CTRL0, tmp);
6191
6192 return 0;
6193 }
6194
6195 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6196 {
6197 if (mode) {
6198 /* stop auto-manage */
6199 if (rdev->pm.dpm.fan.ucode_fan_control)
6200 si_fan_ctrl_stop_smc_fan_control(rdev);
6201 si_fan_ctrl_set_static_mode(rdev, mode);
6202 } else {
6203 /* restart auto-manage */
6204 if (rdev->pm.dpm.fan.ucode_fan_control)
6205 si_thermal_start_smc_fan_control(rdev);
6206 else
6207 si_fan_ctrl_set_default_mode(rdev);
6208 }
6209 }
6210
6211 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6212 {
6213 struct si_power_info *si_pi = si_get_pi(rdev);
6214 u32 tmp;
6215
6216 if (si_pi->fan_is_controlled_by_smc)
6217 return 0;
6218
6219 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6220 return (tmp >> FDO_PWM_MODE_SHIFT);
6221 }
6222
6223 #if 0
6224 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6225 u32 *speed)
6226 {
6227 u32 tach_period;
6228 u32 xclk = radeon_get_xclk(rdev);
6229
6230 if (rdev->pm.no_fan)
6231 return -ENOENT;
6232
6233 if (rdev->pm.fan_pulses_per_revolution == 0)
6234 return -ENOENT;
6235
6236 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6237 if (tach_period == 0)
6238 return -ENOENT;
6239
6240 *speed = 60 * xclk * 10000 / tach_period;
6241
6242 return 0;
6243 }
6244
6245 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6246 u32 speed)
6247 {
6248 u32 tach_period, tmp;
6249 u32 xclk = radeon_get_xclk(rdev);
6250
6251 if (rdev->pm.no_fan)
6252 return -ENOENT;
6253
6254 if (rdev->pm.fan_pulses_per_revolution == 0)
6255 return -ENOENT;
6256
6257 if ((speed < rdev->pm.fan_min_rpm) ||
6258 (speed > rdev->pm.fan_max_rpm))
6259 return -EINVAL;
6260
6261 if (rdev->pm.dpm.fan.ucode_fan_control)
6262 si_fan_ctrl_stop_smc_fan_control(rdev);
6263
6264 tach_period = 60 * xclk * 10000 / (8 * speed);
6265 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6266 tmp |= TARGET_PERIOD(tach_period);
6267 WREG32(CG_TACH_CTRL, tmp);
6268
6269 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6270
6271 return 0;
6272 }
6273 #endif
6274
6275 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6276 {
6277 struct si_power_info *si_pi = si_get_pi(rdev);
6278 u32 tmp;
6279
6280 if (!si_pi->fan_ctrl_is_in_default_mode) {
6281 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6282 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6283 WREG32(CG_FDO_CTRL2, tmp);
6284
6285 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6286 tmp |= TMIN(si_pi->t_min);
6287 WREG32(CG_FDO_CTRL2, tmp);
6288 si_pi->fan_ctrl_is_in_default_mode = true;
6289 }
6290 }
6291
6292 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6293 {
6294 if (rdev->pm.dpm.fan.ucode_fan_control) {
6295 si_fan_ctrl_start_smc_fan_control(rdev);
6296 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6297 }
6298 }
6299
6300 static void si_thermal_initialize(struct radeon_device *rdev)
6301 {
6302 u32 tmp;
6303
6304 if (rdev->pm.fan_pulses_per_revolution) {
6305 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6306 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6307 WREG32(CG_TACH_CTRL, tmp);
6308 }
6309
6310 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6311 tmp |= TACH_PWM_RESP_RATE(0x28);
6312 WREG32(CG_FDO_CTRL2, tmp);
6313 }
6314
6315 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6316 {
6317 int ret;
6318
6319 si_thermal_initialize(rdev);
6320 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6321 if (ret)
6322 return ret;
6323 ret = si_thermal_enable_alert(rdev, true);
6324 if (ret)
6325 return ret;
6326 if (rdev->pm.dpm.fan.ucode_fan_control) {
6327 ret = si_halt_smc(rdev);
6328 if (ret)
6329 return ret;
6330 ret = si_thermal_setup_fan_table(rdev);
6331 if (ret)
6332 return ret;
6333 ret = si_resume_smc(rdev);
6334 if (ret)
6335 return ret;
6336 si_thermal_start_smc_fan_control(rdev);
6337 }
6338
6339 return 0;
6340 }
6341
6342 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6343 {
6344 if (!rdev->pm.no_fan) {
6345 si_fan_ctrl_set_default_mode(rdev);
6346 si_fan_ctrl_stop_smc_fan_control(rdev);
6347 }
6348 }
6349
6350 int si_dpm_enable(struct radeon_device *rdev)
6351 {
6352 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6353 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6354 struct si_power_info *si_pi = si_get_pi(rdev);
6355 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6356 int ret;
6357
6358 if (si_is_smc_running(rdev))
6359 return -EINVAL;
6360 if (pi->voltage_control || si_pi->voltage_control_svi2)
6361 si_enable_voltage_control(rdev, true);
6362 if (pi->mvdd_control)
6363 si_get_mvdd_configuration(rdev);
6364 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6365 ret = si_construct_voltage_tables(rdev);
6366 if (ret) {
6367 DRM_ERROR("si_construct_voltage_tables failed\n");
6368 return ret;
6369 }
6370 }
6371 if (eg_pi->dynamic_ac_timing) {
6372 ret = si_initialize_mc_reg_table(rdev);
6373 if (ret)
6374 eg_pi->dynamic_ac_timing = false;
6375 }
6376 if (pi->dynamic_ss)
6377 si_enable_spread_spectrum(rdev, true);
6378 if (pi->thermal_protection)
6379 si_enable_thermal_protection(rdev, true);
6380 si_setup_bsp(rdev);
6381 si_program_git(rdev);
6382 si_program_tp(rdev);
6383 si_program_tpp(rdev);
6384 si_program_sstp(rdev);
6385 si_enable_display_gap(rdev);
6386 si_program_vc(rdev);
6387 ret = si_upload_firmware(rdev);
6388 if (ret) {
6389 DRM_ERROR("si_upload_firmware failed\n");
6390 return ret;
6391 }
6392 ret = si_process_firmware_header(rdev);
6393 if (ret) {
6394 DRM_ERROR("si_process_firmware_header failed\n");
6395 return ret;
6396 }
6397 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6398 if (ret) {
6399 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6400 return ret;
6401 }
6402 ret = si_init_smc_table(rdev);
6403 if (ret) {
6404 DRM_ERROR("si_init_smc_table failed\n");
6405 return ret;
6406 }
6407 ret = si_init_smc_spll_table(rdev);
6408 if (ret) {
6409 DRM_ERROR("si_init_smc_spll_table failed\n");
6410 return ret;
6411 }
6412 ret = si_init_arb_table_index(rdev);
6413 if (ret) {
6414 DRM_ERROR("si_init_arb_table_index failed\n");
6415 return ret;
6416 }
6417 if (eg_pi->dynamic_ac_timing) {
6418 ret = si_populate_mc_reg_table(rdev, boot_ps);
6419 if (ret) {
6420 DRM_ERROR("si_populate_mc_reg_table failed\n");
6421 return ret;
6422 }
6423 }
6424 ret = si_initialize_smc_cac_tables(rdev);
6425 if (ret) {
6426 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6427 return ret;
6428 }
6429 ret = si_initialize_hardware_cac_manager(rdev);
6430 if (ret) {
6431 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6432 return ret;
6433 }
6434 ret = si_initialize_smc_dte_tables(rdev);
6435 if (ret) {
6436 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6437 return ret;
6438 }
6439 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6440 if (ret) {
6441 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6442 return ret;
6443 }
6444 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6445 if (ret) {
6446 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6447 return ret;
6448 }
6449 si_program_response_times(rdev);
6450 si_program_ds_registers(rdev);
6451 si_dpm_start_smc(rdev);
6452 ret = si_notify_smc_display_change(rdev, false);
6453 if (ret) {
6454 DRM_ERROR("si_notify_smc_display_change failed\n");
6455 return ret;
6456 }
6457 si_enable_sclk_control(rdev, true);
6458 si_start_dpm(rdev);
6459
6460 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6461
6462 si_thermal_start_thermal_controller(rdev);
6463
6464 ni_update_current_ps(rdev, boot_ps);
6465
6466 return 0;
6467 }
6468
6469 static int si_set_temperature_range(struct radeon_device *rdev)
6470 {
6471 int ret;
6472
6473 ret = si_thermal_enable_alert(rdev, false);
6474 if (ret)
6475 return ret;
6476 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6477 if (ret)
6478 return ret;
6479 ret = si_thermal_enable_alert(rdev, true);
6480 if (ret)
6481 return ret;
6482
6483 return ret;
6484 }
6485
6486 int si_dpm_late_enable(struct radeon_device *rdev)
6487 {
6488 int ret;
6489
6490 ret = si_set_temperature_range(rdev);
6491 if (ret)
6492 return ret;
6493
6494 return ret;
6495 }
6496
6497 void si_dpm_disable(struct radeon_device *rdev)
6498 {
6499 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6500 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6501
6502 if (!si_is_smc_running(rdev))
6503 return;
6504 si_thermal_stop_thermal_controller(rdev);
6505 si_disable_ulv(rdev);
6506 si_clear_vc(rdev);
6507 if (pi->thermal_protection)
6508 si_enable_thermal_protection(rdev, false);
6509 si_enable_power_containment(rdev, boot_ps, false);
6510 si_enable_smc_cac(rdev, boot_ps, false);
6511 si_enable_spread_spectrum(rdev, false);
6512 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6513 si_stop_dpm(rdev);
6514 si_reset_to_default(rdev);
6515 si_dpm_stop_smc(rdev);
6516 si_force_switch_to_arb_f0(rdev);
6517
6518 ni_update_current_ps(rdev, boot_ps);
6519 }
6520
6521 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6522 {
6523 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6524 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6525 struct radeon_ps *new_ps = &requested_ps;
6526
6527 ni_update_requested_ps(rdev, new_ps);
6528
6529 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6530
6531 return 0;
6532 }
6533
6534 static int si_power_control_set_level(struct radeon_device *rdev)
6535 {
6536 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6537 int ret;
6538
6539 ret = si_restrict_performance_levels_before_switch(rdev);
6540 if (ret)
6541 return ret;
6542 ret = si_halt_smc(rdev);
6543 if (ret)
6544 return ret;
6545 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6546 if (ret)
6547 return ret;
6548 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6549 if (ret)
6550 return ret;
6551 ret = si_resume_smc(rdev);
6552 if (ret)
6553 return ret;
6554 ret = si_set_sw_state(rdev);
6555 if (ret)
6556 return ret;
6557 return 0;
6558 }
6559
6560 int si_dpm_set_power_state(struct radeon_device *rdev)
6561 {
6562 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6563 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6564 struct radeon_ps *old_ps = &eg_pi->current_rps;
6565 int ret;
6566
6567 ret = si_disable_ulv(rdev);
6568 if (ret) {
6569 DRM_ERROR("si_disable_ulv failed\n");
6570 return ret;
6571 }
6572 ret = si_restrict_performance_levels_before_switch(rdev);
6573 if (ret) {
6574 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6575 return ret;
6576 }
6577 if (eg_pi->pcie_performance_request)
6578 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6579 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6580 ret = si_enable_power_containment(rdev, new_ps, false);
6581 if (ret) {
6582 DRM_ERROR("si_enable_power_containment failed\n");
6583 return ret;
6584 }
6585 ret = si_enable_smc_cac(rdev, new_ps, false);
6586 if (ret) {
6587 DRM_ERROR("si_enable_smc_cac failed\n");
6588 return ret;
6589 }
6590 ret = si_halt_smc(rdev);
6591 if (ret) {
6592 DRM_ERROR("si_halt_smc failed\n");
6593 return ret;
6594 }
6595 ret = si_upload_sw_state(rdev, new_ps);
6596 if (ret) {
6597 DRM_ERROR("si_upload_sw_state failed\n");
6598 return ret;
6599 }
6600 ret = si_upload_smc_data(rdev);
6601 if (ret) {
6602 DRM_ERROR("si_upload_smc_data failed\n");
6603 return ret;
6604 }
6605 ret = si_upload_ulv_state(rdev);
6606 if (ret) {
6607 DRM_ERROR("si_upload_ulv_state failed\n");
6608 return ret;
6609 }
6610 if (eg_pi->dynamic_ac_timing) {
6611 ret = si_upload_mc_reg_table(rdev, new_ps);
6612 if (ret) {
6613 DRM_ERROR("si_upload_mc_reg_table failed\n");
6614 return ret;
6615 }
6616 }
6617 ret = si_program_memory_timing_parameters(rdev, new_ps);
6618 if (ret) {
6619 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6620 return ret;
6621 }
6622 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6623
6624 ret = si_resume_smc(rdev);
6625 if (ret) {
6626 DRM_ERROR("si_resume_smc failed\n");
6627 return ret;
6628 }
6629 ret = si_set_sw_state(rdev);
6630 if (ret) {
6631 DRM_ERROR("si_set_sw_state failed\n");
6632 return ret;
6633 }
6634 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6635 si_set_vce_clock(rdev, new_ps, old_ps);
6636 if (eg_pi->pcie_performance_request)
6637 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6638 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6639 if (ret) {
6640 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6641 return ret;
6642 }
6643 ret = si_enable_smc_cac(rdev, new_ps, true);
6644 if (ret) {
6645 DRM_ERROR("si_enable_smc_cac failed\n");
6646 return ret;
6647 }
6648 ret = si_enable_power_containment(rdev, new_ps, true);
6649 if (ret) {
6650 DRM_ERROR("si_enable_power_containment failed\n");
6651 return ret;
6652 }
6653
6654 ret = si_power_control_set_level(rdev);
6655 if (ret) {
6656 DRM_ERROR("si_power_control_set_level failed\n");
6657 return ret;
6658 }
6659
6660 return 0;
6661 }
6662
6663 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6664 {
6665 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6666 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6667
6668 ni_update_current_ps(rdev, new_ps);
6669 }
6670
6671 #if 0
6672 void si_dpm_reset_asic(struct radeon_device *rdev)
6673 {
6674 si_restrict_performance_levels_before_switch(rdev);
6675 si_disable_ulv(rdev);
6676 si_set_boot_state(rdev);
6677 }
6678 #endif
6679
6680 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6681 {
6682 si_program_display_gap(rdev);
6683 }
6684
6685 union power_info {
6686 struct _ATOM_POWERPLAY_INFO info;
6687 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6688 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6689 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6690 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6691 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6692 };
6693
6694 union pplib_clock_info {
6695 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6696 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6697 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6698 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6699 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6700 };
6701
6702 union pplib_power_state {
6703 struct _ATOM_PPLIB_STATE v1;
6704 struct _ATOM_PPLIB_STATE_V2 v2;
6705 };
6706
6707 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6708 struct radeon_ps *rps,
6709 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6710 u8 table_rev)
6711 {
6712 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6713 rps->class = le16_to_cpu(non_clock_info->usClassification);
6714 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6715
6716 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6717 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6718 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6719 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6720 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6721 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6722 } else {
6723 rps->vclk = 0;
6724 rps->dclk = 0;
6725 }
6726
6727 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6728 rdev->pm.dpm.boot_ps = rps;
6729 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6730 rdev->pm.dpm.uvd_ps = rps;
6731 }
6732
6733 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6734 struct radeon_ps *rps, int index,
6735 union pplib_clock_info *clock_info)
6736 {
6737 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6738 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6739 struct si_power_info *si_pi = si_get_pi(rdev);
6740 struct ni_ps *ps = ni_get_ps(rps);
6741 u16 leakage_voltage;
6742 struct rv7xx_pl *pl = &ps->performance_levels[index];
6743 int ret;
6744
6745 ps->performance_level_count = index + 1;
6746
6747 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6748 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6749 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6750 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6751
6752 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6753 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6754 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6755 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6756 si_pi->sys_pcie_mask,
6757 si_pi->boot_pcie_gen,
6758 clock_info->si.ucPCIEGen);
6759
6760 /* patch up vddc if necessary */
6761 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6762 &leakage_voltage);
6763 if (ret == 0)
6764 pl->vddc = leakage_voltage;
6765
6766 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6767 pi->acpi_vddc = pl->vddc;
6768 eg_pi->acpi_vddci = pl->vddci;
6769 si_pi->acpi_pcie_gen = pl->pcie_gen;
6770 }
6771
6772 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6773 index == 0) {
6774 /* XXX disable for A0 tahiti */
6775 si_pi->ulv.supported = false;
6776 si_pi->ulv.pl = *pl;
6777 si_pi->ulv.one_pcie_lane_in_ulv = false;
6778 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6779 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6780 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6781 }
6782
6783 if (pi->min_vddc_in_table > pl->vddc)
6784 pi->min_vddc_in_table = pl->vddc;
6785
6786 if (pi->max_vddc_in_table < pl->vddc)
6787 pi->max_vddc_in_table = pl->vddc;
6788
6789 /* patch up boot state */
6790 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6791 u16 vddc, vddci, mvdd;
6792 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6793 pl->mclk = rdev->clock.default_mclk;
6794 pl->sclk = rdev->clock.default_sclk;
6795 pl->vddc = vddc;
6796 pl->vddci = vddci;
6797 si_pi->mvdd_bootup_value = mvdd;
6798 }
6799
6800 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6801 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6802 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6804 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6805 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6806 }
6807 }
6808
6809 static int si_parse_power_table(struct radeon_device *rdev)
6810 {
6811 struct radeon_mode_info *mode_info = &rdev->mode_info;
6812 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6813 union pplib_power_state *power_state;
6814 int i, j, k, non_clock_array_index, clock_array_index;
6815 union pplib_clock_info *clock_info;
6816 struct _StateArray *state_array;
6817 struct _ClockInfoArray *clock_info_array;
6818 struct _NonClockInfoArray *non_clock_info_array;
6819 union power_info *power_info;
6820 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6821 u16 data_offset;
6822 u8 frev, crev;
6823 u8 *power_state_offset;
6824 struct ni_ps *ps;
6825
6826 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6827 &frev, &crev, &data_offset))
6828 return -EINVAL;
6829 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6830
6831 state_array = (struct _StateArray *)
6832 (mode_info->atom_context->bios + data_offset +
6833 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6834 clock_info_array = (struct _ClockInfoArray *)
6835 (mode_info->atom_context->bios + data_offset +
6836 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6837 non_clock_info_array = (struct _NonClockInfoArray *)
6838 (mode_info->atom_context->bios + data_offset +
6839 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6840
6841 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6842 state_array->ucNumEntries, GFP_KERNEL);
6843 if (!rdev->pm.dpm.ps)
6844 return -ENOMEM;
6845 power_state_offset = (u8 *)state_array->states;
6846 for (i = 0; i < state_array->ucNumEntries; i++) {
6847 u8 *idx;
6848 power_state = (union pplib_power_state *)power_state_offset;
6849 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6850 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6851 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6852 if (!rdev->pm.power_state[i].clock_info)
6853 return -EINVAL;
6854 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6855 if (ps == NULL) {
6856 kfree(rdev->pm.dpm.ps);
6857 return -ENOMEM;
6858 }
6859 rdev->pm.dpm.ps[i].ps_priv = ps;
6860 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6861 non_clock_info,
6862 non_clock_info_array->ucEntrySize);
6863 k = 0;
6864 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6865 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6866 clock_array_index = idx[j];
6867 if (clock_array_index >= clock_info_array->ucNumEntries)
6868 continue;
6869 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6870 break;
6871 clock_info = (union pplib_clock_info *)
6872 ((u8 *)&clock_info_array->clockInfo[0] +
6873 (clock_array_index * clock_info_array->ucEntrySize));
6874 si_parse_pplib_clock_info(rdev,
6875 &rdev->pm.dpm.ps[i], k,
6876 clock_info);
6877 k++;
6878 }
6879 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6880 }
6881 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6882
6883 /* fill in the vce power states */
6884 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6885 u32 sclk, mclk;
6886 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6887 clock_info = (union pplib_clock_info *)
6888 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6889 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6890 sclk |= clock_info->si.ucEngineClockHigh << 16;
6891 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6892 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6893 rdev->pm.dpm.vce_states[i].sclk = sclk;
6894 rdev->pm.dpm.vce_states[i].mclk = mclk;
6895 }
6896
6897 return 0;
6898 }
6899
6900 int si_dpm_init(struct radeon_device *rdev)
6901 {
6902 struct rv7xx_power_info *pi;
6903 struct evergreen_power_info *eg_pi;
6904 struct ni_power_info *ni_pi;
6905 struct si_power_info *si_pi;
6906 struct atom_clock_dividers dividers;
6907 int ret;
6908 u32 mask;
6909
6910 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6911 if (si_pi == NULL)
6912 return -ENOMEM;
6913 rdev->pm.dpm.priv = si_pi;
6914 ni_pi = &si_pi->ni;
6915 eg_pi = &ni_pi->eg;
6916 pi = &eg_pi->rv7xx;
6917
6918 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6919 if (ret)
6920 si_pi->sys_pcie_mask = 0;
6921 else
6922 si_pi->sys_pcie_mask = mask;
6923 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6924 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6925
6926 si_set_max_cu_value(rdev);
6927
6928 rv770_get_max_vddc(rdev);
6929 si_get_leakage_vddc(rdev);
6930 si_patch_dependency_tables_based_on_leakage(rdev);
6931
6932 pi->acpi_vddc = 0;
6933 eg_pi->acpi_vddci = 0;
6934 pi->min_vddc_in_table = 0;
6935 pi->max_vddc_in_table = 0;
6936
6937 ret = r600_get_platform_caps(rdev);
6938 if (ret)
6939 return ret;
6940
6941 ret = r600_parse_extended_power_table(rdev);
6942 if (ret)
6943 return ret;
6944
6945 ret = si_parse_power_table(rdev);
6946 if (ret)
6947 return ret;
6948
6949 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6950 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6951 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6952 r600_free_extended_power_table(rdev);
6953 return -ENOMEM;
6954 }
6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6957 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6959 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6960 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6961 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6962 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6963 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6964
6965 if (rdev->pm.dpm.voltage_response_time == 0)
6966 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6967 if (rdev->pm.dpm.backbias_response_time == 0)
6968 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6969
6970 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6971 0, false, &dividers);
6972 if (ret)
6973 pi->ref_div = dividers.ref_div + 1;
6974 else
6975 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6976
6977 eg_pi->smu_uvd_hs = false;
6978
6979 pi->mclk_strobe_mode_threshold = 40000;
6980 if (si_is_special_1gb_platform(rdev))
6981 pi->mclk_stutter_mode_threshold = 0;
6982 else
6983 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6984 pi->mclk_edc_enable_threshold = 40000;
6985 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6986
6987 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6988
6989 pi->voltage_control =
6990 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6991 VOLTAGE_OBJ_GPIO_LUT);
6992 if (!pi->voltage_control) {
6993 si_pi->voltage_control_svi2 =
6994 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6995 VOLTAGE_OBJ_SVID2);
6996 if (si_pi->voltage_control_svi2)
6997 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6998 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6999 }
7000
7001 pi->mvdd_control =
7002 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7003 VOLTAGE_OBJ_GPIO_LUT);
7004
7005 eg_pi->vddci_control =
7006 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7007 VOLTAGE_OBJ_GPIO_LUT);
7008 if (!eg_pi->vddci_control)
7009 si_pi->vddci_control_svi2 =
7010 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7011 VOLTAGE_OBJ_SVID2);
7012
7013 si_pi->vddc_phase_shed_control =
7014 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7015 VOLTAGE_OBJ_PHASE_LUT);
7016
7017 rv770_get_engine_memory_ss(rdev);
7018
7019 pi->asi = RV770_ASI_DFLT;
7020 pi->pasi = CYPRESS_HASI_DFLT;
7021 pi->vrc = SISLANDS_VRC_DFLT;
7022
7023 pi->gfx_clock_gating = true;
7024
7025 eg_pi->sclk_deep_sleep = true;
7026 si_pi->sclk_deep_sleep_above_low = false;
7027
7028 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7029 pi->thermal_protection = true;
7030 else
7031 pi->thermal_protection = false;
7032
7033 eg_pi->dynamic_ac_timing = true;
7034
7035 eg_pi->light_sleep = true;
7036 #if defined(CONFIG_ACPI)
7037 eg_pi->pcie_performance_request =
7038 radeon_acpi_is_pcie_performance_request_supported(rdev);
7039 #else
7040 eg_pi->pcie_performance_request = false;
7041 #endif
7042
7043 si_pi->sram_end = SMC_RAM_END;
7044
7045 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7046 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7047 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7048 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7049 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7050 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7051 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7052
7053 si_initialize_powertune_defaults(rdev);
7054
7055 /* make sure dc limits are valid */
7056 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7057 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7058 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7059 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7060
7061 si_pi->fan_ctrl_is_in_default_mode = true;
7062
7063 return 0;
7064 }
7065
7066 void si_dpm_fini(struct radeon_device *rdev)
7067 {
7068 int i;
7069
7070 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7071 kfree(rdev->pm.dpm.ps[i].ps_priv);
7072 }
7073 kfree(rdev->pm.dpm.ps);
7074 kfree(rdev->pm.dpm.priv);
7075 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7076 r600_free_extended_power_table(rdev);
7077 }
7078
7079 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7080 struct seq_file *m)
7081 {
7082 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7083 struct radeon_ps *rps = &eg_pi->current_rps;
7084 struct ni_ps *ps = ni_get_ps(rps);
7085 struct rv7xx_pl *pl;
7086 u32 current_index =
7087 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7088 CURRENT_STATE_INDEX_SHIFT;
7089
7090 if (current_index >= ps->performance_level_count) {
7091 seq_printf(m, "invalid dpm profile %d\n", current_index);
7092 } else {
7093 pl = &ps->performance_levels[current_index];
7094 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7095 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7096 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7097 }
7098 }
7099
7100 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7101 {
7102 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7103 struct radeon_ps *rps = &eg_pi->current_rps;
7104 struct ni_ps *ps = ni_get_ps(rps);
7105 struct rv7xx_pl *pl;
7106 u32 current_index =
7107 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7108 CURRENT_STATE_INDEX_SHIFT;
7109
7110 if (current_index >= ps->performance_level_count) {
7111 return 0;
7112 } else {
7113 pl = &ps->performance_levels[current_index];
7114 return pl->sclk;
7115 }
7116 }
7117
7118 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7119 {
7120 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7121 struct radeon_ps *rps = &eg_pi->current_rps;
7122 struct ni_ps *ps = ni_get_ps(rps);
7123 struct rv7xx_pl *pl;
7124 u32 current_index =
7125 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7126 CURRENT_STATE_INDEX_SHIFT;
7127
7128 if (current_index >= ps->performance_level_count) {
7129 return 0;
7130 } else {
7131 pl = &ps->performance_levels[current_index];
7132 return pl->mclk;
7133 }
7134 }
Linux with added FPC-III support