Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / rcar-du / rcar_du_crtc.c
blob65d6ba6621aca5b1883ac8a4a57a93a92e0ca913
1 /*
2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/mutex.h>
17 #include <drm/drmP.h>
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_crtc_helper.h>
22 #include <drm/drm_fb_cma_helper.h>
23 #include <drm/drm_gem_cma_helper.h>
24 #include <drm/drm_plane_helper.h>
26 #include "rcar_du_crtc.h"
27 #include "rcar_du_drv.h"
28 #include "rcar_du_kms.h"
29 #include "rcar_du_plane.h"
30 #include "rcar_du_regs.h"
32 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
34 struct rcar_du_device *rcdu = rcrtc->group->dev;
36 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
39 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
41 struct rcar_du_device *rcdu = rcrtc->group->dev;
43 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
46 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
48 struct rcar_du_device *rcdu = rcrtc->group->dev;
50 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
51 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
54 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
56 struct rcar_du_device *rcdu = rcrtc->group->dev;
58 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
59 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
62 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
63 u32 clr, u32 set)
65 struct rcar_du_device *rcdu = rcrtc->group->dev;
66 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
68 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
71 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
73 int ret;
75 ret = clk_prepare_enable(rcrtc->clock);
76 if (ret < 0)
77 return ret;
79 ret = clk_prepare_enable(rcrtc->extclock);
80 if (ret < 0)
81 goto error_clock;
83 ret = rcar_du_group_get(rcrtc->group);
84 if (ret < 0)
85 goto error_group;
87 return 0;
89 error_group:
90 clk_disable_unprepare(rcrtc->extclock);
91 error_clock:
92 clk_disable_unprepare(rcrtc->clock);
93 return ret;
96 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
98 rcar_du_group_put(rcrtc->group);
100 clk_disable_unprepare(rcrtc->extclock);
101 clk_disable_unprepare(rcrtc->clock);
104 /* -----------------------------------------------------------------------------
105 * Hardware Setup
108 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
110 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
111 unsigned long mode_clock = mode->clock * 1000;
112 unsigned long clk;
113 u32 value;
114 u32 escr;
115 u32 div;
117 /* Compute the clock divisor and select the internal or external dot
118 * clock based on the requested frequency.
120 clk = clk_get_rate(rcrtc->clock);
121 div = DIV_ROUND_CLOSEST(clk, mode_clock);
122 div = clamp(div, 1U, 64U) - 1;
123 escr = div | ESCR_DCLKSEL_CLKS;
125 if (rcrtc->extclock) {
126 unsigned long extclk;
127 unsigned long extrate;
128 unsigned long rate;
129 u32 extdiv;
131 extclk = clk_get_rate(rcrtc->extclock);
132 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
133 extdiv = clamp(extdiv, 1U, 64U) - 1;
135 rate = clk / (div + 1);
136 extrate = extclk / (extdiv + 1);
138 if (abs((long)extrate - (long)mode_clock) <
139 abs((long)rate - (long)mode_clock)) {
140 dev_dbg(rcrtc->group->dev->dev,
141 "crtc%u: using external clock\n", rcrtc->index);
142 escr = extdiv | ESCR_DCLKSEL_DCLKIN;
146 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
147 escr);
148 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
150 /* Signal polarities */
151 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
152 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
153 | DSMR_DIPM_DE | DSMR_CSPM;
154 rcar_du_crtc_write(rcrtc, DSMR, value);
156 /* Display timings */
157 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
158 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
159 mode->hdisplay - 19);
160 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
161 mode->hsync_start - 1);
162 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
164 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
165 mode->crtc_vsync_end - 2);
166 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
167 mode->crtc_vsync_end +
168 mode->crtc_vdisplay - 2);
169 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
170 mode->crtc_vsync_end +
171 mode->crtc_vsync_start - 1);
172 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
174 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
175 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
178 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
179 enum rcar_du_output output)
181 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
182 struct rcar_du_device *rcdu = rcrtc->group->dev;
184 /* Store the route from the CRTC output to the DU output. The DU will be
185 * configured when starting the CRTC.
187 rcrtc->outputs |= BIT(output);
189 /* Store RGB routing to DPAD0, the hardware will be configured when
190 * starting the CRTC.
192 if (output == RCAR_DU_OUTPUT_DPAD0)
193 rcdu->dpad0_source = rcrtc->index;
196 static unsigned int plane_zpos(struct rcar_du_plane *plane)
198 return to_rcar_plane_state(plane->plane.state)->zpos;
201 static const struct rcar_du_format_info *
202 plane_format(struct rcar_du_plane *plane)
204 return to_rcar_plane_state(plane->plane.state)->format;
207 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
209 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
210 unsigned int num_planes = 0;
211 unsigned int dptsr_planes;
212 unsigned int hwplanes = 0;
213 unsigned int prio = 0;
214 unsigned int i;
215 u32 dspr = 0;
217 for (i = 0; i < rcrtc->group->num_planes; ++i) {
218 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
219 unsigned int j;
221 if (plane->plane.state->crtc != &rcrtc->crtc)
222 continue;
224 /* Insert the plane in the sorted planes array. */
225 for (j = num_planes++; j > 0; --j) {
226 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
227 break;
228 planes[j] = planes[j-1];
231 planes[j] = plane;
232 prio += plane_format(plane)->planes * 4;
235 for (i = 0; i < num_planes; ++i) {
236 struct rcar_du_plane *plane = planes[i];
237 struct drm_plane_state *state = plane->plane.state;
238 unsigned int index = to_rcar_plane_state(state)->hwindex;
240 prio -= 4;
241 dspr |= (index + 1) << prio;
242 hwplanes |= 1 << index;
244 if (plane_format(plane)->planes == 2) {
245 index = (index + 1) % 8;
247 prio -= 4;
248 dspr |= (index + 1) << prio;
249 hwplanes |= 1 << index;
253 /* Update the planes to display timing and dot clock generator
254 * associations.
256 * Updating the DPTSR register requires restarting the CRTC group,
257 * resulting in visible flicker. To mitigate the issue only update the
258 * association if needed by enabled planes. Planes being disabled will
259 * keep their current association.
261 mutex_lock(&rcrtc->group->lock);
263 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
264 : rcrtc->group->dptsr_planes & ~hwplanes;
266 if (dptsr_planes != rcrtc->group->dptsr_planes) {
267 rcar_du_group_write(rcrtc->group, DPTSR,
268 (dptsr_planes << 16) | dptsr_planes);
269 rcrtc->group->dptsr_planes = dptsr_planes;
271 if (rcrtc->group->used_crtcs)
272 rcar_du_group_restart(rcrtc->group);
275 mutex_unlock(&rcrtc->group->lock);
277 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
278 dspr);
281 /* -----------------------------------------------------------------------------
282 * Page Flip
285 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
286 struct drm_file *file)
288 struct drm_pending_vblank_event *event;
289 struct drm_device *dev = rcrtc->crtc.dev;
290 unsigned long flags;
292 /* Destroy the pending vertical blanking event associated with the
293 * pending page flip, if any, and disable vertical blanking interrupts.
295 spin_lock_irqsave(&dev->event_lock, flags);
296 event = rcrtc->event;
297 if (event && event->base.file_priv == file) {
298 rcrtc->event = NULL;
299 event->base.destroy(&event->base);
300 drm_crtc_vblank_put(&rcrtc->crtc);
302 spin_unlock_irqrestore(&dev->event_lock, flags);
305 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
307 struct drm_pending_vblank_event *event;
308 struct drm_device *dev = rcrtc->crtc.dev;
309 unsigned long flags;
311 spin_lock_irqsave(&dev->event_lock, flags);
312 event = rcrtc->event;
313 rcrtc->event = NULL;
314 spin_unlock_irqrestore(&dev->event_lock, flags);
316 if (event == NULL)
317 return;
319 spin_lock_irqsave(&dev->event_lock, flags);
320 drm_send_vblank_event(dev, rcrtc->index, event);
321 wake_up(&rcrtc->flip_wait);
322 spin_unlock_irqrestore(&dev->event_lock, flags);
324 drm_crtc_vblank_put(&rcrtc->crtc);
327 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
329 struct drm_device *dev = rcrtc->crtc.dev;
330 unsigned long flags;
331 bool pending;
333 spin_lock_irqsave(&dev->event_lock, flags);
334 pending = rcrtc->event != NULL;
335 spin_unlock_irqrestore(&dev->event_lock, flags);
337 return pending;
340 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
342 struct rcar_du_device *rcdu = rcrtc->group->dev;
344 if (wait_event_timeout(rcrtc->flip_wait,
345 !rcar_du_crtc_page_flip_pending(rcrtc),
346 msecs_to_jiffies(50)))
347 return;
349 dev_warn(rcdu->dev, "page flip timeout\n");
351 rcar_du_crtc_finish_page_flip(rcrtc);
354 /* -----------------------------------------------------------------------------
355 * Start/Stop and Suspend/Resume
358 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
360 struct drm_crtc *crtc = &rcrtc->crtc;
361 bool interlaced;
363 if (rcrtc->started)
364 return;
366 /* Set display off and background to black */
367 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
368 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
370 /* Configure display timings and output routing */
371 rcar_du_crtc_set_display_timing(rcrtc);
372 rcar_du_group_set_routing(rcrtc->group);
374 /* Start with all planes disabled. */
375 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
377 /* Select master sync mode. This enables display operation in master
378 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
379 * actively driven).
381 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
382 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
383 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
384 DSYSR_TVM_MASTER);
386 rcar_du_group_start_stop(rcrtc->group, true);
388 /* Turn vertical blanking interrupt reporting back on. */
389 drm_crtc_vblank_on(crtc);
391 rcrtc->started = true;
394 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
396 struct drm_crtc *crtc = &rcrtc->crtc;
398 if (!rcrtc->started)
399 return;
401 /* Disable all planes and wait for the change to take effect. This is
402 * required as the DSnPR registers are updated on vblank, and no vblank
403 * will occur once the CRTC is stopped. Disabling planes when starting
404 * the CRTC thus wouldn't be enough as it would start scanning out
405 * immediately from old frame buffers until the next vblank.
407 * This increases the CRTC stop delay, especially when multiple CRTCs
408 * are stopped in one operation as we now wait for one vblank per CRTC.
409 * Whether this can be improved needs to be researched.
411 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
412 drm_crtc_wait_one_vblank(crtc);
414 /* Disable vertical blanking interrupt reporting. We first need to wait
415 * for page flip completion before stopping the CRTC as userspace
416 * expects page flips to eventually complete.
418 rcar_du_crtc_wait_page_flip(rcrtc);
419 drm_crtc_vblank_off(crtc);
421 /* Select switch sync mode. This stops display operation and configures
422 * the HSYNC and VSYNC signals as inputs.
424 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
426 rcar_du_group_start_stop(rcrtc->group, false);
428 rcrtc->started = false;
431 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
433 rcar_du_crtc_stop(rcrtc);
434 rcar_du_crtc_put(rcrtc);
437 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
439 unsigned int i;
441 if (!rcrtc->enabled)
442 return;
444 rcar_du_crtc_get(rcrtc);
445 rcar_du_crtc_start(rcrtc);
447 /* Commit the planes state. */
448 for (i = 0; i < rcrtc->group->num_planes; ++i) {
449 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
451 if (plane->plane.state->crtc != &rcrtc->crtc)
452 continue;
454 rcar_du_plane_setup(plane);
457 rcar_du_crtc_update_planes(rcrtc);
460 /* -----------------------------------------------------------------------------
461 * CRTC Functions
464 static void rcar_du_crtc_enable(struct drm_crtc *crtc)
466 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
468 if (rcrtc->enabled)
469 return;
471 rcar_du_crtc_get(rcrtc);
472 rcar_du_crtc_start(rcrtc);
474 rcrtc->enabled = true;
477 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
479 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
481 if (!rcrtc->enabled)
482 return;
484 rcar_du_crtc_stop(rcrtc);
485 rcar_du_crtc_put(rcrtc);
487 rcrtc->enabled = false;
488 rcrtc->outputs = 0;
491 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
492 const struct drm_display_mode *mode,
493 struct drm_display_mode *adjusted_mode)
495 /* TODO Fixup modes */
496 return true;
499 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
501 struct drm_pending_vblank_event *event = crtc->state->event;
502 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
503 struct drm_device *dev = rcrtc->crtc.dev;
504 unsigned long flags;
506 if (event) {
507 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
509 spin_lock_irqsave(&dev->event_lock, flags);
510 rcrtc->event = event;
511 spin_unlock_irqrestore(&dev->event_lock, flags);
515 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
517 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
519 rcar_du_crtc_update_planes(rcrtc);
522 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
523 .mode_fixup = rcar_du_crtc_mode_fixup,
524 .disable = rcar_du_crtc_disable,
525 .enable = rcar_du_crtc_enable,
526 .atomic_begin = rcar_du_crtc_atomic_begin,
527 .atomic_flush = rcar_du_crtc_atomic_flush,
530 static const struct drm_crtc_funcs crtc_funcs = {
531 .reset = drm_atomic_helper_crtc_reset,
532 .destroy = drm_crtc_cleanup,
533 .set_config = drm_atomic_helper_set_config,
534 .page_flip = drm_atomic_helper_page_flip,
535 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
536 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
539 /* -----------------------------------------------------------------------------
540 * Interrupt Handling
543 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
545 struct rcar_du_crtc *rcrtc = arg;
546 irqreturn_t ret = IRQ_NONE;
547 u32 status;
549 status = rcar_du_crtc_read(rcrtc, DSSR);
550 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
552 if (status & DSSR_FRM) {
553 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
554 rcar_du_crtc_finish_page_flip(rcrtc);
555 ret = IRQ_HANDLED;
558 return ret;
561 /* -----------------------------------------------------------------------------
562 * Initialization
565 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
567 static const unsigned int mmio_offsets[] = {
568 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
571 struct rcar_du_device *rcdu = rgrp->dev;
572 struct platform_device *pdev = to_platform_device(rcdu->dev);
573 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
574 struct drm_crtc *crtc = &rcrtc->crtc;
575 unsigned int irqflags;
576 struct clk *clk;
577 char clk_name[9];
578 char *name;
579 int irq;
580 int ret;
582 /* Get the CRTC clock and the optional external clock. */
583 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
584 sprintf(clk_name, "du.%u", index);
585 name = clk_name;
586 } else {
587 name = NULL;
590 rcrtc->clock = devm_clk_get(rcdu->dev, name);
591 if (IS_ERR(rcrtc->clock)) {
592 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
593 return PTR_ERR(rcrtc->clock);
596 sprintf(clk_name, "dclkin.%u", index);
597 clk = devm_clk_get(rcdu->dev, clk_name);
598 if (!IS_ERR(clk)) {
599 rcrtc->extclock = clk;
600 } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
601 dev_info(rcdu->dev, "can't get external clock %u\n", index);
602 return -EPROBE_DEFER;
605 init_waitqueue_head(&rcrtc->flip_wait);
607 rcrtc->group = rgrp;
608 rcrtc->mmio_offset = mmio_offsets[index];
609 rcrtc->index = index;
610 rcrtc->enabled = false;
612 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc,
613 &rgrp->planes[index % 2].plane,
614 NULL, &crtc_funcs);
615 if (ret < 0)
616 return ret;
618 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
620 /* Start with vertical blanking interrupt reporting disabled. */
621 drm_crtc_vblank_off(crtc);
623 /* Register the interrupt handler. */
624 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
625 irq = platform_get_irq(pdev, index);
626 irqflags = 0;
627 } else {
628 irq = platform_get_irq(pdev, 0);
629 irqflags = IRQF_SHARED;
632 if (irq < 0) {
633 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
634 return irq;
637 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
638 dev_name(rcdu->dev), rcrtc);
639 if (ret < 0) {
640 dev_err(rcdu->dev,
641 "failed to register IRQ for CRTC %u\n", index);
642 return ret;
645 return 0;
648 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
650 if (enable) {
651 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
652 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
653 } else {
654 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);