drivers/gpu/drm/tegra/dpaux.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/gpio.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/reset.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/workqueue.h>
  19
  20 #include <drm/drm_dp_helper.h>
  21 #include <drm/drm_panel.h>
  22
  23 #include "dpaux.h"
  24 #include "drm.h"
  25
  26 static DEFINE_MUTEX(dpaux_lock);
  27 static LIST_HEAD(dpaux_list);
  28
  29 struct tegra_dpaux {
  30         struct drm_dp_aux aux;
  31         struct device *dev;
  32
  33         void __iomem *regs;
  34         int irq;
  35
  36         struct tegra_output *output;
  37
  38         struct reset_control *rst;
  39         struct clk *clk_parent;
  40         struct clk *clk;
  41
  42         struct regulator *vdd;
  43
  44         struct completion complete;
  45         struct work_struct work;
  46         struct list_head list;
  47 };
  48
  49 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
  50 {
  51         return container_of(aux, struct tegra_dpaux, aux);
  52 }
  53
  54 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
  55 {
  56         return container_of(work, struct tegra_dpaux, work);
  57 }
  58
  59 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
  60                                     unsigned long offset)
  61 {
  62         return readl(dpaux->regs + (offset << 2));
  63 }
  64
  65 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
  66                                       u32 value, unsigned long offset)
  67 {
  68         writel(value, dpaux->regs + (offset << 2));
  69 }
  70
  71 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
  72                                    size_t size)
  73 {
  74         size_t i, j;
  75
  76         for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
  77                 size_t num = min_t(size_t, size - i * 4, 4);
  78                 u32 value = 0;
  79
  80                 for (j = 0; j < num; j++)
  81                         value |= buffer[i * 4 + j] << (j * 8);
  82
  83                 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
  84         }
  85 }
  86
  87 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
  88                                   size_t size)
  89 {
  90         size_t i, j;
  91
  92         for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
  93                 size_t num = min_t(size_t, size - i * 4, 4);
  94                 u32 value;
  95
  96                 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
  97
  98                 for (j = 0; j < num; j++)
  99                         buffer[i * 4 + j] = value >> (j * 8);
 100         }
 101 }
 102
 103 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
 104                                     struct drm_dp_aux_msg *msg)
 105 {
 106         unsigned long timeout = msecs_to_jiffies(250);
 107         struct tegra_dpaux *dpaux = to_dpaux(aux);
 108         unsigned long status;
 109         ssize_t ret = 0;
 110         u32 value;
 111
 112         /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
 113         if (msg->size > 16)
 114                 return -EINVAL;
 115
 116         /*
 117          * Allow zero-sized messages only for I2C, in which case they specify
 118          * address-only transactions.
 119          */
 120         if (msg->size < 1) {
 121                 switch (msg->request & ~DP_AUX_I2C_MOT) {
 122                 case DP_AUX_I2C_WRITE:
 123                 case DP_AUX_I2C_READ:
 124                         value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
 125                         break;
 126
 127                 default:
 128                         return -EINVAL;
 129                 }
 130         } else {
 131                 /* For non-zero-sized messages, set the CMDLEN field. */
 132                 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
 133         }
 134
 135         switch (msg->request & ~DP_AUX_I2C_MOT) {
 136         case DP_AUX_I2C_WRITE:
 137                 if (msg->request & DP_AUX_I2C_MOT)
 138                         value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
 139                 else
 140                         value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
 141
 142                 break;
 143
 144         case DP_AUX_I2C_READ:
 145                 if (msg->request & DP_AUX_I2C_MOT)
 146                         value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
 147                 else
 148                         value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
 149
 150                 break;
 151
 152         case DP_AUX_I2C_STATUS:
 153                 if (msg->request & DP_AUX_I2C_MOT)
 154                         value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
 155                 else
 156                         value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
 157
 158                 break;
 159
 160         case DP_AUX_NATIVE_WRITE:
 161                 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
 162                 break;
 163
 164         case DP_AUX_NATIVE_READ:
 165                 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
 166                 break;
 167
 168         default:
 169                 return -EINVAL;
 170         }
 171
 172         tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
 173         tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
 174
 175         if ((msg->request & DP_AUX_I2C_READ) == 0) {
 176                 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
 177                 ret = msg->size;
 178         }
 179
 180         /* start transaction */
 181         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
 182         value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
 183         tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
 184
 185         status = wait_for_completion_timeout(&dpaux->complete, timeout);
 186         if (!status)
 187                 return -ETIMEDOUT;
 188
 189         /* read status and clear errors */
 190         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
 191         tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
 192
 193         if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
 194                 return -ETIMEDOUT;
 195
 196         if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
 197             (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
 198             (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
 199                 return -EIO;
 200
 201         switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
 202         case 0x00:
 203                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
 204                 break;
 205
 206         case 0x01:
 207                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
 208                 break;
 209
 210         case 0x02:
 211                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
 212                 break;
 213
 214         case 0x04:
 215                 msg->reply = DP_AUX_I2C_REPLY_NACK;
 216                 break;
 217
 218         case 0x08:
 219                 msg->reply = DP_AUX_I2C_REPLY_DEFER;
 220                 break;
 221         }
 222
 223         if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
 224                 if (msg->request & DP_AUX_I2C_READ) {
 225                         size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
 226
 227                         if (WARN_ON(count != msg->size))
 228                                 count = min_t(size_t, count, msg->size);
 229
 230                         tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
 231                         ret = count;
 232                 }
 233         }
 234
 235         return ret;
 236 }
 237
 238 static void tegra_dpaux_hotplug(struct work_struct *work)
 239 {
 240         struct tegra_dpaux *dpaux = work_to_dpaux(work);
 241
 242         if (dpaux->output)
 243                 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
 244 }
 245
 246 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
 247 {
 248         struct tegra_dpaux *dpaux = data;
 249         irqreturn_t ret = IRQ_HANDLED;
 250         u32 value;
 251
 252         /* clear interrupts */
 253         value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
 254         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
 255
 256         if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
 257                 schedule_work(&dpaux->work);
 258
 259         if (value & DPAUX_INTR_IRQ_EVENT) {
 260                 /* TODO: handle this */
 261         }
 262
 263         if (value & DPAUX_INTR_AUX_DONE)
 264                 complete(&dpaux->complete);
 265
 266         return ret;
 267 }
 268
 269 static int tegra_dpaux_probe(struct platform_device *pdev)
 270 {
 271         struct tegra_dpaux *dpaux;
 272         struct resource *regs;
 273         u32 value;
 274         int err;
 275
 276         dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
 277         if (!dpaux)
 278                 return -ENOMEM;
 279
 280         INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
 281         init_completion(&dpaux->complete);
 282         INIT_LIST_HEAD(&dpaux->list);
 283         dpaux->dev = &pdev->dev;
 284
 285         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 286         dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
 287         if (IS_ERR(dpaux->regs))
 288                 return PTR_ERR(dpaux->regs);
 289
 290         dpaux->irq = platform_get_irq(pdev, 0);
 291         if (dpaux->irq < 0) {
 292                 dev_err(&pdev->dev, "failed to get IRQ\n");
 293                 return -ENXIO;
 294         }
 295
 296         dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
 297         if (IS_ERR(dpaux->rst))
 298                 return PTR_ERR(dpaux->rst);
 299
 300         dpaux->clk = devm_clk_get(&pdev->dev, NULL);
 301         if (IS_ERR(dpaux->clk))
 302                 return PTR_ERR(dpaux->clk);
 303
 304         err = clk_prepare_enable(dpaux->clk);
 305         if (err < 0)
 306                 return err;
 307
 308         reset_control_deassert(dpaux->rst);
 309
 310         dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
 311         if (IS_ERR(dpaux->clk_parent))
 312                 return PTR_ERR(dpaux->clk_parent);
 313
 314         err = clk_prepare_enable(dpaux->clk_parent);
 315         if (err < 0)
 316                 return err;
 317
 318         err = clk_set_rate(dpaux->clk_parent, 270000000);
 319         if (err < 0) {
 320                 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
 321                         err);
 322                 return err;
 323         }
 324
 325         dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
 326         if (IS_ERR(dpaux->vdd))
 327                 return PTR_ERR(dpaux->vdd);
 328
 329         err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
 330                                dev_name(dpaux->dev), dpaux);
 331         if (err < 0) {
 332                 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
 333                         dpaux->irq, err);
 334                 return err;
 335         }
 336
 337         dpaux->aux.transfer = tegra_dpaux_transfer;
 338         dpaux->aux.dev = &pdev->dev;
 339
 340         err = drm_dp_aux_register(&dpaux->aux);
 341         if (err < 0)
 342                 return err;
 343
 344         /* enable and clear all interrupts */
 345         value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
 346                 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
 347         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
 348         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
 349
 350         mutex_lock(&dpaux_lock);
 351         list_add_tail(&dpaux->list, &dpaux_list);
 352         mutex_unlock(&dpaux_lock);
 353
 354         platform_set_drvdata(pdev, dpaux);
 355
 356         return 0;
 357 }
 358
 359 static int tegra_dpaux_remove(struct platform_device *pdev)
 360 {
 361         struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
 362
 363         drm_dp_aux_unregister(&dpaux->aux);
 364
 365         mutex_lock(&dpaux_lock);
 366         list_del(&dpaux->list);
 367         mutex_unlock(&dpaux_lock);
 368
 369         cancel_work_sync(&dpaux->work);
 370
 371         clk_disable_unprepare(dpaux->clk_parent);
 372         reset_control_assert(dpaux->rst);
 373         clk_disable_unprepare(dpaux->clk);
 374
 375         return 0;
 376 }
 377
 378 static const struct of_device_id tegra_dpaux_of_match[] = {
 379         { .compatible = "nvidia,tegra124-dpaux", },
 380         { },
 381 };
 382 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
 383
 384 struct platform_driver tegra_dpaux_driver = {
 385         .driver = {
 386                 .name = "tegra-dpaux",
 387                 .of_match_table = tegra_dpaux_of_match,
 388         },
 389         .probe = tegra_dpaux_probe,
 390         .remove = tegra_dpaux_remove,
 391 };
 392
 393 struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
 394 {
 395         struct tegra_dpaux *dpaux;
 396
 397         mutex_lock(&dpaux_lock);
 398
 399         list_for_each_entry(dpaux, &dpaux_list, list)
 400                 if (np == dpaux->dev->of_node) {
 401                         mutex_unlock(&dpaux_lock);
 402                         return dpaux;
 403                 }
 404
 405         mutex_unlock(&dpaux_lock);
 406
 407         return NULL;
 408 }
 409
 410 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
 411 {
 412         unsigned long timeout;
 413         int err;
 414
 415         output->connector.polled = DRM_CONNECTOR_POLL_HPD;
 416         dpaux->output = output;
 417
 418         err = regulator_enable(dpaux->vdd);
 419         if (err < 0)
 420                 return err;
 421
 422         timeout = jiffies + msecs_to_jiffies(250);
 423
 424         while (time_before(jiffies, timeout)) {
 425                 enum drm_connector_status status;
 426
 427                 status = tegra_dpaux_detect(dpaux);
 428                 if (status == connector_status_connected)
 429                         return 0;
 430
 431                 usleep_range(1000, 2000);
 432         }
 433
 434         return -ETIMEDOUT;
 435 }
 436
 437 int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
 438 {
 439         unsigned long timeout;
 440         int err;
 441
 442         err = regulator_disable(dpaux->vdd);
 443         if (err < 0)
 444                 return err;
 445
 446         timeout = jiffies + msecs_to_jiffies(250);
 447
 448         while (time_before(jiffies, timeout)) {
 449                 enum drm_connector_status status;
 450
 451                 status = tegra_dpaux_detect(dpaux);
 452                 if (status == connector_status_disconnected) {
 453                         dpaux->output = NULL;
 454                         return 0;
 455                 }
 456
 457                 usleep_range(1000, 2000);
 458         }
 459
 460         return -ETIMEDOUT;
 461 }
 462
 463 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
 464 {
 465         u32 value;
 466
 467         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
 468
 469         if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
 470                 return connector_status_connected;
 471
 472         return connector_status_disconnected;
 473 }
 474
 475 int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
 476 {
 477         u32 value;
 478
 479         value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
 480                 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
 481                 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
 482                 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
 483                 DPAUX_HYBRID_PADCTL_MODE_AUX;
 484         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
 485
 486         value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
 487         value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
 488         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
 489
 490         return 0;
 491 }
 492
 493 int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
 494 {
 495         u32 value;
 496
 497         value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
 498         value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
 499         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
 500
 501         return 0;
 502 }
 503
 504 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
 505 {
 506         int err;
 507
 508         err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 509                                  encoding);
 510         if (err < 0)
 511                 return err;
 512
 513         return 0;
 514 }
 515
 516 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
 517                       u8 pattern)
 518 {
 519         u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
 520         u8 status[DP_LINK_STATUS_SIZE], values[4];
 521         unsigned int i;
 522         int err;
 523
 524         err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
 525         if (err < 0)
 526                 return err;
 527
 528         if (tp == DP_TRAINING_PATTERN_DISABLE)
 529                 return 0;
 530
 531         for (i = 0; i < link->num_lanes; i++)
 532                 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
 533                             DP_TRAIN_PRE_EMPH_LEVEL_0 |
 534                             DP_TRAIN_MAX_SWING_REACHED |
 535                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 536
 537         err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
 538                                 link->num_lanes);
 539         if (err < 0)
 540                 return err;
 541
 542         usleep_range(500, 1000);
 543
 544         err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
 545         if (err < 0)
 546                 return err;
 547
 548         switch (tp) {
 549         case DP_TRAINING_PATTERN_1:
 550                 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
 551                         return -EAGAIN;
 552
 553                 break;
 554
 555         case DP_TRAINING_PATTERN_2:
 556                 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
 557                         return -EAGAIN;
 558
 559                 break;
 560
 561         default:
 562                 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
 563                 return -EINVAL;
 564         }
 565
 566         err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);
 567         if (err < 0)
 568                 return err;
 569
 570         return 0;
 571 }