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Linux 4.2.1
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / dsi.c
blobed970f62290306e5c78158f9600211d51251dc78
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17
18 #include <linux/regulator/consumer.h>
19
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_panel.h>
23
24 #include <video/mipi_display.h>
25
26 #include "dc.h"
27 #include "drm.h"
28 #include "dsi.h"
29 #include "mipi-phy.h"
30
31 struct tegra_dsi_state {
32 struct drm_connector_state base;
33
34 struct mipi_dphy_timing timing;
35 unsigned long period;
36
37 unsigned int vrefresh;
38 unsigned int lanes;
39 unsigned long pclk;
40 unsigned long bclk;
41
42 enum tegra_dsi_format format;
43 unsigned int mul;
44 unsigned int div;
45 };
46
47 static inline struct tegra_dsi_state *
48 to_dsi_state(struct drm_connector_state *state)
49 {
50 return container_of(state, struct tegra_dsi_state, base);
51 }
52
53 struct tegra_dsi {
54 struct host1x_client client;
55 struct tegra_output output;
56 struct device *dev;
57
58 void __iomem *regs;
59
60 struct reset_control *rst;
61 struct clk *clk_parent;
62 struct clk *clk_lp;
63 struct clk *clk;
64
65 struct drm_info_list *debugfs_files;
66 struct drm_minor *minor;
67 struct dentry *debugfs;
68
69 unsigned long flags;
70 enum mipi_dsi_pixel_format format;
71 unsigned int lanes;
72
73 struct tegra_mipi_device *mipi;
74 struct mipi_dsi_host host;
75
76 struct regulator *vdd;
77
78 unsigned int video_fifo_depth;
79 unsigned int host_fifo_depth;
80
81 /* for ganged-mode support */
82 struct tegra_dsi *master;
83 struct tegra_dsi *slave;
84 };
85
86 static inline struct tegra_dsi *
87 host1x_client_to_dsi(struct host1x_client *client)
88 {
89 return container_of(client, struct tegra_dsi, client);
90 }
91
92 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
93 {
94 return container_of(host, struct tegra_dsi, host);
95 }
96
97 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
98 {
99 return container_of(output, struct tegra_dsi, output);
100 }
101
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
103 {
104 return to_dsi_state(dsi->output.connector.state);
105 }
106
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
108 {
109 return readl(dsi->regs + (reg << 2));
110 }
111
112 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
113 unsigned long reg)
114 {
115 writel(value, dsi->regs + (reg << 2));
116 }
117
118 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
119 {
120 struct drm_info_node *node = s->private;
121 struct tegra_dsi *dsi = node->info_ent->data;
122
123 #define DUMP_REG(name) \
124 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
125 tegra_dsi_readl(dsi, name))
126
127 DUMP_REG(DSI_INCR_SYNCPT);
128 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
129 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
130 DUMP_REG(DSI_CTXSW);
131 DUMP_REG(DSI_RD_DATA);
132 DUMP_REG(DSI_WR_DATA);
133 DUMP_REG(DSI_POWER_CONTROL);
134 DUMP_REG(DSI_INT_ENABLE);
135 DUMP_REG(DSI_INT_STATUS);
136 DUMP_REG(DSI_INT_MASK);
137 DUMP_REG(DSI_HOST_CONTROL);
138 DUMP_REG(DSI_CONTROL);
139 DUMP_REG(DSI_SOL_DELAY);
140 DUMP_REG(DSI_MAX_THRESHOLD);
141 DUMP_REG(DSI_TRIGGER);
142 DUMP_REG(DSI_TX_CRC);
143 DUMP_REG(DSI_STATUS);
144
145 DUMP_REG(DSI_INIT_SEQ_CONTROL);
146 DUMP_REG(DSI_INIT_SEQ_DATA_0);
147 DUMP_REG(DSI_INIT_SEQ_DATA_1);
148 DUMP_REG(DSI_INIT_SEQ_DATA_2);
149 DUMP_REG(DSI_INIT_SEQ_DATA_3);
150 DUMP_REG(DSI_INIT_SEQ_DATA_4);
151 DUMP_REG(DSI_INIT_SEQ_DATA_5);
152 DUMP_REG(DSI_INIT_SEQ_DATA_6);
153 DUMP_REG(DSI_INIT_SEQ_DATA_7);
154
155 DUMP_REG(DSI_PKT_SEQ_0_LO);
156 DUMP_REG(DSI_PKT_SEQ_0_HI);
157 DUMP_REG(DSI_PKT_SEQ_1_LO);
158 DUMP_REG(DSI_PKT_SEQ_1_HI);
159 DUMP_REG(DSI_PKT_SEQ_2_LO);
160 DUMP_REG(DSI_PKT_SEQ_2_HI);
161 DUMP_REG(DSI_PKT_SEQ_3_LO);
162 DUMP_REG(DSI_PKT_SEQ_3_HI);
163 DUMP_REG(DSI_PKT_SEQ_4_LO);
164 DUMP_REG(DSI_PKT_SEQ_4_HI);
165 DUMP_REG(DSI_PKT_SEQ_5_LO);
166 DUMP_REG(DSI_PKT_SEQ_5_HI);
167
168 DUMP_REG(DSI_DCS_CMDS);
169
170 DUMP_REG(DSI_PKT_LEN_0_1);
171 DUMP_REG(DSI_PKT_LEN_2_3);
172 DUMP_REG(DSI_PKT_LEN_4_5);
173 DUMP_REG(DSI_PKT_LEN_6_7);
174
175 DUMP_REG(DSI_PHY_TIMING_0);
176 DUMP_REG(DSI_PHY_TIMING_1);
177 DUMP_REG(DSI_PHY_TIMING_2);
178 DUMP_REG(DSI_BTA_TIMING);
179
180 DUMP_REG(DSI_TIMEOUT_0);
181 DUMP_REG(DSI_TIMEOUT_1);
182 DUMP_REG(DSI_TO_TALLY);
183
184 DUMP_REG(DSI_PAD_CONTROL_0);
185 DUMP_REG(DSI_PAD_CONTROL_CD);
186 DUMP_REG(DSI_PAD_CD_STATUS);
187 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
188 DUMP_REG(DSI_PAD_CONTROL_1);
189 DUMP_REG(DSI_PAD_CONTROL_2);
190 DUMP_REG(DSI_PAD_CONTROL_3);
191 DUMP_REG(DSI_PAD_CONTROL_4);
192
193 DUMP_REG(DSI_GANGED_MODE_CONTROL);
194 DUMP_REG(DSI_GANGED_MODE_START);
195 DUMP_REG(DSI_GANGED_MODE_SIZE);
196
197 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
198 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
199
200 DUMP_REG(DSI_INIT_SEQ_DATA_8);
201 DUMP_REG(DSI_INIT_SEQ_DATA_9);
202 DUMP_REG(DSI_INIT_SEQ_DATA_10);
203 DUMP_REG(DSI_INIT_SEQ_DATA_11);
204 DUMP_REG(DSI_INIT_SEQ_DATA_12);
205 DUMP_REG(DSI_INIT_SEQ_DATA_13);
206 DUMP_REG(DSI_INIT_SEQ_DATA_14);
207 DUMP_REG(DSI_INIT_SEQ_DATA_15);
208
209 #undef DUMP_REG
210
211 return 0;
212 }
213
214 static struct drm_info_list debugfs_files[] = {
215 { "regs", tegra_dsi_show_regs, 0, NULL },
216 };
217
218 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
219 struct drm_minor *minor)
220 {
221 const char *name = dev_name(dsi->dev);
222 unsigned int i;
223 int err;
224
225 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
226 if (!dsi->debugfs)
227 return -ENOMEM;
228
229 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
230 GFP_KERNEL);
231 if (!dsi->debugfs_files) {
232 err = -ENOMEM;
233 goto remove;
234 }
235
236 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
237 dsi->debugfs_files[i].data = dsi;
238
239 err = drm_debugfs_create_files(dsi->debugfs_files,
240 ARRAY_SIZE(debugfs_files),
241 dsi->debugfs, minor);
242 if (err < 0)
243 goto free;
244
245 dsi->minor = minor;
246
247 return 0;
248
249 free:
250 kfree(dsi->debugfs_files);
251 dsi->debugfs_files = NULL;
252 remove:
253 debugfs_remove(dsi->debugfs);
254 dsi->debugfs = NULL;
255
256 return err;
257 }
258
259 static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
260 {
261 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
262 dsi->minor);
263 dsi->minor = NULL;
264
265 kfree(dsi->debugfs_files);
266 dsi->debugfs_files = NULL;
267
268 debugfs_remove(dsi->debugfs);
269 dsi->debugfs = NULL;
270 }
271
272 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
273 #define PKT_LEN0(len) (((len) & 0x07) << 0)
274 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
275 #define PKT_LEN1(len) (((len) & 0x07) << 10)
276 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
277 #define PKT_LEN2(len) (((len) & 0x07) << 20)
278
279 #define PKT_LP (1 << 30)
280 #define NUM_PKT_SEQ 12
281
282 /*
283 * non-burst mode with sync pulses
284 */
285 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
286 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
287 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
288 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
289 PKT_LP,
290 [ 1] = 0,
291 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
292 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
293 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
294 PKT_LP,
295 [ 3] = 0,
296 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
297 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
298 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
299 PKT_LP,
300 [ 5] = 0,
301 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
304 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
305 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
306 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
307 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
309 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
310 PKT_LP,
311 [ 9] = 0,
312 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
313 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
314 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
315 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
316 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
317 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
318 };
319
320 /*
321 * non-burst mode with sync events
322 */
323 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
324 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
325 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
326 PKT_LP,
327 [ 1] = 0,
328 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
329 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
330 PKT_LP,
331 [ 3] = 0,
332 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
333 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
334 PKT_LP,
335 [ 5] = 0,
336 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
337 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
338 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
339 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
340 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
341 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
342 PKT_LP,
343 [ 9] = 0,
344 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
345 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
346 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
347 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
348 };
349
350 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
351 [ 0] = 0,
352 [ 1] = 0,
353 [ 2] = 0,
354 [ 3] = 0,
355 [ 4] = 0,
356 [ 5] = 0,
357 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
358 [ 7] = 0,
359 [ 8] = 0,
360 [ 9] = 0,
361 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
362 [11] = 0,
363 };
364
365 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
366 unsigned long period,
367 const struct mipi_dphy_timing *timing)
368 {
369 u32 value;
370
371 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
372 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
373 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
374 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
376
377 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
378 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
379 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
380 DSI_TIMING_FIELD(timing->lpx, period, 1);
381 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
382
383 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
384 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
385 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
386 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
387
388 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
389 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
390 DSI_TIMING_FIELD(timing->tago, period, 1);
391 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
392
393 if (dsi->slave)
394 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
395 }
396
397 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
398 unsigned int *mulp, unsigned int *divp)
399 {
400 switch (format) {
401 case MIPI_DSI_FMT_RGB666_PACKED:
402 case MIPI_DSI_FMT_RGB888:
403 *mulp = 3;
404 *divp = 1;
405 break;
406
407 case MIPI_DSI_FMT_RGB565:
408 *mulp = 2;
409 *divp = 1;
410 break;
411
412 case MIPI_DSI_FMT_RGB666:
413 *mulp = 9;
414 *divp = 4;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 return 0;
422 }
423
424 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
425 enum tegra_dsi_format *fmt)
426 {
427 switch (format) {
428 case MIPI_DSI_FMT_RGB888:
429 *fmt = TEGRA_DSI_FORMAT_24P;
430 break;
431
432 case MIPI_DSI_FMT_RGB666:
433 *fmt = TEGRA_DSI_FORMAT_18NP;
434 break;
435
436 case MIPI_DSI_FMT_RGB666_PACKED:
437 *fmt = TEGRA_DSI_FORMAT_18P;
438 break;
439
440 case MIPI_DSI_FMT_RGB565:
441 *fmt = TEGRA_DSI_FORMAT_16P;
442 break;
443
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449 }
450
451 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
452 unsigned int size)
453 {
454 u32 value;
455
456 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
457 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
458
459 value = DSI_GANGED_MODE_CONTROL_ENABLE;
460 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
461 }
462
463 static void tegra_dsi_enable(struct tegra_dsi *dsi)
464 {
465 u32 value;
466
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value |= DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470
471 if (dsi->slave)
472 tegra_dsi_enable(dsi->slave);
473 }
474
475 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
476 {
477 if (dsi->master)
478 return dsi->master->lanes + dsi->lanes;
479
480 if (dsi->slave)
481 return dsi->lanes + dsi->slave->lanes;
482
483 return dsi->lanes;
484 }
485
486 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
487 const struct drm_display_mode *mode)
488 {
489 unsigned int hact, hsw, hbp, hfp, i, mul, div;
490 struct tegra_dsi_state *state;
491 const u32 *pkt_seq;
492 u32 value;
493
494 /* XXX: pass in state into this function? */
495 if (dsi->master)
496 state = tegra_dsi_get_state(dsi->master);
497 else
498 state = tegra_dsi_get_state(dsi);
499
500 mul = state->mul;
501 div = state->div;
502
503 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
504 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
505 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
506 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
507 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
508 pkt_seq = pkt_seq_video_non_burst_sync_events;
509 } else {
510 DRM_DEBUG_KMS("Command mode\n");
511 pkt_seq = pkt_seq_command_mode;
512 }
513
514 value = DSI_CONTROL_CHANNEL(0) |
515 DSI_CONTROL_FORMAT(state->format) |
516 DSI_CONTROL_LANES(dsi->lanes - 1) |
517 DSI_CONTROL_SOURCE(pipe);
518 tegra_dsi_writel(dsi, value, DSI_CONTROL);
519
520 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
521
522 value = DSI_HOST_CONTROL_HS;
523 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
524
525 value = tegra_dsi_readl(dsi, DSI_CONTROL);
526
527 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
528 value |= DSI_CONTROL_HS_CLK_CTRL;
529
530 value &= ~DSI_CONTROL_TX_TRIG(3);
531
532 /* enable DCS commands for command mode */
533 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
534 value &= ~DSI_CONTROL_DCS_ENABLE;
535 else
536 value |= DSI_CONTROL_DCS_ENABLE;
537
538 value |= DSI_CONTROL_VIDEO_ENABLE;
539 value &= ~DSI_CONTROL_HOST_ENABLE;
540 tegra_dsi_writel(dsi, value, DSI_CONTROL);
541
542 for (i = 0; i < NUM_PKT_SEQ; i++)
543 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
544
545 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
546 /* horizontal active pixels */
547 hact = mode->hdisplay * mul / div;
548
549 /* horizontal sync width */
550 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
551 hsw -= 10;
552
553 /* horizontal back porch */
554 hbp = (mode->htotal - mode->hsync_end) * mul / div;
555 hbp -= 14;
556
557 /* horizontal front porch */
558 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
559 hfp -= 8;
560
561 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
562 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
563 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
564 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
565
566 /* set SOL delay (for non-burst mode only) */
567 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
568
569 /* TODO: implement ganged mode */
570 } else {
571 u16 bytes;
572
573 if (dsi->master || dsi->slave) {
574 /*
575 * For ganged mode, assume symmetric left-right mode.
576 */
577 bytes = 1 + (mode->hdisplay / 2) * mul / div;
578 } else {
579 /* 1 byte (DCS command) + pixel data */
580 bytes = 1 + mode->hdisplay * mul / div;
581 }
582
583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
584 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
585 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
586 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
587
588 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
589 MIPI_DCS_WRITE_MEMORY_CONTINUE;
590 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
591
592 /* set SOL delay */
593 if (dsi->master || dsi->slave) {
594 unsigned long delay, bclk, bclk_ganged;
595 unsigned int lanes = state->lanes;
596
597 /* SOL to valid, valid to FIFO and FIFO write delay */
598 delay = 4 + 4 + 2;
599 delay = DIV_ROUND_UP(delay * mul, div * lanes);
600 /* FIFO read delay */
601 delay = delay + 6;
602
603 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
604 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
605 value = bclk - bclk_ganged + delay + 20;
606 } else {
607 /* TODO: revisit for non-ganged mode */
608 value = 8 * mul / div;
609 }
610
611 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
612 }
613
614 if (dsi->slave) {
615 tegra_dsi_configure(dsi->slave, pipe, mode);
616
617 /*
618 * TODO: Support modes other than symmetrical left-right
619 * split.
620 */
621 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
622 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
623 mode->hdisplay / 2);
624 }
625 }
626
627 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
628 {
629 u32 value;
630
631 timeout = jiffies + msecs_to_jiffies(timeout);
632
633 while (time_before(jiffies, timeout)) {
634 value = tegra_dsi_readl(dsi, DSI_STATUS);
635 if (value & DSI_STATUS_IDLE)
636 return 0;
637
638 usleep_range(1000, 2000);
639 }
640
641 return -ETIMEDOUT;
642 }
643
644 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
645 {
646 u32 value;
647
648 value = tegra_dsi_readl(dsi, DSI_CONTROL);
649 value &= ~DSI_CONTROL_VIDEO_ENABLE;
650 tegra_dsi_writel(dsi, value, DSI_CONTROL);
651
652 if (dsi->slave)
653 tegra_dsi_video_disable(dsi->slave);
654 }
655
656 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
657 {
658 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
660 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
661 }
662
663 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
664 unsigned int vrefresh)
665 {
666 unsigned int timeout;
667 u32 value;
668
669 /* one frame high-speed transmission timeout */
670 timeout = (bclk / vrefresh) / 512;
671 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
672 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
673
674 /* 2 ms peripheral timeout for panel */
675 timeout = 2 * bclk / 512 * 1000;
676 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
677 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
678
679 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
680 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
681
682 if (dsi->slave)
683 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
684 }
685
686 static void tegra_dsi_disable(struct tegra_dsi *dsi)
687 {
688 u32 value;
689
690 if (dsi->slave) {
691 tegra_dsi_ganged_disable(dsi->slave);
692 tegra_dsi_ganged_disable(dsi);
693 }
694
695 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
696 value &= ~DSI_POWER_CONTROL_ENABLE;
697 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
698
699 if (dsi->slave)
700 tegra_dsi_disable(dsi->slave);
701
702 usleep_range(5000, 10000);
703 }
704
705 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
706 {
707 u32 value;
708
709 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
710 value &= ~DSI_POWER_CONTROL_ENABLE;
711 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
712
713 usleep_range(300, 1000);
714
715 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
716 value |= DSI_POWER_CONTROL_ENABLE;
717 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
718
719 usleep_range(300, 1000);
720
721 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
722 if (value)
723 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
724
725 if (dsi->slave)
726 tegra_dsi_soft_reset(dsi->slave);
727 }
728
729 static void tegra_dsi_connector_dpms(struct drm_connector *connector, int mode)
730 {
731 }
732
733 static void tegra_dsi_connector_reset(struct drm_connector *connector)
734 {
735 struct tegra_dsi_state *state;
736
737 kfree(connector->state);
738 connector->state = NULL;
739
740 state = kzalloc(sizeof(*state), GFP_KERNEL);
741 if (state)
742 connector->state = &state->base;
743 }
744
745 static struct drm_connector_state *
746 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
747 {
748 struct tegra_dsi_state *state = to_dsi_state(connector->state);
749 struct tegra_dsi_state *copy;
750
751 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
752 if (!copy)
753 return NULL;
754
755 return &copy->base;
756 }
757
758 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
759 .dpms = tegra_dsi_connector_dpms,
760 .reset = tegra_dsi_connector_reset,
761 .detect = tegra_output_connector_detect,
762 .fill_modes = drm_helper_probe_single_connector_modes,
763 .destroy = tegra_output_connector_destroy,
764 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
765 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
766 };
767
768 static enum drm_mode_status
769 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
770 struct drm_display_mode *mode)
771 {
772 return MODE_OK;
773 }
774
775 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
776 .get_modes = tegra_output_connector_get_modes,
777 .mode_valid = tegra_dsi_connector_mode_valid,
778 .best_encoder = tegra_output_connector_best_encoder,
779 };
780
781 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
782 .destroy = tegra_output_encoder_destroy,
783 };
784
785 static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
786 {
787 }
788
789 static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
790 {
791 }
792
793 static void tegra_dsi_encoder_commit(struct drm_encoder *encoder)
794 {
795 }
796
797 static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
798 struct drm_display_mode *mode,
799 struct drm_display_mode *adjusted)
800 {
801 struct tegra_output *output = encoder_to_output(encoder);
802 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
803 struct tegra_dsi *dsi = to_dsi(output);
804 struct tegra_dsi_state *state;
805 u32 value;
806
807 state = tegra_dsi_get_state(dsi);
808
809 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
810
811 /*
812 * The D-PHY timing fields are expressed in byte-clock cycles, so
813 * multiply the period by 8.
814 */
815 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
816
817 if (output->panel)
818 drm_panel_prepare(output->panel);
819
820 tegra_dsi_configure(dsi, dc->pipe, mode);
821
822 /* enable display controller */
823 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
824 value |= DSI_ENABLE;
825 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
826
827 tegra_dc_commit(dc);
828
829 /* enable DSI controller */
830 tegra_dsi_enable(dsi);
831
832 if (output->panel)
833 drm_panel_enable(output->panel);
834
835 return;
836 }
837
838 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
839 {
840 struct tegra_output *output = encoder_to_output(encoder);
841 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
842 struct tegra_dsi *dsi = to_dsi(output);
843 u32 value;
844 int err;
845
846 if (output->panel)
847 drm_panel_disable(output->panel);
848
849 tegra_dsi_video_disable(dsi);
850
851 /*
852 * The following accesses registers of the display controller, so make
853 * sure it's only executed when the output is attached to one.
854 */
855 if (dc) {
856 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
857 value &= ~DSI_ENABLE;
858 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
859
860 tegra_dc_commit(dc);
861 }
862
863 err = tegra_dsi_wait_idle(dsi, 100);
864 if (err < 0)
865 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
866
867 tegra_dsi_soft_reset(dsi);
868
869 if (output->panel)
870 drm_panel_unprepare(output->panel);
871
872 tegra_dsi_disable(dsi);
873
874 return;
875 }
876
877 static int
878 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
879 struct drm_crtc_state *crtc_state,
880 struct drm_connector_state *conn_state)
881 {
882 struct tegra_output *output = encoder_to_output(encoder);
883 struct tegra_dsi_state *state = to_dsi_state(conn_state);
884 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
885 struct tegra_dsi *dsi = to_dsi(output);
886 unsigned int scdiv;
887 unsigned long plld;
888 int err;
889
890 state->pclk = crtc_state->mode.clock * 1000;
891
892 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
893 if (err < 0)
894 return err;
895
896 state->lanes = tegra_dsi_get_lanes(dsi);
897
898 err = tegra_dsi_get_format(dsi->format, &state->format);
899 if (err < 0)
900 return err;
901
902 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
903
904 /* compute byte clock */
905 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
906
907 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
908 state->lanes);
909 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
910 state->vrefresh);
911 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
912
913 /*
914 * Compute bit clock and round up to the next MHz.
915 */
916 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
917 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
918
919 err = mipi_dphy_timing_get_default(&state->timing, state->period);
920 if (err < 0)
921 return err;
922
923 err = mipi_dphy_timing_validate(&state->timing, state->period);
924 if (err < 0) {
925 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
926 return err;
927 }
928
929 /*
930 * We divide the frequency by two here, but we make up for that by
931 * setting the shift clock divider (further below) to half of the
932 * correct value.
933 */
934 plld /= 2;
935
936 /*
937 * Derive pixel clock from bit clock using the shift clock divider.
938 * Note that this is only half of what we would expect, but we need
939 * that to make up for the fact that we divided the bit clock by a
940 * factor of two above.
941 *
942 * It's not clear exactly why this is necessary, but the display is
943 * not working properly otherwise. Perhaps the PLLs cannot generate
944 * frequencies sufficiently high.
945 */
946 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
947
948 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
949 plld, scdiv);
950 if (err < 0) {
951 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
952 return err;
953 }
954
955 return err;
956 }
957
958 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
959 .dpms = tegra_dsi_encoder_dpms,
960 .prepare = tegra_dsi_encoder_prepare,
961 .commit = tegra_dsi_encoder_commit,
962 .mode_set = tegra_dsi_encoder_mode_set,
963 .disable = tegra_dsi_encoder_disable,
964 .atomic_check = tegra_dsi_encoder_atomic_check,
965 };
966
967 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
968 {
969 u32 value;
970
971 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
972 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
973
974 return 0;
975 }
976
977 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
978 {
979 u32 value;
980
981 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
982 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
983 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
984 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
985 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
986
987 /* start calibration */
988 tegra_dsi_pad_enable(dsi);
989
990 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
991 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
992 DSI_PAD_OUT_CLK(0x0);
993 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
994
995 return tegra_mipi_calibrate(dsi->mipi);
996 }
997
998 static int tegra_dsi_init(struct host1x_client *client)
999 {
1000 struct drm_device *drm = dev_get_drvdata(client->parent);
1001 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1002 int err;
1003
1004 reset_control_deassert(dsi->rst);
1005
1006 err = tegra_dsi_pad_calibrate(dsi);
1007 if (err < 0) {
1008 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
1009 goto reset;
1010 }
1011
1012 /* Gangsters must not register their own outputs. */
1013 if (!dsi->master) {
1014 dsi->output.dev = client->dev;
1015
1016 drm_connector_init(drm, &dsi->output.connector,
1017 &tegra_dsi_connector_funcs,
1018 DRM_MODE_CONNECTOR_DSI);
1019 drm_connector_helper_add(&dsi->output.connector,
1020 &tegra_dsi_connector_helper_funcs);
1021 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1022
1023 drm_encoder_init(drm, &dsi->output.encoder,
1024 &tegra_dsi_encoder_funcs,
1025 DRM_MODE_ENCODER_DSI);
1026 drm_encoder_helper_add(&dsi->output.encoder,
1027 &tegra_dsi_encoder_helper_funcs);
1028
1029 drm_mode_connector_attach_encoder(&dsi->output.connector,
1030 &dsi->output.encoder);
1031 drm_connector_register(&dsi->output.connector);
1032
1033 err = tegra_output_init(drm, &dsi->output);
1034 if (err < 0) {
1035 dev_err(client->dev,
1036 "failed to initialize output: %d\n",
1037 err);
1038 goto reset;
1039 }
1040
1041 dsi->output.encoder.possible_crtcs = 0x3;
1042 }
1043
1044 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1045 err = tegra_dsi_debugfs_init(dsi, drm->primary);
1046 if (err < 0)
1047 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1048 }
1049
1050 return 0;
1051
1052 reset:
1053 reset_control_assert(dsi->rst);
1054 return err;
1055 }
1056
1057 static int tegra_dsi_exit(struct host1x_client *client)
1058 {
1059 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1060
1061 tegra_output_exit(&dsi->output);
1062
1063 if (IS_ENABLED(CONFIG_DEBUG_FS))
1064 tegra_dsi_debugfs_exit(dsi);
1065
1066 reset_control_assert(dsi->rst);
1067
1068 return 0;
1069 }
1070
1071 static const struct host1x_client_ops dsi_client_ops = {
1072 .init = tegra_dsi_init,
1073 .exit = tegra_dsi_exit,
1074 };
1075
1076 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1077 {
1078 struct clk *parent;
1079 int err;
1080
1081 parent = clk_get_parent(dsi->clk);
1082 if (!parent)
1083 return -EINVAL;
1084
1085 err = clk_set_parent(parent, dsi->clk_parent);
1086 if (err < 0)
1087 return err;
1088
1089 return 0;
1090 }
1091
1092 static const char * const error_report[16] = {
1093 "SoT Error",
1094 "SoT Sync Error",
1095 "EoT Sync Error",
1096 "Escape Mode Entry Command Error",
1097 "Low-Power Transmit Sync Error",
1098 "Peripheral Timeout Error",
1099 "False Control Error",
1100 "Contention Detected",
1101 "ECC Error, single-bit",
1102 "ECC Error, multi-bit",
1103 "Checksum Error",
1104 "DSI Data Type Not Recognized",
1105 "DSI VC ID Invalid",
1106 "Invalid Transmission Length",
1107 "Reserved",
1108 "DSI Protocol Violation",
1109 };
1110
1111 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1112 const struct mipi_dsi_msg *msg,
1113 size_t count)
1114 {
1115 u8 *rx = msg->rx_buf;
1116 unsigned int i, j, k;
1117 size_t size = 0;
1118 u16 errors;
1119 u32 value;
1120
1121 /* read and parse packet header */
1122 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1123
1124 switch (value & 0x3f) {
1125 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1126 errors = (value >> 8) & 0xffff;
1127 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1128 errors);
1129 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1130 if (errors & BIT(i))
1131 dev_dbg(dsi->dev, " %2u: %s\n", i,
1132 error_report[i]);
1133 break;
1134
1135 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1136 rx[0] = (value >> 8) & 0xff;
1137 size = 1;
1138 break;
1139
1140 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1141 rx[0] = (value >> 8) & 0xff;
1142 rx[1] = (value >> 16) & 0xff;
1143 size = 2;
1144 break;
1145
1146 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1147 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1148 break;
1149
1150 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1151 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1152 break;
1153
1154 default:
1155 dev_err(dsi->dev, "unhandled response type: %02x\n",
1156 value & 0x3f);
1157 return -EPROTO;
1158 }
1159
1160 size = min(size, msg->rx_len);
1161
1162 if (msg->rx_buf && size > 0) {
1163 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1164 u8 *rx = msg->rx_buf + j;
1165
1166 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1167
1168 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1169 rx[j + k] = (value >> (k << 3)) & 0xff;
1170 }
1171 }
1172
1173 return size;
1174 }
1175
1176 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1177 {
1178 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1179
1180 timeout = jiffies + msecs_to_jiffies(timeout);
1181
1182 while (time_before(jiffies, timeout)) {
1183 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1184 if ((value & DSI_TRIGGER_HOST) == 0)
1185 return 0;
1186
1187 usleep_range(1000, 2000);
1188 }
1189
1190 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1191 return -ETIMEDOUT;
1192 }
1193
1194 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1195 unsigned long timeout)
1196 {
1197 timeout = jiffies + msecs_to_jiffies(250);
1198
1199 while (time_before(jiffies, timeout)) {
1200 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1201 u8 count = value & 0x1f;
1202
1203 if (count > 0)
1204 return count;
1205
1206 usleep_range(1000, 2000);
1207 }
1208
1209 DRM_DEBUG_KMS("peripheral returned no data\n");
1210 return -ETIMEDOUT;
1211 }
1212
1213 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1214 const void *buffer, size_t size)
1215 {
1216 const u8 *buf = buffer;
1217 size_t i, j;
1218 u32 value;
1219
1220 for (j = 0; j < size; j += 4) {
1221 value = 0;
1222
1223 for (i = 0; i < 4 && j + i < size; i++)
1224 value |= buf[j + i] << (i << 3);
1225
1226 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1227 }
1228 }
1229
1230 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1231 const struct mipi_dsi_msg *msg)
1232 {
1233 struct tegra_dsi *dsi = host_to_tegra(host);
1234 struct mipi_dsi_packet packet;
1235 const u8 *header;
1236 size_t count;
1237 ssize_t err;
1238 u32 value;
1239
1240 err = mipi_dsi_create_packet(&packet, msg);
1241 if (err < 0)
1242 return err;
1243
1244 header = packet.header;
1245
1246 /* maximum FIFO depth is 1920 words */
1247 if (packet.size > dsi->video_fifo_depth * 4)
1248 return -ENOSPC;
1249
1250 /* reset underflow/overflow flags */
1251 value = tegra_dsi_readl(dsi, DSI_STATUS);
1252 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1253 value = DSI_HOST_CONTROL_FIFO_RESET;
1254 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1255 usleep_range(10, 20);
1256 }
1257
1258 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1259 value |= DSI_POWER_CONTROL_ENABLE;
1260 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1261
1262 usleep_range(5000, 10000);
1263
1264 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1265 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1266
1267 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1268 value |= DSI_HOST_CONTROL_HS;
1269
1270 /*
1271 * The host FIFO has a maximum of 64 words, so larger transmissions
1272 * need to use the video FIFO.
1273 */
1274 if (packet.size > dsi->host_fifo_depth * 4)
1275 value |= DSI_HOST_CONTROL_FIFO_SEL;
1276
1277 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1278
1279 /*
1280 * For reads and messages with explicitly requested ACK, generate a
1281 * BTA sequence after the transmission of the packet.
1282 */
1283 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1284 (msg->rx_buf && msg->rx_len > 0)) {
1285 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1286 value |= DSI_HOST_CONTROL_PKT_BTA;
1287 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1288 }
1289
1290 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1291 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1292
1293 /* write packet header, ECC is generated by hardware */
1294 value = header[2] << 16 | header[1] << 8 | header[0];
1295 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1296
1297 /* write payload (if any) */
1298 if (packet.payload_length > 0)
1299 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1300 packet.payload_length);
1301
1302 err = tegra_dsi_transmit(dsi, 250);
1303 if (err < 0)
1304 return err;
1305
1306 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1307 (msg->rx_buf && msg->rx_len > 0)) {
1308 err = tegra_dsi_wait_for_response(dsi, 250);
1309 if (err < 0)
1310 return err;
1311
1312 count = err;
1313
1314 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1315 switch (value) {
1316 case 0x84:
1317 /*
1318 dev_dbg(dsi->dev, "ACK\n");
1319 */
1320 break;
1321
1322 case 0x87:
1323 /*
1324 dev_dbg(dsi->dev, "ESCAPE\n");
1325 */
1326 break;
1327
1328 default:
1329 dev_err(dsi->dev, "unknown status: %08x\n", value);
1330 break;
1331 }
1332
1333 if (count > 1) {
1334 err = tegra_dsi_read_response(dsi, msg, count);
1335 if (err < 0)
1336 dev_err(dsi->dev,
1337 "failed to parse response: %zd\n",
1338 err);
1339 else {
1340 /*
1341 * For read commands, return the number of
1342 * bytes returned by the peripheral.
1343 */
1344 count = err;
1345 }
1346 }
1347 } else {
1348 /*
1349 * For write commands, we have transmitted the 4-byte header
1350 * plus the variable-length payload.
1351 */
1352 count = 4 + packet.payload_length;
1353 }
1354
1355 return count;
1356 }
1357
1358 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1359 {
1360 struct clk *parent;
1361 int err;
1362
1363 /* make sure both DSI controllers share the same PLL */
1364 parent = clk_get_parent(dsi->slave->clk);
1365 if (!parent)
1366 return -EINVAL;
1367
1368 err = clk_set_parent(parent, dsi->clk_parent);
1369 if (err < 0)
1370 return err;
1371
1372 return 0;
1373 }
1374
1375 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1376 struct mipi_dsi_device *device)
1377 {
1378 struct tegra_dsi *dsi = host_to_tegra(host);
1379
1380 dsi->flags = device->mode_flags;
1381 dsi->format = device->format;
1382 dsi->lanes = device->lanes;
1383
1384 if (dsi->slave) {
1385 int err;
1386
1387 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1388 dev_name(&device->dev));
1389
1390 err = tegra_dsi_ganged_setup(dsi);
1391 if (err < 0) {
1392 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1393 err);
1394 return err;
1395 }
1396 }
1397
1398 /*
1399 * Slaves don't have a panel associated with them, so they provide
1400 * merely the second channel.
1401 */
1402 if (!dsi->master) {
1403 struct tegra_output *output = &dsi->output;
1404
1405 output->panel = of_drm_find_panel(device->dev.of_node);
1406 if (output->panel && output->connector.dev) {
1407 drm_panel_attach(output->panel, &output->connector);
1408 drm_helper_hpd_irq_event(output->connector.dev);
1409 }
1410 }
1411
1412 return 0;
1413 }
1414
1415 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1416 struct mipi_dsi_device *device)
1417 {
1418 struct tegra_dsi *dsi = host_to_tegra(host);
1419 struct tegra_output *output = &dsi->output;
1420
1421 if (output->panel && &device->dev == output->panel->dev) {
1422 output->panel = NULL;
1423
1424 if (output->connector.dev)
1425 drm_helper_hpd_irq_event(output->connector.dev);
1426 }
1427
1428 return 0;
1429 }
1430
1431 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1432 .attach = tegra_dsi_host_attach,
1433 .detach = tegra_dsi_host_detach,
1434 .transfer = tegra_dsi_host_transfer,
1435 };
1436
1437 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1438 {
1439 struct device_node *np;
1440
1441 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1442 if (np) {
1443 struct platform_device *gangster = of_find_device_by_node(np);
1444
1445 dsi->slave = platform_get_drvdata(gangster);
1446 of_node_put(np);
1447
1448 if (!dsi->slave)
1449 return -EPROBE_DEFER;
1450
1451 dsi->slave->master = dsi;
1452 }
1453
1454 return 0;
1455 }
1456
1457 static int tegra_dsi_probe(struct platform_device *pdev)
1458 {
1459 struct tegra_dsi *dsi;
1460 struct resource *regs;
1461 int err;
1462
1463 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1464 if (!dsi)
1465 return -ENOMEM;
1466
1467 dsi->output.dev = dsi->dev = &pdev->dev;
1468 dsi->video_fifo_depth = 1920;
1469 dsi->host_fifo_depth = 64;
1470
1471 err = tegra_dsi_ganged_probe(dsi);
1472 if (err < 0)
1473 return err;
1474
1475 err = tegra_output_probe(&dsi->output);
1476 if (err < 0)
1477 return err;
1478
1479 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1480
1481 /*
1482 * Assume these values by default. When a DSI peripheral driver
1483 * attaches to the DSI host, the parameters will be taken from
1484 * the attached device.
1485 */
1486 dsi->flags = MIPI_DSI_MODE_VIDEO;
1487 dsi->format = MIPI_DSI_FMT_RGB888;
1488 dsi->lanes = 4;
1489
1490 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1491 if (IS_ERR(dsi->rst))
1492 return PTR_ERR(dsi->rst);
1493
1494 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1495 if (IS_ERR(dsi->clk)) {
1496 dev_err(&pdev->dev, "cannot get DSI clock\n");
1497 err = PTR_ERR(dsi->clk);
1498 goto reset;
1499 }
1500
1501 err = clk_prepare_enable(dsi->clk);
1502 if (err < 0) {
1503 dev_err(&pdev->dev, "cannot enable DSI clock\n");
1504 goto reset;
1505 }
1506
1507 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1508 if (IS_ERR(dsi->clk_lp)) {
1509 dev_err(&pdev->dev, "cannot get low-power clock\n");
1510 err = PTR_ERR(dsi->clk_lp);
1511 goto disable_clk;
1512 }
1513
1514 err = clk_prepare_enable(dsi->clk_lp);
1515 if (err < 0) {
1516 dev_err(&pdev->dev, "cannot enable low-power clock\n");
1517 goto disable_clk;
1518 }
1519
1520 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1521 if (IS_ERR(dsi->clk_parent)) {
1522 dev_err(&pdev->dev, "cannot get parent clock\n");
1523 err = PTR_ERR(dsi->clk_parent);
1524 goto disable_clk_lp;
1525 }
1526
1527 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1528 if (IS_ERR(dsi->vdd)) {
1529 dev_err(&pdev->dev, "cannot get VDD supply\n");
1530 err = PTR_ERR(dsi->vdd);
1531 goto disable_clk_lp;
1532 }
1533
1534 err = regulator_enable(dsi->vdd);
1535 if (err < 0) {
1536 dev_err(&pdev->dev, "cannot enable VDD supply\n");
1537 goto disable_clk_lp;
1538 }
1539
1540 err = tegra_dsi_setup_clocks(dsi);
1541 if (err < 0) {
1542 dev_err(&pdev->dev, "cannot setup clocks\n");
1543 goto disable_vdd;
1544 }
1545
1546 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1548 if (IS_ERR(dsi->regs)) {
1549 err = PTR_ERR(dsi->regs);
1550 goto disable_vdd;
1551 }
1552
1553 dsi->mipi = tegra_mipi_request(&pdev->dev);
1554 if (IS_ERR(dsi->mipi)) {
1555 err = PTR_ERR(dsi->mipi);
1556 goto disable_vdd;
1557 }
1558
1559 dsi->host.ops = &tegra_dsi_host_ops;
1560 dsi->host.dev = &pdev->dev;
1561
1562 err = mipi_dsi_host_register(&dsi->host);
1563 if (err < 0) {
1564 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1565 goto mipi_free;
1566 }
1567
1568 INIT_LIST_HEAD(&dsi->client.list);
1569 dsi->client.ops = &dsi_client_ops;
1570 dsi->client.dev = &pdev->dev;
1571
1572 err = host1x_client_register(&dsi->client);
1573 if (err < 0) {
1574 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1575 err);
1576 goto unregister;
1577 }
1578
1579 platform_set_drvdata(pdev, dsi);
1580
1581 return 0;
1582
1583 unregister:
1584 mipi_dsi_host_unregister(&dsi->host);
1585 mipi_free:
1586 tegra_mipi_free(dsi->mipi);
1587 disable_vdd:
1588 regulator_disable(dsi->vdd);
1589 disable_clk_lp:
1590 clk_disable_unprepare(dsi->clk_lp);
1591 disable_clk:
1592 clk_disable_unprepare(dsi->clk);
1593 reset:
1594 reset_control_assert(dsi->rst);
1595 return err;
1596 }
1597
1598 static int tegra_dsi_remove(struct platform_device *pdev)
1599 {
1600 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1601 int err;
1602
1603 err = host1x_client_unregister(&dsi->client);
1604 if (err < 0) {
1605 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1606 err);
1607 return err;
1608 }
1609
1610 tegra_output_remove(&dsi->output);
1611
1612 mipi_dsi_host_unregister(&dsi->host);
1613 tegra_mipi_free(dsi->mipi);
1614
1615 regulator_disable(dsi->vdd);
1616 clk_disable_unprepare(dsi->clk_lp);
1617 clk_disable_unprepare(dsi->clk);
1618 reset_control_assert(dsi->rst);
1619
1620 return 0;
1621 }
1622
1623 static const struct of_device_id tegra_dsi_of_match[] = {
1624 { .compatible = "nvidia,tegra114-dsi", },
1625 { },
1626 };
1627 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1628
1629 struct platform_driver tegra_dsi_driver = {
1630 .driver = {
1631 .name = "tegra-dsi",
1632 .of_match_table = tegra_dsi_of_match,
1633 },
1634 .probe = tegra_dsi_probe,
1635 .remove = tegra_dsi_remove,
1636 };
Linux with added FPC-III support