1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
27 #include <linux/module.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
35 #include <linux/dma_remapping.h>
37 #define VMWGFX_DRIVER_NAME "vmwgfx"
38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39 #define VMWGFX_CHIP_SVGAII 0
40 #define VMW_FB_RESERVATION 0
42 #define VMW_MIN_INITIAL_WIDTH 800
43 #define VMW_MIN_INITIAL_HEIGHT 600
47 * Fully encoded drm commands. Might move to vmw_drm.h
50 #define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56 #define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
63 #define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66 #define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69 #define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79 #define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82 #define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85 #define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88 #define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91 #define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94 #define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
115 #define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118 #define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
127 #define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
132 * The core DRM version of this macro doesn't account for
136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
143 static const struct drm_ioctl_desc vmw_ioctls
[] = {
144 VMW_IOCTL_DEF(VMW_GET_PARAM
, vmw_getparam_ioctl
,
145 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF
, vmw_dmabuf_alloc_ioctl
,
147 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF
, vmw_dmabuf_unref_ioctl
,
149 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS
,
151 vmw_kms_cursor_bypass_ioctl
,
152 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM
, vmw_overlay_ioctl
,
155 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM
, vmw_stream_claim_ioctl
,
157 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
158 VMW_IOCTL_DEF(VMW_UNREF_STREAM
, vmw_stream_unref_ioctl
,
159 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT
, vmw_context_define_ioctl
,
162 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT
, vmw_context_destroy_ioctl
,
164 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE
, vmw_surface_define_ioctl
,
166 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE
, vmw_surface_destroy_ioctl
,
168 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
169 VMW_IOCTL_DEF(VMW_REF_SURFACE
, vmw_surface_reference_ioctl
,
170 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
171 VMW_IOCTL_DEF(VMW_EXECBUF
, vmw_execbuf_ioctl
,
172 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
173 VMW_IOCTL_DEF(VMW_FENCE_WAIT
, vmw_fence_obj_wait_ioctl
,
174 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED
,
176 vmw_fence_obj_signaled_ioctl
,
177 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
178 VMW_IOCTL_DEF(VMW_FENCE_UNREF
, vmw_fence_obj_unref_ioctl
,
179 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
180 VMW_IOCTL_DEF(VMW_FENCE_EVENT
, vmw_fence_event_ioctl
,
181 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
182 VMW_IOCTL_DEF(VMW_GET_3D_CAP
, vmw_get_cap_3d_ioctl
,
183 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
185 /* these allow direct access to the framebuffers mark as master only */
186 VMW_IOCTL_DEF(VMW_PRESENT
, vmw_present_ioctl
,
187 DRM_MASTER
| DRM_AUTH
| DRM_UNLOCKED
),
188 VMW_IOCTL_DEF(VMW_PRESENT_READBACK
,
189 vmw_present_readback_ioctl
,
190 DRM_MASTER
| DRM_AUTH
| DRM_UNLOCKED
),
191 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT
,
192 vmw_kms_update_layout_ioctl
,
193 DRM_MASTER
| DRM_UNLOCKED
),
194 VMW_IOCTL_DEF(VMW_CREATE_SHADER
,
195 vmw_shader_define_ioctl
,
196 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
197 VMW_IOCTL_DEF(VMW_UNREF_SHADER
,
198 vmw_shader_destroy_ioctl
,
199 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
200 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE
,
201 vmw_gb_surface_define_ioctl
,
202 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
203 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF
,
204 vmw_gb_surface_reference_ioctl
,
205 DRM_AUTH
| DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
206 VMW_IOCTL_DEF(VMW_SYNCCPU
,
207 vmw_user_dmabuf_synccpu_ioctl
,
208 DRM_UNLOCKED
| DRM_RENDER_ALLOW
),
211 static struct pci_device_id vmw_pci_id_list
[] = {
212 {0x15ad, 0x0405, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, VMWGFX_CHIP_SVGAII
},
215 MODULE_DEVICE_TABLE(pci
, vmw_pci_id_list
);
217 static int enable_fbdev
= IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON
);
218 static int vmw_force_iommu
;
219 static int vmw_restrict_iommu
;
220 static int vmw_force_coherent
;
221 static int vmw_restrict_dma_mask
;
223 static int vmw_probe(struct pci_dev
*, const struct pci_device_id
*);
224 static void vmw_master_init(struct vmw_master
*);
225 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
228 MODULE_PARM_DESC(enable_fbdev
, "Enable vmwgfx fbdev");
229 module_param_named(enable_fbdev
, enable_fbdev
, int, 0600);
230 MODULE_PARM_DESC(force_dma_api
, "Force using the DMA API for TTM pages");
231 module_param_named(force_dma_api
, vmw_force_iommu
, int, 0600);
232 MODULE_PARM_DESC(restrict_iommu
, "Try to limit IOMMU usage for TTM pages");
233 module_param_named(restrict_iommu
, vmw_restrict_iommu
, int, 0600);
234 MODULE_PARM_DESC(force_coherent
, "Force coherent TTM pages");
235 module_param_named(force_coherent
, vmw_force_coherent
, int, 0600);
236 MODULE_PARM_DESC(restrict_dma_mask
, "Restrict DMA mask to 44 bits with IOMMU");
237 module_param_named(restrict_dma_mask
, vmw_restrict_dma_mask
, int, 0600);
240 static void vmw_print_capabilities(uint32_t capabilities
)
242 DRM_INFO("Capabilities:\n");
243 if (capabilities
& SVGA_CAP_RECT_COPY
)
244 DRM_INFO(" Rect copy.\n");
245 if (capabilities
& SVGA_CAP_CURSOR
)
246 DRM_INFO(" Cursor.\n");
247 if (capabilities
& SVGA_CAP_CURSOR_BYPASS
)
248 DRM_INFO(" Cursor bypass.\n");
249 if (capabilities
& SVGA_CAP_CURSOR_BYPASS_2
)
250 DRM_INFO(" Cursor bypass 2.\n");
251 if (capabilities
& SVGA_CAP_8BIT_EMULATION
)
252 DRM_INFO(" 8bit emulation.\n");
253 if (capabilities
& SVGA_CAP_ALPHA_CURSOR
)
254 DRM_INFO(" Alpha cursor.\n");
255 if (capabilities
& SVGA_CAP_3D
)
257 if (capabilities
& SVGA_CAP_EXTENDED_FIFO
)
258 DRM_INFO(" Extended Fifo.\n");
259 if (capabilities
& SVGA_CAP_MULTIMON
)
260 DRM_INFO(" Multimon.\n");
261 if (capabilities
& SVGA_CAP_PITCHLOCK
)
262 DRM_INFO(" Pitchlock.\n");
263 if (capabilities
& SVGA_CAP_IRQMASK
)
264 DRM_INFO(" Irq mask.\n");
265 if (capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
)
266 DRM_INFO(" Display Topology.\n");
267 if (capabilities
& SVGA_CAP_GMR
)
269 if (capabilities
& SVGA_CAP_TRACES
)
270 DRM_INFO(" Traces.\n");
271 if (capabilities
& SVGA_CAP_GMR2
)
272 DRM_INFO(" GMR2.\n");
273 if (capabilities
& SVGA_CAP_SCREEN_OBJECT_2
)
274 DRM_INFO(" Screen Object 2.\n");
275 if (capabilities
& SVGA_CAP_COMMAND_BUFFERS
)
276 DRM_INFO(" Command Buffers.\n");
277 if (capabilities
& SVGA_CAP_CMD_BUFFERS_2
)
278 DRM_INFO(" Command Buffers 2.\n");
279 if (capabilities
& SVGA_CAP_GBOBJECTS
)
280 DRM_INFO(" Guest Backed Resources.\n");
284 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
286 * @dev_priv: A device private structure.
288 * This function creates a small buffer object that holds the query
289 * result for dummy queries emitted as query barriers.
290 * The function will then map the first page and initialize a pending
291 * occlusion query result structure, Finally it will unmap the buffer.
292 * No interruptible waits are done within this function.
294 * Returns an error if bo creation or initialization fails.
296 static int vmw_dummy_query_bo_create(struct vmw_private
*dev_priv
)
299 struct ttm_buffer_object
*bo
;
300 struct ttm_bo_kmap_obj map
;
301 volatile SVGA3dQueryResult
*result
;
305 * Create the bo as pinned, so that a tryreserve will
306 * immediately succeed. This is because we're the only
307 * user of the bo currently.
309 ret
= ttm_bo_create(&dev_priv
->bdev
,
312 &vmw_sys_ne_placement
,
316 if (unlikely(ret
!= 0))
319 ret
= ttm_bo_reserve(bo
, false, true, false, NULL
);
322 ret
= ttm_bo_kmap(bo
, 0, 1, &map
);
323 if (likely(ret
== 0)) {
324 result
= ttm_kmap_obj_virtual(&map
, &dummy
);
325 result
->totalSize
= sizeof(*result
);
326 result
->state
= SVGA3D_QUERYSTATE_PENDING
;
327 result
->result32
= 0xff;
330 vmw_bo_pin(bo
, false);
331 ttm_bo_unreserve(bo
);
333 if (unlikely(ret
!= 0)) {
334 DRM_ERROR("Dummy query buffer map failed.\n");
337 dev_priv
->dummy_query_bo
= bo
;
342 static int vmw_request_device(struct vmw_private
*dev_priv
)
346 ret
= vmw_fifo_init(dev_priv
, &dev_priv
->fifo
);
347 if (unlikely(ret
!= 0)) {
348 DRM_ERROR("Unable to initialize FIFO.\n");
351 vmw_fence_fifo_up(dev_priv
->fman
);
352 if (dev_priv
->has_mob
) {
353 ret
= vmw_otables_setup(dev_priv
);
354 if (unlikely(ret
!= 0)) {
355 DRM_ERROR("Unable to initialize "
356 "guest Memory OBjects.\n");
360 ret
= vmw_dummy_query_bo_create(dev_priv
);
361 if (unlikely(ret
!= 0))
362 goto out_no_query_bo
;
367 if (dev_priv
->has_mob
)
368 vmw_otables_takedown(dev_priv
);
370 vmw_fence_fifo_down(dev_priv
->fman
);
371 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
375 static void vmw_release_device(struct vmw_private
*dev_priv
)
378 * Previous destructions should've released
382 BUG_ON(dev_priv
->pinned_bo
!= NULL
);
384 ttm_bo_unref(&dev_priv
->dummy_query_bo
);
385 if (dev_priv
->has_mob
)
386 vmw_otables_takedown(dev_priv
);
387 vmw_fence_fifo_down(dev_priv
->fman
);
388 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
393 * Increase the 3d resource refcount.
394 * If the count was prevously zero, initialize the fifo, switching to svga
395 * mode. Note that the master holds a ref as well, and may request an
396 * explicit switch to svga mode if fb is not running, using @unhide_svga.
398 int vmw_3d_resource_inc(struct vmw_private
*dev_priv
,
403 mutex_lock(&dev_priv
->release_mutex
);
404 if (unlikely(dev_priv
->num_3d_resources
++ == 0)) {
405 ret
= vmw_request_device(dev_priv
);
406 if (unlikely(ret
!= 0))
407 --dev_priv
->num_3d_resources
;
408 } else if (unhide_svga
) {
409 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
410 vmw_read(dev_priv
, SVGA_REG_ENABLE
) &
411 ~SVGA_REG_ENABLE_HIDE
);
414 mutex_unlock(&dev_priv
->release_mutex
);
419 * Decrease the 3d resource refcount.
420 * If the count reaches zero, disable the fifo, switching to vga mode.
421 * Note that the master holds a refcount as well, and may request an
422 * explicit switch to vga mode when it releases its refcount to account
423 * for the situation of an X server vt switch to VGA with 3d resources
426 void vmw_3d_resource_dec(struct vmw_private
*dev_priv
,
431 mutex_lock(&dev_priv
->release_mutex
);
432 if (unlikely(--dev_priv
->num_3d_resources
== 0))
433 vmw_release_device(dev_priv
);
435 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
436 vmw_read(dev_priv
, SVGA_REG_ENABLE
) |
437 SVGA_REG_ENABLE_HIDE
);
439 n3d
= (int32_t) dev_priv
->num_3d_resources
;
440 mutex_unlock(&dev_priv
->release_mutex
);
446 * Sets the initial_[width|height] fields on the given vmw_private.
448 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
449 * clamping the value to fb_max_[width|height] fields and the
450 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
451 * If the values appear to be invalid, set them to
452 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
454 static void vmw_get_initial_size(struct vmw_private
*dev_priv
)
459 width
= vmw_read(dev_priv
, SVGA_REG_WIDTH
);
460 height
= vmw_read(dev_priv
, SVGA_REG_HEIGHT
);
462 width
= max_t(uint32_t, width
, VMW_MIN_INITIAL_WIDTH
);
463 height
= max_t(uint32_t, height
, VMW_MIN_INITIAL_HEIGHT
);
465 if (width
> dev_priv
->fb_max_width
||
466 height
> dev_priv
->fb_max_height
) {
469 * This is a host error and shouldn't occur.
472 width
= VMW_MIN_INITIAL_WIDTH
;
473 height
= VMW_MIN_INITIAL_HEIGHT
;
476 dev_priv
->initial_width
= width
;
477 dev_priv
->initial_height
= height
;
481 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
484 * @dev_priv: Pointer to a struct vmw_private
486 * This functions tries to determine the IOMMU setup and what actions
487 * need to be taken by the driver to make system pages visible to the
489 * If this function decides that DMA is not possible, it returns -EINVAL.
490 * The driver may then try to disable features of the device that require
493 static int vmw_dma_select_mode(struct vmw_private
*dev_priv
)
495 static const char *names
[vmw_dma_map_max
] = {
496 [vmw_dma_phys
] = "Using physical TTM page addresses.",
497 [vmw_dma_alloc_coherent
] = "Using coherent TTM pages.",
498 [vmw_dma_map_populate
] = "Keeping DMA mappings.",
499 [vmw_dma_map_bind
] = "Giving up DMA mappings early."};
501 const struct dma_map_ops
*dma_ops
= get_dma_ops(dev_priv
->dev
->dev
);
503 #ifdef CONFIG_INTEL_IOMMU
504 if (intel_iommu_enabled
) {
505 dev_priv
->map_mode
= vmw_dma_map_populate
;
510 if (!(vmw_force_iommu
|| vmw_force_coherent
)) {
511 dev_priv
->map_mode
= vmw_dma_phys
;
512 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
516 dev_priv
->map_mode
= vmw_dma_map_populate
;
518 if (dma_ops
->sync_single_for_cpu
)
519 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
520 #ifdef CONFIG_SWIOTLB
521 if (swiotlb_nr_tbl() == 0)
522 dev_priv
->map_mode
= vmw_dma_map_populate
;
525 #ifdef CONFIG_INTEL_IOMMU
528 if (dev_priv
->map_mode
== vmw_dma_map_populate
&&
530 dev_priv
->map_mode
= vmw_dma_map_bind
;
532 if (vmw_force_coherent
)
533 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
535 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
537 * No coherent page pool
539 if (dev_priv
->map_mode
== vmw_dma_alloc_coherent
)
543 #else /* CONFIG_X86 */
544 dev_priv
->map_mode
= vmw_dma_map_populate
;
545 #endif /* CONFIG_X86 */
547 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
553 * vmw_dma_masks - set required page- and dma masks
555 * @dev: Pointer to struct drm-device
557 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
558 * restriction also for 64-bit systems.
560 #ifdef CONFIG_INTEL_IOMMU
561 static int vmw_dma_masks(struct vmw_private
*dev_priv
)
563 struct drm_device
*dev
= dev_priv
->dev
;
565 if (intel_iommu_enabled
&&
566 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask
)) {
567 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
568 return dma_set_mask(dev
->dev
, DMA_BIT_MASK(44));
573 static int vmw_dma_masks(struct vmw_private
*dev_priv
)
579 static int vmw_driver_load(struct drm_device
*dev
, unsigned long chipset
)
581 struct vmw_private
*dev_priv
;
585 bool refuse_dma
= false;
587 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
588 if (unlikely(dev_priv
== NULL
)) {
589 DRM_ERROR("Failed allocating a device private struct.\n");
593 pci_set_master(dev
->pdev
);
596 dev_priv
->vmw_chipset
= chipset
;
597 dev_priv
->last_read_seqno
= (uint32_t) -100;
598 mutex_init(&dev_priv
->cmdbuf_mutex
);
599 mutex_init(&dev_priv
->release_mutex
);
600 mutex_init(&dev_priv
->binding_mutex
);
601 rwlock_init(&dev_priv
->resource_lock
);
602 ttm_lock_init(&dev_priv
->reservation_sem
);
603 spin_lock_init(&dev_priv
->hw_lock
);
604 spin_lock_init(&dev_priv
->waiter_lock
);
605 spin_lock_init(&dev_priv
->cap_lock
);
607 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
) {
608 idr_init(&dev_priv
->res_idr
[i
]);
609 INIT_LIST_HEAD(&dev_priv
->res_lru
[i
]);
612 mutex_init(&dev_priv
->init_mutex
);
613 init_waitqueue_head(&dev_priv
->fence_queue
);
614 init_waitqueue_head(&dev_priv
->fifo_queue
);
615 dev_priv
->fence_queue_waiters
= 0;
616 atomic_set(&dev_priv
->fifo_queue_waiters
, 0);
618 dev_priv
->used_memory_size
= 0;
620 dev_priv
->io_start
= pci_resource_start(dev
->pdev
, 0);
621 dev_priv
->vram_start
= pci_resource_start(dev
->pdev
, 1);
622 dev_priv
->mmio_start
= pci_resource_start(dev
->pdev
, 2);
624 dev_priv
->enable_fb
= enable_fbdev
;
626 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
627 svga_id
= vmw_read(dev_priv
, SVGA_REG_ID
);
628 if (svga_id
!= SVGA_ID_2
) {
630 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id
);
634 dev_priv
->capabilities
= vmw_read(dev_priv
, SVGA_REG_CAPABILITIES
);
635 ret
= vmw_dma_select_mode(dev_priv
);
636 if (unlikely(ret
!= 0)) {
637 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
641 dev_priv
->vram_size
= vmw_read(dev_priv
, SVGA_REG_VRAM_SIZE
);
642 dev_priv
->mmio_size
= vmw_read(dev_priv
, SVGA_REG_MEM_SIZE
);
643 dev_priv
->fb_max_width
= vmw_read(dev_priv
, SVGA_REG_MAX_WIDTH
);
644 dev_priv
->fb_max_height
= vmw_read(dev_priv
, SVGA_REG_MAX_HEIGHT
);
646 vmw_get_initial_size(dev_priv
);
648 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
649 dev_priv
->max_gmr_ids
=
650 vmw_read(dev_priv
, SVGA_REG_GMR_MAX_IDS
);
651 dev_priv
->max_gmr_pages
=
652 vmw_read(dev_priv
, SVGA_REG_GMRS_MAX_PAGES
);
653 dev_priv
->memory_size
=
654 vmw_read(dev_priv
, SVGA_REG_MEMORY_SIZE
);
655 dev_priv
->memory_size
-= dev_priv
->vram_size
;
658 * An arbitrary limit of 512MiB on surface
659 * memory. But all HWV8 hardware supports GMR2.
661 dev_priv
->memory_size
= 512*1024*1024;
663 dev_priv
->max_mob_pages
= 0;
664 dev_priv
->max_mob_size
= 0;
665 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
) {
668 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB
);
670 dev_priv
->max_mob_pages
= mem_size
* 1024 / PAGE_SIZE
;
671 dev_priv
->prim_bb_mem
=
673 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM
);
674 dev_priv
->max_mob_size
=
675 vmw_read(dev_priv
, SVGA_REG_MOB_MAX_SIZE
);
677 dev_priv
->prim_bb_mem
= dev_priv
->vram_size
;
679 ret
= vmw_dma_masks(dev_priv
);
680 if (unlikely(ret
!= 0))
684 * Limit back buffer size to VRAM size. Remove this once
685 * screen targets are implemented.
687 if (dev_priv
->prim_bb_mem
> dev_priv
->vram_size
)
688 dev_priv
->prim_bb_mem
= dev_priv
->vram_size
;
690 vmw_print_capabilities(dev_priv
->capabilities
);
692 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
693 DRM_INFO("Max GMR ids is %u\n",
694 (unsigned)dev_priv
->max_gmr_ids
);
695 DRM_INFO("Max number of GMR pages is %u\n",
696 (unsigned)dev_priv
->max_gmr_pages
);
697 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
698 (unsigned)dev_priv
->memory_size
/ 1024);
700 DRM_INFO("Maximum display memory size is %u kiB\n",
701 dev_priv
->prim_bb_mem
/ 1024);
702 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
703 dev_priv
->vram_start
, dev_priv
->vram_size
/ 1024);
704 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
705 dev_priv
->mmio_start
, dev_priv
->mmio_size
/ 1024);
707 ret
= vmw_ttm_global_init(dev_priv
);
708 if (unlikely(ret
!= 0))
712 vmw_master_init(&dev_priv
->fbdev_master
);
713 ttm_lock_set_kill(&dev_priv
->fbdev_master
.lock
, false, SIGTERM
);
714 dev_priv
->active_master
= &dev_priv
->fbdev_master
;
717 ret
= ttm_bo_device_init(&dev_priv
->bdev
,
718 dev_priv
->bo_global_ref
.ref
.object
,
720 dev
->anon_inode
->i_mapping
,
721 VMWGFX_FILE_PAGE_OFFSET
,
723 if (unlikely(ret
!= 0)) {
724 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
728 dev_priv
->mmio_mtrr
= arch_phys_wc_add(dev_priv
->mmio_start
,
729 dev_priv
->mmio_size
);
731 dev_priv
->mmio_virt
= ioremap_wc(dev_priv
->mmio_start
,
732 dev_priv
->mmio_size
);
734 if (unlikely(dev_priv
->mmio_virt
== NULL
)) {
736 DRM_ERROR("Failed mapping MMIO.\n");
740 /* Need mmio memory to check for fifo pitchlock cap. */
741 if (!(dev_priv
->capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
) &&
742 !(dev_priv
->capabilities
& SVGA_CAP_PITCHLOCK
) &&
743 !vmw_fifo_have_pitchlock(dev_priv
)) {
745 DRM_ERROR("Hardware has no pitchlock\n");
749 dev_priv
->tdev
= ttm_object_device_init
750 (dev_priv
->mem_global_ref
.object
, 12, &vmw_prime_dmabuf_ops
);
752 if (unlikely(dev_priv
->tdev
== NULL
)) {
753 DRM_ERROR("Unable to initialize TTM object management.\n");
758 dev
->dev_private
= dev_priv
;
760 ret
= pci_request_regions(dev
->pdev
, "vmwgfx probe");
761 dev_priv
->stealth
= (ret
!= 0);
762 if (dev_priv
->stealth
) {
764 * Request at least the mmio PCI resource.
767 DRM_INFO("It appears like vesafb is loaded. "
768 "Ignore above error if any.\n");
769 ret
= pci_request_region(dev
->pdev
, 2, "vmwgfx stealth probe");
770 if (unlikely(ret
!= 0)) {
771 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
776 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
) {
777 ret
= drm_irq_install(dev
, dev
->pdev
->irq
);
779 DRM_ERROR("Failed installing irq: %d\n", ret
);
784 dev_priv
->fman
= vmw_fence_manager_init(dev_priv
);
785 if (unlikely(dev_priv
->fman
== NULL
)) {
791 ret
= ttm_bo_init_mm(&dev_priv
->bdev
, TTM_PL_VRAM
,
792 (dev_priv
->vram_size
>> PAGE_SHIFT
));
793 if (unlikely(ret
!= 0)) {
794 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
798 dev_priv
->has_gmr
= true;
799 if (((dev_priv
->capabilities
& (SVGA_CAP_GMR
| SVGA_CAP_GMR2
)) == 0) ||
800 refuse_dma
|| ttm_bo_init_mm(&dev_priv
->bdev
, VMW_PL_GMR
,
802 DRM_INFO("No GMR memory available. "
803 "Graphics memory resources are very limited.\n");
804 dev_priv
->has_gmr
= false;
807 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
) {
808 dev_priv
->has_mob
= true;
809 if (ttm_bo_init_mm(&dev_priv
->bdev
, VMW_PL_MOB
,
811 DRM_INFO("No MOB memory available. "
812 "3D will be disabled.\n");
813 dev_priv
->has_mob
= false;
817 vmw_kms_save_vga(dev_priv
);
819 /* Start kms and overlay systems, needs fifo. */
820 ret
= vmw_kms_init(dev_priv
);
821 if (unlikely(ret
!= 0))
823 vmw_overlay_init(dev_priv
);
825 if (dev_priv
->enable_fb
) {
826 ret
= vmw_3d_resource_inc(dev_priv
, true);
827 if (unlikely(ret
!= 0))
829 vmw_fb_init(dev_priv
);
832 dev_priv
->pm_nb
.notifier_call
= vmwgfx_pm_notifier
;
833 register_pm_notifier(&dev_priv
->pm_nb
);
838 vmw_overlay_close(dev_priv
);
839 vmw_kms_close(dev_priv
);
841 vmw_kms_restore_vga(dev_priv
);
842 if (dev_priv
->has_mob
)
843 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_MOB
);
844 if (dev_priv
->has_gmr
)
845 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_GMR
);
846 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
848 vmw_fence_manager_takedown(dev_priv
->fman
);
850 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
851 drm_irq_uninstall(dev_priv
->dev
);
853 if (dev_priv
->stealth
)
854 pci_release_region(dev
->pdev
, 2);
856 pci_release_regions(dev
->pdev
);
858 ttm_object_device_release(&dev_priv
->tdev
);
860 iounmap(dev_priv
->mmio_virt
);
862 arch_phys_wc_del(dev_priv
->mmio_mtrr
);
863 (void)ttm_bo_device_release(&dev_priv
->bdev
);
865 vmw_ttm_global_release(dev_priv
);
867 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
868 idr_destroy(&dev_priv
->res_idr
[i
]);
874 static int vmw_driver_unload(struct drm_device
*dev
)
876 struct vmw_private
*dev_priv
= vmw_priv(dev
);
879 unregister_pm_notifier(&dev_priv
->pm_nb
);
881 if (dev_priv
->ctx
.res_ht_initialized
)
882 drm_ht_remove(&dev_priv
->ctx
.res_ht
);
883 vfree(dev_priv
->ctx
.cmd_bounce
);
884 if (dev_priv
->enable_fb
) {
885 vmw_fb_close(dev_priv
);
886 vmw_kms_restore_vga(dev_priv
);
887 vmw_3d_resource_dec(dev_priv
, false);
889 vmw_kms_close(dev_priv
);
890 vmw_overlay_close(dev_priv
);
892 if (dev_priv
->has_mob
)
893 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_MOB
);
894 if (dev_priv
->has_gmr
)
895 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_GMR
);
896 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
898 vmw_fence_manager_takedown(dev_priv
->fman
);
899 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
900 drm_irq_uninstall(dev_priv
->dev
);
901 if (dev_priv
->stealth
)
902 pci_release_region(dev
->pdev
, 2);
904 pci_release_regions(dev
->pdev
);
906 ttm_object_device_release(&dev_priv
->tdev
);
907 iounmap(dev_priv
->mmio_virt
);
908 arch_phys_wc_del(dev_priv
->mmio_mtrr
);
909 (void)ttm_bo_device_release(&dev_priv
->bdev
);
910 vmw_ttm_global_release(dev_priv
);
912 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
913 idr_destroy(&dev_priv
->res_idr
[i
]);
920 static void vmw_preclose(struct drm_device
*dev
,
921 struct drm_file
*file_priv
)
923 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
924 struct vmw_private
*dev_priv
= vmw_priv(dev
);
926 vmw_event_fence_fpriv_gone(dev_priv
->fman
, &vmw_fp
->fence_events
);
929 static void vmw_postclose(struct drm_device
*dev
,
930 struct drm_file
*file_priv
)
932 struct vmw_fpriv
*vmw_fp
;
934 vmw_fp
= vmw_fpriv(file_priv
);
936 if (vmw_fp
->locked_master
) {
937 struct vmw_master
*vmaster
=
938 vmw_master(vmw_fp
->locked_master
);
940 ttm_lock_set_kill(&vmaster
->lock
, true, SIGTERM
);
941 ttm_vt_unlock(&vmaster
->lock
);
942 drm_master_put(&vmw_fp
->locked_master
);
945 ttm_object_file_release(&vmw_fp
->tfile
);
949 static int vmw_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
951 struct vmw_private
*dev_priv
= vmw_priv(dev
);
952 struct vmw_fpriv
*vmw_fp
;
955 vmw_fp
= kzalloc(sizeof(*vmw_fp
), GFP_KERNEL
);
956 if (unlikely(vmw_fp
== NULL
))
959 INIT_LIST_HEAD(&vmw_fp
->fence_events
);
960 vmw_fp
->tfile
= ttm_object_file_init(dev_priv
->tdev
, 10);
961 if (unlikely(vmw_fp
->tfile
== NULL
))
964 file_priv
->driver_priv
= vmw_fp
;
973 static struct vmw_master
*vmw_master_check(struct drm_device
*dev
,
974 struct drm_file
*file_priv
,
978 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
979 struct vmw_master
*vmaster
;
981 if (file_priv
->minor
->type
!= DRM_MINOR_LEGACY
||
985 ret
= mutex_lock_interruptible(&dev
->master_mutex
);
986 if (unlikely(ret
!= 0))
987 return ERR_PTR(-ERESTARTSYS
);
989 if (file_priv
->is_master
) {
990 mutex_unlock(&dev
->master_mutex
);
995 * Check if we were previously master, but now dropped.
997 if (vmw_fp
->locked_master
) {
998 mutex_unlock(&dev
->master_mutex
);
999 DRM_ERROR("Dropped master trying to access ioctl that "
1000 "requires authentication.\n");
1001 return ERR_PTR(-EACCES
);
1003 mutex_unlock(&dev
->master_mutex
);
1006 * Taking the drm_global_mutex after the TTM lock might deadlock
1008 if (!(flags
& DRM_UNLOCKED
)) {
1009 DRM_ERROR("Refusing locked ioctl access.\n");
1010 return ERR_PTR(-EDEADLK
);
1014 * Take the TTM lock. Possibly sleep waiting for the authenticating
1015 * master to become master again, or for a SIGTERM if the
1016 * authenticating master exits.
1018 vmaster
= vmw_master(file_priv
->master
);
1019 ret
= ttm_read_lock(&vmaster
->lock
, true);
1020 if (unlikely(ret
!= 0))
1021 vmaster
= ERR_PTR(ret
);
1026 static long vmw_generic_ioctl(struct file
*filp
, unsigned int cmd
,
1028 long (*ioctl_func
)(struct file
*, unsigned int,
1031 struct drm_file
*file_priv
= filp
->private_data
;
1032 struct drm_device
*dev
= file_priv
->minor
->dev
;
1033 unsigned int nr
= DRM_IOCTL_NR(cmd
);
1034 struct vmw_master
*vmaster
;
1039 * Do extra checking on driver private ioctls.
1042 if ((nr
>= DRM_COMMAND_BASE
) && (nr
< DRM_COMMAND_END
)
1043 && (nr
< DRM_COMMAND_BASE
+ dev
->driver
->num_ioctls
)) {
1044 const struct drm_ioctl_desc
*ioctl
=
1045 &vmw_ioctls
[nr
- DRM_COMMAND_BASE
];
1047 if (unlikely(ioctl
->cmd
!= cmd
)) {
1048 DRM_ERROR("Invalid command format, ioctl %d\n",
1049 nr
- DRM_COMMAND_BASE
);
1052 flags
= ioctl
->flags
;
1053 } else if (!drm_ioctl_flags(nr
, &flags
))
1056 vmaster
= vmw_master_check(dev
, file_priv
, flags
);
1057 if (unlikely(IS_ERR(vmaster
))) {
1058 ret
= PTR_ERR(vmaster
);
1060 if (ret
!= -ERESTARTSYS
)
1061 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1066 ret
= ioctl_func(filp
, cmd
, arg
);
1068 ttm_read_unlock(&vmaster
->lock
);
1073 static long vmw_unlocked_ioctl(struct file
*filp
, unsigned int cmd
,
1076 return vmw_generic_ioctl(filp
, cmd
, arg
, &drm_ioctl
);
1079 #ifdef CONFIG_COMPAT
1080 static long vmw_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1083 return vmw_generic_ioctl(filp
, cmd
, arg
, &drm_compat_ioctl
);
1087 static void vmw_lastclose(struct drm_device
*dev
)
1089 struct drm_crtc
*crtc
;
1090 struct drm_mode_set set
;
1097 set
.connectors
= NULL
;
1098 set
.num_connectors
= 0;
1100 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1102 ret
= drm_mode_set_config_internal(&set
);
1108 static void vmw_master_init(struct vmw_master
*vmaster
)
1110 ttm_lock_init(&vmaster
->lock
);
1111 INIT_LIST_HEAD(&vmaster
->fb_surf
);
1112 mutex_init(&vmaster
->fb_surf_mutex
);
1115 static int vmw_master_create(struct drm_device
*dev
,
1116 struct drm_master
*master
)
1118 struct vmw_master
*vmaster
;
1120 vmaster
= kzalloc(sizeof(*vmaster
), GFP_KERNEL
);
1121 if (unlikely(vmaster
== NULL
))
1124 vmw_master_init(vmaster
);
1125 ttm_lock_set_kill(&vmaster
->lock
, true, SIGTERM
);
1126 master
->driver_priv
= vmaster
;
1131 static void vmw_master_destroy(struct drm_device
*dev
,
1132 struct drm_master
*master
)
1134 struct vmw_master
*vmaster
= vmw_master(master
);
1136 master
->driver_priv
= NULL
;
1141 static int vmw_master_set(struct drm_device
*dev
,
1142 struct drm_file
*file_priv
,
1145 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1146 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1147 struct vmw_master
*active
= dev_priv
->active_master
;
1148 struct vmw_master
*vmaster
= vmw_master(file_priv
->master
);
1151 if (!dev_priv
->enable_fb
) {
1152 ret
= vmw_3d_resource_inc(dev_priv
, true);
1153 if (unlikely(ret
!= 0))
1155 vmw_kms_save_vga(dev_priv
);
1156 vmw_write(dev_priv
, SVGA_REG_TRACES
, 0);
1160 BUG_ON(active
!= &dev_priv
->fbdev_master
);
1161 ret
= ttm_vt_lock(&active
->lock
, false, vmw_fp
->tfile
);
1162 if (unlikely(ret
!= 0))
1163 goto out_no_active_lock
;
1165 ttm_lock_set_kill(&active
->lock
, true, SIGTERM
);
1166 ret
= ttm_bo_evict_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
1167 if (unlikely(ret
!= 0)) {
1168 DRM_ERROR("Unable to clean VRAM on "
1172 dev_priv
->active_master
= NULL
;
1175 ttm_lock_set_kill(&vmaster
->lock
, false, SIGTERM
);
1177 ttm_vt_unlock(&vmaster
->lock
);
1178 BUG_ON(vmw_fp
->locked_master
!= file_priv
->master
);
1179 drm_master_put(&vmw_fp
->locked_master
);
1182 dev_priv
->active_master
= vmaster
;
1187 if (!dev_priv
->enable_fb
) {
1188 vmw_kms_restore_vga(dev_priv
);
1189 vmw_3d_resource_dec(dev_priv
, true);
1190 vmw_write(dev_priv
, SVGA_REG_TRACES
, 1);
1195 static void vmw_master_drop(struct drm_device
*dev
,
1196 struct drm_file
*file_priv
,
1199 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1200 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1201 struct vmw_master
*vmaster
= vmw_master(file_priv
->master
);
1205 * Make sure the master doesn't disappear while we have
1209 vmw_fp
->locked_master
= drm_master_get(file_priv
->master
);
1210 ret
= ttm_vt_lock(&vmaster
->lock
, false, vmw_fp
->tfile
);
1211 if (unlikely((ret
!= 0))) {
1212 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1213 drm_master_put(&vmw_fp
->locked_master
);
1216 ttm_lock_set_kill(&vmaster
->lock
, false, SIGTERM
);
1217 vmw_execbuf_release_pinned_bo(dev_priv
);
1219 if (!dev_priv
->enable_fb
) {
1220 ret
= ttm_bo_evict_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
1221 if (unlikely(ret
!= 0))
1222 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1223 vmw_kms_restore_vga(dev_priv
);
1224 vmw_3d_resource_dec(dev_priv
, true);
1225 vmw_write(dev_priv
, SVGA_REG_TRACES
, 1);
1228 dev_priv
->active_master
= &dev_priv
->fbdev_master
;
1229 ttm_lock_set_kill(&dev_priv
->fbdev_master
.lock
, false, SIGTERM
);
1230 ttm_vt_unlock(&dev_priv
->fbdev_master
.lock
);
1232 if (dev_priv
->enable_fb
)
1233 vmw_fb_on(dev_priv
);
1237 static void vmw_remove(struct pci_dev
*pdev
)
1239 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1241 pci_disable_device(pdev
);
1245 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
1248 struct vmw_private
*dev_priv
=
1249 container_of(nb
, struct vmw_private
, pm_nb
);
1252 case PM_HIBERNATION_PREPARE
:
1253 case PM_SUSPEND_PREPARE
:
1254 ttm_suspend_lock(&dev_priv
->reservation_sem
);
1257 * This empties VRAM and unbinds all GMR bindings.
1258 * Buffer contents is moved to swappable memory.
1260 vmw_execbuf_release_pinned_bo(dev_priv
);
1261 vmw_resource_evict_all(dev_priv
);
1262 ttm_bo_swapout_all(&dev_priv
->bdev
);
1265 case PM_POST_HIBERNATION
:
1266 case PM_POST_SUSPEND
:
1267 case PM_POST_RESTORE
:
1268 ttm_suspend_unlock(&dev_priv
->reservation_sem
);
1271 case PM_RESTORE_PREPARE
:
1280 * These might not be needed with the virtual SVGA device.
1283 static int vmw_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1285 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1286 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1288 if (dev_priv
->num_3d_resources
!= 0) {
1289 DRM_INFO("Can't suspend or hibernate "
1290 "while 3D resources are active.\n");
1294 pci_save_state(pdev
);
1295 pci_disable_device(pdev
);
1296 pci_set_power_state(pdev
, PCI_D3hot
);
1300 static int vmw_pci_resume(struct pci_dev
*pdev
)
1302 pci_set_power_state(pdev
, PCI_D0
);
1303 pci_restore_state(pdev
);
1304 return pci_enable_device(pdev
);
1307 static int vmw_pm_suspend(struct device
*kdev
)
1309 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1310 struct pm_message dummy
;
1314 return vmw_pci_suspend(pdev
, dummy
);
1317 static int vmw_pm_resume(struct device
*kdev
)
1319 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1321 return vmw_pci_resume(pdev
);
1324 static int vmw_pm_prepare(struct device
*kdev
)
1326 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1327 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1328 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1331 * Release 3d reference held by fbdev and potentially
1334 dev_priv
->suspended
= true;
1335 if (dev_priv
->enable_fb
)
1336 vmw_3d_resource_dec(dev_priv
, true);
1338 if (dev_priv
->num_3d_resources
!= 0) {
1340 DRM_INFO("Can't suspend or hibernate "
1341 "while 3D resources are active.\n");
1343 if (dev_priv
->enable_fb
)
1344 vmw_3d_resource_inc(dev_priv
, true);
1345 dev_priv
->suspended
= false;
1352 static void vmw_pm_complete(struct device
*kdev
)
1354 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1355 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1356 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1358 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
1359 (void) vmw_read(dev_priv
, SVGA_REG_ID
);
1362 * Reclaim 3d reference held by fbdev and potentially
1365 if (dev_priv
->enable_fb
)
1366 vmw_3d_resource_inc(dev_priv
, false);
1368 dev_priv
->suspended
= false;
1371 static const struct dev_pm_ops vmw_pm_ops
= {
1372 .prepare
= vmw_pm_prepare
,
1373 .complete
= vmw_pm_complete
,
1374 .suspend
= vmw_pm_suspend
,
1375 .resume
= vmw_pm_resume
,
1378 static const struct file_operations vmwgfx_driver_fops
= {
1379 .owner
= THIS_MODULE
,
1381 .release
= drm_release
,
1382 .unlocked_ioctl
= vmw_unlocked_ioctl
,
1384 .poll
= vmw_fops_poll
,
1385 .read
= vmw_fops_read
,
1386 #if defined(CONFIG_COMPAT)
1387 .compat_ioctl
= vmw_compat_ioctl
,
1389 .llseek
= noop_llseek
,
1392 static struct drm_driver driver
= {
1393 .driver_features
= DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
|
1394 DRIVER_MODESET
| DRIVER_PRIME
| DRIVER_RENDER
,
1395 .load
= vmw_driver_load
,
1396 .unload
= vmw_driver_unload
,
1397 .lastclose
= vmw_lastclose
,
1398 .irq_preinstall
= vmw_irq_preinstall
,
1399 .irq_postinstall
= vmw_irq_postinstall
,
1400 .irq_uninstall
= vmw_irq_uninstall
,
1401 .irq_handler
= vmw_irq_handler
,
1402 .get_vblank_counter
= vmw_get_vblank_counter
,
1403 .enable_vblank
= vmw_enable_vblank
,
1404 .disable_vblank
= vmw_disable_vblank
,
1405 .ioctls
= vmw_ioctls
,
1406 .num_ioctls
= ARRAY_SIZE(vmw_ioctls
),
1407 .master_create
= vmw_master_create
,
1408 .master_destroy
= vmw_master_destroy
,
1409 .master_set
= vmw_master_set
,
1410 .master_drop
= vmw_master_drop
,
1411 .open
= vmw_driver_open
,
1412 .preclose
= vmw_preclose
,
1413 .postclose
= vmw_postclose
,
1414 .set_busid
= drm_pci_set_busid
,
1416 .dumb_create
= vmw_dumb_create
,
1417 .dumb_map_offset
= vmw_dumb_map_offset
,
1418 .dumb_destroy
= vmw_dumb_destroy
,
1420 .prime_fd_to_handle
= vmw_prime_fd_to_handle
,
1421 .prime_handle_to_fd
= vmw_prime_handle_to_fd
,
1423 .fops
= &vmwgfx_driver_fops
,
1424 .name
= VMWGFX_DRIVER_NAME
,
1425 .desc
= VMWGFX_DRIVER_DESC
,
1426 .date
= VMWGFX_DRIVER_DATE
,
1427 .major
= VMWGFX_DRIVER_MAJOR
,
1428 .minor
= VMWGFX_DRIVER_MINOR
,
1429 .patchlevel
= VMWGFX_DRIVER_PATCHLEVEL
1432 static struct pci_driver vmw_pci_driver
= {
1433 .name
= VMWGFX_DRIVER_NAME
,
1434 .id_table
= vmw_pci_id_list
,
1436 .remove
= vmw_remove
,
1442 static int vmw_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1444 return drm_get_pci_dev(pdev
, ent
, &driver
);
1447 static int __init
vmwgfx_init(void)
1450 ret
= drm_pci_init(&driver
, &vmw_pci_driver
);
1452 DRM_ERROR("Failed initializing DRM.\n");
1456 static void __exit
vmwgfx_exit(void)
1458 drm_pci_exit(&driver
, &vmw_pci_driver
);
1461 module_init(vmwgfx_init
);
1462 module_exit(vmwgfx_exit
);
1464 MODULE_AUTHOR("VMware Inc. and others");
1465 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1466 MODULE_LICENSE("GPL and additional rights");
1467 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR
) "."
1468 __stringify(VMWGFX_DRIVER_MINOR
) "."
1469 __stringify(VMWGFX_DRIVER_PATCHLEVEL
) "."