drivers/misc/cxl/vphb.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/pci.h>
  11 #include <misc/cxl.h>
  12 #include "cxl.h"
  13
  14 static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
  15 {
  16         if (dma_mask < DMA_BIT_MASK(64)) {
  17                 pr_info("%s only 64bit DMA supported on CXL", __func__);
  18                 return -EIO;
  19         }
  20
  21         *(pdev->dev.dma_mask) = dma_mask;
  22         return 0;
  23 }
  24
  25 static int cxl_pci_probe_mode(struct pci_bus *bus)
  26 {
  27         return PCI_PROBE_NORMAL;
  28 }
  29
  30 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  31 {
  32         return -ENODEV;
  33 }
  34
  35 static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
  36 {
  37         /*
  38          * MSI should never be set but need still need to provide this call
  39          * back.
  40          */
  41 }
  42
  43 static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
  44 {
  45         struct pci_controller *phb;
  46         struct cxl_afu *afu;
  47         struct cxl_context *ctx;
  48
  49         phb = pci_bus_to_host(dev->bus);
  50         afu = (struct cxl_afu *)phb->private_data;
  51         set_dma_ops(&dev->dev, &dma_direct_ops);
  52         set_dma_offset(&dev->dev, PAGE_OFFSET);
  53
  54         /*
  55          * Allocate a context to do cxl things too.  If we eventually do real
  56          * DMA ops, we'll need a default context to attach them to
  57          */
  58         ctx = cxl_dev_context_init(dev);
  59         if (!ctx)
  60                 return false;
  61         dev->dev.archdata.cxl_ctx = ctx;
  62
  63         return (cxl_afu_check_and_enable(afu) == 0);
  64 }
  65
  66 static void cxl_pci_disable_device(struct pci_dev *dev)
  67 {
  68         struct cxl_context *ctx = cxl_get_context(dev);
  69
  70         if (ctx) {
  71                 if (ctx->status == STARTED) {
  72                         dev_err(&dev->dev, "Default context started\n");
  73                         return;
  74                 }
  75                 dev->dev.archdata.cxl_ctx = NULL;
  76                 cxl_release_context(ctx);
  77         }
  78 }
  79
  80 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
  81                                                 unsigned long type)
  82 {
  83         return 1;
  84 }
  85
  86 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
  87 {
  88         /* Should we do an AFU reset here ? */
  89 }
  90
  91 static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
  92 {
  93         return (bus << 8) + devfn;
  94 }
  95
  96 static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb,
  97                                        u8 bus, u8 devfn, int offset)
  98 {
  99         int record = cxl_pcie_cfg_record(bus, devfn);
 100
 101         return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset;
 102 }
 103
 104
 105 static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
 106                                 int offset, int len,
 107                                 volatile void __iomem **ioaddr,
 108                                 u32 *mask, int *shift)
 109 {
 110         struct pci_controller *phb;
 111         struct cxl_afu *afu;
 112         unsigned long addr;
 113
 114         phb = pci_bus_to_host(bus);
 115         if (phb == NULL)
 116                 return PCIBIOS_DEVICE_NOT_FOUND;
 117         afu = (struct cxl_afu *)phb->private_data;
 118
 119         if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num)
 120                 return PCIBIOS_DEVICE_NOT_FOUND;
 121         if (offset >= (unsigned long)phb->cfg_data)
 122                 return PCIBIOS_BAD_REGISTER_NUMBER;
 123         addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset);
 124
 125         *ioaddr = (void *)(addr & ~0x3ULL);
 126         *shift = ((addr & 0x3) * 8);
 127         switch (len) {
 128         case 1:
 129                 *mask = 0xff;
 130                 break;
 131         case 2:
 132                 *mask = 0xffff;
 133                 break;
 134         default:
 135                 *mask = 0xffffffff;
 136                 break;
 137         }
 138         return 0;
 139 }
 140
 141 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
 142                                 int offset, int len, u32 *val)
 143 {
 144         volatile void __iomem *ioaddr;
 145         int shift, rc;
 146         u32 mask;
 147
 148         rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
 149                                   &mask, &shift);
 150         if (rc)
 151                 return rc;
 152
 153         /* Can only read 32 bits */
 154         *val = (in_le32(ioaddr) >> shift) & mask;
 155         return PCIBIOS_SUCCESSFUL;
 156 }
 157
 158 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
 159                                  int offset, int len, u32 val)
 160 {
 161         volatile void __iomem *ioaddr;
 162         u32 v, mask;
 163         int shift, rc;
 164
 165         rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
 166                                   &mask, &shift);
 167         if (rc)
 168                 return rc;
 169
 170         /* Can only write 32 bits so do read-modify-write */
 171         mask <<= shift;
 172         val <<= shift;
 173
 174         v = (in_le32(ioaddr) & ~mask) || (val & mask);
 175
 176         out_le32(ioaddr, v);
 177         return PCIBIOS_SUCCESSFUL;
 178 }
 179
 180 static struct pci_ops cxl_pcie_pci_ops =
 181 {
 182         .read = cxl_pcie_read_config,
 183         .write = cxl_pcie_write_config,
 184 };
 185
 186
 187 static struct pci_controller_ops cxl_pci_controller_ops =
 188 {
 189         .probe_mode = cxl_pci_probe_mode,
 190         .enable_device_hook = cxl_pci_enable_device_hook,
 191         .disable_device = cxl_pci_disable_device,
 192         .release_device = cxl_pci_disable_device,
 193         .window_alignment = cxl_pci_window_alignment,
 194         .reset_secondary_bus = cxl_pci_reset_secondary_bus,
 195         .setup_msi_irqs = cxl_setup_msi_irqs,
 196         .teardown_msi_irqs = cxl_teardown_msi_irqs,
 197         .dma_set_mask = cxl_dma_set_mask,
 198 };
 199
 200 int cxl_pci_vphb_add(struct cxl_afu *afu)
 201 {
 202         struct pci_dev *phys_dev;
 203         struct pci_controller *phb, *phys_phb;
 204
 205         phys_dev = to_pci_dev(afu->adapter->dev.parent);
 206         phys_phb = pci_bus_to_host(phys_dev->bus);
 207
 208         /* Alloc and setup PHB data structure */
 209         phb = pcibios_alloc_controller(phys_phb->dn);
 210
 211         if (!phb)
 212                 return -ENODEV;
 213
 214         /* Setup parent in sysfs */
 215         phb->parent = &phys_dev->dev;
 216
 217         /* Setup the PHB using arch provided callback */
 218         phb->ops = &cxl_pcie_pci_ops;
 219         phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
 220         phb->cfg_data = (void *)(u64)afu->crs_len;
 221         phb->private_data = afu;
 222         phb->controller_ops = cxl_pci_controller_ops;
 223
 224         /* Scan the bus */
 225         pcibios_scan_phb(phb);
 226         if (phb->bus == NULL)
 227                 return -ENXIO;
 228
 229         /* Claim resources. This might need some rework as well depending
 230          * whether we are doing probe-only or not, like assigning unassigned
 231          * resources etc...
 232          */
 233         pcibios_claim_one_bus(phb->bus);
 234
 235         /* Add probed PCI devices to the device model */
 236         pci_bus_add_devices(phb->bus);
 237
 238         afu->phb = phb;
 239
 240         return 0;
 241 }
 242
 243
 244 void cxl_pci_vphb_remove(struct cxl_afu *afu)
 245 {
 246         struct pci_controller *phb;
 247
 248         /* If there is no configuration record we won't have one of these */
 249         if (!afu || !afu->phb)
 250                 return;
 251
 252         phb = afu->phb;
 253
 254         pci_remove_root_bus(phb->bus);
 255 }
 256
 257 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
 258 {
 259         struct pci_controller *phb;
 260
 261         phb = pci_bus_to_host(dev->bus);
 262
 263         return (struct cxl_afu *)phb->private_data;
 264 }
 265 EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
 266
 267 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
 268 {
 269         return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
 270 }
 271 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);