drivers/misc/mei/hw-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18
  19 #include <linux/kthread.h>
  20 #include <linux/interrupt.h>
  21
  22 #include "mei_dev.h"
  23 #include "hbm.h"
  24
  25 #include "hw-me.h"
  26 #include "hw-me-regs.h"
  27
  28 #include "mei-trace.h"
  29
  30 /**
  31  * mei_me_reg_read - Reads 32bit data from the mei device
  32  *
  33  * @hw: the me hardware structure
  34  * @offset: offset from which to read the data
  35  *
  36  * Return: register value (u32)
  37  */
  38 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
  39                                unsigned long offset)
  40 {
  41         return ioread32(hw->mem_addr + offset);
  42 }
  43
  44
  45 /**
  46  * mei_me_reg_write - Writes 32bit data to the mei device
  47  *
  48  * @hw: the me hardware structure
  49  * @offset: offset from which to write the data
  50  * @value: register value to write (u32)
  51  */
  52 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
  53                                  unsigned long offset, u32 value)
  54 {
  55         iowrite32(value, hw->mem_addr + offset);
  56 }
  57
  58 /**
  59  * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
  60  *  read window register
  61  *
  62  * @dev: the device structure
  63  *
  64  * Return: ME_CB_RW register value (u32)
  65  */
  66 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
  67 {
  68         return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
  69 }
  70
  71 /**
  72  * mei_me_hcbww_write - write 32bit data to the host circular buffer
  73  *
  74  * @dev: the device structure
  75  * @data: 32bit data to be written to the host circular buffer
  76  */
  77 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
  78 {
  79         mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
  80 }
  81
  82 /**
  83  * mei_me_mecsr_read - Reads 32bit data from the ME CSR
  84  *
  85  * @dev: the device structure
  86  *
  87  * Return: ME_CSR_HA register value (u32)
  88  */
  89 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
  90 {
  91         u32 reg;
  92
  93         reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
  94         trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
  95
  96         return reg;
  97 }
  98
  99 /**
 100  * mei_hcsr_read - Reads 32bit data from the host CSR
 101  *
 102  * @dev: the device structure
 103  *
 104  * Return: H_CSR register value (u32)
 105  */
 106 static inline u32 mei_hcsr_read(const struct mei_device *dev)
 107 {
 108         u32 reg;
 109
 110         reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
 111         trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
 112
 113         return reg;
 114 }
 115
 116 /**
 117  * mei_hcsr_write - writes H_CSR register to the mei device
 118  *
 119  * @dev: the device structure
 120  * @reg: new register value
 121  */
 122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
 123 {
 124         trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
 125         mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
 126 }
 127
 128 /**
 129  * mei_hcsr_set - writes H_CSR register to the mei device,
 130  * and ignores the H_IS bit for it is write-one-to-zero.
 131  *
 132  * @dev: the device structure
 133  * @reg: new register value
 134  */
 135 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
 136 {
 137         reg &= ~H_IS;
 138         mei_hcsr_write(dev, reg);
 139 }
 140
 141 /**
 142  * mei_me_fw_status - read fw status register from pci config space
 143  *
 144  * @dev: mei device
 145  * @fw_status: fw status register values
 146  *
 147  * Return: 0 on success, error otherwise
 148  */
 149 static int mei_me_fw_status(struct mei_device *dev,
 150                             struct mei_fw_status *fw_status)
 151 {
 152         struct pci_dev *pdev = to_pci_dev(dev->dev);
 153         struct mei_me_hw *hw = to_me_hw(dev);
 154         const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
 155         int ret;
 156         int i;
 157
 158         if (!fw_status)
 159                 return -EINVAL;
 160
 161         fw_status->count = fw_src->count;
 162         for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
 163                 ret = pci_read_config_dword(pdev,
 164                         fw_src->status[i], &fw_status->status[i]);
 165                 if (ret)
 166                         return ret;
 167         }
 168
 169         return 0;
 170 }
 171
 172 /**
 173  * mei_me_hw_config - configure hw dependent settings
 174  *
 175  * @dev: mei device
 176  */
 177 static void mei_me_hw_config(struct mei_device *dev)
 178 {
 179         struct mei_me_hw *hw = to_me_hw(dev);
 180         u32 hcsr = mei_hcsr_read(dev);
 181         /* Doesn't change in runtime */
 182         dev->hbuf_depth = (hcsr & H_CBD) >> 24;
 183
 184         hw->pg_state = MEI_PG_OFF;
 185 }
 186
 187 /**
 188  * mei_me_pg_state  - translate internal pg state
 189  *   to the mei power gating state
 190  *
 191  * @dev:  mei device
 192  *
 193  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
 194  */
 195 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
 196 {
 197         struct mei_me_hw *hw = to_me_hw(dev);
 198
 199         return hw->pg_state;
 200 }
 201
 202 /**
 203  * mei_me_intr_clear - clear and stop interrupts
 204  *
 205  * @dev: the device structure
 206  */
 207 static void mei_me_intr_clear(struct mei_device *dev)
 208 {
 209         u32 hcsr = mei_hcsr_read(dev);
 210
 211         if ((hcsr & H_IS) == H_IS)
 212                 mei_hcsr_write(dev, hcsr);
 213 }
 214 /**
 215  * mei_me_intr_enable - enables mei device interrupts
 216  *
 217  * @dev: the device structure
 218  */
 219 static void mei_me_intr_enable(struct mei_device *dev)
 220 {
 221         u32 hcsr = mei_hcsr_read(dev);
 222
 223         hcsr |= H_IE;
 224         mei_hcsr_set(dev, hcsr);
 225 }
 226
 227 /**
 228  * mei_me_intr_disable - disables mei device interrupts
 229  *
 230  * @dev: the device structure
 231  */
 232 static void mei_me_intr_disable(struct mei_device *dev)
 233 {
 234         u32 hcsr = mei_hcsr_read(dev);
 235
 236         hcsr  &= ~H_IE;
 237         mei_hcsr_set(dev, hcsr);
 238 }
 239
 240 /**
 241  * mei_me_hw_reset_release - release device from the reset
 242  *
 243  * @dev: the device structure
 244  */
 245 static void mei_me_hw_reset_release(struct mei_device *dev)
 246 {
 247         u32 hcsr = mei_hcsr_read(dev);
 248
 249         hcsr |= H_IG;
 250         hcsr &= ~H_RST;
 251         mei_hcsr_set(dev, hcsr);
 252
 253         /* complete this write before we set host ready on another CPU */
 254         mmiowb();
 255 }
 256 /**
 257  * mei_me_hw_reset - resets fw via mei csr register.
 258  *
 259  * @dev: the device structure
 260  * @intr_enable: if interrupt should be enabled after reset.
 261  *
 262  * Return: always 0
 263  */
 264 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 265 {
 266         u32 hcsr = mei_hcsr_read(dev);
 267
 268         /* H_RST may be found lit before reset is started,
 269          * for example if preceding reset flow hasn't completed.
 270          * In that case asserting H_RST will be ignored, therefore
 271          * we need to clean H_RST bit to start a successful reset sequence.
 272          */
 273         if ((hcsr & H_RST) == H_RST) {
 274                 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
 275                 hcsr &= ~H_RST;
 276                 mei_hcsr_set(dev, hcsr);
 277                 hcsr = mei_hcsr_read(dev);
 278         }
 279
 280         hcsr |= H_RST | H_IG | H_IS;
 281
 282         if (intr_enable)
 283                 hcsr |= H_IE;
 284         else
 285                 hcsr &= ~H_IE;
 286
 287         dev->recvd_hw_ready = false;
 288         mei_hcsr_write(dev, hcsr);
 289
 290         /*
 291          * Host reads the H_CSR once to ensure that the
 292          * posted write to H_CSR completes.
 293          */
 294         hcsr = mei_hcsr_read(dev);
 295
 296         if ((hcsr & H_RST) == 0)
 297                 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
 298
 299         if ((hcsr & H_RDY) == H_RDY)
 300                 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
 301
 302         if (intr_enable == false)
 303                 mei_me_hw_reset_release(dev);
 304
 305         return 0;
 306 }
 307
 308 /**
 309  * mei_me_host_set_ready - enable device
 310  *
 311  * @dev: mei device
 312  */
 313 static void mei_me_host_set_ready(struct mei_device *dev)
 314 {
 315         u32 hcsr = mei_hcsr_read(dev);
 316
 317         hcsr |= H_IE | H_IG | H_RDY;
 318         mei_hcsr_set(dev, hcsr);
 319 }
 320
 321 /**
 322  * mei_me_host_is_ready - check whether the host has turned ready
 323  *
 324  * @dev: mei device
 325  * Return: bool
 326  */
 327 static bool mei_me_host_is_ready(struct mei_device *dev)
 328 {
 329         u32 hcsr = mei_hcsr_read(dev);
 330
 331         return (hcsr & H_RDY) == H_RDY;
 332 }
 333
 334 /**
 335  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
 336  *
 337  * @dev: mei device
 338  * Return: bool
 339  */
 340 static bool mei_me_hw_is_ready(struct mei_device *dev)
 341 {
 342         u32 mecsr = mei_me_mecsr_read(dev);
 343
 344         return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
 345 }
 346
 347 /**
 348  * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
 349  *  or timeout is reached
 350  *
 351  * @dev: mei device
 352  * Return: 0 on success, error otherwise
 353  */
 354 static int mei_me_hw_ready_wait(struct mei_device *dev)
 355 {
 356         mutex_unlock(&dev->device_lock);
 357         wait_event_timeout(dev->wait_hw_ready,
 358                         dev->recvd_hw_ready,
 359                         mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
 360         mutex_lock(&dev->device_lock);
 361         if (!dev->recvd_hw_ready) {
 362                 dev_err(dev->dev, "wait hw ready failed\n");
 363                 return -ETIME;
 364         }
 365
 366         mei_me_hw_reset_release(dev);
 367         dev->recvd_hw_ready = false;
 368         return 0;
 369 }
 370
 371 /**
 372  * mei_me_hw_start - hw start routine
 373  *
 374  * @dev: mei device
 375  * Return: 0 on success, error otherwise
 376  */
 377 static int mei_me_hw_start(struct mei_device *dev)
 378 {
 379         int ret = mei_me_hw_ready_wait(dev);
 380
 381         if (ret)
 382                 return ret;
 383         dev_dbg(dev->dev, "hw is ready\n");
 384
 385         mei_me_host_set_ready(dev);
 386         return ret;
 387 }
 388
 389
 390 /**
 391  * mei_hbuf_filled_slots - gets number of device filled buffer slots
 392  *
 393  * @dev: the device structure
 394  *
 395  * Return: number of filled slots
 396  */
 397 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
 398 {
 399         u32 hcsr;
 400         char read_ptr, write_ptr;
 401
 402         hcsr = mei_hcsr_read(dev);
 403
 404         read_ptr = (char) ((hcsr & H_CBRP) >> 8);
 405         write_ptr = (char) ((hcsr & H_CBWP) >> 16);
 406
 407         return (unsigned char) (write_ptr - read_ptr);
 408 }
 409
 410 /**
 411  * mei_me_hbuf_is_empty - checks if host buffer is empty.
 412  *
 413  * @dev: the device structure
 414  *
 415  * Return: true if empty, false - otherwise.
 416  */
 417 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
 418 {
 419         return mei_hbuf_filled_slots(dev) == 0;
 420 }
 421
 422 /**
 423  * mei_me_hbuf_empty_slots - counts write empty slots.
 424  *
 425  * @dev: the device structure
 426  *
 427  * Return: -EOVERFLOW if overflow, otherwise empty slots count
 428  */
 429 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
 430 {
 431         unsigned char filled_slots, empty_slots;
 432
 433         filled_slots = mei_hbuf_filled_slots(dev);
 434         empty_slots = dev->hbuf_depth - filled_slots;
 435
 436         /* check for overflow */
 437         if (filled_slots > dev->hbuf_depth)
 438                 return -EOVERFLOW;
 439
 440         return empty_slots;
 441 }
 442
 443 /**
 444  * mei_me_hbuf_max_len - returns size of hw buffer.
 445  *
 446  * @dev: the device structure
 447  *
 448  * Return: size of hw buffer in bytes
 449  */
 450 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
 451 {
 452         return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
 453 }
 454
 455
 456 /**
 457  * mei_me_write_message - writes a message to mei device.
 458  *
 459  * @dev: the device structure
 460  * @header: mei HECI header of message
 461  * @buf: message payload will be written
 462  *
 463  * Return: -EIO if write has failed
 464  */
 465 static int mei_me_write_message(struct mei_device *dev,
 466                         struct mei_msg_hdr *header,
 467                         unsigned char *buf)
 468 {
 469         unsigned long rem;
 470         unsigned long length = header->length;
 471         u32 *reg_buf = (u32 *)buf;
 472         u32 hcsr;
 473         u32 dw_cnt;
 474         int i;
 475         int empty_slots;
 476
 477         dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 478
 479         empty_slots = mei_hbuf_empty_slots(dev);
 480         dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
 481
 482         dw_cnt = mei_data2slots(length);
 483         if (empty_slots < 0 || dw_cnt > empty_slots)
 484                 return -EMSGSIZE;
 485
 486         mei_me_hcbww_write(dev, *((u32 *) header));
 487
 488         for (i = 0; i < length / 4; i++)
 489                 mei_me_hcbww_write(dev, reg_buf[i]);
 490
 491         rem = length & 0x3;
 492         if (rem > 0) {
 493                 u32 reg = 0;
 494
 495                 memcpy(&reg, &buf[length - rem], rem);
 496                 mei_me_hcbww_write(dev, reg);
 497         }
 498
 499         hcsr = mei_hcsr_read(dev) | H_IG;
 500         mei_hcsr_set(dev, hcsr);
 501         if (!mei_me_hw_is_ready(dev))
 502                 return -EIO;
 503
 504         return 0;
 505 }
 506
 507 /**
 508  * mei_me_count_full_read_slots - counts read full slots.
 509  *
 510  * @dev: the device structure
 511  *
 512  * Return: -EOVERFLOW if overflow, otherwise filled slots count
 513  */
 514 static int mei_me_count_full_read_slots(struct mei_device *dev)
 515 {
 516         u32 me_csr;
 517         char read_ptr, write_ptr;
 518         unsigned char buffer_depth, filled_slots;
 519
 520         me_csr = mei_me_mecsr_read(dev);
 521         buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
 522         read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
 523         write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
 524         filled_slots = (unsigned char) (write_ptr - read_ptr);
 525
 526         /* check for overflow */
 527         if (filled_slots > buffer_depth)
 528                 return -EOVERFLOW;
 529
 530         dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
 531         return (int)filled_slots;
 532 }
 533
 534 /**
 535  * mei_me_read_slots - reads a message from mei device.
 536  *
 537  * @dev: the device structure
 538  * @buffer: message buffer will be written
 539  * @buffer_length: message size will be read
 540  *
 541  * Return: always 0
 542  */
 543 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
 544                     unsigned long buffer_length)
 545 {
 546         u32 *reg_buf = (u32 *)buffer;
 547         u32 hcsr;
 548
 549         for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
 550                 *reg_buf++ = mei_me_mecbrw_read(dev);
 551
 552         if (buffer_length > 0) {
 553                 u32 reg = mei_me_mecbrw_read(dev);
 554
 555                 memcpy(reg_buf, &reg, buffer_length);
 556         }
 557
 558         hcsr = mei_hcsr_read(dev) | H_IG;
 559         mei_hcsr_set(dev, hcsr);
 560         return 0;
 561 }
 562
 563 /**
 564  * mei_me_pg_set - write pg enter register
 565  *
 566  * @dev: the device structure
 567  */
 568 static void mei_me_pg_set(struct mei_device *dev)
 569 {
 570         struct mei_me_hw *hw = to_me_hw(dev);
 571         u32 reg;
 572
 573         reg = mei_me_reg_read(hw, H_HPG_CSR);
 574         trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 575
 576         reg |= H_HPG_CSR_PGI;
 577
 578         trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 579         mei_me_reg_write(hw, H_HPG_CSR, reg);
 580 }
 581
 582 /**
 583  * mei_me_pg_unset - write pg exit register
 584  *
 585  * @dev: the device structure
 586  */
 587 static void mei_me_pg_unset(struct mei_device *dev)
 588 {
 589         struct mei_me_hw *hw = to_me_hw(dev);
 590         u32 reg;
 591
 592         reg = mei_me_reg_read(hw, H_HPG_CSR);
 593         trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 594
 595         WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
 596
 597         reg |= H_HPG_CSR_PGIHEXR;
 598
 599         trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 600         mei_me_reg_write(hw, H_HPG_CSR, reg);
 601 }
 602
 603 /**
 604  * mei_me_pg_enter_sync - perform pg entry procedure
 605  *
 606  * @dev: the device structure
 607  *
 608  * Return: 0 on success an error code otherwise
 609  */
 610 int mei_me_pg_enter_sync(struct mei_device *dev)
 611 {
 612         struct mei_me_hw *hw = to_me_hw(dev);
 613         unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
 614         int ret;
 615
 616         dev->pg_event = MEI_PG_EVENT_WAIT;
 617
 618         ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
 619         if (ret)
 620                 return ret;
 621
 622         mutex_unlock(&dev->device_lock);
 623         wait_event_timeout(dev->wait_pg,
 624                 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 625         mutex_lock(&dev->device_lock);
 626
 627         if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
 628                 mei_me_pg_set(dev);
 629                 ret = 0;
 630         } else {
 631                 ret = -ETIME;
 632         }
 633
 634         dev->pg_event = MEI_PG_EVENT_IDLE;
 635         hw->pg_state = MEI_PG_ON;
 636
 637         return ret;
 638 }
 639
 640 /**
 641  * mei_me_pg_exit_sync - perform pg exit procedure
 642  *
 643  * @dev: the device structure
 644  *
 645  * Return: 0 on success an error code otherwise
 646  */
 647 int mei_me_pg_exit_sync(struct mei_device *dev)
 648 {
 649         struct mei_me_hw *hw = to_me_hw(dev);
 650         unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
 651         int ret;
 652
 653         if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
 654                 goto reply;
 655
 656         dev->pg_event = MEI_PG_EVENT_WAIT;
 657
 658         mei_me_pg_unset(dev);
 659
 660         mutex_unlock(&dev->device_lock);
 661         wait_event_timeout(dev->wait_pg,
 662                 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 663         mutex_lock(&dev->device_lock);
 664
 665 reply:
 666         if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
 667                 ret = -ETIME;
 668                 goto out;
 669         }
 670
 671         dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
 672         ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
 673         if (ret)
 674                 return ret;
 675
 676         mutex_unlock(&dev->device_lock);
 677         wait_event_timeout(dev->wait_pg,
 678                 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
 679         mutex_lock(&dev->device_lock);
 680
 681         if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
 682                 ret = 0;
 683         else
 684                 ret = -ETIME;
 685
 686 out:
 687         dev->pg_event = MEI_PG_EVENT_IDLE;
 688         hw->pg_state = MEI_PG_OFF;
 689
 690         return ret;
 691 }
 692
 693 /**
 694  * mei_me_pg_in_transition - is device now in pg transition
 695  *
 696  * @dev: the device structure
 697  *
 698  * Return: true if in pg transition, false otherwise
 699  */
 700 static bool mei_me_pg_in_transition(struct mei_device *dev)
 701 {
 702         return dev->pg_event >= MEI_PG_EVENT_WAIT &&
 703                dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
 704 }
 705
 706 /**
 707  * mei_me_pg_is_enabled - detect if PG is supported by HW
 708  *
 709  * @dev: the device structure
 710  *
 711  * Return: true is pg supported, false otherwise
 712  */
 713 static bool mei_me_pg_is_enabled(struct mei_device *dev)
 714 {
 715         u32 reg = mei_me_mecsr_read(dev);
 716
 717         if ((reg & ME_PGIC_HRA) == 0)
 718                 goto notsupported;
 719
 720         if (!dev->hbm_f_pg_supported)
 721                 goto notsupported;
 722
 723         return true;
 724
 725 notsupported:
 726         dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
 727                 !!(reg & ME_PGIC_HRA),
 728                 dev->version.major_version,
 729                 dev->version.minor_version,
 730                 HBM_MAJOR_VERSION_PGI,
 731                 HBM_MINOR_VERSION_PGI);
 732
 733         return false;
 734 }
 735
 736 /**
 737  * mei_me_pg_intr - perform pg processing in interrupt thread handler
 738  *
 739  * @dev: the device structure
 740  */
 741 static void mei_me_pg_intr(struct mei_device *dev)
 742 {
 743         struct mei_me_hw *hw = to_me_hw(dev);
 744
 745         if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
 746                 return;
 747
 748         dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
 749         hw->pg_state = MEI_PG_OFF;
 750         if (waitqueue_active(&dev->wait_pg))
 751                 wake_up(&dev->wait_pg);
 752 }
 753
 754 /**
 755  * mei_me_irq_quick_handler - The ISR of the MEI device
 756  *
 757  * @irq: The irq number
 758  * @dev_id: pointer to the device structure
 759  *
 760  * Return: irqreturn_t
 761  */
 762
 763 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
 764 {
 765         struct mei_device *dev = (struct mei_device *) dev_id;
 766         u32 hcsr = mei_hcsr_read(dev);
 767
 768         if ((hcsr & H_IS) != H_IS)
 769                 return IRQ_NONE;
 770
 771         /* clear H_IS bit in H_CSR */
 772         mei_hcsr_write(dev, hcsr);
 773
 774         return IRQ_WAKE_THREAD;
 775 }
 776
 777 /**
 778  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 779  * processing.
 780  *
 781  * @irq: The irq number
 782  * @dev_id: pointer to the device structure
 783  *
 784  * Return: irqreturn_t
 785  *
 786  */
 787 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 788 {
 789         struct mei_device *dev = (struct mei_device *) dev_id;
 790         struct mei_cl_cb complete_list;
 791         s32 slots;
 792         int rets = 0;
 793
 794         dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
 795         /* initialize our complete list */
 796         mutex_lock(&dev->device_lock);
 797         mei_io_list_init(&complete_list);
 798
 799         /* Ack the interrupt here
 800          * In case of MSI we don't go through the quick handler */
 801         if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
 802                 mei_clear_interrupts(dev);
 803
 804         /* check if ME wants a reset */
 805         if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
 806                 dev_warn(dev->dev, "FW not ready: resetting.\n");
 807                 schedule_work(&dev->reset_work);
 808                 goto end;
 809         }
 810
 811         mei_me_pg_intr(dev);
 812
 813         /*  check if we need to start the dev */
 814         if (!mei_host_is_ready(dev)) {
 815                 if (mei_hw_is_ready(dev)) {
 816                         dev_dbg(dev->dev, "we need to start the dev.\n");
 817                         dev->recvd_hw_ready = true;
 818                         wake_up(&dev->wait_hw_ready);
 819                 } else {
 820                         dev_dbg(dev->dev, "Spurious Interrupt\n");
 821                 }
 822                 goto end;
 823         }
 824         /* check slots available for reading */
 825         slots = mei_count_full_read_slots(dev);
 826         while (slots > 0) {
 827                 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
 828                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
 829                 /* There is a race between ME write and interrupt delivery:
 830                  * Not all data is always available immediately after the
 831                  * interrupt, so try to read again on the next interrupt.
 832                  */
 833                 if (rets == -ENODATA)
 834                         break;
 835
 836                 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
 837                         dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
 838                                                 rets);
 839                         schedule_work(&dev->reset_work);
 840                         goto end;
 841                 }
 842         }
 843
 844         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 845
 846         /*
 847          * During PG handshake only allowed write is the replay to the
 848          * PG exit message, so block calling write function
 849          * if the pg event is in PG handshake
 850          */
 851         if (dev->pg_event != MEI_PG_EVENT_WAIT &&
 852             dev->pg_event != MEI_PG_EVENT_RECEIVED) {
 853                 rets = mei_irq_write_handler(dev, &complete_list);
 854                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 855         }
 856
 857         mei_irq_compl_handler(dev, &complete_list);
 858
 859 end:
 860         dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
 861         mutex_unlock(&dev->device_lock);
 862         return IRQ_HANDLED;
 863 }
 864
 865 static const struct mei_hw_ops mei_me_hw_ops = {
 866
 867         .fw_status = mei_me_fw_status,
 868         .pg_state  = mei_me_pg_state,
 869
 870         .host_is_ready = mei_me_host_is_ready,
 871
 872         .hw_is_ready = mei_me_hw_is_ready,
 873         .hw_reset = mei_me_hw_reset,
 874         .hw_config = mei_me_hw_config,
 875         .hw_start = mei_me_hw_start,
 876
 877         .pg_in_transition = mei_me_pg_in_transition,
 878         .pg_is_enabled = mei_me_pg_is_enabled,
 879
 880         .intr_clear = mei_me_intr_clear,
 881         .intr_enable = mei_me_intr_enable,
 882         .intr_disable = mei_me_intr_disable,
 883
 884         .hbuf_free_slots = mei_me_hbuf_empty_slots,
 885         .hbuf_is_ready = mei_me_hbuf_is_empty,
 886         .hbuf_max_len = mei_me_hbuf_max_len,
 887
 888         .write = mei_me_write_message,
 889
 890         .rdbuf_full_slots = mei_me_count_full_read_slots,
 891         .read_hdr = mei_me_mecbrw_read,
 892         .read = mei_me_read_slots
 893 };
 894
 895 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
 896 {
 897         u32 reg;
 898
 899         pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
 900         /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
 901         return (reg & 0x600) == 0x200;
 902 }
 903
 904 #define MEI_CFG_FW_NM                           \
 905         .quirk_probe = mei_me_fw_type_nm
 906
 907 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
 908 {
 909         u32 reg;
 910         /* Read ME FW Status check for SPS Firmware */
 911         pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
 912         /* if bits [19:16] = 15, running SPS Firmware */
 913         return (reg & 0xf0000) == 0xf0000;
 914 }
 915
 916 #define MEI_CFG_FW_SPS                           \
 917         .quirk_probe = mei_me_fw_type_sps
 918
 919
 920 #define MEI_CFG_LEGACY_HFS                      \
 921         .fw_status.count = 0
 922
 923 #define MEI_CFG_ICH_HFS                        \
 924         .fw_status.count = 1,                   \
 925         .fw_status.status[0] = PCI_CFG_HFS_1
 926
 927 #define MEI_CFG_PCH_HFS                         \
 928         .fw_status.count = 2,                   \
 929         .fw_status.status[0] = PCI_CFG_HFS_1,   \
 930         .fw_status.status[1] = PCI_CFG_HFS_2
 931
 932 #define MEI_CFG_PCH8_HFS                        \
 933         .fw_status.count = 6,                   \
 934         .fw_status.status[0] = PCI_CFG_HFS_1,   \
 935         .fw_status.status[1] = PCI_CFG_HFS_2,   \
 936         .fw_status.status[2] = PCI_CFG_HFS_3,   \
 937         .fw_status.status[3] = PCI_CFG_HFS_4,   \
 938         .fw_status.status[4] = PCI_CFG_HFS_5,   \
 939         .fw_status.status[5] = PCI_CFG_HFS_6
 940
 941 /* ICH Legacy devices */
 942 const struct mei_cfg mei_me_legacy_cfg = {
 943         MEI_CFG_LEGACY_HFS,
 944 };
 945
 946 /* ICH devices */
 947 const struct mei_cfg mei_me_ich_cfg = {
 948         MEI_CFG_ICH_HFS,
 949 };
 950
 951 /* PCH devices */
 952 const struct mei_cfg mei_me_pch_cfg = {
 953         MEI_CFG_PCH_HFS,
 954 };
 955
 956
 957 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
 958 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
 959         MEI_CFG_PCH_HFS,
 960         MEI_CFG_FW_NM,
 961 };
 962
 963 /* PCH8 Lynx Point and newer devices */
 964 const struct mei_cfg mei_me_pch8_cfg = {
 965         MEI_CFG_PCH8_HFS,
 966 };
 967
 968 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
 969 const struct mei_cfg mei_me_pch8_sps_cfg = {
 970         MEI_CFG_PCH8_HFS,
 971         MEI_CFG_FW_SPS,
 972 };
 973
 974 /**
 975  * mei_me_dev_init - allocates and initializes the mei device structure
 976  *
 977  * @pdev: The pci device structure
 978  * @cfg: per device generation config
 979  *
 980  * Return: The mei_device_device pointer on success, NULL on failure.
 981  */
 982 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
 983                                    const struct mei_cfg *cfg)
 984 {
 985         struct mei_device *dev;
 986         struct mei_me_hw *hw;
 987
 988         dev = kzalloc(sizeof(struct mei_device) +
 989                          sizeof(struct mei_me_hw), GFP_KERNEL);
 990         if (!dev)
 991                 return NULL;
 992         hw = to_me_hw(dev);
 993
 994         mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);
 995         hw->cfg = cfg;
 996         return dev;
 997 }
 998