drivers/phy/phy-rcar-gen2.c

   1 /*
   2  * Renesas R-Car Gen2 PHY driver
   3  *
   4  * Copyright (C) 2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spinlock.h>
  20
  21 #include <asm/cmpxchg.h>
  22
  23 #define USBHS_LPSTS                     0x02
  24 #define USBHS_UGCTRL                    0x80
  25 #define USBHS_UGCTRL2                   0x84
  26 #define USBHS_UGSTS                     0x88    /* From technical update */
  27
  28 /* Low Power Status register (LPSTS) */
  29 #define USBHS_LPSTS_SUSPM               0x4000
  30
  31 /* USB General control register (UGCTRL) */
  32 #define USBHS_UGCTRL_CONNECT            0x00000004
  33 #define USBHS_UGCTRL_PLLRESET           0x00000001
  34
  35 /* USB General control register 2 (UGCTRL2) */
  36 #define USBHS_UGCTRL2_USB2SEL           0x80000000
  37 #define USBHS_UGCTRL2_USB2SEL_PCI       0x00000000
  38 #define USBHS_UGCTRL2_USB2SEL_USB30     0x80000000
  39 #define USBHS_UGCTRL2_USB0SEL           0x00000030
  40 #define USBHS_UGCTRL2_USB0SEL_PCI       0x00000010
  41 #define USBHS_UGCTRL2_USB0SEL_HS_USB    0x00000030
  42
  43 /* USB General status register (UGSTS) */
  44 #define USBHS_UGSTS_LOCK                0x00000100 /* From technical update */
  45
  46 #define PHYS_PER_CHANNEL        2
  47
  48 struct rcar_gen2_phy {
  49         struct phy *phy;
  50         struct rcar_gen2_channel *channel;
  51         int number;
  52         u32 select_value;
  53 };
  54
  55 struct rcar_gen2_channel {
  56         struct device_node *of_node;
  57         struct rcar_gen2_phy_driver *drv;
  58         struct rcar_gen2_phy phys[PHYS_PER_CHANNEL];
  59         int selected_phy;
  60         u32 select_mask;
  61 };
  62
  63 struct rcar_gen2_phy_driver {
  64         void __iomem *base;
  65         struct clk *clk;
  66         spinlock_t lock;
  67         int num_channels;
  68         struct rcar_gen2_channel *channels;
  69 };
  70
  71 static int rcar_gen2_phy_init(struct phy *p)
  72 {
  73         struct rcar_gen2_phy *phy = phy_get_drvdata(p);
  74         struct rcar_gen2_channel *channel = phy->channel;
  75         struct rcar_gen2_phy_driver *drv = channel->drv;
  76         unsigned long flags;
  77         u32 ugctrl2;
  78
  79         /*
  80          * Try to acquire exclusive access to PHY.  The first driver calling
  81          * phy_init()  on a given channel wins, and all attempts  to use another
  82          * PHY on this channel will fail until phy_exit() is called by the first
  83          * driver.   Achieving this with cmpxcgh() should be SMP-safe.
  84          */
  85         if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1)
  86                 return -EBUSY;
  87
  88         clk_prepare_enable(drv->clk);
  89
  90         spin_lock_irqsave(&drv->lock, flags);
  91         ugctrl2 = readl(drv->base + USBHS_UGCTRL2);
  92         ugctrl2 &= ~channel->select_mask;
  93         ugctrl2 |= phy->select_value;
  94         writel(ugctrl2, drv->base + USBHS_UGCTRL2);
  95         spin_unlock_irqrestore(&drv->lock, flags);
  96         return 0;
  97 }
  98
  99 static int rcar_gen2_phy_exit(struct phy *p)
 100 {
 101         struct rcar_gen2_phy *phy = phy_get_drvdata(p);
 102         struct rcar_gen2_channel *channel = phy->channel;
 103
 104         clk_disable_unprepare(channel->drv->clk);
 105
 106         channel->selected_phy = -1;
 107
 108         return 0;
 109 }
 110
 111 static int rcar_gen2_phy_power_on(struct phy *p)
 112 {
 113         struct rcar_gen2_phy *phy = phy_get_drvdata(p);
 114         struct rcar_gen2_phy_driver *drv = phy->channel->drv;
 115         void __iomem *base = drv->base;
 116         unsigned long flags;
 117         u32 value;
 118         int err = 0, i;
 119
 120         /* Skip if it's not USBHS */
 121         if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
 122                 return 0;
 123
 124         spin_lock_irqsave(&drv->lock, flags);
 125
 126         /* Power on USBHS PHY */
 127         value = readl(base + USBHS_UGCTRL);
 128         value &= ~USBHS_UGCTRL_PLLRESET;
 129         writel(value, base + USBHS_UGCTRL);
 130
 131         value = readw(base + USBHS_LPSTS);
 132         value |= USBHS_LPSTS_SUSPM;
 133         writew(value, base + USBHS_LPSTS);
 134
 135         for (i = 0; i < 20; i++) {
 136                 value = readl(base + USBHS_UGSTS);
 137                 if ((value & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
 138                         value = readl(base + USBHS_UGCTRL);
 139                         value |= USBHS_UGCTRL_CONNECT;
 140                         writel(value, base + USBHS_UGCTRL);
 141                         goto out;
 142                 }
 143                 udelay(1);
 144         }
 145
 146         /* Timed out waiting for the PLL lock */
 147         err = -ETIMEDOUT;
 148
 149 out:
 150         spin_unlock_irqrestore(&drv->lock, flags);
 151
 152         return err;
 153 }
 154
 155 static int rcar_gen2_phy_power_off(struct phy *p)
 156 {
 157         struct rcar_gen2_phy *phy = phy_get_drvdata(p);
 158         struct rcar_gen2_phy_driver *drv = phy->channel->drv;
 159         void __iomem *base = drv->base;
 160         unsigned long flags;
 161         u32 value;
 162
 163         /* Skip if it's not USBHS */
 164         if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
 165                 return 0;
 166
 167         spin_lock_irqsave(&drv->lock, flags);
 168
 169         /* Power off USBHS PHY */
 170         value = readl(base + USBHS_UGCTRL);
 171         value &= ~USBHS_UGCTRL_CONNECT;
 172         writel(value, base + USBHS_UGCTRL);
 173
 174         value = readw(base + USBHS_LPSTS);
 175         value &= ~USBHS_LPSTS_SUSPM;
 176         writew(value, base + USBHS_LPSTS);
 177
 178         value = readl(base + USBHS_UGCTRL);
 179         value |= USBHS_UGCTRL_PLLRESET;
 180         writel(value, base + USBHS_UGCTRL);
 181
 182         spin_unlock_irqrestore(&drv->lock, flags);
 183
 184         return 0;
 185 }
 186
 187 static struct phy_ops rcar_gen2_phy_ops = {
 188         .init           = rcar_gen2_phy_init,
 189         .exit           = rcar_gen2_phy_exit,
 190         .power_on       = rcar_gen2_phy_power_on,
 191         .power_off      = rcar_gen2_phy_power_off,
 192         .owner          = THIS_MODULE,
 193 };
 194
 195 static const struct of_device_id rcar_gen2_phy_match_table[] = {
 196         { .compatible = "renesas,usb-phy-r8a7790" },
 197         { .compatible = "renesas,usb-phy-r8a7791" },
 198         { .compatible = "renesas,usb-phy-r8a7794" },
 199         { }
 200 };
 201 MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table);
 202
 203 static struct phy *rcar_gen2_phy_xlate(struct device *dev,
 204                                        struct of_phandle_args *args)
 205 {
 206         struct rcar_gen2_phy_driver *drv;
 207         struct device_node *np = args->np;
 208         int i;
 209
 210         drv = dev_get_drvdata(dev);
 211         if (!drv)
 212                 return ERR_PTR(-EINVAL);
 213
 214         for (i = 0; i < drv->num_channels; i++) {
 215                 if (np == drv->channels[i].of_node)
 216                         break;
 217         }
 218
 219         if (i >= drv->num_channels || args->args[0] >= 2)
 220                 return ERR_PTR(-ENODEV);
 221
 222         return drv->channels[i].phys[args->args[0]].phy;
 223 }
 224
 225 static const u32 select_mask[] = {
 226         [0]     = USBHS_UGCTRL2_USB0SEL,
 227         [2]     = USBHS_UGCTRL2_USB2SEL,
 228 };
 229
 230 static const u32 select_value[][PHYS_PER_CHANNEL] = {
 231         [0]     = { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB },
 232         [2]     = { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 },
 233 };
 234
 235 static int rcar_gen2_phy_probe(struct platform_device *pdev)
 236 {
 237         struct device *dev = &pdev->dev;
 238         struct rcar_gen2_phy_driver *drv;
 239         struct phy_provider *provider;
 240         struct device_node *np;
 241         struct resource *res;
 242         void __iomem *base;
 243         struct clk *clk;
 244         int i = 0;
 245
 246         if (!dev->of_node) {
 247                 dev_err(dev,
 248                         "This driver is required to be instantiated from device tree\n");
 249                 return -EINVAL;
 250         }
 251
 252         clk = devm_clk_get(dev, "usbhs");
 253         if (IS_ERR(clk)) {
 254                 dev_err(dev, "Can't get USBHS clock\n");
 255                 return PTR_ERR(clk);
 256         }
 257
 258         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 259         base = devm_ioremap_resource(dev, res);
 260         if (IS_ERR(base))
 261                 return PTR_ERR(base);
 262
 263         drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
 264         if (!drv)
 265                 return -ENOMEM;
 266
 267         spin_lock_init(&drv->lock);
 268
 269         drv->clk = clk;
 270         drv->base = base;
 271
 272         drv->num_channels = of_get_child_count(dev->of_node);
 273         drv->channels = devm_kcalloc(dev, drv->num_channels,
 274                                      sizeof(struct rcar_gen2_channel),
 275                                      GFP_KERNEL);
 276         if (!drv->channels)
 277                 return -ENOMEM;
 278
 279         for_each_child_of_node(dev->of_node, np) {
 280                 struct rcar_gen2_channel *channel = drv->channels + i;
 281                 u32 channel_num;
 282                 int error, n;
 283
 284                 channel->of_node = np;
 285                 channel->drv = drv;
 286                 channel->selected_phy = -1;
 287
 288                 error = of_property_read_u32(np, "reg", &channel_num);
 289                 if (error || channel_num > 2) {
 290                         dev_err(dev, "Invalid \"reg\" property\n");
 291                         return error;
 292                 }
 293                 channel->select_mask = select_mask[channel_num];
 294
 295                 for (n = 0; n < PHYS_PER_CHANNEL; n++) {
 296                         struct rcar_gen2_phy *phy = &channel->phys[n];
 297
 298                         phy->channel = channel;
 299                         phy->number = n;
 300                         phy->select_value = select_value[channel_num][n];
 301
 302                         phy->phy = devm_phy_create(dev, NULL,
 303                                                    &rcar_gen2_phy_ops);
 304                         if (IS_ERR(phy->phy)) {
 305                                 dev_err(dev, "Failed to create PHY\n");
 306                                 return PTR_ERR(phy->phy);
 307                         }
 308                         phy_set_drvdata(phy->phy, phy);
 309                 }
 310
 311                 i++;
 312         }
 313
 314         provider = devm_of_phy_provider_register(dev, rcar_gen2_phy_xlate);
 315         if (IS_ERR(provider)) {
 316                 dev_err(dev, "Failed to register PHY provider\n");
 317                 return PTR_ERR(provider);
 318         }
 319
 320         dev_set_drvdata(dev, drv);
 321
 322         return 0;
 323 }
 324
 325 static struct platform_driver rcar_gen2_phy_driver = {
 326         .driver = {
 327                 .name           = "phy_rcar_gen2",
 328                 .of_match_table = rcar_gen2_phy_match_table,
 329         },
 330         .probe  = rcar_gen2_phy_probe,
 331 };
 332
 333 module_platform_driver(rcar_gen2_phy_driver);
 334
 335 MODULE_LICENSE("GPL v2");
 336 MODULE_DESCRIPTION("Renesas R-Car Gen2 PHY");
 337 MODULE_AUTHOR("Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>");