drivers/phy/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB phy driver
   3  *
   4  * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
   5  *
   6  * Based on code from
   7  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   8  *
   9  * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  10  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  11  * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/mutex.h>
  30 #include <linux/of.h>
  31 #include <linux/of_address.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/phy/phy-sun4i-usb.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/reset.h>
  37
  38 #define REG_ISCR                        0x00
  39 #define REG_PHYCTL                      0x04
  40 #define REG_PHYBIST                     0x08
  41 #define REG_PHYTUNE                     0x0c
  42
  43 #define PHYCTL_DATA                     BIT(7)
  44
  45 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  46 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  47 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  48 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  49
  50 /* Common Control Bits for Both PHYs */
  51 #define PHY_PLL_BW                      0x03
  52 #define PHY_RES45_CAL_EN                0x0c
  53
  54 /* Private Control Bits for Each PHY */
  55 #define PHY_TX_AMPLITUDE_TUNE           0x20
  56 #define PHY_TX_SLEWRATE_TUNE            0x22
  57 #define PHY_VBUSVALID_TH_SEL            0x25
  58 #define PHY_PULLUP_RES_SEL              0x27
  59 #define PHY_OTG_FUNC_EN                 0x28
  60 #define PHY_VBUS_DET_EN                 0x29
  61 #define PHY_DISCON_TH_SEL               0x2a
  62 #define PHY_SQUELCH_DETECT              0x3c
  63
  64 #define MAX_PHYS                        3
  65
  66 struct sun4i_usb_phy_data {
  67         void __iomem *base;
  68         struct mutex mutex;
  69         int num_phys;
  70         u32 disc_thresh;
  71         struct sun4i_usb_phy {
  72                 struct phy *phy;
  73                 void __iomem *pmu;
  74                 struct regulator *vbus;
  75                 struct reset_control *reset;
  76                 struct clk *clk;
  77                 int index;
  78         } phys[MAX_PHYS];
  79 };
  80
  81 #define to_sun4i_usb_phy_data(phy) \
  82         container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
  83
  84 static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
  85                                 int len)
  86 {
  87         struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
  88         u32 temp, usbc_bit = BIT(phy->index * 2);
  89         int i;
  90
  91         mutex_lock(&phy_data->mutex);
  92
  93         for (i = 0; i < len; i++) {
  94                 temp = readl(phy_data->base + REG_PHYCTL);
  95
  96                 /* clear the address portion */
  97                 temp &= ~(0xff << 8);
  98
  99                 /* set the address */
 100                 temp |= ((addr + i) << 8);
 101                 writel(temp, phy_data->base + REG_PHYCTL);
 102
 103                 /* set the data bit and clear usbc bit*/
 104                 temp = readb(phy_data->base + REG_PHYCTL);
 105                 if (data & 0x1)
 106                         temp |= PHYCTL_DATA;
 107                 else
 108                         temp &= ~PHYCTL_DATA;
 109                 temp &= ~usbc_bit;
 110                 writeb(temp, phy_data->base + REG_PHYCTL);
 111
 112                 /* pulse usbc_bit */
 113                 temp = readb(phy_data->base + REG_PHYCTL);
 114                 temp |= usbc_bit;
 115                 writeb(temp, phy_data->base + REG_PHYCTL);
 116
 117                 temp = readb(phy_data->base + REG_PHYCTL);
 118                 temp &= ~usbc_bit;
 119                 writeb(temp, phy_data->base + REG_PHYCTL);
 120
 121                 data >>= 1;
 122         }
 123         mutex_unlock(&phy_data->mutex);
 124 }
 125
 126 static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
 127 {
 128         u32 bits, reg_value;
 129
 130         if (!phy->pmu)
 131                 return;
 132
 133         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 134                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 135
 136         reg_value = readl(phy->pmu);
 137
 138         if (enable)
 139                 reg_value |= bits;
 140         else
 141                 reg_value &= ~bits;
 142
 143         writel(reg_value, phy->pmu);
 144 }
 145
 146 static int sun4i_usb_phy_init(struct phy *_phy)
 147 {
 148         struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 149         struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 150         int ret;
 151
 152         ret = clk_prepare_enable(phy->clk);
 153         if (ret)
 154                 return ret;
 155
 156         ret = reset_control_deassert(phy->reset);
 157         if (ret) {
 158                 clk_disable_unprepare(phy->clk);
 159                 return ret;
 160         }
 161
 162         /* Enable USB 45 Ohm resistor calibration */
 163         if (phy->index == 0)
 164                 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
 165
 166         /* Adjust PHY's magnitude and rate */
 167         sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 168
 169         /* Disconnect threshold adjustment */
 170         sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
 171
 172         sun4i_usb_phy_passby(phy, 1);
 173
 174         return 0;
 175 }
 176
 177 static int sun4i_usb_phy_exit(struct phy *_phy)
 178 {
 179         struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 180
 181         sun4i_usb_phy_passby(phy, 0);
 182         reset_control_assert(phy->reset);
 183         clk_disable_unprepare(phy->clk);
 184
 185         return 0;
 186 }
 187
 188 static int sun4i_usb_phy_power_on(struct phy *_phy)
 189 {
 190         struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 191         int ret = 0;
 192
 193         if (phy->vbus)
 194                 ret = regulator_enable(phy->vbus);
 195
 196         return ret;
 197 }
 198
 199 static int sun4i_usb_phy_power_off(struct phy *_phy)
 200 {
 201         struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 202
 203         if (phy->vbus)
 204                 regulator_disable(phy->vbus);
 205
 206         return 0;
 207 }
 208
 209 void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
 210 {
 211         struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 212
 213         sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
 214 }
 215 EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
 216
 217 static struct phy_ops sun4i_usb_phy_ops = {
 218         .init           = sun4i_usb_phy_init,
 219         .exit           = sun4i_usb_phy_exit,
 220         .power_on       = sun4i_usb_phy_power_on,
 221         .power_off      = sun4i_usb_phy_power_off,
 222         .owner          = THIS_MODULE,
 223 };
 224
 225 static struct phy *sun4i_usb_phy_xlate(struct device *dev,
 226                                         struct of_phandle_args *args)
 227 {
 228         struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
 229
 230         if (args->args[0] >= data->num_phys)
 231                 return ERR_PTR(-ENODEV);
 232
 233         return data->phys[args->args[0]].phy;
 234 }
 235
 236 static int sun4i_usb_phy_probe(struct platform_device *pdev)
 237 {
 238         struct sun4i_usb_phy_data *data;
 239         struct device *dev = &pdev->dev;
 240         struct device_node *np = dev->of_node;
 241         struct phy_provider *phy_provider;
 242         bool dedicated_clocks;
 243         struct resource *res;
 244         int i;
 245
 246         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 247         if (!data)
 248                 return -ENOMEM;
 249
 250         mutex_init(&data->mutex);
 251
 252         if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
 253                 data->num_phys = 2;
 254         else
 255                 data->num_phys = 3;
 256
 257         if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy") ||
 258             of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
 259                 data->disc_thresh = 3;
 260         else
 261                 data->disc_thresh = 2;
 262
 263         if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
 264                 dedicated_clocks = true;
 265         else
 266                 dedicated_clocks = false;
 267
 268         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
 269         data->base = devm_ioremap_resource(dev, res);
 270         if (IS_ERR(data->base))
 271                 return PTR_ERR(data->base);
 272
 273         for (i = 0; i < data->num_phys; i++) {
 274                 struct sun4i_usb_phy *phy = data->phys + i;
 275                 char name[16];
 276
 277                 snprintf(name, sizeof(name), "usb%d_vbus", i);
 278                 phy->vbus = devm_regulator_get_optional(dev, name);
 279                 if (IS_ERR(phy->vbus)) {
 280                         if (PTR_ERR(phy->vbus) == -EPROBE_DEFER)
 281                                 return -EPROBE_DEFER;
 282                         phy->vbus = NULL;
 283                 }
 284
 285                 if (dedicated_clocks)
 286                         snprintf(name, sizeof(name), "usb%d_phy", i);
 287                 else
 288                         strlcpy(name, "usb_phy", sizeof(name));
 289
 290                 phy->clk = devm_clk_get(dev, name);
 291                 if (IS_ERR(phy->clk)) {
 292                         dev_err(dev, "failed to get clock %s\n", name);
 293                         return PTR_ERR(phy->clk);
 294                 }
 295
 296                 snprintf(name, sizeof(name), "usb%d_reset", i);
 297                 phy->reset = devm_reset_control_get(dev, name);
 298                 if (IS_ERR(phy->reset)) {
 299                         dev_err(dev, "failed to get reset %s\n", name);
 300                         return PTR_ERR(phy->reset);
 301                 }
 302
 303                 if (i) { /* No pmu for usbc0 */
 304                         snprintf(name, sizeof(name), "pmu%d", i);
 305                         res = platform_get_resource_byname(pdev,
 306                                                         IORESOURCE_MEM, name);
 307                         phy->pmu = devm_ioremap_resource(dev, res);
 308                         if (IS_ERR(phy->pmu))
 309                                 return PTR_ERR(phy->pmu);
 310                 }
 311
 312                 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
 313                 if (IS_ERR(phy->phy)) {
 314                         dev_err(dev, "failed to create PHY %d\n", i);
 315                         return PTR_ERR(phy->phy);
 316                 }
 317
 318                 phy->index = i;
 319                 phy_set_drvdata(phy->phy, &data->phys[i]);
 320         }
 321
 322         dev_set_drvdata(dev, data);
 323         phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
 324
 325         return PTR_ERR_OR_ZERO(phy_provider);
 326 }
 327
 328 static const struct of_device_id sun4i_usb_phy_of_match[] = {
 329         { .compatible = "allwinner,sun4i-a10-usb-phy" },
 330         { .compatible = "allwinner,sun5i-a13-usb-phy" },
 331         { .compatible = "allwinner,sun6i-a31-usb-phy" },
 332         { .compatible = "allwinner,sun7i-a20-usb-phy" },
 333         { },
 334 };
 335 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
 336
 337 static struct platform_driver sun4i_usb_phy_driver = {
 338         .probe  = sun4i_usb_phy_probe,
 339         .driver = {
 340                 .of_match_table = sun4i_usb_phy_of_match,
 341                 .name  = "sun4i-usb-phy",
 342         }
 343 };
 344 module_platform_driver(sun4i_usb_phy_driver);
 345
 346 MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
 347 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
 348 MODULE_LICENSE("GPL v2");