drivers/spi/spi-bcm63xx-hsspi.c

   1 /*
   2  * Broadcom BCM63XX High Speed SPI Controller driver
   3  *
   4  * Copyright 2000-2010 Broadcom Corporation
   5  * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
   6  *
   7  * Licensed under the GNU/GPL. See COPYING for details.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/mutex.h>
  22
  23 #define HSSPI_GLOBAL_CTRL_REG                   0x0
  24 #define GLOBAL_CTRL_CS_POLARITY_SHIFT           0
  25 #define GLOBAL_CTRL_CS_POLARITY_MASK            0x000000ff
  26 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT          8
  27 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK           0x0000ff00
  28 #define GLOBAL_CTRL_CLK_GATE_SSOFF              BIT(16)
  29 #define GLOBAL_CTRL_CLK_POLARITY                BIT(17)
  30 #define GLOBAL_CTRL_MOSI_IDLE                   BIT(18)
  31
  32 #define HSSPI_GLOBAL_EXT_TRIGGER_REG            0x4
  33
  34 #define HSSPI_INT_STATUS_REG                    0x8
  35 #define HSSPI_INT_STATUS_MASKED_REG             0xc
  36 #define HSSPI_INT_MASK_REG                      0x10
  37
  38 #define HSSPI_PINGx_CMD_DONE(i)                 BIT((i * 8) + 0)
  39 #define HSSPI_PINGx_RX_OVER(i)                  BIT((i * 8) + 1)
  40 #define HSSPI_PINGx_TX_UNDER(i)                 BIT((i * 8) + 2)
  41 #define HSSPI_PINGx_POLL_TIMEOUT(i)             BIT((i * 8) + 3)
  42 #define HSSPI_PINGx_CTRL_INVAL(i)               BIT((i * 8) + 4)
  43
  44 #define HSSPI_INT_CLEAR_ALL                     0xff001f1f
  45
  46 #define HSSPI_PINGPONG_COMMAND_REG(x)           (0x80 + (x) * 0x40)
  47 #define PINGPONG_CMD_COMMAND_MASK               0xf
  48 #define PINGPONG_COMMAND_NOOP                   0
  49 #define PINGPONG_COMMAND_START_NOW              1
  50 #define PINGPONG_COMMAND_START_TRIGGER          2
  51 #define PINGPONG_COMMAND_HALT                   3
  52 #define PINGPONG_COMMAND_FLUSH                  4
  53 #define PINGPONG_CMD_PROFILE_SHIFT              8
  54 #define PINGPONG_CMD_SS_SHIFT                   12
  55
  56 #define HSSPI_PINGPONG_STATUS_REG(x)            (0x84 + (x) * 0x40)
  57
  58 #define HSSPI_PROFILE_CLK_CTRL_REG(x)           (0x100 + (x) * 0x20)
  59 #define CLK_CTRL_FREQ_CTRL_MASK                 0x0000ffff
  60 #define CLK_CTRL_SPI_CLK_2X_SEL                 BIT(14)
  61 #define CLK_CTRL_ACCUM_RST_ON_LOOP              BIT(15)
  62
  63 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)        (0x104 + (x) * 0x20)
  64 #define SIGNAL_CTRL_LATCH_RISING                BIT(12)
  65 #define SIGNAL_CTRL_LAUNCH_RISING               BIT(13)
  66 #define SIGNAL_CTRL_ASYNC_INPUT_PATH            BIT(16)
  67
  68 #define HSSPI_PROFILE_MODE_CTRL_REG(x)          (0x108 + (x) * 0x20)
  69 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT       8
  70 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT       12
  71 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT       16
  72 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT       18
  73 #define MODE_CTRL_MODE_3WIRE                    BIT(20)
  74 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT         24
  75
  76 #define HSSPI_FIFO_REG(x)                       (0x200 + (x) * 0x200)
  77
  78
  79 #define HSSPI_OP_CODE_SHIFT                     13
  80 #define HSSPI_OP_SLEEP                          (0 << HSSPI_OP_CODE_SHIFT)
  81 #define HSSPI_OP_READ_WRITE                     (1 << HSSPI_OP_CODE_SHIFT)
  82 #define HSSPI_OP_WRITE                          (2 << HSSPI_OP_CODE_SHIFT)
  83 #define HSSPI_OP_READ                           (3 << HSSPI_OP_CODE_SHIFT)
  84 #define HSSPI_OP_SETIRQ                         (4 << HSSPI_OP_CODE_SHIFT)
  85
  86 #define HSSPI_BUFFER_LEN                        512
  87 #define HSSPI_OPCODE_LEN                        2
  88
  89 #define HSSPI_MAX_PREPEND_LEN                   15
  90
  91 #define HSSPI_MAX_SYNC_CLOCK                    30000000
  92
  93 #define HSSPI_BUS_NUM                           1 /* 0 is legacy SPI */
  94
  95 struct bcm63xx_hsspi {
  96         struct completion done;
  97         struct mutex bus_mutex;
  98
  99         struct platform_device *pdev;
 100         struct clk *clk;
 101         void __iomem *regs;
 102         u8 __iomem *fifo;
 103
 104         u32 speed_hz;
 105         u8 cs_polarity;
 106 };
 107
 108 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
 109                                  bool active)
 110 {
 111         u32 reg;
 112
 113         mutex_lock(&bs->bus_mutex);
 114         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 115
 116         reg &= ~BIT(cs);
 117         if (active == !(bs->cs_polarity & BIT(cs)))
 118                 reg |= BIT(cs);
 119
 120         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 121         mutex_unlock(&bs->bus_mutex);
 122 }
 123
 124 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
 125                                   struct spi_device *spi, int hz)
 126 {
 127         unsigned profile = spi->chip_select;
 128         u32 reg;
 129
 130         reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
 131         __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
 132                      bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
 133
 134         reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 135         if (hz > HSSPI_MAX_SYNC_CLOCK)
 136                 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
 137         else
 138                 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
 139         __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 140
 141         mutex_lock(&bs->bus_mutex);
 142         /* setup clock polarity */
 143         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 144         reg &= ~GLOBAL_CTRL_CLK_POLARITY;
 145         if (spi->mode & SPI_CPOL)
 146                 reg |= GLOBAL_CTRL_CLK_POLARITY;
 147         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 148         mutex_unlock(&bs->bus_mutex);
 149 }
 150
 151 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
 152 {
 153         struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 154         unsigned chip_select = spi->chip_select;
 155         u16 opcode = 0;
 156         int pending = t->len;
 157         int step_size = HSSPI_BUFFER_LEN;
 158         const u8 *tx = t->tx_buf;
 159         u8 *rx = t->rx_buf;
 160
 161         bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
 162         bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
 163
 164         if (tx && rx)
 165                 opcode = HSSPI_OP_READ_WRITE;
 166         else if (tx)
 167                 opcode = HSSPI_OP_WRITE;
 168         else if (rx)
 169                 opcode = HSSPI_OP_READ;
 170
 171         if (opcode != HSSPI_OP_READ)
 172                 step_size -= HSSPI_OPCODE_LEN;
 173
 174         __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
 175                      2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
 176                      2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
 177                      bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 178
 179         while (pending > 0) {
 180                 int curr_step = min_t(int, step_size, pending);
 181
 182                 reinit_completion(&bs->done);
 183                 if (tx) {
 184                         memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
 185                         tx += curr_step;
 186                 }
 187
 188                 __raw_writew(opcode | curr_step, bs->fifo);
 189
 190                 /* enable interrupt */
 191                 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
 192                              bs->regs + HSSPI_INT_MASK_REG);
 193
 194                 /* start the transfer */
 195                 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
 196                              chip_select << PINGPONG_CMD_PROFILE_SHIFT |
 197                              PINGPONG_COMMAND_START_NOW,
 198                              bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
 199
 200                 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
 201                         dev_err(&bs->pdev->dev, "transfer timed out!\n");
 202                         return -ETIMEDOUT;
 203                 }
 204
 205                 if (rx) {
 206                         memcpy_fromio(rx, bs->fifo, curr_step);
 207                         rx += curr_step;
 208                 }
 209
 210                 pending -= curr_step;
 211         }
 212
 213         return 0;
 214 }
 215
 216 static int bcm63xx_hsspi_setup(struct spi_device *spi)
 217 {
 218         struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 219         u32 reg;
 220
 221         reg = __raw_readl(bs->regs +
 222                           HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 223         reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
 224         if (spi->mode & SPI_CPHA)
 225                 reg |= SIGNAL_CTRL_LAUNCH_RISING;
 226         else
 227                 reg |= SIGNAL_CTRL_LATCH_RISING;
 228         __raw_writel(reg, bs->regs +
 229                      HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 230
 231         mutex_lock(&bs->bus_mutex);
 232         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 233
 234         /* only change actual polarities if there is no transfer */
 235         if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
 236                 if (spi->mode & SPI_CS_HIGH)
 237                         reg |= BIT(spi->chip_select);
 238                 else
 239                         reg &= ~BIT(spi->chip_select);
 240                 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 241         }
 242
 243         if (spi->mode & SPI_CS_HIGH)
 244                 bs->cs_polarity |= BIT(spi->chip_select);
 245         else
 246                 bs->cs_polarity &= ~BIT(spi->chip_select);
 247
 248         mutex_unlock(&bs->bus_mutex);
 249
 250         return 0;
 251 }
 252
 253 static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
 254                                       struct spi_message *msg)
 255 {
 256         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 257         struct spi_transfer *t;
 258         struct spi_device *spi = msg->spi;
 259         int status = -EINVAL;
 260         int dummy_cs;
 261         u32 reg;
 262
 263         /* This controller does not support keeping CS active during idle.
 264          * To work around this, we use the following ugly hack:
 265          *
 266          * a. Invert the target chip select's polarity so it will be active.
 267          * b. Select a "dummy" chip select to use as the hardware target.
 268          * c. Invert the dummy chip select's polarity so it will be inactive
 269          *    during the actual transfers.
 270          * d. Tell the hardware to send to the dummy chip select. Thanks to
 271          *    the multiplexed nature of SPI the actual target will receive
 272          *    the transfer and we see its response.
 273          *
 274          * e. At the end restore the polarities again to their default values.
 275          */
 276
 277         dummy_cs = !spi->chip_select;
 278         bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
 279
 280         list_for_each_entry(t, &msg->transfers, transfer_list) {
 281                 status = bcm63xx_hsspi_do_txrx(spi, t);
 282                 if (status)
 283                         break;
 284
 285                 msg->actual_length += t->len;
 286
 287                 if (t->delay_usecs)
 288                         udelay(t->delay_usecs);
 289
 290                 if (t->cs_change)
 291                         bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
 292         }
 293
 294         mutex_lock(&bs->bus_mutex);
 295         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 296         reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
 297         reg |= bs->cs_polarity;
 298         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 299         mutex_unlock(&bs->bus_mutex);
 300
 301         msg->status = status;
 302         spi_finalize_current_message(master);
 303
 304         return 0;
 305 }
 306
 307 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
 308 {
 309         struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
 310
 311         if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
 312                 return IRQ_NONE;
 313
 314         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 315         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 316
 317         complete(&bs->done);
 318
 319         return IRQ_HANDLED;
 320 }
 321
 322 static int bcm63xx_hsspi_probe(struct platform_device *pdev)
 323 {
 324         struct spi_master *master;
 325         struct bcm63xx_hsspi *bs;
 326         struct resource *res_mem;
 327         void __iomem *regs;
 328         struct device *dev = &pdev->dev;
 329         struct clk *clk;
 330         int irq, ret;
 331         u32 reg, rate;
 332
 333         irq = platform_get_irq(pdev, 0);
 334         if (irq < 0) {
 335                 dev_err(dev, "no irq\n");
 336                 return -ENXIO;
 337         }
 338
 339         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 340         regs = devm_ioremap_resource(dev, res_mem);
 341         if (IS_ERR(regs))
 342                 return PTR_ERR(regs);
 343
 344         clk = devm_clk_get(dev, "hsspi");
 345
 346         if (IS_ERR(clk))
 347                 return PTR_ERR(clk);
 348
 349         rate = clk_get_rate(clk);
 350         if (!rate)
 351                 return -EINVAL;
 352
 353         ret = clk_prepare_enable(clk);
 354         if (ret)
 355                 return ret;
 356
 357         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 358         if (!master) {
 359                 ret = -ENOMEM;
 360                 goto out_disable_clk;
 361         }
 362
 363         bs = spi_master_get_devdata(master);
 364         bs->pdev = pdev;
 365         bs->clk = clk;
 366         bs->regs = regs;
 367         bs->speed_hz = rate;
 368         bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
 369
 370         mutex_init(&bs->bus_mutex);
 371         init_completion(&bs->done);
 372
 373         master->bus_num = HSSPI_BUS_NUM;
 374         master->num_chipselect = 8;
 375         master->setup = bcm63xx_hsspi_setup;
 376         master->transfer_one_message = bcm63xx_hsspi_transfer_one;
 377         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 378         master->bits_per_word_mask = SPI_BPW_MASK(8);
 379         master->auto_runtime_pm = true;
 380
 381         platform_set_drvdata(pdev, master);
 382
 383         /* Initialize the hardware */
 384         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 385
 386         /* clean up any pending interrupts */
 387         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 388
 389         /* read out default CS polarities */
 390         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 391         bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
 392         __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
 393                      bs->regs + HSSPI_GLOBAL_CTRL_REG);
 394
 395         ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
 396                                pdev->name, bs);
 397
 398         if (ret)
 399                 goto out_put_master;
 400
 401         /* register and we are done */
 402         ret = devm_spi_register_master(dev, master);
 403         if (ret)
 404                 goto out_put_master;
 405
 406         return 0;
 407
 408 out_put_master:
 409         spi_master_put(master);
 410 out_disable_clk:
 411         clk_disable_unprepare(clk);
 412         return ret;
 413 }
 414
 415
 416 static int bcm63xx_hsspi_remove(struct platform_device *pdev)
 417 {
 418         struct spi_master *master = platform_get_drvdata(pdev);
 419         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 420
 421         /* reset the hardware and block queue progress */
 422         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 423         clk_disable_unprepare(bs->clk);
 424
 425         return 0;
 426 }
 427
 428 #ifdef CONFIG_PM_SLEEP
 429 static int bcm63xx_hsspi_suspend(struct device *dev)
 430 {
 431         struct spi_master *master = dev_get_drvdata(dev);
 432         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 433
 434         spi_master_suspend(master);
 435         clk_disable_unprepare(bs->clk);
 436
 437         return 0;
 438 }
 439
 440 static int bcm63xx_hsspi_resume(struct device *dev)
 441 {
 442         struct spi_master *master = dev_get_drvdata(dev);
 443         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 444         int ret;
 445
 446         ret = clk_prepare_enable(bs->clk);
 447         if (ret)
 448                 return ret;
 449
 450         spi_master_resume(master);
 451
 452         return 0;
 453 }
 454 #endif
 455
 456 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
 457                          bcm63xx_hsspi_resume);
 458
 459 static struct platform_driver bcm63xx_hsspi_driver = {
 460         .driver = {
 461                 .name   = "bcm63xx-hsspi",
 462                 .pm     = &bcm63xx_hsspi_pm_ops,
 463         },
 464         .probe          = bcm63xx_hsspi_probe,
 465         .remove         = bcm63xx_hsspi_remove,
 466 };
 467
 468 module_platform_driver(bcm63xx_hsspi_driver);
 469
 470 MODULE_ALIAS("platform:bcm63xx_hsspi");
 471 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
 472 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
 473 MODULE_LICENSE("GPL");