drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <addy.ke@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/of.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/io.h>
  29 #include <linux/dmaengine.h>
  30
  31 #define DRIVER_NAME "rockchip-spi"
  32
  33 /* SPI register offsets */
  34 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  35 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  36 #define ROCKCHIP_SPI_SSIENR                     0x0008
  37 #define ROCKCHIP_SPI_SER                        0x000c
  38 #define ROCKCHIP_SPI_BAUDR                      0x0010
  39 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  40 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  41 #define ROCKCHIP_SPI_TXFLR                      0x001c
  42 #define ROCKCHIP_SPI_RXFLR                      0x0020
  43 #define ROCKCHIP_SPI_SR                         0x0024
  44 #define ROCKCHIP_SPI_IPR                        0x0028
  45 #define ROCKCHIP_SPI_IMR                        0x002c
  46 #define ROCKCHIP_SPI_ISR                        0x0030
  47 #define ROCKCHIP_SPI_RISR                       0x0034
  48 #define ROCKCHIP_SPI_ICR                        0x0038
  49 #define ROCKCHIP_SPI_DMACR                      0x003c
  50 #define ROCKCHIP_SPI_DMATDLR            0x0040
  51 #define ROCKCHIP_SPI_DMARDLR            0x0044
  52 #define ROCKCHIP_SPI_TXDR                       0x0400
  53 #define ROCKCHIP_SPI_RXDR                       0x0800
  54
  55 /* Bit fields in CTRLR0 */
  56 #define CR0_DFS_OFFSET                          0
  57
  58 #define CR0_CFS_OFFSET                          2
  59
  60 #define CR0_SCPH_OFFSET                         6
  61
  62 #define CR0_SCPOL_OFFSET                        7
  63
  64 #define CR0_CSM_OFFSET                          8
  65 #define CR0_CSM_KEEP                            0x0
  66 /* ss_n be high for half sclk_out cycles */
  67 #define CR0_CSM_HALF                            0X1
  68 /* ss_n be high for one sclk_out cycle */
  69 #define CR0_CSM_ONE                                     0x2
  70
  71 /* ss_n to sclk_out delay */
  72 #define CR0_SSD_OFFSET                          10
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is half sclk_out cycles
  76  */
  77 #define CR0_SSD_HALF                            0x0
  78 /*
  79  * The period between ss_n active and
  80  * sclk_out active is one sclk_out cycle
  81  */
  82 #define CR0_SSD_ONE                                     0x1
  83
  84 #define CR0_EM_OFFSET                           11
  85 #define CR0_EM_LITTLE                           0x0
  86 #define CR0_EM_BIG                                      0x1
  87
  88 #define CR0_FBM_OFFSET                          12
  89 #define CR0_FBM_MSB                                     0x0
  90 #define CR0_FBM_LSB                                     0x1
  91
  92 #define CR0_BHT_OFFSET                          13
  93 #define CR0_BHT_16BIT                           0x0
  94 #define CR0_BHT_8BIT                            0x1
  95
  96 #define CR0_RSD_OFFSET                          14
  97
  98 #define CR0_FRF_OFFSET                          16
  99 #define CR0_FRF_SPI                                     0x0
 100 #define CR0_FRF_SSP                                     0x1
 101 #define CR0_FRF_MICROWIRE                       0x2
 102
 103 #define CR0_XFM_OFFSET                          18
 104 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 105 #define CR0_XFM_TR                                      0x0
 106 #define CR0_XFM_TO                                      0x1
 107 #define CR0_XFM_RO                                      0x2
 108
 109 #define CR0_OPM_OFFSET                          20
 110 #define CR0_OPM_MASTER                          0x0
 111 #define CR0_OPM_SLAVE                           0x1
 112
 113 #define CR0_MTM_OFFSET                          0x21
 114
 115 /* Bit fields in SER, 2bit */
 116 #define SER_MASK                                        0x3
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 #define RXBUSY                                          (1 << 0)
 146 #define TXBUSY                                          (1 << 1)
 147
 148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 149 #define MAX_SCLK_OUT            50000000
 150
 151 enum rockchip_ssi_type {
 152         SSI_MOTO_SPI = 0,
 153         SSI_TI_SSP,
 154         SSI_NS_MICROWIRE,
 155 };
 156
 157 struct rockchip_spi_dma_data {
 158         struct dma_chan *ch;
 159         enum dma_transfer_direction direction;
 160         dma_addr_t addr;
 161 };
 162
 163 struct rockchip_spi {
 164         struct device *dev;
 165         struct spi_master *master;
 166
 167         struct clk *spiclk;
 168         struct clk *apb_pclk;
 169
 170         void __iomem *regs;
 171         /*depth of the FIFO buffer */
 172         u32 fifo_len;
 173         /* max bus freq supported */
 174         u32 max_freq;
 175         /* supported slave numbers */
 176         enum rockchip_ssi_type type;
 177
 178         u16 mode;
 179         u8 tmode;
 180         u8 bpw;
 181         u8 n_bytes;
 182         u8 rsd_nsecs;
 183         unsigned len;
 184         u32 speed;
 185
 186         const void *tx;
 187         const void *tx_end;
 188         void *rx;
 189         void *rx_end;
 190
 191         u32 state;
 192         /* protect state */
 193         spinlock_t lock;
 194
 195         struct completion xfer_completion;
 196
 197         u32 use_dma;
 198         struct sg_table tx_sg;
 199         struct sg_table rx_sg;
 200         struct rockchip_spi_dma_data dma_rx;
 201         struct rockchip_spi_dma_data dma_tx;
 202 };
 203
 204 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
 205 {
 206         writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
 207 }
 208
 209 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
 210 {
 211         writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
 212 }
 213
 214 static inline void flush_fifo(struct rockchip_spi *rs)
 215 {
 216         while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
 217                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 218 }
 219
 220 static inline void wait_for_idle(struct rockchip_spi *rs)
 221 {
 222         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 223
 224         do {
 225                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 226                         return;
 227         } while (!time_after(jiffies, timeout));
 228
 229         dev_warn(rs->dev, "spi controller is in busy state!\n");
 230 }
 231
 232 static u32 get_fifo_len(struct rockchip_spi *rs)
 233 {
 234         u32 fifo;
 235
 236         for (fifo = 2; fifo < 32; fifo++) {
 237                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 238                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 239                         break;
 240         }
 241
 242         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 243
 244         return (fifo == 31) ? 0 : fifo;
 245 }
 246
 247 static inline u32 tx_max(struct rockchip_spi *rs)
 248 {
 249         u32 tx_left, tx_room;
 250
 251         tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
 252         tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 253
 254         return min(tx_left, tx_room);
 255 }
 256
 257 static inline u32 rx_max(struct rockchip_spi *rs)
 258 {
 259         u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
 260         u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 261
 262         return min(rx_left, rx_room);
 263 }
 264
 265 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 266 {
 267         u32 ser;
 268         struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
 269
 270         ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
 271
 272         /*
 273          * drivers/spi/spi.c:
 274          * static void spi_set_cs(struct spi_device *spi, bool enable)
 275          * {
 276          *              if (spi->mode & SPI_CS_HIGH)
 277          *                      enable = !enable;
 278          *
 279          *              if (spi->cs_gpio >= 0)
 280          *                      gpio_set_value(spi->cs_gpio, !enable);
 281          *              else if (spi->master->set_cs)
 282          *              spi->master->set_cs(spi, !enable);
 283          * }
 284          *
 285          * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
 286          */
 287         if (!enable)
 288                 ser |= 1 << spi->chip_select;
 289         else
 290                 ser &= ~(1 << spi->chip_select);
 291
 292         writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
 293 }
 294
 295 static int rockchip_spi_prepare_message(struct spi_master *master,
 296                                         struct spi_message *msg)
 297 {
 298         struct rockchip_spi *rs = spi_master_get_devdata(master);
 299         struct spi_device *spi = msg->spi;
 300
 301         rs->mode = spi->mode;
 302
 303         return 0;
 304 }
 305
 306 static void rockchip_spi_handle_err(struct spi_master *master,
 307                                     struct spi_message *msg)
 308 {
 309         unsigned long flags;
 310         struct rockchip_spi *rs = spi_master_get_devdata(master);
 311
 312         spin_lock_irqsave(&rs->lock, flags);
 313
 314         /*
 315          * For DMA mode, we need terminate DMA channel and flush
 316          * fifo for the next transfer if DMA thansfer timeout.
 317          * handle_err() was called by core if transfer failed.
 318          * Maybe it is reasonable for error handling here.
 319          */
 320         if (rs->use_dma) {
 321                 if (rs->state & RXBUSY) {
 322                         dmaengine_terminate_all(rs->dma_rx.ch);
 323                         flush_fifo(rs);
 324                 }
 325
 326                 if (rs->state & TXBUSY)
 327                         dmaengine_terminate_all(rs->dma_tx.ch);
 328         }
 329
 330         spin_unlock_irqrestore(&rs->lock, flags);
 331 }
 332
 333 static int rockchip_spi_unprepare_message(struct spi_master *master,
 334                                           struct spi_message *msg)
 335 {
 336         struct rockchip_spi *rs = spi_master_get_devdata(master);
 337
 338         spi_enable_chip(rs, 0);
 339
 340         return 0;
 341 }
 342
 343 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 344 {
 345         u32 max = tx_max(rs);
 346         u32 txw = 0;
 347
 348         while (max--) {
 349                 if (rs->n_bytes == 1)
 350                         txw = *(u8 *)(rs->tx);
 351                 else
 352                         txw = *(u16 *)(rs->tx);
 353
 354                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 355                 rs->tx += rs->n_bytes;
 356         }
 357 }
 358
 359 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 360 {
 361         u32 max = rx_max(rs);
 362         u32 rxw;
 363
 364         while (max--) {
 365                 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 366                 if (rs->n_bytes == 1)
 367                         *(u8 *)(rs->rx) = (u8)rxw;
 368                 else
 369                         *(u16 *)(rs->rx) = (u16)rxw;
 370                 rs->rx += rs->n_bytes;
 371         }
 372 }
 373
 374 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
 375 {
 376         int remain = 0;
 377
 378         do {
 379                 if (rs->tx) {
 380                         remain = rs->tx_end - rs->tx;
 381                         rockchip_spi_pio_writer(rs);
 382                 }
 383
 384                 if (rs->rx) {
 385                         remain = rs->rx_end - rs->rx;
 386                         rockchip_spi_pio_reader(rs);
 387                 }
 388
 389                 cpu_relax();
 390         } while (remain);
 391
 392         /* If tx, wait until the FIFO data completely. */
 393         if (rs->tx)
 394                 wait_for_idle(rs);
 395
 396         spi_enable_chip(rs, 0);
 397
 398         return 0;
 399 }
 400
 401 static void rockchip_spi_dma_rxcb(void *data)
 402 {
 403         unsigned long flags;
 404         struct rockchip_spi *rs = data;
 405
 406         spin_lock_irqsave(&rs->lock, flags);
 407
 408         rs->state &= ~RXBUSY;
 409         if (!(rs->state & TXBUSY)) {
 410                 spi_enable_chip(rs, 0);
 411                 spi_finalize_current_transfer(rs->master);
 412         }
 413
 414         spin_unlock_irqrestore(&rs->lock, flags);
 415 }
 416
 417 static void rockchip_spi_dma_txcb(void *data)
 418 {
 419         unsigned long flags;
 420         struct rockchip_spi *rs = data;
 421
 422         /* Wait until the FIFO data completely. */
 423         wait_for_idle(rs);
 424
 425         spin_lock_irqsave(&rs->lock, flags);
 426
 427         rs->state &= ~TXBUSY;
 428         if (!(rs->state & RXBUSY)) {
 429                 spi_enable_chip(rs, 0);
 430                 spi_finalize_current_transfer(rs->master);
 431         }
 432
 433         spin_unlock_irqrestore(&rs->lock, flags);
 434 }
 435
 436 static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
 437 {
 438         unsigned long flags;
 439         struct dma_slave_config rxconf, txconf;
 440         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 441
 442         spin_lock_irqsave(&rs->lock, flags);
 443         rs->state &= ~RXBUSY;
 444         rs->state &= ~TXBUSY;
 445         spin_unlock_irqrestore(&rs->lock, flags);
 446
 447         rxdesc = NULL;
 448         if (rs->rx) {
 449                 rxconf.direction = rs->dma_rx.direction;
 450                 rxconf.src_addr = rs->dma_rx.addr;
 451                 rxconf.src_addr_width = rs->n_bytes;
 452                 rxconf.src_maxburst = rs->n_bytes;
 453                 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
 454
 455                 rxdesc = dmaengine_prep_slave_sg(
 456                                 rs->dma_rx.ch,
 457                                 rs->rx_sg.sgl, rs->rx_sg.nents,
 458                                 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
 459
 460                 rxdesc->callback = rockchip_spi_dma_rxcb;
 461                 rxdesc->callback_param = rs;
 462         }
 463
 464         txdesc = NULL;
 465         if (rs->tx) {
 466                 txconf.direction = rs->dma_tx.direction;
 467                 txconf.dst_addr = rs->dma_tx.addr;
 468                 txconf.dst_addr_width = rs->n_bytes;
 469                 txconf.dst_maxburst = rs->n_bytes;
 470                 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
 471
 472                 txdesc = dmaengine_prep_slave_sg(
 473                                 rs->dma_tx.ch,
 474                                 rs->tx_sg.sgl, rs->tx_sg.nents,
 475                                 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
 476
 477                 txdesc->callback = rockchip_spi_dma_txcb;
 478                 txdesc->callback_param = rs;
 479         }
 480
 481         /* rx must be started before tx due to spi instinct */
 482         if (rxdesc) {
 483                 spin_lock_irqsave(&rs->lock, flags);
 484                 rs->state |= RXBUSY;
 485                 spin_unlock_irqrestore(&rs->lock, flags);
 486                 dmaengine_submit(rxdesc);
 487                 dma_async_issue_pending(rs->dma_rx.ch);
 488         }
 489
 490         if (txdesc) {
 491                 spin_lock_irqsave(&rs->lock, flags);
 492                 rs->state |= TXBUSY;
 493                 spin_unlock_irqrestore(&rs->lock, flags);
 494                 dmaengine_submit(txdesc);
 495                 dma_async_issue_pending(rs->dma_tx.ch);
 496         }
 497 }
 498
 499 static void rockchip_spi_config(struct rockchip_spi *rs)
 500 {
 501         u32 div = 0;
 502         u32 dmacr = 0;
 503         int rsd = 0;
 504
 505         u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
 506                 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
 507
 508         cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
 509         cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
 510         cr0 |= (rs->tmode << CR0_XFM_OFFSET);
 511         cr0 |= (rs->type << CR0_FRF_OFFSET);
 512
 513         if (rs->use_dma) {
 514                 if (rs->tx)
 515                         dmacr |= TF_DMA_EN;
 516                 if (rs->rx)
 517                         dmacr |= RF_DMA_EN;
 518         }
 519
 520         if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 521                 rs->speed = MAX_SCLK_OUT;
 522
 523         /* the minimum divsor is 2 */
 524         if (rs->max_freq < 2 * rs->speed) {
 525                 clk_set_rate(rs->spiclk, 2 * rs->speed);
 526                 rs->max_freq = clk_get_rate(rs->spiclk);
 527         }
 528
 529         /* div doesn't support odd number */
 530         div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 531         div = (div + 1) & 0xfffe;
 532
 533         /* Rx sample delay is expressed in parent clock cycles (max 3) */
 534         rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 535                                 1000000000 >> 8);
 536         if (!rsd && rs->rsd_nsecs) {
 537                 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
 538                              rs->max_freq, rs->rsd_nsecs);
 539         } else if (rsd > 3) {
 540                 rsd = 3;
 541                 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 542                              rs->max_freq, rs->rsd_nsecs,
 543                              rsd * 1000000000U / rs->max_freq);
 544         }
 545         cr0 |= rsd << CR0_RSD_OFFSET;
 546
 547         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 548
 549         writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 550         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
 551         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 552
 553         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
 554         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 555         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 556
 557         spi_set_clk(rs, div);
 558
 559         dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 560 }
 561
 562 static int rockchip_spi_transfer_one(
 563                 struct spi_master *master,
 564                 struct spi_device *spi,
 565                 struct spi_transfer *xfer)
 566 {
 567         int ret = 1;
 568         struct rockchip_spi *rs = spi_master_get_devdata(master);
 569
 570         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 571                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 572
 573         if (!xfer->tx_buf && !xfer->rx_buf) {
 574                 dev_err(rs->dev, "No buffer for transfer\n");
 575                 return -EINVAL;
 576         }
 577
 578         rs->speed = xfer->speed_hz;
 579         rs->bpw = xfer->bits_per_word;
 580         rs->n_bytes = rs->bpw >> 3;
 581
 582         rs->tx = xfer->tx_buf;
 583         rs->tx_end = rs->tx + xfer->len;
 584         rs->rx = xfer->rx_buf;
 585         rs->rx_end = rs->rx + xfer->len;
 586         rs->len = xfer->len;
 587
 588         rs->tx_sg = xfer->tx_sg;
 589         rs->rx_sg = xfer->rx_sg;
 590
 591         if (rs->tx && rs->rx)
 592                 rs->tmode = CR0_XFM_TR;
 593         else if (rs->tx)
 594                 rs->tmode = CR0_XFM_TO;
 595         else if (rs->rx)
 596                 rs->tmode = CR0_XFM_RO;
 597
 598         /* we need prepare dma before spi was enabled */
 599         if (master->can_dma && master->can_dma(master, spi, xfer))
 600                 rs->use_dma = 1;
 601         else
 602                 rs->use_dma = 0;
 603
 604         rockchip_spi_config(rs);
 605
 606         if (rs->use_dma) {
 607                 if (rs->tmode == CR0_XFM_RO) {
 608                         /* rx: dma must be prepared first */
 609                         rockchip_spi_prepare_dma(rs);
 610                         spi_enable_chip(rs, 1);
 611                 } else {
 612                         /* tx or tr: spi must be enabled first */
 613                         spi_enable_chip(rs, 1);
 614                         rockchip_spi_prepare_dma(rs);
 615                 }
 616         } else {
 617                 spi_enable_chip(rs, 1);
 618                 ret = rockchip_spi_pio_transfer(rs);
 619         }
 620
 621         return ret;
 622 }
 623
 624 static bool rockchip_spi_can_dma(struct spi_master *master,
 625                                  struct spi_device *spi,
 626                                  struct spi_transfer *xfer)
 627 {
 628         struct rockchip_spi *rs = spi_master_get_devdata(master);
 629
 630         return (xfer->len > rs->fifo_len);
 631 }
 632
 633 static int rockchip_spi_probe(struct platform_device *pdev)
 634 {
 635         int ret = 0;
 636         struct rockchip_spi *rs;
 637         struct spi_master *master;
 638         struct resource *mem;
 639         u32 rsd_nsecs;
 640
 641         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 642         if (!master)
 643                 return -ENOMEM;
 644
 645         platform_set_drvdata(pdev, master);
 646
 647         rs = spi_master_get_devdata(master);
 648         memset(rs, 0, sizeof(struct rockchip_spi));
 649
 650         /* Get basic io resource and map it */
 651         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 652         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 653         if (IS_ERR(rs->regs)) {
 654                 ret =  PTR_ERR(rs->regs);
 655                 goto err_ioremap_resource;
 656         }
 657
 658         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 659         if (IS_ERR(rs->apb_pclk)) {
 660                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 661                 ret = PTR_ERR(rs->apb_pclk);
 662                 goto err_ioremap_resource;
 663         }
 664
 665         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 666         if (IS_ERR(rs->spiclk)) {
 667                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 668                 ret = PTR_ERR(rs->spiclk);
 669                 goto err_ioremap_resource;
 670         }
 671
 672         ret = clk_prepare_enable(rs->apb_pclk);
 673         if (ret) {
 674                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 675                 goto err_ioremap_resource;
 676         }
 677
 678         ret = clk_prepare_enable(rs->spiclk);
 679         if (ret) {
 680                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 681                 goto err_spiclk_enable;
 682         }
 683
 684         spi_enable_chip(rs, 0);
 685
 686         rs->type = SSI_MOTO_SPI;
 687         rs->master = master;
 688         rs->dev = &pdev->dev;
 689         rs->max_freq = clk_get_rate(rs->spiclk);
 690
 691         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 692                                   &rsd_nsecs))
 693                 rs->rsd_nsecs = rsd_nsecs;
 694
 695         rs->fifo_len = get_fifo_len(rs);
 696         if (!rs->fifo_len) {
 697                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 698                 ret = -EINVAL;
 699                 goto err_get_fifo_len;
 700         }
 701
 702         spin_lock_init(&rs->lock);
 703
 704         pm_runtime_set_active(&pdev->dev);
 705         pm_runtime_enable(&pdev->dev);
 706
 707         master->auto_runtime_pm = true;
 708         master->bus_num = pdev->id;
 709         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 710         master->num_chipselect = 2;
 711         master->dev.of_node = pdev->dev.of_node;
 712         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
 713
 714         master->set_cs = rockchip_spi_set_cs;
 715         master->prepare_message = rockchip_spi_prepare_message;
 716         master->unprepare_message = rockchip_spi_unprepare_message;
 717         master->transfer_one = rockchip_spi_transfer_one;
 718         master->handle_err = rockchip_spi_handle_err;
 719
 720         rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
 721         if (!rs->dma_tx.ch)
 722                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 723
 724         rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
 725         if (!rs->dma_rx.ch) {
 726                 if (rs->dma_tx.ch) {
 727                         dma_release_channel(rs->dma_tx.ch);
 728                         rs->dma_tx.ch = NULL;
 729                 }
 730                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 731         }
 732
 733         if (rs->dma_tx.ch && rs->dma_rx.ch) {
 734                 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
 735                 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
 736                 rs->dma_tx.direction = DMA_MEM_TO_DEV;
 737                 rs->dma_rx.direction = DMA_DEV_TO_MEM;
 738
 739                 master->can_dma = rockchip_spi_can_dma;
 740                 master->dma_tx = rs->dma_tx.ch;
 741                 master->dma_rx = rs->dma_rx.ch;
 742         }
 743
 744         ret = devm_spi_register_master(&pdev->dev, master);
 745         if (ret) {
 746                 dev_err(&pdev->dev, "Failed to register master\n");
 747                 goto err_register_master;
 748         }
 749
 750         return 0;
 751
 752 err_register_master:
 753         if (rs->dma_tx.ch)
 754                 dma_release_channel(rs->dma_tx.ch);
 755         if (rs->dma_rx.ch)
 756                 dma_release_channel(rs->dma_rx.ch);
 757 err_get_fifo_len:
 758         clk_disable_unprepare(rs->spiclk);
 759 err_spiclk_enable:
 760         clk_disable_unprepare(rs->apb_pclk);
 761 err_ioremap_resource:
 762         spi_master_put(master);
 763
 764         return ret;
 765 }
 766
 767 static int rockchip_spi_remove(struct platform_device *pdev)
 768 {
 769         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 770         struct rockchip_spi *rs = spi_master_get_devdata(master);
 771
 772         pm_runtime_disable(&pdev->dev);
 773
 774         clk_disable_unprepare(rs->spiclk);
 775         clk_disable_unprepare(rs->apb_pclk);
 776
 777         if (rs->dma_tx.ch)
 778                 dma_release_channel(rs->dma_tx.ch);
 779         if (rs->dma_rx.ch)
 780                 dma_release_channel(rs->dma_rx.ch);
 781
 782         return 0;
 783 }
 784
 785 #ifdef CONFIG_PM_SLEEP
 786 static int rockchip_spi_suspend(struct device *dev)
 787 {
 788         int ret = 0;
 789         struct spi_master *master = dev_get_drvdata(dev);
 790         struct rockchip_spi *rs = spi_master_get_devdata(master);
 791
 792         ret = spi_master_suspend(rs->master);
 793         if (ret)
 794                 return ret;
 795
 796         if (!pm_runtime_suspended(dev)) {
 797                 clk_disable_unprepare(rs->spiclk);
 798                 clk_disable_unprepare(rs->apb_pclk);
 799         }
 800
 801         return ret;
 802 }
 803
 804 static int rockchip_spi_resume(struct device *dev)
 805 {
 806         int ret = 0;
 807         struct spi_master *master = dev_get_drvdata(dev);
 808         struct rockchip_spi *rs = spi_master_get_devdata(master);
 809
 810         if (!pm_runtime_suspended(dev)) {
 811                 ret = clk_prepare_enable(rs->apb_pclk);
 812                 if (ret < 0)
 813                         return ret;
 814
 815                 ret = clk_prepare_enable(rs->spiclk);
 816                 if (ret < 0) {
 817                         clk_disable_unprepare(rs->apb_pclk);
 818                         return ret;
 819                 }
 820         }
 821
 822         ret = spi_master_resume(rs->master);
 823         if (ret < 0) {
 824                 clk_disable_unprepare(rs->spiclk);
 825                 clk_disable_unprepare(rs->apb_pclk);
 826         }
 827
 828         return ret;
 829 }
 830 #endif /* CONFIG_PM_SLEEP */
 831
 832 #ifdef CONFIG_PM
 833 static int rockchip_spi_runtime_suspend(struct device *dev)
 834 {
 835         struct spi_master *master = dev_get_drvdata(dev);
 836         struct rockchip_spi *rs = spi_master_get_devdata(master);
 837
 838         clk_disable_unprepare(rs->spiclk);
 839         clk_disable_unprepare(rs->apb_pclk);
 840
 841         return 0;
 842 }
 843
 844 static int rockchip_spi_runtime_resume(struct device *dev)
 845 {
 846         int ret;
 847         struct spi_master *master = dev_get_drvdata(dev);
 848         struct rockchip_spi *rs = spi_master_get_devdata(master);
 849
 850         ret = clk_prepare_enable(rs->apb_pclk);
 851         if (ret)
 852                 return ret;
 853
 854         ret = clk_prepare_enable(rs->spiclk);
 855         if (ret)
 856                 clk_disable_unprepare(rs->apb_pclk);
 857
 858         return ret;
 859 }
 860 #endif /* CONFIG_PM */
 861
 862 static const struct dev_pm_ops rockchip_spi_pm = {
 863         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 864         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 865                            rockchip_spi_runtime_resume, NULL)
 866 };
 867
 868 static const struct of_device_id rockchip_spi_dt_match[] = {
 869         { .compatible = "rockchip,rk3066-spi", },
 870         { .compatible = "rockchip,rk3188-spi", },
 871         { .compatible = "rockchip,rk3288-spi", },
 872         { },
 873 };
 874 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 875
 876 static struct platform_driver rockchip_spi_driver = {
 877         .driver = {
 878                 .name   = DRIVER_NAME,
 879                 .pm = &rockchip_spi_pm,
 880                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 881         },
 882         .probe = rockchip_spi_probe,
 883         .remove = rockchip_spi_remove,
 884 };
 885
 886 module_platform_driver(rockchip_spi_driver);
 887
 888 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 889 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 890 MODULE_LICENSE("GPL v2");