2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Cavium Networks
8 * Some parts of the code were originally released under BSD license:
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/prefetch.h>
51 #include <linux/interrupt.h>
52 #include <linux/platform_device.h>
53 #include <linux/usb.h>
55 #include <linux/time.h>
56 #include <linux/delay.h>
58 #include <asm/octeon/cvmx.h>
59 #include <asm/octeon/cvmx-iob-defs.h>
61 #include <linux/usb/hcd.h>
63 #include <linux/err.h>
65 #include <asm/octeon/octeon.h>
66 #include <asm/octeon/cvmx-helper.h>
67 #include <asm/octeon/cvmx-sysinfo.h>
68 #include <asm/octeon/cvmx-helper-board.h>
70 #include "octeon-hcd.h"
73 * enum cvmx_usb_speed - the possible USB device speeds
75 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
76 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
77 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
80 CVMX_USB_SPEED_HIGH
= 0,
81 CVMX_USB_SPEED_FULL
= 1,
82 CVMX_USB_SPEED_LOW
= 2,
86 * enum cvmx_usb_transfer - the possible USB transfer types
88 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
90 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
91 * priority periodic transfers
92 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
94 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
97 enum cvmx_usb_transfer
{
98 CVMX_USB_TRANSFER_CONTROL
= 0,
99 CVMX_USB_TRANSFER_ISOCHRONOUS
= 1,
100 CVMX_USB_TRANSFER_BULK
= 2,
101 CVMX_USB_TRANSFER_INTERRUPT
= 3,
105 * enum cvmx_usb_direction - the transfer directions
107 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
108 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
110 enum cvmx_usb_direction
{
111 CVMX_USB_DIRECTION_OUT
,
112 CVMX_USB_DIRECTION_IN
,
116 * enum cvmx_usb_complete - possible callback function status codes
118 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
120 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
121 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
122 * by a user call to cvmx_usb_cancel
123 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
125 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
127 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
128 * device even after a number of retries
129 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
130 * error even after a number of retries
131 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
132 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
133 * even after a number of retries
135 enum cvmx_usb_complete
{
136 CVMX_USB_COMPLETE_SUCCESS
,
137 CVMX_USB_COMPLETE_SHORT
,
138 CVMX_USB_COMPLETE_CANCEL
,
139 CVMX_USB_COMPLETE_ERROR
,
140 CVMX_USB_COMPLETE_STALL
,
141 CVMX_USB_COMPLETE_XACTERR
,
142 CVMX_USB_COMPLETE_DATATGLERR
,
143 CVMX_USB_COMPLETE_BABBLEERR
,
144 CVMX_USB_COMPLETE_FRAMEERR
,
148 * struct cvmx_usb_port_status - the USB port status information
150 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
151 * @port_over_current: 1 = Over current detected, 0 = Over current not
152 * detected. Octeon doesn't support over current detection.
153 * @port_powered: 1 = Port power is being supplied to the device, 0 =
154 * power is off. Octeon doesn't support turning port power
156 * @port_speed: Current port speed.
157 * @connected: 1 = A device is connected to the port, 0 = No device is
159 * @connect_change: 1 = Device connected state changed since the last set
162 struct cvmx_usb_port_status
{
163 uint32_t reserved
: 25;
164 uint32_t port_enabled
: 1;
165 uint32_t port_over_current
: 1;
166 uint32_t port_powered
: 1;
167 enum cvmx_usb_speed port_speed
: 2;
168 uint32_t connected
: 1;
169 uint32_t connect_change
: 1;
173 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
175 * @offset: This is the offset in bytes into the main buffer where this data
177 * @length: This is the length in bytes of the data.
178 * @status: This is the status of this individual packet transfer.
180 struct cvmx_usb_iso_packet
{
183 enum cvmx_usb_complete status
;
187 * enum cvmx_usb_initialize_flags - flags used by the initialization function
189 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
190 * as clock source at USB_XO and
192 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
193 * board clock source at USB_XO.
194 * USB_XI should be tied to GND.
195 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
196 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
198 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
199 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
200 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
201 * data transfer use for the USB
203 enum cvmx_usb_initialize_flags
{
204 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
= 1 << 0,
205 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
= 1 << 1,
206 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
= 3 << 3,
207 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
= 1 << 3,
208 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
= 2 << 3,
209 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
= 3 << 3,
210 /* Bits 3-4 used to encode the clock frequency */
211 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
= 1 << 5,
215 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
217 * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
218 * actively using hardware.
219 * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed
220 * pipe is in the ping state.
222 enum cvmx_usb_pipe_flags
{
223 CVMX_USB_PIPE_FLAGS_SCHEDULED
= 1 << 17,
224 CVMX_USB_PIPE_FLAGS_NEED_PING
= 1 << 18,
227 /* Maximum number of times to retry failed transactions */
228 #define MAX_RETRIES 3
230 /* Maximum number of hardware channels supported by the USB block */
231 #define MAX_CHANNELS 8
234 * The low level hardware can transfer a maximum of this number of bytes in each
235 * transfer. The field is 19 bits wide
237 #define MAX_TRANSFER_BYTES ((1<<19)-1)
240 * The low level hardware can transfer a maximum of this number of packets in
241 * each transfer. The field is 10 bits wide
243 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
246 * Logical transactions may take numerous low level
247 * transactions, especially when splits are concerned. This
248 * enum represents all of the possible stages a transaction can
249 * be in. Note that split completes are always even. This is so
250 * the NAK handler can backup to the previous low level
251 * transaction with a simple clearing of bit 0.
253 enum cvmx_usb_stage
{
254 CVMX_USB_STAGE_NON_CONTROL
,
255 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
,
256 CVMX_USB_STAGE_SETUP
,
257 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
,
259 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
,
260 CVMX_USB_STAGE_STATUS
,
261 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
,
265 * struct cvmx_usb_transaction - describes each pending USB transaction
266 * regardless of type. These are linked together
267 * to form a list of pending requests for a pipe.
269 * @node: List node for transactions in the pipe.
270 * @type: Type of transaction, duplicated of the pipe.
271 * @flags: State flags for this transaction.
272 * @buffer: User's physical buffer address to read/write.
273 * @buffer_length: Size of the user's buffer in bytes.
274 * @control_header: For control transactions, physical address of the 8
275 * byte standard header.
276 * @iso_start_frame: For ISO transactions, the starting frame number.
277 * @iso_number_packets: For ISO transactions, the number of packets in the
279 * @iso_packets: For ISO transactions, the sub packets in the request.
280 * @actual_bytes: Actual bytes transfer for this transaction.
281 * @stage: For control transactions, the current stage.
284 struct cvmx_usb_transaction
{
285 struct list_head node
;
286 enum cvmx_usb_transfer type
;
289 uint64_t control_header
;
291 int iso_number_packets
;
292 struct cvmx_usb_iso_packet
*iso_packets
;
297 enum cvmx_usb_stage stage
;
302 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
303 * and some USB device. It contains a list of pending
304 * request to the device.
306 * @node: List node for pipe list
307 * @next: Pipe after this one in the list
308 * @transactions: List of pending transactions
309 * @interval: For periodic pipes, the interval between packets in
311 * @next_tx_frame: The next frame this pipe is allowed to transmit on
312 * @flags: State flags for this pipe
313 * @device_speed: Speed of device connected to this pipe
314 * @transfer_type: Type of transaction supported by this pipe
315 * @transfer_dir: IN or OUT. Ignored for Control
316 * @multi_count: Max packet in a row for the device
317 * @max_packet: The device's maximum packet size in bytes
318 * @device_addr: USB device address at other end of pipe
319 * @endpoint_num: USB endpoint number at other end of pipe
320 * @hub_device_addr: Hub address this device is connected to
321 * @hub_port: Hub port this device is connected to
322 * @pid_toggle: This toggles between 0/1 on every packet send to track
323 * the data pid needed
324 * @channel: Hardware DMA channel for this pipe
325 * @split_sc_frame: The low order bits of the frame number the split
326 * complete should be sent on
328 struct cvmx_usb_pipe
{
329 struct list_head node
;
330 struct list_head transactions
;
332 uint64_t next_tx_frame
;
333 enum cvmx_usb_pipe_flags flags
;
334 enum cvmx_usb_speed device_speed
;
335 enum cvmx_usb_transfer transfer_type
;
336 enum cvmx_usb_direction transfer_dir
;
340 uint8_t endpoint_num
;
341 uint8_t hub_device_addr
;
345 int8_t split_sc_frame
;
348 struct cvmx_usb_tx_fifo
{
353 } entry
[MAX_CHANNELS
+1];
359 * struct cvmx_usb_state - the state of the USB block
361 * init_flags: Flags passed to initialize.
362 * index: Which USB block this is for.
363 * idle_hardware_channels: Bit set for every idle hardware channel.
364 * usbcx_hprt: Stored port status so we don't need to read a CSR to
366 * pipe_for_channel: Map channels to pipes.
367 * pipe: Storage for pipes.
368 * indent: Used by debug output to indent functions.
369 * port_status: Last port status used for change notification.
370 * idle_pipes: List of open pipes that have no transactions.
371 * active_pipes: Active pipes indexed by transfer type.
372 * frame_number: Increments every SOF interrupt for time keeping.
373 * active_split: Points to the current active split, or NULL.
375 struct cvmx_usb_state
{
378 int idle_hardware_channels
;
379 union cvmx_usbcx_hprt usbcx_hprt
;
380 struct cvmx_usb_pipe
*pipe_for_channel
[MAX_CHANNELS
];
382 struct cvmx_usb_port_status port_status
;
383 struct list_head idle_pipes
;
384 struct list_head active_pipes
[4];
385 uint64_t frame_number
;
386 struct cvmx_usb_transaction
*active_split
;
387 struct cvmx_usb_tx_fifo periodic
;
388 struct cvmx_usb_tx_fifo nonperiodic
;
393 struct cvmx_usb_state usb
;
396 /* This macro spins on a register waiting for it to reach a condition. */
397 #define CVMX_WAIT_FOR_FIELD32(address, _union, cond, timeout_usec) \
400 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
401 octeon_get_clock_rate() / 1000000; \
405 c.u32 = cvmx_usb_read_csr32(usb, address); \
410 } else if (cvmx_get_cycle() > done) { \
420 * This macro logically sets a single field in a CSR. It does the sequence
421 * read, modify, and write
423 #define USB_SET_FIELD32(address, _union, field, value) \
427 c.u32 = cvmx_usb_read_csr32(usb, address); \
429 cvmx_usb_write_csr32(usb, address, c.u32); \
432 /* Returns the IO address to push/pop stuff data from the FIFOs */
433 #define USB_FIFO_ADDRESS(channel, usb_index) \
434 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
437 * struct octeon_temp_buffer - a bounce buffer for USB transfers
438 * @orig_buffer: the original buffer passed by the USB stack
439 * @data: the newly allocated temporary buffer (excluding meta-data)
441 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
442 * the buffer is too short, we need to allocate a temporary one, and this struct
445 struct octeon_temp_buffer
{
450 static inline struct octeon_hcd
*cvmx_usb_to_octeon(struct cvmx_usb_state
*p
)
452 return container_of(p
, struct octeon_hcd
, usb
);
455 static inline struct usb_hcd
*octeon_to_hcd(struct octeon_hcd
*p
)
457 return container_of((void *)p
, struct usb_hcd
, hcd_priv
);
461 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
464 * @mem_flags: Memory allocation flags.
466 * This function allocates a temporary bounce buffer whenever it's needed
467 * due to HW limitations.
469 static int octeon_alloc_temp_buffer(struct urb
*urb
, gfp_t mem_flags
)
471 struct octeon_temp_buffer
*temp
;
473 if (urb
->num_sgs
|| urb
->sg
||
474 (urb
->transfer_flags
& URB_NO_TRANSFER_DMA_MAP
) ||
475 !(urb
->transfer_buffer_length
% sizeof(u32
)))
478 temp
= kmalloc(ALIGN(urb
->transfer_buffer_length
, sizeof(u32
)) +
479 sizeof(*temp
), mem_flags
);
483 temp
->orig_buffer
= urb
->transfer_buffer
;
484 if (usb_urb_dir_out(urb
))
485 memcpy(temp
->data
, urb
->transfer_buffer
,
486 urb
->transfer_buffer_length
);
487 urb
->transfer_buffer
= temp
->data
;
488 urb
->transfer_flags
|= URB_ALIGNED_TEMP_BUFFER
;
494 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
497 * Frees a buffer allocated by octeon_alloc_temp_buffer().
499 static void octeon_free_temp_buffer(struct urb
*urb
)
501 struct octeon_temp_buffer
*temp
;
504 if (!(urb
->transfer_flags
& URB_ALIGNED_TEMP_BUFFER
))
507 temp
= container_of(urb
->transfer_buffer
, struct octeon_temp_buffer
,
509 if (usb_urb_dir_in(urb
)) {
510 if (usb_pipeisoc(urb
->pipe
))
511 length
= urb
->transfer_buffer_length
;
513 length
= urb
->actual_length
;
515 memcpy(temp
->orig_buffer
, urb
->transfer_buffer
, length
);
517 urb
->transfer_buffer
= temp
->orig_buffer
;
518 urb
->transfer_flags
&= ~URB_ALIGNED_TEMP_BUFFER
;
523 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
524 * @hcd: USB HCD structure.
526 * @mem_flags: Memory allocation flags.
528 static int octeon_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
533 ret
= octeon_alloc_temp_buffer(urb
, mem_flags
);
537 ret
= usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
539 octeon_free_temp_buffer(urb
);
545 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
546 * @hcd: USB HCD structure.
549 static void octeon_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
551 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
552 octeon_free_temp_buffer(urb
);
556 * Read a USB 32bit CSR. It performs the necessary address swizzle
557 * for 32bit CSRs and logs the value in a readable format if
560 * @usb: USB block this access is for
561 * @address: 64bit address to read
563 * Returns: Result of the read
565 static inline uint32_t cvmx_usb_read_csr32(struct cvmx_usb_state
*usb
,
568 uint32_t result
= cvmx_read64_uint32(address
^ 4);
574 * Write a USB 32bit CSR. It performs the necessary address
575 * swizzle for 32bit CSRs and logs the value in a readable format
576 * if debugging is on.
578 * @usb: USB block this access is for
579 * @address: 64bit address to write
580 * @value: Value to write
582 static inline void cvmx_usb_write_csr32(struct cvmx_usb_state
*usb
,
583 uint64_t address
, uint32_t value
)
585 cvmx_write64_uint32(address
^ 4, value
);
586 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
590 * Return non zero if this pipe connects to a non HIGH speed
591 * device through a high speed hub.
593 * @usb: USB block this access is for
594 * @pipe: Pipe to check
596 * Returns: Non zero if we need to do split transactions
598 static inline int cvmx_usb_pipe_needs_split(struct cvmx_usb_state
*usb
,
599 struct cvmx_usb_pipe
*pipe
)
601 return pipe
->device_speed
!= CVMX_USB_SPEED_HIGH
&&
602 usb
->usbcx_hprt
.s
.prtspd
== CVMX_USB_SPEED_HIGH
;
607 * Trivial utility function to return the correct PID for a pipe
609 * @pipe: pipe to check
611 * Returns: PID for pipe
613 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe
*pipe
)
615 if (pipe
->pid_toggle
)
616 return 2; /* Data1 */
617 return 0; /* Data0 */
620 static void cvmx_fifo_setup(struct cvmx_usb_state
*usb
)
622 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3
;
623 union cvmx_usbcx_gnptxfsiz npsiz
;
624 union cvmx_usbcx_hptxfsiz psiz
;
626 usbcx_ghwcfg3
.u32
= cvmx_usb_read_csr32(usb
,
627 CVMX_USBCX_GHWCFG3(usb
->index
));
630 * Program the USBC_GRXFSIZ register to select the size of the receive
633 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb
->index
), cvmx_usbcx_grxfsiz
,
634 rxfdep
, usbcx_ghwcfg3
.s
.dfifodepth
/ 4);
637 * Program the USBC_GNPTXFSIZ register to select the size and the start
638 * address of the non-periodic transmit FIFO for nonperiodic
639 * transactions (50%).
641 npsiz
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
));
642 npsiz
.s
.nptxfdep
= usbcx_ghwcfg3
.s
.dfifodepth
/ 2;
643 npsiz
.s
.nptxfstaddr
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
644 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
), npsiz
.u32
);
647 * Program the USBC_HPTXFSIZ register to select the size and start
648 * address of the periodic transmit FIFO for periodic transactions
651 psiz
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
));
652 psiz
.s
.ptxfsize
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
653 psiz
.s
.ptxfstaddr
= 3 * usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
654 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
), psiz
.u32
);
656 /* Flush all FIFOs */
657 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
658 cvmx_usbcx_grstctl
, txfnum
, 0x10);
659 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
660 cvmx_usbcx_grstctl
, txfflsh
, 1);
661 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
662 cvmx_usbcx_grstctl
, c
.s
.txfflsh
== 0, 100);
663 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
664 cvmx_usbcx_grstctl
, rxfflsh
, 1);
665 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
666 cvmx_usbcx_grstctl
, c
.s
.rxfflsh
== 0, 100);
670 * Shutdown a USB port after a call to cvmx_usb_initialize().
671 * The port should be disabled with all pipes closed when this
672 * function is called.
674 * @usb: USB device state populated by cvmx_usb_initialize().
676 * Returns: 0 or a negative error code.
678 static int cvmx_usb_shutdown(struct cvmx_usb_state
*usb
)
680 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
682 /* Make sure all pipes are closed */
683 if (!list_empty(&usb
->idle_pipes
) ||
684 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_ISOCHRONOUS
]) ||
685 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_INTERRUPT
]) ||
686 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_CONTROL
]) ||
687 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_BULK
]))
690 /* Disable the clocks and put them in power on reset */
691 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
692 usbn_clk_ctl
.s
.enable
= 1;
693 usbn_clk_ctl
.s
.por
= 1;
694 usbn_clk_ctl
.s
.hclk_rst
= 1;
695 usbn_clk_ctl
.s
.prst
= 0;
696 usbn_clk_ctl
.s
.hrst
= 0;
697 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
702 * Initialize a USB port for use. This must be called before any
703 * other access to the Octeon USB port is made. The port starts
704 * off in the disabled state.
706 * @dev: Pointer to struct device for logging purposes.
707 * @usb: Pointer to struct cvmx_usb_state.
709 * Returns: 0 or a negative error code.
711 static int cvmx_usb_initialize(struct device
*dev
,
712 struct cvmx_usb_state
*usb
)
717 union cvmx_usbcx_hcfg usbcx_hcfg
;
718 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
719 union cvmx_usbcx_gintsts usbc_gintsts
;
720 union cvmx_usbcx_gahbcfg usbcx_gahbcfg
;
721 union cvmx_usbcx_gintmsk usbcx_gintmsk
;
722 union cvmx_usbcx_gusbcfg usbcx_gusbcfg
;
723 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status
;
727 * Power On Reset and PHY Initialization
729 * 1. Wait for DCOK to assert (nothing to do)
731 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
732 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
734 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
735 usbn_clk_ctl
.s
.por
= 1;
736 usbn_clk_ctl
.s
.hrst
= 0;
737 usbn_clk_ctl
.s
.prst
= 0;
738 usbn_clk_ctl
.s
.hclk_rst
= 0;
739 usbn_clk_ctl
.s
.enable
= 0;
741 * 2b. Select the USB reference clock/crystal parameters by writing
742 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
744 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
) {
746 * The USB port uses 12/24/48MHz 2.5V board clock
747 * source at USB_XO. USB_XI should be tied to GND.
748 * Most Octeon evaluation boards require this setting
750 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
) ||
751 OCTEON_IS_MODEL(OCTEON_CN56XX
) ||
752 OCTEON_IS_MODEL(OCTEON_CN50XX
))
753 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
754 usbn_clk_ctl
.s
.p_rtype
= 2; /* p_rclk=1 & p_xenbn=0 */
756 /* From CN52XX manual */
757 usbn_clk_ctl
.s
.p_rtype
= 1;
759 switch (usb
->init_flags
&
760 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
) {
761 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
:
762 usbn_clk_ctl
.s
.p_c_sel
= 0;
764 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
:
765 usbn_clk_ctl
.s
.p_c_sel
= 1;
767 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
:
768 usbn_clk_ctl
.s
.p_c_sel
= 2;
773 * The USB port uses a 12MHz crystal as clock source
774 * at USB_XO and USB_XI
776 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
))
777 /* From CN31XX,CN30XX manual */
778 usbn_clk_ctl
.s
.p_rtype
= 3; /* p_rclk=1 & p_xenbn=1 */
780 /* From CN56XX,CN52XX,CN50XX manuals. */
781 usbn_clk_ctl
.s
.p_rtype
= 0;
783 usbn_clk_ctl
.s
.p_c_sel
= 0;
786 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
787 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
788 * such that USB is as close as possible to 125Mhz
790 divisor
= DIV_ROUND_UP(octeon_get_clock_rate(), 125000000);
791 /* Lower than 4 doesn't seem to work properly */
794 usbn_clk_ctl
.s
.divide
= divisor
;
795 usbn_clk_ctl
.s
.divide2
= 0;
796 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
798 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
799 usbn_clk_ctl
.s
.hclk_rst
= 1;
800 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
801 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
804 * 3. Program the power-on reset field in the USBN clock-control
806 * USBN_CLK_CTL[POR] = 0
808 usbn_clk_ctl
.s
.por
= 0;
809 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
810 /* 4. Wait 1 ms for PHY clock to start */
813 * 5. Program the Reset input from automatic test equipment field in the
814 * USBP control and status register:
815 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
817 usbn_usbp_ctl_status
.u64
=
818 cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
));
819 usbn_usbp_ctl_status
.s
.ate_reset
= 1;
820 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
821 usbn_usbp_ctl_status
.u64
);
822 /* 6. Wait 10 cycles */
825 * 7. Clear ATE_RESET field in the USBN clock-control register:
826 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
828 usbn_usbp_ctl_status
.s
.ate_reset
= 0;
829 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
830 usbn_usbp_ctl_status
.u64
);
832 * 8. Program the PHY reset field in the USBN clock-control register:
833 * USBN_CLK_CTL[PRST] = 1
835 usbn_clk_ctl
.s
.prst
= 1;
836 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
838 * 9. Program the USBP control and status register to select host or
839 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
842 usbn_usbp_ctl_status
.s
.hst_mode
= 0;
843 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
844 usbn_usbp_ctl_status
.u64
);
848 * 11. Program the hreset_n field in the USBN clock-control register:
849 * USBN_CLK_CTL[HRST] = 1
851 usbn_clk_ctl
.s
.hrst
= 1;
852 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
853 /* 12. Proceed to USB core initialization */
854 usbn_clk_ctl
.s
.enable
= 1;
855 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
859 * USB Core Initialization
861 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
862 * determine USB core configuration parameters.
866 * 2. Program the following fields in the global AHB configuration
867 * register (USBC_GAHBCFG)
868 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
869 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
870 * Nonperiodic TxFIFO empty level (slave mode only),
871 * USBC_GAHBCFG[NPTXFEMPLVL]
872 * Periodic TxFIFO empty level (slave mode only),
873 * USBC_GAHBCFG[PTXFEMPLVL]
874 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
876 usbcx_gahbcfg
.u32
= 0;
877 usbcx_gahbcfg
.s
.dmaen
= !(usb
->init_flags
&
878 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
);
879 usbcx_gahbcfg
.s
.hbstlen
= 0;
880 usbcx_gahbcfg
.s
.nptxfemplvl
= 1;
881 usbcx_gahbcfg
.s
.ptxfemplvl
= 1;
882 usbcx_gahbcfg
.s
.glblintrmsk
= 1;
883 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GAHBCFG(usb
->index
),
887 * 3. Program the following fields in USBC_GUSBCFG register.
888 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
889 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
890 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
891 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
893 usbcx_gusbcfg
.u32
= cvmx_usb_read_csr32(usb
,
894 CVMX_USBCX_GUSBCFG(usb
->index
));
895 usbcx_gusbcfg
.s
.toutcal
= 0;
896 usbcx_gusbcfg
.s
.ddrsel
= 0;
897 usbcx_gusbcfg
.s
.usbtrdtim
= 0x5;
898 usbcx_gusbcfg
.s
.phylpwrclksel
= 0;
899 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GUSBCFG(usb
->index
),
903 * 4. The software must unmask the following bits in the USBC_GINTMSK
905 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
906 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
908 usbcx_gintmsk
.u32
= cvmx_usb_read_csr32(usb
,
909 CVMX_USBCX_GINTMSK(usb
->index
));
910 usbcx_gintmsk
.s
.otgintmsk
= 1;
911 usbcx_gintmsk
.s
.modemismsk
= 1;
912 usbcx_gintmsk
.s
.hchintmsk
= 1;
913 usbcx_gintmsk
.s
.sofmsk
= 0;
914 /* We need RX FIFO interrupts if we don't have DMA */
915 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
916 usbcx_gintmsk
.s
.rxflvlmsk
= 1;
917 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTMSK(usb
->index
),
921 * Disable all channel interrupts. We'll enable them per channel later.
923 for (channel
= 0; channel
< 8; channel
++)
924 cvmx_usb_write_csr32(usb
,
925 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
929 * Host Port Initialization
931 * 1. Program the host-port interrupt-mask field to unmask,
932 * USBC_GINTMSK[PRTINT] = 1
934 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
935 cvmx_usbcx_gintmsk
, prtintmsk
, 1);
936 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
937 cvmx_usbcx_gintmsk
, disconnintmsk
, 1);
940 * 2. Program the USBC_HCFG register to select full-speed host
941 * or high-speed host.
943 usbcx_hcfg
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
));
944 usbcx_hcfg
.s
.fslssupp
= 0;
945 usbcx_hcfg
.s
.fslspclksel
= 0;
946 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
), usbcx_hcfg
.u32
);
948 cvmx_fifo_setup(usb
);
951 * If the controller is getting port events right after the reset, it
952 * means the initialization failed. Try resetting the controller again
953 * in such case. This is seen to happen after cold boot on DSR-1000N.
955 usbc_gintsts
.u32
= cvmx_usb_read_csr32(usb
,
956 CVMX_USBCX_GINTSTS(usb
->index
));
957 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
),
959 dev_dbg(dev
, "gintsts after reset: 0x%x\n", (int)usbc_gintsts
.u32
);
960 if (!usbc_gintsts
.s
.disconnint
&& !usbc_gintsts
.s
.prtint
)
964 dev_info(dev
, "controller reset failed (gintsts=0x%x) - retrying\n",
965 (int)usbc_gintsts
.u32
);
967 cvmx_usb_shutdown(usb
);
973 * Reset a USB port. After this call succeeds, the USB port is
974 * online and servicing requests.
976 * @usb: USB device state populated by cvmx_usb_initialize().
978 static void cvmx_usb_reset_port(struct cvmx_usb_state
*usb
)
980 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
981 CVMX_USBCX_HPRT(usb
->index
));
983 /* Program the port reset bit to start the reset process */
984 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), cvmx_usbcx_hprt
,
988 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
989 * process to complete.
993 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
994 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), cvmx_usbcx_hprt
,
998 * Read the port speed field to get the enumerated speed,
1001 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
1002 CVMX_USBCX_HPRT(usb
->index
));
1007 * Disable a USB port. After this call the USB port will not
1008 * generate data transfers and will not generate events.
1009 * Transactions in process will fail and call their
1010 * associated callbacks.
1012 * @usb: USB device state populated by cvmx_usb_initialize().
1014 * Returns: 0 or a negative error code.
1016 static int cvmx_usb_disable(struct cvmx_usb_state
*usb
)
1018 /* Disable the port */
1019 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), cvmx_usbcx_hprt
,
1026 * Get the current state of the USB port. Use this call to
1027 * determine if the usb port has anything connected, is enabled,
1028 * or has some sort of error condition. The return value of this
1029 * call has "changed" bits to signal of the value of some fields
1030 * have changed between calls.
1032 * @usb: USB device state populated by cvmx_usb_initialize().
1034 * Returns: Port status information
1036 static struct cvmx_usb_port_status
cvmx_usb_get_status(
1037 struct cvmx_usb_state
*usb
)
1039 union cvmx_usbcx_hprt usbc_hprt
;
1040 struct cvmx_usb_port_status result
;
1042 memset(&result
, 0, sizeof(result
));
1044 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1045 result
.port_enabled
= usbc_hprt
.s
.prtena
;
1046 result
.port_over_current
= usbc_hprt
.s
.prtovrcurract
;
1047 result
.port_powered
= usbc_hprt
.s
.prtpwr
;
1048 result
.port_speed
= usbc_hprt
.s
.prtspd
;
1049 result
.connected
= usbc_hprt
.s
.prtconnsts
;
1050 result
.connect_change
=
1051 (result
.connected
!= usb
->port_status
.connected
);
1057 * Open a virtual pipe between the host and a USB device. A pipe
1058 * must be opened before data can be transferred between a device
1061 * @usb: USB device state populated by cvmx_usb_initialize().
1063 * USB device address to open the pipe to
1066 * USB endpoint number to open the pipe to
1069 * The speed of the device the pipe is going
1070 * to. This must match the device's speed,
1071 * which may be different than the port speed.
1072 * @max_packet: The maximum packet length the device can
1073 * transmit/receive (low speed=0-8, full
1074 * speed=0-1023, high speed=0-1024). This value
1075 * comes from the standard endpoint descriptor
1076 * field wMaxPacketSize bits <10:0>.
1078 * The type of transfer this pipe is for.
1080 * The direction the pipe is in. This is not
1081 * used for control pipes.
1082 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1083 * this is how often the transfer is scheduled
1084 * for. All other transfers should specify
1085 * zero. The units are in frames (8000/sec at
1086 * high speed, 1000/sec for full speed).
1088 * For high speed devices, this is the maximum
1089 * allowed number of packet per microframe.
1090 * Specify zero for non high speed devices. This
1091 * value comes from the standard endpoint descriptor
1092 * field wMaxPacketSize bits <12:11>.
1094 * Hub device address this device is connected
1095 * to. Devices connected directly to Octeon
1096 * use zero. This is only used when the device
1097 * is full/low speed behind a high speed hub.
1098 * The address will be of the high speed hub,
1099 * not and full speed hubs after it.
1100 * @hub_port: Which port on the hub the device is
1101 * connected. Use zero for devices connected
1102 * directly to Octeon. Like hub_device_addr,
1103 * this is only used for full/low speed
1104 * devices behind a high speed hub.
1106 * Returns: A non-NULL value is a pipe. NULL means an error.
1108 static struct cvmx_usb_pipe
*cvmx_usb_open_pipe(struct cvmx_usb_state
*usb
,
1114 enum cvmx_usb_transfer
1116 enum cvmx_usb_direction
1118 int interval
, int multi_count
,
1119 int hub_device_addr
,
1122 struct cvmx_usb_pipe
*pipe
;
1124 pipe
= kzalloc(sizeof(*pipe
), GFP_ATOMIC
);
1127 if ((device_speed
== CVMX_USB_SPEED_HIGH
) &&
1128 (transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1129 (transfer_type
== CVMX_USB_TRANSFER_BULK
))
1130 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
1131 pipe
->device_addr
= device_addr
;
1132 pipe
->endpoint_num
= endpoint_num
;
1133 pipe
->device_speed
= device_speed
;
1134 pipe
->max_packet
= max_packet
;
1135 pipe
->transfer_type
= transfer_type
;
1136 pipe
->transfer_dir
= transfer_dir
;
1137 INIT_LIST_HEAD(&pipe
->transactions
);
1140 * All pipes use interval to rate limit NAK processing. Force an
1141 * interval if one wasn't supplied
1145 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1146 pipe
->interval
= interval
*8;
1147 /* Force start splits to be schedule on uFrame 0 */
1148 pipe
->next_tx_frame
= ((usb
->frame_number
+7)&~7) +
1151 pipe
->interval
= interval
;
1152 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
;
1154 pipe
->multi_count
= multi_count
;
1155 pipe
->hub_device_addr
= hub_device_addr
;
1156 pipe
->hub_port
= hub_port
;
1157 pipe
->pid_toggle
= 0;
1158 pipe
->split_sc_frame
= -1;
1159 list_add_tail(&pipe
->node
, &usb
->idle_pipes
);
1162 * We don't need to tell the hardware about this pipe yet since
1163 * it doesn't have any submitted requests
1171 * Poll the RX FIFOs and remove data as needed. This function is only used
1172 * in non DMA mode. It is very important that this function be called quickly
1173 * enough to prevent FIFO overflow.
1175 * @usb: USB device state populated by cvmx_usb_initialize().
1177 static void cvmx_usb_poll_rx_fifo(struct cvmx_usb_state
*usb
)
1179 union cvmx_usbcx_grxstsph rx_status
;
1185 rx_status
.u32
= cvmx_usb_read_csr32(usb
,
1186 CVMX_USBCX_GRXSTSPH(usb
->index
));
1187 /* Only read data if IN data is there */
1188 if (rx_status
.s
.pktsts
!= 2)
1190 /* Check if no data is available */
1191 if (!rx_status
.s
.bcnt
)
1194 channel
= rx_status
.s
.chnum
;
1195 bytes
= rx_status
.s
.bcnt
;
1199 /* Get where the DMA engine would have written this data */
1200 address
= cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) +
1203 ptr
= cvmx_phys_to_ptr(address
);
1204 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
* 8,
1207 /* Loop writing the FIFO data for this packet into memory */
1209 *ptr
++ = cvmx_usb_read_csr32(usb
,
1210 USB_FIFO_ADDRESS(channel
, usb
->index
));
1218 * Fill the TX hardware fifo with data out of the software
1221 * @usb: USB device state populated by cvmx_usb_initialize().
1222 * @fifo: Software fifo to use
1223 * @available: Amount of space in the hardware fifo
1225 * Returns: Non zero if the hardware fifo was too small and needs
1226 * to be serviced again.
1228 static int cvmx_usb_fill_tx_hw(struct cvmx_usb_state
*usb
,
1229 struct cvmx_usb_tx_fifo
*fifo
, int available
)
1232 * We're done either when there isn't anymore space or the software FIFO
1235 while (available
&& (fifo
->head
!= fifo
->tail
)) {
1237 const uint32_t *ptr
= cvmx_phys_to_ptr(fifo
->entry
[i
].address
);
1238 uint64_t csr_address
= USB_FIFO_ADDRESS(fifo
->entry
[i
].channel
,
1240 int words
= available
;
1242 /* Limit the amount of data to what the SW fifo has */
1243 if (fifo
->entry
[i
].size
<= available
) {
1244 words
= fifo
->entry
[i
].size
;
1246 if (fifo
->tail
> MAX_CHANNELS
)
1250 /* Update the next locations and counts */
1252 fifo
->entry
[i
].address
+= words
* 4;
1253 fifo
->entry
[i
].size
-= words
;
1256 * Write the HW fifo data. The read every three writes is due
1257 * to an errata on CN3XXX chips
1260 cvmx_write64_uint32(csr_address
, *ptr
++);
1261 cvmx_write64_uint32(csr_address
, *ptr
++);
1262 cvmx_write64_uint32(csr_address
, *ptr
++);
1264 CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1267 cvmx_write64_uint32(csr_address
, *ptr
++);
1269 cvmx_write64_uint32(csr_address
, *ptr
++);
1271 cvmx_write64_uint32(csr_address
, *ptr
++);
1273 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1275 return fifo
->head
!= fifo
->tail
;
1280 * Check the hardware FIFOs and fill them as needed
1282 * @usb: USB device state populated by cvmx_usb_initialize().
1284 static void cvmx_usb_poll_tx_fifo(struct cvmx_usb_state
*usb
)
1286 if (usb
->periodic
.head
!= usb
->periodic
.tail
) {
1287 union cvmx_usbcx_hptxsts tx_status
;
1289 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1290 CVMX_USBCX_HPTXSTS(usb
->index
));
1291 if (cvmx_usb_fill_tx_hw(usb
, &usb
->periodic
,
1292 tx_status
.s
.ptxfspcavail
))
1293 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1294 cvmx_usbcx_gintmsk
, ptxfempmsk
, 1);
1296 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1297 cvmx_usbcx_gintmsk
, ptxfempmsk
, 0);
1300 if (usb
->nonperiodic
.head
!= usb
->nonperiodic
.tail
) {
1301 union cvmx_usbcx_gnptxsts tx_status
;
1303 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1304 CVMX_USBCX_GNPTXSTS(usb
->index
));
1305 if (cvmx_usb_fill_tx_hw(usb
, &usb
->nonperiodic
,
1306 tx_status
.s
.nptxfspcavail
))
1307 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1308 cvmx_usbcx_gintmsk
, nptxfempmsk
, 1);
1310 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1311 cvmx_usbcx_gintmsk
, nptxfempmsk
, 0);
1317 * Fill the TX FIFO with an outgoing packet
1319 * @usb: USB device state populated by cvmx_usb_initialize().
1320 * @channel: Channel number to get packet from
1322 static void cvmx_usb_fill_tx_fifo(struct cvmx_usb_state
*usb
, int channel
)
1324 union cvmx_usbcx_hccharx hcchar
;
1325 union cvmx_usbcx_hcspltx usbc_hcsplt
;
1326 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1327 struct cvmx_usb_tx_fifo
*fifo
;
1329 /* We only need to fill data on outbound channels */
1330 hcchar
.u32
= cvmx_usb_read_csr32(usb
,
1331 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
1332 if (hcchar
.s
.epdir
!= CVMX_USB_DIRECTION_OUT
)
1335 /* OUT Splits only have data on the start and not the complete */
1336 usbc_hcsplt
.u32
= cvmx_usb_read_csr32(usb
,
1337 CVMX_USBCX_HCSPLTX(channel
, usb
->index
));
1338 if (usbc_hcsplt
.s
.spltena
&& usbc_hcsplt
.s
.compsplt
)
1342 * Find out how many bytes we need to fill and convert it into 32bit
1345 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1346 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1347 if (!usbc_hctsiz
.s
.xfersize
)
1350 if ((hcchar
.s
.eptype
== CVMX_USB_TRANSFER_INTERRUPT
) ||
1351 (hcchar
.s
.eptype
== CVMX_USB_TRANSFER_ISOCHRONOUS
))
1352 fifo
= &usb
->periodic
;
1354 fifo
= &usb
->nonperiodic
;
1356 fifo
->entry
[fifo
->head
].channel
= channel
;
1357 fifo
->entry
[fifo
->head
].address
=
1358 cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1360 fifo
->entry
[fifo
->head
].size
= (usbc_hctsiz
.s
.xfersize
+3)>>2;
1362 if (fifo
->head
> MAX_CHANNELS
)
1365 cvmx_usb_poll_tx_fifo(usb
);
1369 * Perform channel specific setup for Control transactions. All
1370 * the generic stuff will already have been done in cvmx_usb_start_channel().
1372 * @usb: USB device state populated by cvmx_usb_initialize().
1373 * @channel: Channel to setup
1374 * @pipe: Pipe for control transaction
1376 static void cvmx_usb_start_channel_control(struct cvmx_usb_state
*usb
,
1378 struct cvmx_usb_pipe
*pipe
)
1380 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
1381 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
1382 struct device
*dev
= hcd
->self
.controller
;
1383 struct cvmx_usb_transaction
*transaction
=
1384 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1386 struct usb_ctrlrequest
*header
=
1387 cvmx_phys_to_ptr(transaction
->control_header
);
1388 int bytes_to_transfer
= transaction
->buffer_length
-
1389 transaction
->actual_bytes
;
1390 int packets_to_transfer
;
1391 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1393 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1394 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1396 switch (transaction
->stage
) {
1397 case CVMX_USB_STAGE_NON_CONTROL
:
1398 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
1399 dev_err(dev
, "%s: ERROR - Non control stage\n", __func__
);
1401 case CVMX_USB_STAGE_SETUP
:
1402 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1403 bytes_to_transfer
= sizeof(*header
);
1404 /* All Control operations start with a setup going OUT */
1405 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1406 cvmx_usbcx_hccharx
, epdir
,
1407 CVMX_USB_DIRECTION_OUT
);
1409 * Setup send the control header instead of the buffer data. The
1410 * buffer data will be used in the next stage
1412 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1414 transaction
->control_header
);
1416 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
1417 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1418 bytes_to_transfer
= 0;
1419 /* All Control operations start with a setup going OUT */
1420 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1421 cvmx_usbcx_hccharx
, epdir
,
1422 CVMX_USB_DIRECTION_OUT
);
1424 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1425 cvmx_usbcx_hcspltx
, compsplt
, 1);
1427 case CVMX_USB_STAGE_DATA
:
1428 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1429 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1430 if (header
->bRequestType
& USB_DIR_IN
)
1431 bytes_to_transfer
= 0;
1432 else if (bytes_to_transfer
> pipe
->max_packet
)
1433 bytes_to_transfer
= pipe
->max_packet
;
1435 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1436 cvmx_usbcx_hccharx
, epdir
,
1437 ((header
->bRequestType
& USB_DIR_IN
) ?
1438 CVMX_USB_DIRECTION_IN
:
1439 CVMX_USB_DIRECTION_OUT
));
1441 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
1442 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1443 if (!(header
->bRequestType
& USB_DIR_IN
))
1444 bytes_to_transfer
= 0;
1445 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1446 cvmx_usbcx_hccharx
, epdir
,
1447 ((header
->bRequestType
& USB_DIR_IN
) ?
1448 CVMX_USB_DIRECTION_IN
:
1449 CVMX_USB_DIRECTION_OUT
));
1450 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1451 cvmx_usbcx_hcspltx
, compsplt
, 1);
1453 case CVMX_USB_STAGE_STATUS
:
1454 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1455 bytes_to_transfer
= 0;
1456 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1457 cvmx_usbcx_hccharx
, epdir
,
1458 ((header
->bRequestType
& USB_DIR_IN
) ?
1459 CVMX_USB_DIRECTION_OUT
:
1460 CVMX_USB_DIRECTION_IN
));
1462 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
1463 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1464 bytes_to_transfer
= 0;
1465 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1466 cvmx_usbcx_hccharx
, epdir
,
1467 ((header
->bRequestType
& USB_DIR_IN
) ?
1468 CVMX_USB_DIRECTION_OUT
:
1469 CVMX_USB_DIRECTION_IN
));
1470 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1471 cvmx_usbcx_hcspltx
, compsplt
, 1);
1476 * Make sure the transfer never exceeds the byte limit of the hardware.
1477 * Further bytes will be sent as continued transactions
1479 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1480 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1481 bytes_to_transfer
= MAX_TRANSFER_BYTES
/ pipe
->max_packet
;
1482 bytes_to_transfer
*= pipe
->max_packet
;
1486 * Calculate the number of packets to transfer. If the length is zero
1487 * we still need to transfer one packet
1489 packets_to_transfer
= DIV_ROUND_UP(bytes_to_transfer
,
1491 if (packets_to_transfer
== 0)
1492 packets_to_transfer
= 1;
1493 else if ((packets_to_transfer
> 1) &&
1494 (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1496 * Limit to one packet when not using DMA. Channels must be
1497 * restarted between every packet for IN transactions, so there
1498 * is no reason to do multiple packets in a row
1500 packets_to_transfer
= 1;
1501 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1502 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1504 * Limit the number of packet and data transferred to what the
1505 * hardware can handle
1507 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1508 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1511 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1512 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1514 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1520 * Start a channel to perform the pipe's head transaction
1522 * @usb: USB device state populated by cvmx_usb_initialize().
1523 * @channel: Channel to setup
1524 * @pipe: Pipe to start
1526 static void cvmx_usb_start_channel(struct cvmx_usb_state
*usb
, int channel
,
1527 struct cvmx_usb_pipe
*pipe
)
1529 struct cvmx_usb_transaction
*transaction
=
1530 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1533 /* Make sure all writes to the DMA region get flushed */
1536 /* Attach the channel to the pipe */
1537 usb
->pipe_for_channel
[channel
] = pipe
;
1538 pipe
->channel
= channel
;
1539 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_SCHEDULED
;
1541 /* Mark this channel as in use */
1542 usb
->idle_hardware_channels
&= ~(1<<channel
);
1544 /* Enable the channel interrupt bits */
1546 union cvmx_usbcx_hcintx usbc_hcint
;
1547 union cvmx_usbcx_hcintmskx usbc_hcintmsk
;
1548 union cvmx_usbcx_haintmsk usbc_haintmsk
;
1550 /* Clear all channel status bits */
1551 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
1552 CVMX_USBCX_HCINTX(channel
, usb
->index
));
1554 cvmx_usb_write_csr32(usb
,
1555 CVMX_USBCX_HCINTX(channel
, usb
->index
),
1558 usbc_hcintmsk
.u32
= 0;
1559 usbc_hcintmsk
.s
.chhltdmsk
= 1;
1560 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1562 * Channels need these extra interrupts when we aren't
1565 usbc_hcintmsk
.s
.datatglerrmsk
= 1;
1566 usbc_hcintmsk
.s
.frmovrunmsk
= 1;
1567 usbc_hcintmsk
.s
.bblerrmsk
= 1;
1568 usbc_hcintmsk
.s
.xacterrmsk
= 1;
1569 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1571 * Splits don't generate xfercompl, so we need
1574 usbc_hcintmsk
.s
.nyetmsk
= 1;
1575 usbc_hcintmsk
.s
.ackmsk
= 1;
1577 usbc_hcintmsk
.s
.nakmsk
= 1;
1578 usbc_hcintmsk
.s
.stallmsk
= 1;
1579 usbc_hcintmsk
.s
.xfercomplmsk
= 1;
1581 cvmx_usb_write_csr32(usb
,
1582 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
1585 /* Enable the channel interrupt to propagate */
1586 usbc_haintmsk
.u32
= cvmx_usb_read_csr32(usb
,
1587 CVMX_USBCX_HAINTMSK(usb
->index
));
1588 usbc_haintmsk
.s
.haintmsk
|= 1<<channel
;
1589 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HAINTMSK(usb
->index
),
1593 /* Setup the location the DMA engine uses. */
1596 uint64_t dma_address
= transaction
->buffer
+
1597 transaction
->actual_bytes
;
1599 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1600 dma_address
= transaction
->buffer
+
1601 transaction
->iso_packets
[0].offset
+
1602 transaction
->actual_bytes
;
1604 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
)
1605 reg
= CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
);
1607 reg
= CVMX_USBNX_DMA0_INB_CHN0(usb
->index
);
1608 cvmx_write64_uint64(reg
+ channel
* 8, dma_address
);
1611 /* Setup both the size of the transfer and the SPLIT characteristics */
1613 union cvmx_usbcx_hcspltx usbc_hcsplt
= {.u32
= 0};
1614 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
= 0};
1615 int packets_to_transfer
;
1616 int bytes_to_transfer
= transaction
->buffer_length
-
1617 transaction
->actual_bytes
;
1620 * ISOCHRONOUS transactions store each individual transfer size
1621 * in the packet structure, not the global buffer_length
1623 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1625 transaction
->iso_packets
[0].length
-
1626 transaction
->actual_bytes
;
1629 * We need to do split transactions when we are talking to non
1630 * high speed devices that are behind a high speed hub
1632 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1634 * On the start split phase (stage is even) record the
1635 * frame number we will need to send the split complete.
1636 * We only store the lower two bits since the time ahead
1637 * can only be two frames
1639 if ((transaction
->stage
&1) == 0) {
1640 if (transaction
->type
== CVMX_USB_TRANSFER_BULK
)
1641 pipe
->split_sc_frame
=
1642 (usb
->frame_number
+ 1) & 0x7f;
1644 pipe
->split_sc_frame
=
1645 (usb
->frame_number
+ 2) & 0x7f;
1647 pipe
->split_sc_frame
= -1;
1649 usbc_hcsplt
.s
.spltena
= 1;
1650 usbc_hcsplt
.s
.hubaddr
= pipe
->hub_device_addr
;
1651 usbc_hcsplt
.s
.prtaddr
= pipe
->hub_port
;
1652 usbc_hcsplt
.s
.compsplt
= (transaction
->stage
==
1653 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
);
1656 * SPLIT transactions can only ever transmit one data
1657 * packet so limit the transfer size to the max packet
1660 if (bytes_to_transfer
> pipe
->max_packet
)
1661 bytes_to_transfer
= pipe
->max_packet
;
1664 * ISOCHRONOUS OUT splits are unique in that they limit
1665 * data transfers to 188 byte chunks representing the
1666 * begin/middle/end of the data or all
1668 if (!usbc_hcsplt
.s
.compsplt
&&
1669 (pipe
->transfer_dir
==
1670 CVMX_USB_DIRECTION_OUT
) &&
1671 (pipe
->transfer_type
==
1672 CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
1674 * Clear the split complete frame number as
1675 * there isn't going to be a split complete
1677 pipe
->split_sc_frame
= -1;
1679 * See if we've started this transfer and sent
1682 if (transaction
->actual_bytes
== 0) {
1684 * Nothing sent yet, this is either a
1685 * begin or the entire payload
1687 if (bytes_to_transfer
<= 188)
1688 /* Entire payload in one go */
1689 usbc_hcsplt
.s
.xactpos
= 3;
1691 /* First part of payload */
1692 usbc_hcsplt
.s
.xactpos
= 2;
1695 * Continuing the previous data, we must
1696 * either be in the middle or at the end
1698 if (bytes_to_transfer
<= 188)
1699 /* End of payload */
1700 usbc_hcsplt
.s
.xactpos
= 1;
1702 /* Middle of payload */
1703 usbc_hcsplt
.s
.xactpos
= 0;
1706 * Again, the transfer size is limited to 188
1709 if (bytes_to_transfer
> 188)
1710 bytes_to_transfer
= 188;
1715 * Make sure the transfer never exceeds the byte limit of the
1716 * hardware. Further bytes will be sent as continued
1719 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1721 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1724 bytes_to_transfer
= MAX_TRANSFER_BYTES
/
1726 bytes_to_transfer
*= pipe
->max_packet
;
1730 * Calculate the number of packets to transfer. If the length is
1731 * zero we still need to transfer one packet
1733 packets_to_transfer
=
1734 DIV_ROUND_UP(bytes_to_transfer
, pipe
->max_packet
);
1735 if (packets_to_transfer
== 0)
1736 packets_to_transfer
= 1;
1737 else if ((packets_to_transfer
> 1) &&
1739 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1741 * Limit to one packet when not using DMA. Channels must
1742 * be restarted between every packet for IN
1743 * transactions, so there is no reason to do multiple
1746 packets_to_transfer
= 1;
1747 bytes_to_transfer
= packets_to_transfer
*
1749 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1751 * Limit the number of packet and data transferred to
1752 * what the hardware can handle
1754 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1755 bytes_to_transfer
= packets_to_transfer
*
1759 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1760 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1762 /* Update the DATA0/DATA1 toggle */
1763 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1765 * High speed pipes may need a hardware ping before they start
1767 if (pipe
->flags
& CVMX_USB_PIPE_FLAGS_NEED_PING
)
1768 usbc_hctsiz
.s
.dopng
= 1;
1770 cvmx_usb_write_csr32(usb
,
1771 CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1773 cvmx_usb_write_csr32(usb
,
1774 CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1778 /* Setup the Host Channel Characteristics Register */
1780 union cvmx_usbcx_hccharx usbc_hcchar
= {.u32
= 0};
1783 * Set the startframe odd/even properly. This is only used for
1786 usbc_hcchar
.s
.oddfrm
= usb
->frame_number
&1;
1789 * Set the number of back to back packets allowed by this
1790 * endpoint. Split transactions interpret "ec" as the number of
1791 * immediate retries of failure. These retries happen too
1792 * quickly, so we disable these entirely for splits
1794 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1795 usbc_hcchar
.s
.ec
= 1;
1796 else if (pipe
->multi_count
< 1)
1797 usbc_hcchar
.s
.ec
= 1;
1798 else if (pipe
->multi_count
> 3)
1799 usbc_hcchar
.s
.ec
= 3;
1801 usbc_hcchar
.s
.ec
= pipe
->multi_count
;
1803 /* Set the rest of the endpoint specific settings */
1804 usbc_hcchar
.s
.devaddr
= pipe
->device_addr
;
1805 usbc_hcchar
.s
.eptype
= transaction
->type
;
1806 usbc_hcchar
.s
.lspddev
=
1807 (pipe
->device_speed
== CVMX_USB_SPEED_LOW
);
1808 usbc_hcchar
.s
.epdir
= pipe
->transfer_dir
;
1809 usbc_hcchar
.s
.epnum
= pipe
->endpoint_num
;
1810 usbc_hcchar
.s
.mps
= pipe
->max_packet
;
1811 cvmx_usb_write_csr32(usb
,
1812 CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1816 /* Do transaction type specific fixups as needed */
1817 switch (transaction
->type
) {
1818 case CVMX_USB_TRANSFER_CONTROL
:
1819 cvmx_usb_start_channel_control(usb
, channel
, pipe
);
1821 case CVMX_USB_TRANSFER_BULK
:
1822 case CVMX_USB_TRANSFER_INTERRUPT
:
1824 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
1825 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1827 * ISO transactions require different PIDs depending on
1828 * direction and how many packets are needed
1830 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
1831 if (pipe
->multi_count
< 2) /* Need DATA0 */
1833 CVMX_USBCX_HCTSIZX(channel
,
1835 cvmx_usbcx_hctsizx
, pid
, 0);
1836 else /* Need MDATA */
1838 CVMX_USBCX_HCTSIZX(channel
,
1840 cvmx_usbcx_hctsizx
, pid
, 3);
1846 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
=
1847 cvmx_usb_read_csr32(usb
,
1848 CVMX_USBCX_HCTSIZX(channel
, usb
->index
))};
1849 transaction
->xfersize
= usbc_hctsiz
.s
.xfersize
;
1850 transaction
->pktcnt
= usbc_hctsiz
.s
.pktcnt
;
1852 /* Remember when we start a split transaction */
1853 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1854 usb
->active_split
= transaction
;
1855 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1856 cvmx_usbcx_hccharx
, chena
, 1);
1857 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
1858 cvmx_usb_fill_tx_fifo(usb
, channel
);
1863 * Find a pipe that is ready to be scheduled to hardware.
1864 * @usb: USB device state populated by cvmx_usb_initialize().
1865 * @list: Pipe list to search
1867 * Frame counter to use as a time reference.
1869 * Returns: Pipe or NULL if none are ready
1871 static struct cvmx_usb_pipe
*cvmx_usb_find_ready_pipe(
1872 struct cvmx_usb_state
*usb
,
1873 struct list_head
*list
,
1874 uint64_t current_frame
)
1876 struct cvmx_usb_pipe
*pipe
;
1878 list_for_each_entry(pipe
, list
, node
) {
1879 struct cvmx_usb_transaction
*t
=
1880 list_first_entry(&pipe
->transactions
, typeof(*t
),
1882 if (!(pipe
->flags
& CVMX_USB_PIPE_FLAGS_SCHEDULED
) && t
&&
1883 (pipe
->next_tx_frame
<= current_frame
) &&
1884 ((pipe
->split_sc_frame
== -1) ||
1885 ((((int)current_frame
- (int)pipe
->split_sc_frame
)
1887 (!usb
->active_split
|| (usb
->active_split
== t
))) {
1897 * Called whenever a pipe might need to be scheduled to the
1900 * @usb: USB device state populated by cvmx_usb_initialize().
1901 * @is_sof: True if this schedule was called on a SOF interrupt.
1903 static void cvmx_usb_schedule(struct cvmx_usb_state
*usb
, int is_sof
)
1906 struct cvmx_usb_pipe
*pipe
;
1908 enum cvmx_usb_transfer ttype
;
1910 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1912 * Without DMA we need to be careful to not schedule something
1913 * at the end of a frame and cause an overrun.
1915 union cvmx_usbcx_hfnum hfnum
= {
1916 .u32
= cvmx_usb_read_csr32(usb
,
1917 CVMX_USBCX_HFNUM(usb
->index
))
1920 union cvmx_usbcx_hfir hfir
= {
1921 .u32
= cvmx_usb_read_csr32(usb
,
1922 CVMX_USBCX_HFIR(usb
->index
))
1925 if (hfnum
.s
.frrem
< hfir
.s
.frint
/4)
1929 while (usb
->idle_hardware_channels
) {
1930 /* Find an idle channel */
1931 channel
= __fls(usb
->idle_hardware_channels
);
1932 if (unlikely(channel
> 7))
1935 /* Find a pipe needing service */
1939 * Only process periodic pipes on SOF interrupts. This
1940 * way we are sure that the periodic data is sent in the
1941 * beginning of the frame
1943 pipe
= cvmx_usb_find_ready_pipe(usb
,
1945 CVMX_USB_TRANSFER_ISOCHRONOUS
,
1948 pipe
= cvmx_usb_find_ready_pipe(usb
,
1950 CVMX_USB_TRANSFER_INTERRUPT
,
1953 if (likely(!pipe
)) {
1954 pipe
= cvmx_usb_find_ready_pipe(usb
,
1956 CVMX_USB_TRANSFER_CONTROL
,
1959 pipe
= cvmx_usb_find_ready_pipe(usb
,
1961 CVMX_USB_TRANSFER_BULK
,
1967 cvmx_usb_start_channel(usb
, channel
, pipe
);
1972 * Only enable SOF interrupts when we have transactions pending in the
1973 * future that might need to be scheduled
1976 for (ttype
= CVMX_USB_TRANSFER_CONTROL
;
1977 ttype
<= CVMX_USB_TRANSFER_INTERRUPT
; ttype
++) {
1978 list_for_each_entry(pipe
, &usb
->active_pipes
[ttype
], node
) {
1979 if (pipe
->next_tx_frame
> usb
->frame_number
) {
1985 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1986 cvmx_usbcx_gintmsk
, sofmsk
, need_sof
);
1989 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state
*usb
,
1990 enum cvmx_usb_complete status
,
1991 struct cvmx_usb_pipe
*pipe
,
1992 struct cvmx_usb_transaction
1994 int bytes_transferred
,
1997 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
1998 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
1999 struct device
*dev
= hcd
->self
.controller
;
2001 if (likely(status
== CVMX_USB_COMPLETE_SUCCESS
))
2002 urb
->actual_length
= bytes_transferred
;
2004 urb
->actual_length
= 0;
2008 /* For Isochronous transactions we need to update the URB packet status
2009 list from data in our private copy */
2010 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2013 * The pointer to the private list is stored in the setup_packet
2016 struct cvmx_usb_iso_packet
*iso_packet
=
2017 (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2018 /* Recalculate the transfer size by adding up each packet */
2019 urb
->actual_length
= 0;
2020 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
2021 if (iso_packet
[i
].status
==
2022 CVMX_USB_COMPLETE_SUCCESS
) {
2023 urb
->iso_frame_desc
[i
].status
= 0;
2024 urb
->iso_frame_desc
[i
].actual_length
=
2025 iso_packet
[i
].length
;
2026 urb
->actual_length
+=
2027 urb
->iso_frame_desc
[i
].actual_length
;
2029 dev_dbg(dev
, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2030 i
, urb
->number_of_packets
,
2031 iso_packet
[i
].status
, pipe
,
2032 transaction
, iso_packet
[i
].length
);
2033 urb
->iso_frame_desc
[i
].status
= -EREMOTEIO
;
2036 /* Free the private list now that we don't need it anymore */
2038 urb
->setup_packet
= NULL
;
2042 case CVMX_USB_COMPLETE_SUCCESS
:
2045 case CVMX_USB_COMPLETE_CANCEL
:
2046 if (urb
->status
== 0)
2047 urb
->status
= -ENOENT
;
2049 case CVMX_USB_COMPLETE_STALL
:
2050 dev_dbg(dev
, "status=stall pipe=%p transaction=%p size=%d\n",
2051 pipe
, transaction
, bytes_transferred
);
2052 urb
->status
= -EPIPE
;
2054 case CVMX_USB_COMPLETE_BABBLEERR
:
2055 dev_dbg(dev
, "status=babble pipe=%p transaction=%p size=%d\n",
2056 pipe
, transaction
, bytes_transferred
);
2057 urb
->status
= -EPIPE
;
2059 case CVMX_USB_COMPLETE_SHORT
:
2060 dev_dbg(dev
, "status=short pipe=%p transaction=%p size=%d\n",
2061 pipe
, transaction
, bytes_transferred
);
2062 urb
->status
= -EREMOTEIO
;
2064 case CVMX_USB_COMPLETE_ERROR
:
2065 case CVMX_USB_COMPLETE_XACTERR
:
2066 case CVMX_USB_COMPLETE_DATATGLERR
:
2067 case CVMX_USB_COMPLETE_FRAMEERR
:
2068 dev_dbg(dev
, "status=%d pipe=%p transaction=%p size=%d\n",
2069 status
, pipe
, transaction
, bytes_transferred
);
2070 urb
->status
= -EPROTO
;
2073 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(priv
), urb
);
2074 spin_unlock(&priv
->lock
);
2075 usb_hcd_giveback_urb(octeon_to_hcd(priv
), urb
, urb
->status
);
2076 spin_lock(&priv
->lock
);
2080 * Signal the completion of a transaction and free it. The
2081 * transaction will be removed from the pipe transaction list.
2083 * @usb: USB device state populated by cvmx_usb_initialize().
2084 * @pipe: Pipe the transaction is on
2086 * Transaction that completed
2090 static void cvmx_usb_perform_complete(struct cvmx_usb_state
*usb
,
2091 struct cvmx_usb_pipe
*pipe
,
2092 struct cvmx_usb_transaction
*transaction
,
2093 enum cvmx_usb_complete complete_code
)
2095 /* If this was a split then clear our split in progress marker */
2096 if (usb
->active_split
== transaction
)
2097 usb
->active_split
= NULL
;
2100 * Isochronous transactions need extra processing as they might not be
2101 * done after a single data transfer
2103 if (unlikely(transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
2104 /* Update the number of bytes transferred in this ISO packet */
2105 transaction
->iso_packets
[0].length
= transaction
->actual_bytes
;
2106 transaction
->iso_packets
[0].status
= complete_code
;
2109 * If there are more ISOs pending and we succeeded, schedule the
2112 if ((transaction
->iso_number_packets
> 1) &&
2113 (complete_code
== CVMX_USB_COMPLETE_SUCCESS
)) {
2114 /* No bytes transferred for this packet as of yet */
2115 transaction
->actual_bytes
= 0;
2116 /* One less ISO waiting to transfer */
2117 transaction
->iso_number_packets
--;
2118 /* Increment to the next location in our packet array */
2119 transaction
->iso_packets
++;
2120 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2125 /* Remove the transaction from the pipe list */
2126 list_del(&transaction
->node
);
2127 if (list_empty(&pipe
->transactions
))
2128 list_move_tail(&pipe
->node
, &usb
->idle_pipes
);
2129 octeon_usb_urb_complete_callback(usb
, complete_code
, pipe
,
2131 transaction
->actual_bytes
,
2138 * Submit a usb transaction to a pipe. Called for all types
2142 * @pipe: Which pipe to submit to.
2143 * @type: Transaction type
2144 * @buffer: User buffer for the transaction
2146 * User buffer's length in bytes
2148 * For control transactions, the 8 byte standard header
2150 * For ISO transactions, the start frame
2151 * @iso_number_packets:
2152 * For ISO, the number of packet in the transaction.
2154 * A description of each ISO packet
2155 * @urb: URB for the callback
2157 * Returns: Transaction or NULL on failure.
2159 static struct cvmx_usb_transaction
*cvmx_usb_submit_transaction(
2160 struct cvmx_usb_state
*usb
,
2161 struct cvmx_usb_pipe
*pipe
,
2162 enum cvmx_usb_transfer type
,
2165 uint64_t control_header
,
2166 int iso_start_frame
,
2167 int iso_number_packets
,
2168 struct cvmx_usb_iso_packet
*iso_packets
,
2171 struct cvmx_usb_transaction
*transaction
;
2173 if (unlikely(pipe
->transfer_type
!= type
))
2176 transaction
= kzalloc(sizeof(*transaction
), GFP_ATOMIC
);
2177 if (unlikely(!transaction
))
2180 transaction
->type
= type
;
2181 transaction
->buffer
= buffer
;
2182 transaction
->buffer_length
= buffer_length
;
2183 transaction
->control_header
= control_header
;
2184 /* FIXME: This is not used, implement it. */
2185 transaction
->iso_start_frame
= iso_start_frame
;
2186 transaction
->iso_number_packets
= iso_number_packets
;
2187 transaction
->iso_packets
= iso_packets
;
2188 transaction
->urb
= urb
;
2189 if (transaction
->type
== CVMX_USB_TRANSFER_CONTROL
)
2190 transaction
->stage
= CVMX_USB_STAGE_SETUP
;
2192 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2194 if (!list_empty(&pipe
->transactions
)) {
2195 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2197 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2198 list_move_tail(&pipe
->node
,
2199 &usb
->active_pipes
[pipe
->transfer_type
]);
2202 * We may need to schedule the pipe if this was the head of the
2205 cvmx_usb_schedule(usb
, 0);
2213 * Call to submit a USB Bulk transfer to a pipe.
2215 * @usb: USB device state populated by cvmx_usb_initialize().
2216 * @pipe: Handle to the pipe for the transfer.
2219 * Returns: A submitted transaction or NULL on failure.
2221 static struct cvmx_usb_transaction
*cvmx_usb_submit_bulk(
2222 struct cvmx_usb_state
*usb
,
2223 struct cvmx_usb_pipe
*pipe
,
2226 return cvmx_usb_submit_transaction(usb
, pipe
, CVMX_USB_TRANSFER_BULK
,
2228 urb
->transfer_buffer_length
,
2229 0, /* control_header */
2230 0, /* iso_start_frame */
2231 0, /* iso_number_packets */
2232 NULL
, /* iso_packets */
2238 * Call to submit a USB Interrupt transfer to a pipe.
2240 * @usb: USB device state populated by cvmx_usb_initialize().
2241 * @pipe: Handle to the pipe for the transfer.
2242 * @urb: URB returned when the callback is called.
2244 * Returns: A submitted transaction or NULL on failure.
2246 static struct cvmx_usb_transaction
*cvmx_usb_submit_interrupt(
2247 struct cvmx_usb_state
*usb
,
2248 struct cvmx_usb_pipe
*pipe
,
2251 return cvmx_usb_submit_transaction(usb
, pipe
,
2252 CVMX_USB_TRANSFER_INTERRUPT
,
2254 urb
->transfer_buffer_length
,
2255 0, /* control_header */
2256 0, /* iso_start_frame */
2257 0, /* iso_number_packets */
2258 NULL
, /* iso_packets */
2264 * Call to submit a USB Control transfer to a pipe.
2266 * @usb: USB device state populated by cvmx_usb_initialize().
2267 * @pipe: Handle to the pipe for the transfer.
2270 * Returns: A submitted transaction or NULL on failure.
2272 static struct cvmx_usb_transaction
*cvmx_usb_submit_control(
2273 struct cvmx_usb_state
*usb
,
2274 struct cvmx_usb_pipe
*pipe
,
2277 int buffer_length
= urb
->transfer_buffer_length
;
2278 uint64_t control_header
= urb
->setup_dma
;
2279 struct usb_ctrlrequest
*header
= cvmx_phys_to_ptr(control_header
);
2281 if ((header
->bRequestType
& USB_DIR_IN
) == 0)
2282 buffer_length
= le16_to_cpu(header
->wLength
);
2284 return cvmx_usb_submit_transaction(usb
, pipe
,
2285 CVMX_USB_TRANSFER_CONTROL
,
2286 urb
->transfer_dma
, buffer_length
,
2288 0, /* iso_start_frame */
2289 0, /* iso_number_packets */
2290 NULL
, /* iso_packets */
2296 * Call to submit a USB Isochronous transfer to a pipe.
2298 * @usb: USB device state populated by cvmx_usb_initialize().
2299 * @pipe: Handle to the pipe for the transfer.
2300 * @urb: URB returned when the callback is called.
2302 * Returns: A submitted transaction or NULL on failure.
2304 static struct cvmx_usb_transaction
*cvmx_usb_submit_isochronous(
2305 struct cvmx_usb_state
*usb
,
2306 struct cvmx_usb_pipe
*pipe
,
2309 struct cvmx_usb_iso_packet
*packets
;
2311 packets
= (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2312 return cvmx_usb_submit_transaction(usb
, pipe
,
2313 CVMX_USB_TRANSFER_ISOCHRONOUS
,
2315 urb
->transfer_buffer_length
,
2316 0, /* control_header */
2318 urb
->number_of_packets
,
2324 * Cancel one outstanding request in a pipe. Canceling a request
2325 * can fail if the transaction has already completed before cancel
2326 * is called. Even after a successful cancel call, it may take
2327 * a frame or two for the cvmx_usb_poll() function to call the
2328 * associated callback.
2330 * @usb: USB device state populated by cvmx_usb_initialize().
2331 * @pipe: Pipe to cancel requests in.
2332 * @transaction: Transaction to cancel, returned by the submit function.
2334 * Returns: 0 or a negative error code.
2336 static int cvmx_usb_cancel(struct cvmx_usb_state
*usb
,
2337 struct cvmx_usb_pipe
*pipe
,
2338 struct cvmx_usb_transaction
*transaction
)
2341 * If the transaction is the HEAD of the queue and scheduled. We need to
2344 if (list_first_entry(&pipe
->transactions
, typeof(*transaction
), node
) ==
2345 transaction
&& (pipe
->flags
& CVMX_USB_PIPE_FLAGS_SCHEDULED
)) {
2346 union cvmx_usbcx_hccharx usbc_hcchar
;
2348 usb
->pipe_for_channel
[pipe
->channel
] = NULL
;
2349 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2353 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2354 CVMX_USBCX_HCCHARX(pipe
->channel
, usb
->index
));
2356 * If the channel isn't enabled then the transaction already
2359 if (usbc_hcchar
.s
.chena
) {
2360 usbc_hcchar
.s
.chdis
= 1;
2361 cvmx_usb_write_csr32(usb
,
2362 CVMX_USBCX_HCCHARX(pipe
->channel
,
2367 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2368 CVMX_USB_COMPLETE_CANCEL
);
2374 * Cancel all outstanding requests in a pipe. Logically all this
2375 * does is call cvmx_usb_cancel() in a loop.
2377 * @usb: USB device state populated by cvmx_usb_initialize().
2378 * @pipe: Pipe to cancel requests in.
2380 * Returns: 0 or a negative error code.
2382 static int cvmx_usb_cancel_all(struct cvmx_usb_state
*usb
,
2383 struct cvmx_usb_pipe
*pipe
)
2385 struct cvmx_usb_transaction
*transaction
, *next
;
2387 /* Simply loop through and attempt to cancel each transaction */
2388 list_for_each_entry_safe(transaction
, next
, &pipe
->transactions
, node
) {
2389 int result
= cvmx_usb_cancel(usb
, pipe
, transaction
);
2391 if (unlikely(result
!= 0))
2399 * Close a pipe created with cvmx_usb_open_pipe().
2401 * @usb: USB device state populated by cvmx_usb_initialize().
2402 * @pipe: Pipe to close.
2404 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2405 * outstanding transfers.
2407 static int cvmx_usb_close_pipe(struct cvmx_usb_state
*usb
,
2408 struct cvmx_usb_pipe
*pipe
)
2410 /* Fail if the pipe has pending transactions */
2411 if (!list_empty(&pipe
->transactions
))
2414 list_del(&pipe
->node
);
2421 * Get the current USB protocol level frame number. The frame
2422 * number is always in the range of 0-0x7ff.
2424 * @usb: USB device state populated by cvmx_usb_initialize().
2426 * Returns: USB frame number
2428 static int cvmx_usb_get_frame_number(struct cvmx_usb_state
*usb
)
2431 union cvmx_usbcx_hfnum usbc_hfnum
;
2433 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2434 frame_number
= usbc_hfnum
.s
.frnum
;
2436 return frame_number
;
2441 * Poll a channel for status
2444 * @channel: Channel to poll
2446 * Returns: Zero on success
2448 static int cvmx_usb_poll_channel(struct cvmx_usb_state
*usb
, int channel
)
2450 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2451 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
2452 struct device
*dev
= hcd
->self
.controller
;
2453 union cvmx_usbcx_hcintx usbc_hcint
;
2454 union cvmx_usbcx_hctsizx usbc_hctsiz
;
2455 union cvmx_usbcx_hccharx usbc_hcchar
;
2456 struct cvmx_usb_pipe
*pipe
;
2457 struct cvmx_usb_transaction
*transaction
;
2458 int bytes_this_transfer
;
2459 int bytes_in_last_packet
;
2460 int packets_processed
;
2461 int buffer_space_left
;
2463 /* Read the interrupt status bits for the channel */
2464 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
2465 CVMX_USBCX_HCINTX(channel
, usb
->index
));
2467 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
2468 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2469 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2471 if (usbc_hcchar
.s
.chena
&& usbc_hcchar
.s
.chdis
) {
2473 * There seems to be a bug in CN31XX which can cause
2474 * interrupt IN transfers to get stuck until we do a
2475 * write of HCCHARX without changing things
2477 cvmx_usb_write_csr32(usb
,
2478 CVMX_USBCX_HCCHARX(channel
,
2485 * In non DMA mode the channels don't halt themselves. We need
2486 * to manually disable channels that are left running
2488 if (!usbc_hcint
.s
.chhltd
) {
2489 if (usbc_hcchar
.s
.chena
) {
2490 union cvmx_usbcx_hcintmskx hcintmsk
;
2491 /* Disable all interrupts except CHHLTD */
2493 hcintmsk
.s
.chhltdmsk
= 1;
2494 cvmx_usb_write_csr32(usb
,
2495 CVMX_USBCX_HCINTMSKX(channel
,
2498 usbc_hcchar
.s
.chdis
= 1;
2499 cvmx_usb_write_csr32(usb
,
2500 CVMX_USBCX_HCCHARX(channel
,
2504 } else if (usbc_hcint
.s
.xfercompl
) {
2506 * Successful IN/OUT with transfer complete.
2507 * Channel halt isn't needed.
2510 dev_err(dev
, "USB%d: Channel %d interrupt without halt\n",
2511 usb
->index
, channel
);
2517 * There is are no interrupts that we need to process when the
2518 * channel is still running
2520 if (!usbc_hcint
.s
.chhltd
)
2524 /* Disable the channel interrupts now that it is done */
2525 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
2526 usb
->idle_hardware_channels
|= (1<<channel
);
2528 /* Make sure this channel is tied to a valid pipe */
2529 pipe
= usb
->pipe_for_channel
[channel
];
2533 transaction
= list_first_entry(&pipe
->transactions
,
2534 typeof(*transaction
),
2536 prefetch(transaction
);
2539 * Disconnect this pipe from the HW channel. Later the schedule
2540 * function will figure out which pipe needs to go
2542 usb
->pipe_for_channel
[channel
] = NULL
;
2543 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2546 * Read the channel config info so we can figure out how much data
2549 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2550 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2551 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
2552 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
2555 * Calculating the number of bytes successfully transferred is dependent
2556 * on the transfer direction
2558 packets_processed
= transaction
->pktcnt
- usbc_hctsiz
.s
.pktcnt
;
2559 if (usbc_hcchar
.s
.epdir
) {
2561 * IN transactions are easy. For every byte received the
2562 * hardware decrements xfersize. All we need to do is subtract
2563 * the current value of xfersize from its starting value and we
2564 * know how many bytes were written to the buffer
2566 bytes_this_transfer
= transaction
->xfersize
-
2567 usbc_hctsiz
.s
.xfersize
;
2570 * OUT transaction don't decrement xfersize. Instead pktcnt is
2571 * decremented on every successful packet send. The hardware
2572 * does this when it receives an ACK, or NYET. If it doesn't
2573 * receive one of these responses pktcnt doesn't change
2575 bytes_this_transfer
= packets_processed
* usbc_hcchar
.s
.mps
;
2577 * The last packet may not be a full transfer if we didn't have
2580 if (bytes_this_transfer
> transaction
->xfersize
)
2581 bytes_this_transfer
= transaction
->xfersize
;
2583 /* Figure out how many bytes were in the last packet of the transfer */
2584 if (packets_processed
)
2585 bytes_in_last_packet
= bytes_this_transfer
-
2586 (packets_processed
- 1) * usbc_hcchar
.s
.mps
;
2588 bytes_in_last_packet
= bytes_this_transfer
;
2591 * As a special case, setup transactions output the setup header, not
2592 * the user's data. For this reason we don't count setup data as bytes
2595 if ((transaction
->stage
== CVMX_USB_STAGE_SETUP
) ||
2596 (transaction
->stage
== CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
))
2597 bytes_this_transfer
= 0;
2600 * Add the bytes transferred to the running total. It is important that
2601 * bytes_this_transfer doesn't count any data that needs to be
2604 transaction
->actual_bytes
+= bytes_this_transfer
;
2605 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
2606 buffer_space_left
= transaction
->iso_packets
[0].length
-
2607 transaction
->actual_bytes
;
2609 buffer_space_left
= transaction
->buffer_length
-
2610 transaction
->actual_bytes
;
2613 * We need to remember the PID toggle state for the next transaction.
2614 * The hardware already updated it for the next transaction
2616 pipe
->pid_toggle
= !(usbc_hctsiz
.s
.pid
== 0);
2619 * For high speed bulk out, assume the next transaction will need to do
2620 * a ping before proceeding. If this isn't true the ACK processing below
2621 * will clear this flag
2623 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2624 (pipe
->transfer_type
== CVMX_USB_TRANSFER_BULK
) &&
2625 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
))
2626 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
2628 if (unlikely(WARN_ON_ONCE(bytes_this_transfer
< 0))) {
2630 * In some rare cases the DMA engine seems to get stuck and
2631 * keeps substracting same byte count over and over again. In
2632 * such case we just need to fail every transaction.
2634 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2635 CVMX_USB_COMPLETE_ERROR
);
2639 if (usbc_hcint
.s
.stall
) {
2641 * STALL as a response means this transaction cannot be
2642 * completed because the device can't process transactions. Tell
2643 * the user. Any data that was transferred will be counted on
2644 * the actual bytes transferred
2646 pipe
->pid_toggle
= 0;
2647 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2648 CVMX_USB_COMPLETE_STALL
);
2649 } else if (usbc_hcint
.s
.xacterr
) {
2651 * XactErr as a response means the device signaled
2652 * something wrong with the transfer. For example, PID
2653 * toggle errors cause these.
2655 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2656 CVMX_USB_COMPLETE_XACTERR
);
2657 } else if (usbc_hcint
.s
.bblerr
) {
2658 /* Babble Error (BblErr) */
2659 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2660 CVMX_USB_COMPLETE_BABBLEERR
);
2661 } else if (usbc_hcint
.s
.datatglerr
) {
2662 /* Data toggle error */
2663 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2664 CVMX_USB_COMPLETE_DATATGLERR
);
2665 } else if (usbc_hcint
.s
.nyet
) {
2667 * NYET as a response is only allowed in three cases: as a
2668 * response to a ping, as a response to a split transaction, and
2669 * as a response to a bulk out. The ping case is handled by
2670 * hardware, so we only have splits and bulk out
2672 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2673 transaction
->retries
= 0;
2675 * If there is more data to go then we need to try
2676 * again. Otherwise this transaction is complete
2678 if ((buffer_space_left
== 0) ||
2679 (bytes_in_last_packet
< pipe
->max_packet
))
2680 cvmx_usb_perform_complete(usb
, pipe
,
2682 CVMX_USB_COMPLETE_SUCCESS
);
2685 * Split transactions retry the split complete 4 times
2686 * then rewind to the start split and do the entire
2687 * transactions again
2689 transaction
->retries
++;
2690 if ((transaction
->retries
& 0x3) == 0) {
2692 * Rewind to the beginning of the transaction by
2693 * anding off the split complete bit
2695 transaction
->stage
&= ~1;
2696 pipe
->split_sc_frame
= -1;
2699 } else if (usbc_hcint
.s
.ack
) {
2700 transaction
->retries
= 0;
2702 * The ACK bit can only be checked after the other error bits.
2703 * This is because a multi packet transfer may succeed in a
2704 * number of packets and then get a different response on the
2705 * last packet. In this case both ACK and the last response bit
2706 * will be set. If none of the other response bits is set, then
2707 * the last packet must have been an ACK
2709 * Since we got an ACK, we know we don't need to do a ping on
2712 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_NEED_PING
;
2714 switch (transaction
->type
) {
2715 case CVMX_USB_TRANSFER_CONTROL
:
2716 switch (transaction
->stage
) {
2717 case CVMX_USB_STAGE_NON_CONTROL
:
2718 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
2719 /* This should be impossible */
2720 cvmx_usb_perform_complete(usb
, pipe
,
2721 transaction
, CVMX_USB_COMPLETE_ERROR
);
2723 case CVMX_USB_STAGE_SETUP
:
2724 pipe
->pid_toggle
= 1;
2725 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2726 transaction
->stage
=
2727 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
;
2729 struct usb_ctrlrequest
*header
=
2730 cvmx_phys_to_ptr(transaction
->control_header
);
2731 if (header
->wLength
)
2732 transaction
->stage
=
2733 CVMX_USB_STAGE_DATA
;
2735 transaction
->stage
=
2736 CVMX_USB_STAGE_STATUS
;
2739 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
2741 struct usb_ctrlrequest
*header
=
2742 cvmx_phys_to_ptr(transaction
->control_header
);
2743 if (header
->wLength
)
2744 transaction
->stage
=
2745 CVMX_USB_STAGE_DATA
;
2747 transaction
->stage
=
2748 CVMX_USB_STAGE_STATUS
;
2751 case CVMX_USB_STAGE_DATA
:
2752 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2753 transaction
->stage
=
2754 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
;
2756 * For setup OUT data that are splits,
2757 * the hardware doesn't appear to count
2758 * transferred data. Here we manually
2759 * update the data transferred
2761 if (!usbc_hcchar
.s
.epdir
) {
2762 if (buffer_space_left
< pipe
->max_packet
)
2763 transaction
->actual_bytes
+=
2766 transaction
->actual_bytes
+=
2769 } else if ((buffer_space_left
== 0) ||
2770 (bytes_in_last_packet
<
2771 pipe
->max_packet
)) {
2772 pipe
->pid_toggle
= 1;
2773 transaction
->stage
=
2774 CVMX_USB_STAGE_STATUS
;
2777 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
2778 if ((buffer_space_left
== 0) ||
2779 (bytes_in_last_packet
<
2780 pipe
->max_packet
)) {
2781 pipe
->pid_toggle
= 1;
2782 transaction
->stage
=
2783 CVMX_USB_STAGE_STATUS
;
2785 transaction
->stage
=
2786 CVMX_USB_STAGE_DATA
;
2789 case CVMX_USB_STAGE_STATUS
:
2790 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2791 transaction
->stage
=
2792 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
;
2794 cvmx_usb_perform_complete(usb
, pipe
,
2796 CVMX_USB_COMPLETE_SUCCESS
);
2798 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
2799 cvmx_usb_perform_complete(usb
, pipe
,
2801 CVMX_USB_COMPLETE_SUCCESS
);
2805 case CVMX_USB_TRANSFER_BULK
:
2806 case CVMX_USB_TRANSFER_INTERRUPT
:
2808 * The only time a bulk transfer isn't complete when it
2809 * finishes with an ACK is during a split transaction.
2810 * For splits we need to continue the transfer if more
2813 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2814 if (transaction
->stage
==
2815 CVMX_USB_STAGE_NON_CONTROL
)
2816 transaction
->stage
=
2817 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2819 if (buffer_space_left
&&
2820 (bytes_in_last_packet
==
2822 transaction
->stage
=
2823 CVMX_USB_STAGE_NON_CONTROL
;
2825 if (transaction
->type
==
2826 CVMX_USB_TRANSFER_INTERRUPT
)
2827 pipe
->next_tx_frame
+=
2829 cvmx_usb_perform_complete(
2833 CVMX_USB_COMPLETE_SUCCESS
);
2837 if ((pipe
->device_speed
==
2838 CVMX_USB_SPEED_HIGH
) &&
2839 (pipe
->transfer_type
==
2840 CVMX_USB_TRANSFER_BULK
) &&
2841 (pipe
->transfer_dir
==
2842 CVMX_USB_DIRECTION_OUT
) &&
2845 CVMX_USB_PIPE_FLAGS_NEED_PING
;
2846 if (!buffer_space_left
||
2847 (bytes_in_last_packet
<
2848 pipe
->max_packet
)) {
2849 if (transaction
->type
==
2850 CVMX_USB_TRANSFER_INTERRUPT
)
2851 pipe
->next_tx_frame
+=
2853 cvmx_usb_perform_complete(usb
, pipe
,
2855 CVMX_USB_COMPLETE_SUCCESS
);
2859 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
2860 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2862 * ISOCHRONOUS OUT splits don't require a
2863 * complete split stage. Instead they use a
2864 * sequence of begin OUT splits to transfer the
2865 * data 188 bytes at a time. Once the transfer
2866 * is complete, the pipe sleeps until the next
2869 if (pipe
->transfer_dir
==
2870 CVMX_USB_DIRECTION_OUT
) {
2872 * If no space left or this wasn't a max
2873 * size packet then this transfer is
2874 * complete. Otherwise start it again to
2875 * send the next 188 bytes
2877 if (!buffer_space_left
||
2878 (bytes_this_transfer
< 188)) {
2879 pipe
->next_tx_frame
+=
2881 cvmx_usb_perform_complete(usb
,
2883 CVMX_USB_COMPLETE_SUCCESS
);
2886 if (transaction
->stage
==
2887 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
) {
2889 * We are in the incoming data
2890 * phase. Keep getting data
2891 * until we run out of space or
2892 * get a small packet
2894 if ((buffer_space_left
== 0) ||
2895 (bytes_in_last_packet
<
2896 pipe
->max_packet
)) {
2897 pipe
->next_tx_frame
+=
2899 cvmx_usb_perform_complete(
2903 CVMX_USB_COMPLETE_SUCCESS
);
2906 transaction
->stage
=
2907 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2910 pipe
->next_tx_frame
+= pipe
->interval
;
2911 cvmx_usb_perform_complete(usb
, pipe
,
2913 CVMX_USB_COMPLETE_SUCCESS
);
2917 } else if (usbc_hcint
.s
.nak
) {
2919 * If this was a split then clear our split in progress marker.
2921 if (usb
->active_split
== transaction
)
2922 usb
->active_split
= NULL
;
2924 * NAK as a response means the device couldn't accept the
2925 * transaction, but it should be retried in the future. Rewind
2926 * to the beginning of the transaction by anding off the split
2927 * complete bit. Retry in the next interval
2929 transaction
->retries
= 0;
2930 transaction
->stage
&= ~1;
2931 pipe
->next_tx_frame
+= pipe
->interval
;
2932 if (pipe
->next_tx_frame
< usb
->frame_number
)
2933 pipe
->next_tx_frame
= usb
->frame_number
+
2935 (usb
->frame_number
- pipe
->next_tx_frame
) %
2938 struct cvmx_usb_port_status port
;
2940 port
= cvmx_usb_get_status(usb
);
2941 if (port
.port_enabled
) {
2942 /* We'll retry the exact same transaction again */
2943 transaction
->retries
++;
2946 * We get channel halted interrupts with no result bits
2947 * sets when the cable is unplugged
2949 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2950 CVMX_USB_COMPLETE_ERROR
);
2956 static void octeon_usb_port_callback(struct cvmx_usb_state
*usb
)
2958 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2960 spin_unlock(&priv
->lock
);
2961 usb_hcd_poll_rh_status(octeon_to_hcd(priv
));
2962 spin_lock(&priv
->lock
);
2966 * Poll the USB block for status and call all needed callback
2967 * handlers. This function is meant to be called in the interrupt
2968 * handler for the USB controller. It can also be called
2969 * periodically in a loop for non-interrupt based operation.
2971 * @usb: USB device state populated by cvmx_usb_initialize().
2973 * Returns: 0 or a negative error code.
2975 static int cvmx_usb_poll(struct cvmx_usb_state
*usb
)
2977 union cvmx_usbcx_hfnum usbc_hfnum
;
2978 union cvmx_usbcx_gintsts usbc_gintsts
;
2980 prefetch_range(usb
, sizeof(*usb
));
2982 /* Update the frame counter */
2983 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2984 if ((usb
->frame_number
&0x3fff) > usbc_hfnum
.s
.frnum
)
2985 usb
->frame_number
+= 0x4000;
2986 usb
->frame_number
&= ~0x3fffull
;
2987 usb
->frame_number
|= usbc_hfnum
.s
.frnum
;
2989 /* Read the pending interrupts */
2990 usbc_gintsts
.u32
= cvmx_usb_read_csr32(usb
,
2991 CVMX_USBCX_GINTSTS(usb
->index
));
2993 /* Clear the interrupts now that we know about them */
2994 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
),
2997 if (usbc_gintsts
.s
.rxflvl
) {
2999 * RxFIFO Non-Empty (RxFLvl)
3000 * Indicates that there is at least one packet pending to be
3001 * read from the RxFIFO.
3003 * In DMA mode this is handled by hardware
3005 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3006 cvmx_usb_poll_rx_fifo(usb
);
3008 if (usbc_gintsts
.s
.ptxfemp
|| usbc_gintsts
.s
.nptxfemp
) {
3009 /* Fill the Tx FIFOs when not in DMA mode */
3010 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3011 cvmx_usb_poll_tx_fifo(usb
);
3013 if (usbc_gintsts
.s
.disconnint
|| usbc_gintsts
.s
.prtint
) {
3014 union cvmx_usbcx_hprt usbc_hprt
;
3016 * Disconnect Detected Interrupt (DisconnInt)
3017 * Asserted when a device disconnect is detected.
3019 * Host Port Interrupt (PrtInt)
3020 * The core sets this bit to indicate a change in port status of
3021 * one of the O2P USB core ports in Host mode. The application
3022 * must read the Host Port Control and Status (HPRT) register to
3023 * determine the exact event that caused this interrupt. The
3024 * application must clear the appropriate status bit in the Host
3025 * Port Control and Status register to clear this bit.
3027 * Call the user's port callback
3029 octeon_usb_port_callback(usb
);
3030 /* Clear the port change bits */
3031 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
,
3032 CVMX_USBCX_HPRT(usb
->index
));
3033 usbc_hprt
.s
.prtena
= 0;
3034 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
),
3037 if (usbc_gintsts
.s
.hchint
) {
3039 * Host Channels Interrupt (HChInt)
3040 * The core sets this bit to indicate that an interrupt is
3041 * pending on one of the channels of the core (in Host mode).
3042 * The application must read the Host All Channels Interrupt
3043 * (HAINT) register to determine the exact number of the channel
3044 * on which the interrupt occurred, and then read the
3045 * corresponding Host Channel-n Interrupt (HCINTn) register to
3046 * determine the exact cause of the interrupt. The application
3047 * must clear the appropriate status bit in the HCINTn register
3048 * to clear this bit.
3050 union cvmx_usbcx_haint usbc_haint
;
3052 usbc_haint
.u32
= cvmx_usb_read_csr32(usb
,
3053 CVMX_USBCX_HAINT(usb
->index
));
3054 while (usbc_haint
.u32
) {
3057 channel
= __fls(usbc_haint
.u32
);
3058 cvmx_usb_poll_channel(usb
, channel
);
3059 usbc_haint
.u32
^= 1<<channel
;
3063 cvmx_usb_schedule(usb
, usbc_gintsts
.s
.sof
);
3068 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3069 static inline struct octeon_hcd
*hcd_to_octeon(struct usb_hcd
*hcd
)
3071 return (struct octeon_hcd
*)(hcd
->hcd_priv
);
3074 static irqreturn_t
octeon_usb_irq(struct usb_hcd
*hcd
)
3076 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3077 unsigned long flags
;
3079 spin_lock_irqsave(&priv
->lock
, flags
);
3080 cvmx_usb_poll(&priv
->usb
);
3081 spin_unlock_irqrestore(&priv
->lock
, flags
);
3085 static int octeon_usb_start(struct usb_hcd
*hcd
)
3087 hcd
->state
= HC_STATE_RUNNING
;
3091 static void octeon_usb_stop(struct usb_hcd
*hcd
)
3093 hcd
->state
= HC_STATE_HALT
;
3096 static int octeon_usb_get_frame_number(struct usb_hcd
*hcd
)
3098 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3100 return cvmx_usb_get_frame_number(&priv
->usb
);
3103 static int octeon_usb_urb_enqueue(struct usb_hcd
*hcd
,
3107 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3108 struct device
*dev
= hcd
->self
.controller
;
3109 struct cvmx_usb_transaction
*transaction
= NULL
;
3110 struct cvmx_usb_pipe
*pipe
;
3111 unsigned long flags
;
3112 struct cvmx_usb_iso_packet
*iso_packet
;
3113 struct usb_host_endpoint
*ep
= urb
->ep
;
3117 spin_lock_irqsave(&priv
->lock
, flags
);
3119 rc
= usb_hcd_link_urb_to_ep(hcd
, urb
);
3121 spin_unlock_irqrestore(&priv
->lock
, flags
);
3126 enum cvmx_usb_transfer transfer_type
;
3127 enum cvmx_usb_speed speed
;
3128 int split_device
= 0;
3131 switch (usb_pipetype(urb
->pipe
)) {
3132 case PIPE_ISOCHRONOUS
:
3133 transfer_type
= CVMX_USB_TRANSFER_ISOCHRONOUS
;
3135 case PIPE_INTERRUPT
:
3136 transfer_type
= CVMX_USB_TRANSFER_INTERRUPT
;
3139 transfer_type
= CVMX_USB_TRANSFER_CONTROL
;
3142 transfer_type
= CVMX_USB_TRANSFER_BULK
;
3145 switch (urb
->dev
->speed
) {
3147 speed
= CVMX_USB_SPEED_LOW
;
3149 case USB_SPEED_FULL
:
3150 speed
= CVMX_USB_SPEED_FULL
;
3153 speed
= CVMX_USB_SPEED_HIGH
;
3157 * For slow devices on high speed ports we need to find the hub
3158 * that does the speed translation so we know where to send the
3159 * split transactions.
3161 if (speed
!= CVMX_USB_SPEED_HIGH
) {
3163 * Start at this device and work our way up the usb
3166 struct usb_device
*dev
= urb
->dev
;
3168 while (dev
->parent
) {
3170 * If our parent is high speed then he'll
3171 * receive the splits.
3173 if (dev
->parent
->speed
== USB_SPEED_HIGH
) {
3174 split_device
= dev
->parent
->devnum
;
3175 split_port
= dev
->portnum
;
3179 * Move up the tree one level. If we make it all
3180 * the way up the tree, then the port must not
3181 * be in high speed mode and we don't need a
3187 pipe
= cvmx_usb_open_pipe(&priv
->usb
, usb_pipedevice(urb
->pipe
),
3188 usb_pipeendpoint(urb
->pipe
), speed
,
3189 le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3192 usb_pipein(urb
->pipe
) ?
3193 CVMX_USB_DIRECTION_IN
:
3194 CVMX_USB_DIRECTION_OUT
,
3196 (le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3198 split_device
, split_port
);
3200 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3201 spin_unlock_irqrestore(&priv
->lock
, flags
);
3202 dev_dbg(dev
, "Failed to create pipe\n");
3210 switch (usb_pipetype(urb
->pipe
)) {
3211 case PIPE_ISOCHRONOUS
:
3212 dev_dbg(dev
, "Submit isochronous to %d.%d\n",
3213 usb_pipedevice(urb
->pipe
),
3214 usb_pipeendpoint(urb
->pipe
));
3216 * Allocate a structure to use for our private list of
3217 * isochronous packets.
3219 iso_packet
= kmalloc(urb
->number_of_packets
*
3220 sizeof(struct cvmx_usb_iso_packet
),
3224 /* Fill the list with the data from the URB */
3225 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
3226 iso_packet
[i
].offset
=
3227 urb
->iso_frame_desc
[i
].offset
;
3228 iso_packet
[i
].length
=
3229 urb
->iso_frame_desc
[i
].length
;
3230 iso_packet
[i
].status
=
3231 CVMX_USB_COMPLETE_ERROR
;
3234 * Store a pointer to the list in the URB setup_packet
3235 * field. We know this currently isn't being used and
3236 * this saves us a bunch of logic.
3238 urb
->setup_packet
= (char *)iso_packet
;
3239 transaction
= cvmx_usb_submit_isochronous(&priv
->usb
,
3242 * If submit failed we need to free our private packet
3246 urb
->setup_packet
= NULL
;
3251 case PIPE_INTERRUPT
:
3252 dev_dbg(dev
, "Submit interrupt to %d.%d\n",
3253 usb_pipedevice(urb
->pipe
),
3254 usb_pipeendpoint(urb
->pipe
));
3255 transaction
= cvmx_usb_submit_interrupt(&priv
->usb
, pipe
, urb
);
3258 dev_dbg(dev
, "Submit control to %d.%d\n",
3259 usb_pipedevice(urb
->pipe
),
3260 usb_pipeendpoint(urb
->pipe
));
3261 transaction
= cvmx_usb_submit_control(&priv
->usb
, pipe
, urb
);
3264 dev_dbg(dev
, "Submit bulk to %d.%d\n",
3265 usb_pipedevice(urb
->pipe
),
3266 usb_pipeendpoint(urb
->pipe
));
3267 transaction
= cvmx_usb_submit_bulk(&priv
->usb
, pipe
, urb
);
3271 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3272 spin_unlock_irqrestore(&priv
->lock
, flags
);
3273 dev_dbg(dev
, "Failed to submit\n");
3276 urb
->hcpriv
= transaction
;
3277 spin_unlock_irqrestore(&priv
->lock
, flags
);
3281 static int octeon_usb_urb_dequeue(struct usb_hcd
*hcd
,
3285 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3286 unsigned long flags
;
3292 spin_lock_irqsave(&priv
->lock
, flags
);
3294 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
3298 urb
->status
= status
;
3299 cvmx_usb_cancel(&priv
->usb
, urb
->ep
->hcpriv
, urb
->hcpriv
);
3302 spin_unlock_irqrestore(&priv
->lock
, flags
);
3307 static void octeon_usb_endpoint_disable(struct usb_hcd
*hcd
,
3308 struct usb_host_endpoint
*ep
)
3310 struct device
*dev
= hcd
->self
.controller
;
3313 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3314 struct cvmx_usb_pipe
*pipe
= ep
->hcpriv
;
3315 unsigned long flags
;
3317 spin_lock_irqsave(&priv
->lock
, flags
);
3318 cvmx_usb_cancel_all(&priv
->usb
, pipe
);
3319 if (cvmx_usb_close_pipe(&priv
->usb
, pipe
))
3320 dev_dbg(dev
, "Closing pipe %p failed\n", pipe
);
3321 spin_unlock_irqrestore(&priv
->lock
, flags
);
3326 static int octeon_usb_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
3328 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3329 struct cvmx_usb_port_status port_status
;
3330 unsigned long flags
;
3332 spin_lock_irqsave(&priv
->lock
, flags
);
3333 port_status
= cvmx_usb_get_status(&priv
->usb
);
3334 spin_unlock_irqrestore(&priv
->lock
, flags
);
3336 buf
[0] = port_status
.connect_change
<< 1;
3341 static int octeon_usb_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
3342 u16 wIndex
, char *buf
, u16 wLength
)
3344 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3345 struct device
*dev
= hcd
->self
.controller
;
3346 struct cvmx_usb_port_status usb_port_status
;
3347 struct cvmx_usb_state
*usb
= &priv
->usb
;
3349 struct usb_hub_descriptor
*desc
;
3350 unsigned long flags
;
3353 case ClearHubFeature
:
3354 dev_dbg(dev
, "ClearHubFeature\n");
3356 case C_HUB_LOCAL_POWER
:
3357 case C_HUB_OVER_CURRENT
:
3358 /* Nothing required here */
3364 case ClearPortFeature
:
3365 dev_dbg(dev
, "ClearPortFeature\n");
3367 dev_dbg(dev
, " INVALID\n");
3372 case USB_PORT_FEAT_ENABLE
:
3373 dev_dbg(dev
, " ENABLE\n");
3374 spin_lock_irqsave(&priv
->lock
, flags
);
3375 cvmx_usb_disable(&priv
->usb
);
3376 spin_unlock_irqrestore(&priv
->lock
, flags
);
3378 case USB_PORT_FEAT_SUSPEND
:
3379 dev_dbg(dev
, " SUSPEND\n");
3380 /* Not supported on Octeon */
3382 case USB_PORT_FEAT_POWER
:
3383 dev_dbg(dev
, " POWER\n");
3384 /* Not supported on Octeon */
3386 case USB_PORT_FEAT_INDICATOR
:
3387 dev_dbg(dev
, " INDICATOR\n");
3388 /* Port inidicator not supported */
3390 case USB_PORT_FEAT_C_CONNECTION
:
3391 dev_dbg(dev
, " C_CONNECTION\n");
3392 /* Clears drivers internal connect status change flag */
3393 spin_lock_irqsave(&priv
->lock
, flags
);
3394 priv
->usb
.port_status
=
3395 cvmx_usb_get_status(&priv
->usb
);
3396 spin_unlock_irqrestore(&priv
->lock
, flags
);
3398 case USB_PORT_FEAT_C_RESET
:
3399 dev_dbg(dev
, " C_RESET\n");
3401 * Clears the driver's internal Port Reset Change flag.
3403 spin_lock_irqsave(&priv
->lock
, flags
);
3404 priv
->usb
.port_status
=
3405 cvmx_usb_get_status(&priv
->usb
);
3406 spin_unlock_irqrestore(&priv
->lock
, flags
);
3408 case USB_PORT_FEAT_C_ENABLE
:
3409 dev_dbg(dev
, " C_ENABLE\n");
3411 * Clears the driver's internal Port Enable/Disable
3414 spin_lock_irqsave(&priv
->lock
, flags
);
3415 priv
->usb
.port_status
=
3416 cvmx_usb_get_status(&priv
->usb
);
3417 spin_unlock_irqrestore(&priv
->lock
, flags
);
3419 case USB_PORT_FEAT_C_SUSPEND
:
3420 dev_dbg(dev
, " C_SUSPEND\n");
3422 * Clears the driver's internal Port Suspend Change
3423 * flag, which is set when resume signaling on the host
3427 case USB_PORT_FEAT_C_OVER_CURRENT
:
3428 dev_dbg(dev
, " C_OVER_CURRENT\n");
3429 /* Clears the driver's overcurrent Change flag */
3430 spin_lock_irqsave(&priv
->lock
, flags
);
3431 priv
->usb
.port_status
=
3432 cvmx_usb_get_status(&priv
->usb
);
3433 spin_unlock_irqrestore(&priv
->lock
, flags
);
3436 dev_dbg(dev
, " UNKNOWN\n");
3440 case GetHubDescriptor
:
3441 dev_dbg(dev
, "GetHubDescriptor\n");
3442 desc
= (struct usb_hub_descriptor
*)buf
;
3443 desc
->bDescLength
= 9;
3444 desc
->bDescriptorType
= 0x29;
3445 desc
->bNbrPorts
= 1;
3446 desc
->wHubCharacteristics
= cpu_to_le16(0x08);
3447 desc
->bPwrOn2PwrGood
= 1;
3448 desc
->bHubContrCurrent
= 0;
3449 desc
->u
.hs
.DeviceRemovable
[0] = 0;
3450 desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
3453 dev_dbg(dev
, "GetHubStatus\n");
3454 *(__le32
*) buf
= 0;
3457 dev_dbg(dev
, "GetPortStatus\n");
3459 dev_dbg(dev
, " INVALID\n");
3463 spin_lock_irqsave(&priv
->lock
, flags
);
3464 usb_port_status
= cvmx_usb_get_status(&priv
->usb
);
3465 spin_unlock_irqrestore(&priv
->lock
, flags
);
3468 if (usb_port_status
.connect_change
) {
3469 port_status
|= (1 << USB_PORT_FEAT_C_CONNECTION
);
3470 dev_dbg(dev
, " C_CONNECTION\n");
3473 if (usb_port_status
.port_enabled
) {
3474 port_status
|= (1 << USB_PORT_FEAT_C_ENABLE
);
3475 dev_dbg(dev
, " C_ENABLE\n");
3478 if (usb_port_status
.connected
) {
3479 port_status
|= (1 << USB_PORT_FEAT_CONNECTION
);
3480 dev_dbg(dev
, " CONNECTION\n");
3483 if (usb_port_status
.port_enabled
) {
3484 port_status
|= (1 << USB_PORT_FEAT_ENABLE
);
3485 dev_dbg(dev
, " ENABLE\n");
3488 if (usb_port_status
.port_over_current
) {
3489 port_status
|= (1 << USB_PORT_FEAT_OVER_CURRENT
);
3490 dev_dbg(dev
, " OVER_CURRENT\n");
3493 if (usb_port_status
.port_powered
) {
3494 port_status
|= (1 << USB_PORT_FEAT_POWER
);
3495 dev_dbg(dev
, " POWER\n");
3498 if (usb_port_status
.port_speed
== CVMX_USB_SPEED_HIGH
) {
3499 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
3500 dev_dbg(dev
, " HIGHSPEED\n");
3501 } else if (usb_port_status
.port_speed
== CVMX_USB_SPEED_LOW
) {
3502 port_status
|= (1 << USB_PORT_FEAT_LOWSPEED
);
3503 dev_dbg(dev
, " LOWSPEED\n");
3506 *((__le32
*) buf
) = cpu_to_le32(port_status
);
3509 dev_dbg(dev
, "SetHubFeature\n");
3510 /* No HUB features supported */
3512 case SetPortFeature
:
3513 dev_dbg(dev
, "SetPortFeature\n");
3515 dev_dbg(dev
, " INVALID\n");
3520 case USB_PORT_FEAT_SUSPEND
:
3521 dev_dbg(dev
, " SUSPEND\n");
3523 case USB_PORT_FEAT_POWER
:
3524 dev_dbg(dev
, " POWER\n");
3526 * Program the port power bit to drive VBUS on the USB.
3528 spin_lock_irqsave(&priv
->lock
, flags
);
3529 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
),
3530 cvmx_usbcx_hprt
, prtpwr
, 1);
3531 spin_unlock_irqrestore(&priv
->lock
, flags
);
3533 case USB_PORT_FEAT_RESET
:
3534 dev_dbg(dev
, " RESET\n");
3535 spin_lock_irqsave(&priv
->lock
, flags
);
3536 cvmx_usb_reset_port(&priv
->usb
);
3537 spin_unlock_irqrestore(&priv
->lock
, flags
);
3539 case USB_PORT_FEAT_INDICATOR
:
3540 dev_dbg(dev
, " INDICATOR\n");
3544 dev_dbg(dev
, " UNKNOWN\n");
3549 dev_dbg(dev
, "Unknown root hub request\n");
3555 static const struct hc_driver octeon_hc_driver
= {
3556 .description
= "Octeon USB",
3557 .product_desc
= "Octeon Host Controller",
3558 .hcd_priv_size
= sizeof(struct octeon_hcd
),
3559 .irq
= octeon_usb_irq
,
3560 .flags
= HCD_MEMORY
| HCD_USB2
,
3561 .start
= octeon_usb_start
,
3562 .stop
= octeon_usb_stop
,
3563 .urb_enqueue
= octeon_usb_urb_enqueue
,
3564 .urb_dequeue
= octeon_usb_urb_dequeue
,
3565 .endpoint_disable
= octeon_usb_endpoint_disable
,
3566 .get_frame_number
= octeon_usb_get_frame_number
,
3567 .hub_status_data
= octeon_usb_hub_status_data
,
3568 .hub_control
= octeon_usb_hub_control
,
3569 .map_urb_for_dma
= octeon_map_urb_for_dma
,
3570 .unmap_urb_for_dma
= octeon_unmap_urb_for_dma
,
3573 static int octeon_usb_probe(struct platform_device
*pdev
)
3576 int initialize_flags
;
3578 struct resource
*res_mem
;
3579 struct device_node
*usbn_node
;
3580 int irq
= platform_get_irq(pdev
, 0);
3581 struct device
*dev
= &pdev
->dev
;
3582 struct octeon_hcd
*priv
;
3583 struct usb_hcd
*hcd
;
3584 u32 clock_rate
= 48000000;
3585 bool is_crystal_clock
= false;
3586 const char *clock_type
;
3589 if (dev
->of_node
== NULL
) {
3590 dev_err(dev
, "Error: empty of_node\n");
3593 usbn_node
= dev
->of_node
->parent
;
3595 i
= of_property_read_u32(usbn_node
,
3596 "refclk-frequency", &clock_rate
);
3598 dev_err(dev
, "No USBN \"refclk-frequency\"\n");
3601 switch (clock_rate
) {
3603 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
;
3606 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
;
3609 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
;
3612 dev_err(dev
, "Illebal USBN \"refclk-frequency\" %u\n",
3618 i
= of_property_read_string(usbn_node
,
3619 "refclk-type", &clock_type
);
3621 if (!i
&& strcmp("crystal", clock_type
) == 0)
3622 is_crystal_clock
= true;
3624 if (is_crystal_clock
)
3625 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
;
3627 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
;
3629 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3630 if (res_mem
== NULL
) {
3631 dev_err(dev
, "found no memory resource\n");
3634 usb_num
= (res_mem
->start
>> 44) & 1;
3637 /* Defective device tree, but we know how to fix it. */
3638 irq_hw_number_t hwirq
= usb_num
? (1 << 6) + 17 : 56;
3640 irq
= irq_create_mapping(NULL
, hwirq
);
3644 * Set the DMA mask to 64bits so we get buffers already translated for
3647 dev
->coherent_dma_mask
= ~0;
3648 dev
->dma_mask
= &dev
->coherent_dma_mask
;
3651 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3652 * IOB priority registers. Under heavy network load USB
3653 * hardware can be starved by the IOB causing a crash. Give
3654 * it a priority boost if it has been waiting more than 400
3655 * cycles to avoid this situation.
3657 * Testing indicates that a cnt_val of 8192 is not sufficient,
3658 * but no failures are seen with 4096. We choose a value of
3659 * 400 to give a safety factor of 10.
3661 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) || OCTEON_IS_MODEL(OCTEON_CN56XX
)) {
3662 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt
;
3665 pri_cnt
.s
.cnt_enb
= 1;
3666 pri_cnt
.s
.cnt_val
= 400;
3667 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT
, pri_cnt
.u64
);
3670 hcd
= usb_create_hcd(&octeon_hc_driver
, dev
, dev_name(dev
));
3672 dev_dbg(dev
, "Failed to allocate memory for HCD\n");
3675 hcd
->uses_new_polling
= 1;
3676 priv
= (struct octeon_hcd
*)hcd
->hcd_priv
;
3678 spin_lock_init(&priv
->lock
);
3680 priv
->usb
.init_flags
= initialize_flags
;
3682 /* Initialize the USB state structure */
3683 priv
->usb
.index
= usb_num
;
3684 INIT_LIST_HEAD(&priv
->usb
.idle_pipes
);
3685 for (i
= 0; i
< ARRAY_SIZE(priv
->usb
.active_pipes
); i
++)
3686 INIT_LIST_HEAD(&priv
->usb
.active_pipes
[i
]);
3688 /* Due to an errata, CN31XX doesn't support DMA */
3689 if (OCTEON_IS_MODEL(OCTEON_CN31XX
)) {
3690 priv
->usb
.init_flags
|= CVMX_USB_INITIALIZE_FLAGS_NO_DMA
;
3691 /* Only use one channel with non DMA */
3692 priv
->usb
.idle_hardware_channels
= 0x1;
3693 } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX
)) {
3694 /* CN5XXX have an errata with channel 3 */
3695 priv
->usb
.idle_hardware_channels
= 0xf7;
3697 priv
->usb
.idle_hardware_channels
= 0xff;
3700 status
= cvmx_usb_initialize(dev
, &priv
->usb
);
3702 dev_dbg(dev
, "USB initialization failed with %d\n", status
);
3707 status
= usb_add_hcd(hcd
, irq
, 0);
3709 dev_dbg(dev
, "USB add HCD failed with %d\n", status
);
3713 device_wakeup_enable(hcd
->self
.controller
);
3715 dev_info(dev
, "Registered HCD for port %d on irq %d\n", usb_num
, irq
);
3720 static int octeon_usb_remove(struct platform_device
*pdev
)
3723 struct device
*dev
= &pdev
->dev
;
3724 struct usb_hcd
*hcd
= dev_get_drvdata(dev
);
3725 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3726 unsigned long flags
;
3728 usb_remove_hcd(hcd
);
3729 spin_lock_irqsave(&priv
->lock
, flags
);
3730 status
= cvmx_usb_shutdown(&priv
->usb
);
3731 spin_unlock_irqrestore(&priv
->lock
, flags
);
3733 dev_dbg(dev
, "USB shutdown failed with %d\n", status
);
3740 static const struct of_device_id octeon_usb_match
[] = {
3742 .compatible
= "cavium,octeon-5750-usbc",
3747 static struct platform_driver octeon_usb_driver
= {
3749 .name
= "OcteonUSB",
3750 .of_match_table
= octeon_usb_match
,
3752 .probe
= octeon_usb_probe
,
3753 .remove
= octeon_usb_remove
,
3756 static int __init
octeon_usb_driver_init(void)
3761 return platform_driver_register(&octeon_usb_driver
);
3763 module_init(octeon_usb_driver_init
);
3765 static void __exit
octeon_usb_driver_exit(void)
3770 platform_driver_unregister(&octeon_usb_driver
);
3772 module_exit(octeon_usb_driver_exit
);
3774 MODULE_LICENSE("GPL");
3775 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3776 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");