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Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
[linux/fpc-iii.git] / drivers / sh / intc / core.c
blob7e562ccb699734b3b6ce77579309cbdb87437817
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #define pr_fmt(fmt) "intc: " fmt
20
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/stat.h>
26 #include <linux/interrupt.h>
27 #include <linux/sh_intc.h>
28 #include <linux/device.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/list.h>
31 #include <linux/spinlock.h>
32 #include <linux/radix-tree.h>
33 #include <linux/export.h>
34 #include <linux/sort.h>
35 #include "internals.h"
36
37 LIST_HEAD(intc_list);
38 DEFINE_RAW_SPINLOCK(intc_big_lock);
39 static unsigned int nr_intc_controllers;
40
41 /*
42 * Default priority level
43 * - this needs to be at least 2 for 5-bit priorities on 7780
44 */
45 static unsigned int default_prio_level = 2; /* 2 - 16 */
46 static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */
47
48 unsigned int intc_get_dfl_prio_level(void)
49 {
50 return default_prio_level;
51 }
52
53 unsigned int intc_get_prio_level(unsigned int irq)
54 {
55 return intc_prio_level[irq];
56 }
57
58 void intc_set_prio_level(unsigned int irq, unsigned int level)
59 {
60 unsigned long flags;
61
62 raw_spin_lock_irqsave(&intc_big_lock, flags);
63 intc_prio_level[irq] = level;
64 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
65 }
66
67 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
68 {
69 generic_handle_irq((unsigned int)irq_get_handler_data(irq));
70 }
71
72 static void __init intc_register_irq(struct intc_desc *desc,
73 struct intc_desc_int *d,
74 intc_enum enum_id,
75 unsigned int irq)
76 {
77 struct intc_handle_int *hp;
78 struct irq_data *irq_data;
79 unsigned int data[2], primary;
80 unsigned long flags;
81
82 /*
83 * Register the IRQ position with the global IRQ map, then insert
84 * it in to the radix tree.
85 */
86 irq_reserve_irq(irq);
87
88 raw_spin_lock_irqsave(&intc_big_lock, flags);
89 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
90 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
91
92 /*
93 * Prefer single interrupt source bitmap over other combinations:
94 *
95 * 1. bitmap, single interrupt source
96 * 2. priority, single interrupt source
97 * 3. bitmap, multiple interrupt sources (groups)
98 * 4. priority, multiple interrupt sources (groups)
99 */
100 data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
101 data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
102
103 primary = 0;
104 if (!data[0] && data[1])
105 primary = 1;
106
107 if (!data[0] && !data[1])
108 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
109 irq, irq2evt(irq));
110
111 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
112 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
113
114 if (!data[primary])
115 primary ^= 1;
116
117 BUG_ON(!data[primary]); /* must have primary masking method */
118
119 irq_data = irq_get_irq_data(irq);
120
121 disable_irq_nosync(irq);
122 irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
123 "level");
124 irq_set_chip_data(irq, (void *)data[primary]);
125
126 /*
127 * set priority level
128 */
129 intc_set_prio_level(irq, intc_get_dfl_prio_level());
130
131 /* enable secondary masking method if present */
132 if (data[!primary])
133 _intc_enable(irq_data, data[!primary]);
134
135 /* add irq to d->prio list if priority is available */
136 if (data[1]) {
137 hp = d->prio + d->nr_prio;
138 hp->irq = irq;
139 hp->handle = data[1];
140
141 if (primary) {
142 /*
143 * only secondary priority should access registers, so
144 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
145 */
146 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
147 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
148 }
149 d->nr_prio++;
150 }
151
152 /* add irq to d->sense list if sense is available */
153 data[0] = intc_get_sense_handle(desc, d, enum_id);
154 if (data[0]) {
155 (d->sense + d->nr_sense)->irq = irq;
156 (d->sense + d->nr_sense)->handle = data[0];
157 d->nr_sense++;
158 }
159
160 /* irq should be disabled by default */
161 d->chip.irq_mask(irq_data);
162
163 intc_set_ack_handle(irq, desc, d, enum_id);
164 intc_set_dist_handle(irq, desc, d, enum_id);
165
166 activate_irq(irq);
167 }
168
169 static unsigned int __init save_reg(struct intc_desc_int *d,
170 unsigned int cnt,
171 unsigned long value,
172 unsigned int smp)
173 {
174 if (value) {
175 value = intc_phys_to_virt(d, value);
176
177 d->reg[cnt] = value;
178 #ifdef CONFIG_SMP
179 d->smp[cnt] = smp;
180 #endif
181 return 1;
182 }
183
184 return 0;
185 }
186
187 int __init register_intc_controller(struct intc_desc *desc)
188 {
189 unsigned int i, k, smp;
190 struct intc_hw_desc *hw = &desc->hw;
191 struct intc_desc_int *d;
192 struct resource *res;
193
194 pr_info("Registered controller '%s' with %u IRQs\n",
195 desc->name, hw->nr_vectors);
196
197 d = kzalloc(sizeof(*d), GFP_NOWAIT);
198 if (!d)
199 goto err0;
200
201 INIT_LIST_HEAD(&d->list);
202 list_add_tail(&d->list, &intc_list);
203
204 raw_spin_lock_init(&d->lock);
205 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
206
207 d->index = nr_intc_controllers;
208
209 if (desc->num_resources) {
210 d->nr_windows = desc->num_resources;
211 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
212 GFP_NOWAIT);
213 if (!d->window)
214 goto err1;
215
216 for (k = 0; k < d->nr_windows; k++) {
217 res = desc->resource + k;
218 WARN_ON(resource_type(res) != IORESOURCE_MEM);
219 d->window[k].phys = res->start;
220 d->window[k].size = resource_size(res);
221 d->window[k].virt = ioremap_nocache(res->start,
222 resource_size(res));
223 if (!d->window[k].virt)
224 goto err2;
225 }
226 }
227
228 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
229 #ifdef CONFIG_INTC_BALANCING
230 if (d->nr_reg)
231 d->nr_reg += hw->nr_mask_regs;
232 #endif
233 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
234 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
235 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
236 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
237
238 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
239 if (!d->reg)
240 goto err2;
241
242 #ifdef CONFIG_SMP
243 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
244 if (!d->smp)
245 goto err3;
246 #endif
247 k = 0;
248
249 if (hw->mask_regs) {
250 for (i = 0; i < hw->nr_mask_regs; i++) {
251 smp = IS_SMP(hw->mask_regs[i]);
252 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
253 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
254 #ifdef CONFIG_INTC_BALANCING
255 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
256 #endif
257 }
258 }
259
260 if (hw->prio_regs) {
261 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
262 GFP_NOWAIT);
263 if (!d->prio)
264 goto err4;
265
266 for (i = 0; i < hw->nr_prio_regs; i++) {
267 smp = IS_SMP(hw->prio_regs[i]);
268 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
269 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
270 }
271
272 sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio),
273 intc_handle_int_cmp, NULL);
274 }
275
276 if (hw->sense_regs) {
277 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
278 GFP_NOWAIT);
279 if (!d->sense)
280 goto err5;
281
282 for (i = 0; i < hw->nr_sense_regs; i++)
283 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
284
285 sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense),
286 intc_handle_int_cmp, NULL);
287 }
288
289 if (hw->subgroups)
290 for (i = 0; i < hw->nr_subgroups; i++)
291 if (hw->subgroups[i].reg)
292 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
293
294 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
295 d->chip.name = desc->name;
296
297 if (hw->ack_regs)
298 for (i = 0; i < hw->nr_ack_regs; i++)
299 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
300 else
301 d->chip.irq_mask_ack = d->chip.irq_disable;
302
303 /* disable bits matching force_disable before registering irqs */
304 if (desc->force_disable)
305 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
306
307 /* disable bits matching force_enable before registering irqs */
308 if (desc->force_enable)
309 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
310
311 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
312
313 /* register the vectors one by one */
314 for (i = 0; i < hw->nr_vectors; i++) {
315 struct intc_vect *vect = hw->vectors + i;
316 unsigned int irq = evt2irq(vect->vect);
317 int res;
318
319 if (!vect->enum_id)
320 continue;
321
322 res = irq_alloc_desc_at(irq, numa_node_id());
323 if (res != irq && res != -EEXIST) {
324 pr_err("can't get irq_desc for %d\n", irq);
325 continue;
326 }
327
328 intc_irq_xlate_set(irq, vect->enum_id, d);
329 intc_register_irq(desc, d, vect->enum_id, irq);
330
331 for (k = i + 1; k < hw->nr_vectors; k++) {
332 struct intc_vect *vect2 = hw->vectors + k;
333 unsigned int irq2 = evt2irq(vect2->vect);
334
335 if (vect->enum_id != vect2->enum_id)
336 continue;
337
338 /*
339 * In the case of multi-evt handling and sparse
340 * IRQ support, each vector still needs to have
341 * its own backing irq_desc.
342 */
343 res = irq_alloc_desc_at(irq2, numa_node_id());
344 if (res != irq2 && res != -EEXIST) {
345 pr_err("can't get irq_desc for %d\n", irq2);
346 continue;
347 }
348
349 vect2->enum_id = 0;
350
351 /* redirect this interrupts to the first one */
352 irq_set_chip(irq2, &dummy_irq_chip);
353 irq_set_chained_handler(irq2, intc_redirect_irq);
354 irq_set_handler_data(irq2, (void *)irq);
355 }
356 }
357
358 intc_subgroup_init(desc, d);
359
360 /* enable bits matching force_enable after registering irqs */
361 if (desc->force_enable)
362 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
363
364 d->skip_suspend = desc->skip_syscore_suspend;
365
366 nr_intc_controllers++;
367
368 return 0;
369 err5:
370 kfree(d->prio);
371 err4:
372 #ifdef CONFIG_SMP
373 kfree(d->smp);
374 err3:
375 #endif
376 kfree(d->reg);
377 err2:
378 for (k = 0; k < d->nr_windows; k++)
379 if (d->window[k].virt)
380 iounmap(d->window[k].virt);
381
382 kfree(d->window);
383 err1:
384 kfree(d);
385 err0:
386 pr_err("unable to allocate INTC memory\n");
387
388 return -ENOMEM;
389 }
390
391 static int intc_suspend(void)
392 {
393 struct intc_desc_int *d;
394
395 list_for_each_entry(d, &intc_list, list) {
396 int irq;
397
398 if (d->skip_suspend)
399 continue;
400
401 /* enable wakeup irqs belonging to this intc controller */
402 for_each_active_irq(irq) {
403 struct irq_data *data;
404 struct irq_chip *chip;
405
406 data = irq_get_irq_data(irq);
407 chip = irq_data_get_irq_chip(data);
408 if (chip != &d->chip)
409 continue;
410 if (irqd_is_wakeup_set(data))
411 chip->irq_enable(data);
412 }
413 }
414 return 0;
415 }
416
417 static void intc_resume(void)
418 {
419 struct intc_desc_int *d;
420
421 list_for_each_entry(d, &intc_list, list) {
422 int irq;
423
424 if (d->skip_suspend)
425 continue;
426
427 for_each_active_irq(irq) {
428 struct irq_data *data;
429 struct irq_chip *chip;
430
431 data = irq_get_irq_data(irq);
432 chip = irq_data_get_irq_chip(data);
433 /*
434 * This will catch the redirect and VIRQ cases
435 * due to the dummy_irq_chip being inserted.
436 */
437 if (chip != &d->chip)
438 continue;
439 if (irqd_irq_disabled(data))
440 chip->irq_disable(data);
441 else
442 chip->irq_enable(data);
443 }
444 }
445 }
446
447 struct syscore_ops intc_syscore_ops = {
448 .suspend = intc_suspend,
449 .resume = intc_resume,
450 };
451
452 struct bus_type intc_subsys = {
453 .name = "intc",
454 .dev_name = "intc",
455 };
456
457 static ssize_t
458 show_intc_name(struct device *dev, struct device_attribute *attr, char *buf)
459 {
460 struct intc_desc_int *d;
461
462 d = container_of(dev, struct intc_desc_int, dev);
463
464 return sprintf(buf, "%s\n", d->chip.name);
465 }
466
467 static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL);
468
469 static int __init register_intc_devs(void)
470 {
471 struct intc_desc_int *d;
472 int error;
473
474 register_syscore_ops(&intc_syscore_ops);
475
476 error = subsys_system_register(&intc_subsys, NULL);
477 if (!error) {
478 list_for_each_entry(d, &intc_list, list) {
479 d->dev.id = d->index;
480 d->dev.bus = &intc_subsys;
481 error = device_register(&d->dev);
482 if (error == 0)
483 error = device_create_file(&d->dev,
484 &dev_attr_name);
485 if (error)
486 break;
487 }
488 }
489
490 if (error)
491 pr_err("device registration error\n");
492
493 return error;
494 }
495 device_initcall(register_intc_devs);
Linux with added FPC-III support