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vme: trivial spelling and capitalization fixes
[linux/fpc-iii.git] / arch / powerpc / kvm / booke.c
blob4d66f44a165789df702242c622024a269da745a2
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
22 */
23
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/kvm_host.h>
27 #include <linux/gfp.h>
28 #include <linux/module.h>
29 #include <linux/vmalloc.h>
30 #include <linux/fs.h>
31
32 #include <asm/cputable.h>
33 #include <asm/uaccess.h>
34 #include <asm/kvm_ppc.h>
35 #include <asm/cacheflush.h>
36 #include <asm/dbell.h>
37 #include <asm/hw_irq.h>
38 #include <asm/irq.h>
39 #include <asm/time.h>
40
41 #include "timing.h"
42 #include "booke.h"
43
44 #define CREATE_TRACE_POINTS
45 #include "trace_booke.h"
46
47 unsigned long kvmppc_booke_handlers;
48
49 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
50 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
51
52 struct kvm_stats_debugfs_item debugfs_entries[] = {
53 { "mmio", VCPU_STAT(mmio_exits) },
54 { "sig", VCPU_STAT(signal_exits) },
55 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
56 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
57 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
58 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
59 { "sysc", VCPU_STAT(syscall_exits) },
60 { "isi", VCPU_STAT(isi_exits) },
61 { "dsi", VCPU_STAT(dsi_exits) },
62 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
63 { "dec", VCPU_STAT(dec_exits) },
64 { "ext_intr", VCPU_STAT(ext_intr_exits) },
65 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
66 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
67 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
68 { "doorbell", VCPU_STAT(dbell_exits) },
69 { "guest doorbell", VCPU_STAT(gdbell_exits) },
70 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
71 { NULL }
72 };
73
74 /* TODO: use vcpu_printf() */
75 void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
76 {
77 int i;
78
79 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
80 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
81 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
82 vcpu->arch.shared->srr1);
83
84 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
85
86 for (i = 0; i < 32; i += 4) {
87 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
88 kvmppc_get_gpr(vcpu, i),
89 kvmppc_get_gpr(vcpu, i+1),
90 kvmppc_get_gpr(vcpu, i+2),
91 kvmppc_get_gpr(vcpu, i+3));
92 }
93 }
94
95 #ifdef CONFIG_SPE
96 void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
97 {
98 preempt_disable();
99 enable_kernel_spe();
100 kvmppc_save_guest_spe(vcpu);
101 disable_kernel_spe();
102 vcpu->arch.shadow_msr &= ~MSR_SPE;
103 preempt_enable();
104 }
105
106 static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
107 {
108 preempt_disable();
109 enable_kernel_spe();
110 kvmppc_load_guest_spe(vcpu);
111 disable_kernel_spe();
112 vcpu->arch.shadow_msr |= MSR_SPE;
113 preempt_enable();
114 }
115
116 static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
117 {
118 if (vcpu->arch.shared->msr & MSR_SPE) {
119 if (!(vcpu->arch.shadow_msr & MSR_SPE))
120 kvmppc_vcpu_enable_spe(vcpu);
121 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
122 kvmppc_vcpu_disable_spe(vcpu);
123 }
124 }
125 #else
126 static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
127 {
128 }
129 #endif
130
131 /*
132 * Load up guest vcpu FP state if it's needed.
133 * It also set the MSR_FP in thread so that host know
134 * we're holding FPU, and then host can help to save
135 * guest vcpu FP state if other threads require to use FPU.
136 * This simulates an FP unavailable fault.
137 *
138 * It requires to be called with preemption disabled.
139 */
140 static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
141 {
142 #ifdef CONFIG_PPC_FPU
143 if (!(current->thread.regs->msr & MSR_FP)) {
144 enable_kernel_fp();
145 load_fp_state(&vcpu->arch.fp);
146 disable_kernel_fp();
147 current->thread.fp_save_area = &vcpu->arch.fp;
148 current->thread.regs->msr |= MSR_FP;
149 }
150 #endif
151 }
152
153 /*
154 * Save guest vcpu FP state into thread.
155 * It requires to be called with preemption disabled.
156 */
157 static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
158 {
159 #ifdef CONFIG_PPC_FPU
160 if (current->thread.regs->msr & MSR_FP)
161 giveup_fpu(current);
162 current->thread.fp_save_area = NULL;
163 #endif
164 }
165
166 static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
167 {
168 #if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
169 /* We always treat the FP bit as enabled from the host
170 perspective, so only need to adjust the shadow MSR */
171 vcpu->arch.shadow_msr &= ~MSR_FP;
172 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
173 #endif
174 }
175
176 /*
177 * Simulate AltiVec unavailable fault to load guest state
178 * from thread to AltiVec unit.
179 * It requires to be called with preemption disabled.
180 */
181 static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
182 {
183 #ifdef CONFIG_ALTIVEC
184 if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
185 if (!(current->thread.regs->msr & MSR_VEC)) {
186 enable_kernel_altivec();
187 load_vr_state(&vcpu->arch.vr);
188 disable_kernel_altivec();
189 current->thread.vr_save_area = &vcpu->arch.vr;
190 current->thread.regs->msr |= MSR_VEC;
191 }
192 }
193 #endif
194 }
195
196 /*
197 * Save guest vcpu AltiVec state into thread.
198 * It requires to be called with preemption disabled.
199 */
200 static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu)
201 {
202 #ifdef CONFIG_ALTIVEC
203 if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
204 if (current->thread.regs->msr & MSR_VEC)
205 giveup_altivec(current);
206 current->thread.vr_save_area = NULL;
207 }
208 #endif
209 }
210
211 static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
212 {
213 /* Synchronize guest's desire to get debug interrupts into shadow MSR */
214 #ifndef CONFIG_KVM_BOOKE_HV
215 vcpu->arch.shadow_msr &= ~MSR_DE;
216 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE;
217 #endif
218
219 /* Force enable debug interrupts when user space wants to debug */
220 if (vcpu->guest_debug) {
221 #ifdef CONFIG_KVM_BOOKE_HV
222 /*
223 * Since there is no shadow MSR, sync MSR_DE into the guest
224 * visible MSR.
225 */
226 vcpu->arch.shared->msr |= MSR_DE;
227 #else
228 vcpu->arch.shadow_msr |= MSR_DE;
229 vcpu->arch.shared->msr &= ~MSR_DE;
230 #endif
231 }
232 }
233
234 /*
235 * Helper function for "full" MSR writes. No need to call this if only
236 * EE/CE/ME/DE/RI are changing.
237 */
238 void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
239 {
240 u32 old_msr = vcpu->arch.shared->msr;
241
242 #ifdef CONFIG_KVM_BOOKE_HV
243 new_msr |= MSR_GS;
244 #endif
245
246 vcpu->arch.shared->msr = new_msr;
247
248 kvmppc_mmu_msr_notify(vcpu, old_msr);
249 kvmppc_vcpu_sync_spe(vcpu);
250 kvmppc_vcpu_sync_fpu(vcpu);
251 kvmppc_vcpu_sync_debug(vcpu);
252 }
253
254 static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
255 unsigned int priority)
256 {
257 trace_kvm_booke_queue_irqprio(vcpu, priority);
258 set_bit(priority, &vcpu->arch.pending_exceptions);
259 }
260
261 void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
262 ulong dear_flags, ulong esr_flags)
263 {
264 vcpu->arch.queued_dear = dear_flags;
265 vcpu->arch.queued_esr = esr_flags;
266 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
267 }
268
269 void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
270 ulong dear_flags, ulong esr_flags)
271 {
272 vcpu->arch.queued_dear = dear_flags;
273 vcpu->arch.queued_esr = esr_flags;
274 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
275 }
276
277 void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu)
278 {
279 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
280 }
281
282 void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong esr_flags)
283 {
284 vcpu->arch.queued_esr = esr_flags;
285 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
286 }
287
288 static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags,
289 ulong esr_flags)
290 {
291 vcpu->arch.queued_dear = dear_flags;
292 vcpu->arch.queued_esr = esr_flags;
293 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT);
294 }
295
296 void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
297 {
298 vcpu->arch.queued_esr = esr_flags;
299 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
300 }
301
302 void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
303 {
304 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
305 }
306
307 int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
308 {
309 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
310 }
311
312 void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
313 {
314 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
315 }
316
317 void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
318 struct kvm_interrupt *irq)
319 {
320 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
321
322 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
323 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
324
325 kvmppc_booke_queue_irqprio(vcpu, prio);
326 }
327
328 void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
329 {
330 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
331 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
332 }
333
334 static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
335 {
336 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
337 }
338
339 static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
340 {
341 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
342 }
343
344 void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu)
345 {
346 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DEBUG);
347 }
348
349 void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu)
350 {
351 clear_bit(BOOKE_IRQPRIO_DEBUG, &vcpu->arch.pending_exceptions);
352 }
353
354 static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
355 {
356 kvmppc_set_srr0(vcpu, srr0);
357 kvmppc_set_srr1(vcpu, srr1);
358 }
359
360 static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
361 {
362 vcpu->arch.csrr0 = srr0;
363 vcpu->arch.csrr1 = srr1;
364 }
365
366 static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
367 {
368 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
369 vcpu->arch.dsrr0 = srr0;
370 vcpu->arch.dsrr1 = srr1;
371 } else {
372 set_guest_csrr(vcpu, srr0, srr1);
373 }
374 }
375
376 static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
377 {
378 vcpu->arch.mcsrr0 = srr0;
379 vcpu->arch.mcsrr1 = srr1;
380 }
381
382 /* Deliver the interrupt of the corresponding priority, if possible. */
383 static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
384 unsigned int priority)
385 {
386 int allowed = 0;
387 ulong msr_mask = 0;
388 bool update_esr = false, update_dear = false, update_epr = false;
389 ulong crit_raw = vcpu->arch.shared->critical;
390 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
391 bool crit;
392 bool keep_irq = false;
393 enum int_class int_class;
394 ulong new_msr = vcpu->arch.shared->msr;
395
396 /* Truncate crit indicators in 32 bit mode */
397 if (!(vcpu->arch.shared->msr & MSR_SF)) {
398 crit_raw &= 0xffffffff;
399 crit_r1 &= 0xffffffff;
400 }
401
402 /* Critical section when crit == r1 */
403 crit = (crit_raw == crit_r1);
404 /* ... and we're in supervisor mode */
405 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
406
407 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
408 priority = BOOKE_IRQPRIO_EXTERNAL;
409 keep_irq = true;
410 }
411
412 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
413 update_epr = true;
414
415 switch (priority) {
416 case BOOKE_IRQPRIO_DTLB_MISS:
417 case BOOKE_IRQPRIO_DATA_STORAGE:
418 case BOOKE_IRQPRIO_ALIGNMENT:
419 update_dear = true;
420 /* fall through */
421 case BOOKE_IRQPRIO_INST_STORAGE:
422 case BOOKE_IRQPRIO_PROGRAM:
423 update_esr = true;
424 /* fall through */
425 case BOOKE_IRQPRIO_ITLB_MISS:
426 case BOOKE_IRQPRIO_SYSCALL:
427 case BOOKE_IRQPRIO_FP_UNAVAIL:
428 #ifdef CONFIG_SPE_POSSIBLE
429 case BOOKE_IRQPRIO_SPE_UNAVAIL:
430 case BOOKE_IRQPRIO_SPE_FP_DATA:
431 case BOOKE_IRQPRIO_SPE_FP_ROUND:
432 #endif
433 #ifdef CONFIG_ALTIVEC
434 case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL:
435 case BOOKE_IRQPRIO_ALTIVEC_ASSIST:
436 #endif
437 case BOOKE_IRQPRIO_AP_UNAVAIL:
438 allowed = 1;
439 msr_mask = MSR_CE | MSR_ME | MSR_DE;
440 int_class = INT_CLASS_NONCRIT;
441 break;
442 case BOOKE_IRQPRIO_WATCHDOG:
443 case BOOKE_IRQPRIO_CRITICAL:
444 case BOOKE_IRQPRIO_DBELL_CRIT:
445 allowed = vcpu->arch.shared->msr & MSR_CE;
446 allowed = allowed && !crit;
447 msr_mask = MSR_ME;
448 int_class = INT_CLASS_CRIT;
449 break;
450 case BOOKE_IRQPRIO_MACHINE_CHECK:
451 allowed = vcpu->arch.shared->msr & MSR_ME;
452 allowed = allowed && !crit;
453 int_class = INT_CLASS_MC;
454 break;
455 case BOOKE_IRQPRIO_DECREMENTER:
456 case BOOKE_IRQPRIO_FIT:
457 keep_irq = true;
458 /* fall through */
459 case BOOKE_IRQPRIO_EXTERNAL:
460 case BOOKE_IRQPRIO_DBELL:
461 allowed = vcpu->arch.shared->msr & MSR_EE;
462 allowed = allowed && !crit;
463 msr_mask = MSR_CE | MSR_ME | MSR_DE;
464 int_class = INT_CLASS_NONCRIT;
465 break;
466 case BOOKE_IRQPRIO_DEBUG:
467 allowed = vcpu->arch.shared->msr & MSR_DE;
468 allowed = allowed && !crit;
469 msr_mask = MSR_ME;
470 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
471 int_class = INT_CLASS_DBG;
472 else
473 int_class = INT_CLASS_CRIT;
474
475 break;
476 }
477
478 if (allowed) {
479 switch (int_class) {
480 case INT_CLASS_NONCRIT:
481 set_guest_srr(vcpu, vcpu->arch.pc,
482 vcpu->arch.shared->msr);
483 break;
484 case INT_CLASS_CRIT:
485 set_guest_csrr(vcpu, vcpu->arch.pc,
486 vcpu->arch.shared->msr);
487 break;
488 case INT_CLASS_DBG:
489 set_guest_dsrr(vcpu, vcpu->arch.pc,
490 vcpu->arch.shared->msr);
491 break;
492 case INT_CLASS_MC:
493 set_guest_mcsrr(vcpu, vcpu->arch.pc,
494 vcpu->arch.shared->msr);
495 break;
496 }
497
498 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
499 if (update_esr == true)
500 kvmppc_set_esr(vcpu, vcpu->arch.queued_esr);
501 if (update_dear == true)
502 kvmppc_set_dar(vcpu, vcpu->arch.queued_dear);
503 if (update_epr == true) {
504 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
505 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
506 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
507 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
508 kvmppc_mpic_set_epr(vcpu);
509 }
510 }
511
512 new_msr &= msr_mask;
513 #if defined(CONFIG_64BIT)
514 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
515 new_msr |= MSR_CM;
516 #endif
517 kvmppc_set_msr(vcpu, new_msr);
518
519 if (!keep_irq)
520 clear_bit(priority, &vcpu->arch.pending_exceptions);
521 }
522
523 #ifdef CONFIG_KVM_BOOKE_HV
524 /*
525 * If an interrupt is pending but masked, raise a guest doorbell
526 * so that we are notified when the guest enables the relevant
527 * MSR bit.
528 */
529 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
530 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
531 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
532 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
533 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
534 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
535 #endif
536
537 return allowed;
538 }
539
540 /*
541 * Return the number of jiffies until the next timeout. If the timeout is
542 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
543 * because the larger value can break the timer APIs.
544 */
545 static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
546 {
547 u64 tb, wdt_tb, wdt_ticks = 0;
548 u64 nr_jiffies = 0;
549 u32 period = TCR_GET_WP(vcpu->arch.tcr);
550
551 wdt_tb = 1ULL << (63 - period);
552 tb = get_tb();
553 /*
554 * The watchdog timeout will hapeen when TB bit corresponding
555 * to watchdog will toggle from 0 to 1.
556 */
557 if (tb & wdt_tb)
558 wdt_ticks = wdt_tb;
559
560 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
561
562 /* Convert timebase ticks to jiffies */
563 nr_jiffies = wdt_ticks;
564
565 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
566 nr_jiffies++;
567
568 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
569 }
570
571 static void arm_next_watchdog(struct kvm_vcpu *vcpu)
572 {
573 unsigned long nr_jiffies;
574 unsigned long flags;
575
576 /*
577 * If TSR_ENW and TSR_WIS are not set then no need to exit to
578 * userspace, so clear the KVM_REQ_WATCHDOG request.
579 */
580 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
581 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
582
583 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
584 nr_jiffies = watchdog_next_timeout(vcpu);
585 /*
586 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
587 * then do not run the watchdog timer as this can break timer APIs.
588 */
589 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
590 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
591 else
592 del_timer(&vcpu->arch.wdt_timer);
593 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
594 }
595
596 void kvmppc_watchdog_func(unsigned long data)
597 {
598 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
599 u32 tsr, new_tsr;
600 int final;
601
602 do {
603 new_tsr = tsr = vcpu->arch.tsr;
604 final = 0;
605
606 /* Time out event */
607 if (tsr & TSR_ENW) {
608 if (tsr & TSR_WIS)
609 final = 1;
610 else
611 new_tsr = tsr | TSR_WIS;
612 } else {
613 new_tsr = tsr | TSR_ENW;
614 }
615 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
616
617 if (new_tsr & TSR_WIS) {
618 smp_wmb();
619 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
620 kvm_vcpu_kick(vcpu);
621 }
622
623 /*
624 * If this is final watchdog expiry and some action is required
625 * then exit to userspace.
626 */
627 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
628 vcpu->arch.watchdog_enabled) {
629 smp_wmb();
630 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
631 kvm_vcpu_kick(vcpu);
632 }
633
634 /*
635 * Stop running the watchdog timer after final expiration to
636 * prevent the host from being flooded with timers if the
637 * guest sets a short period.
638 * Timers will resume when TSR/TCR is updated next time.
639 */
640 if (!final)
641 arm_next_watchdog(vcpu);
642 }
643
644 static void update_timer_ints(struct kvm_vcpu *vcpu)
645 {
646 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
647 kvmppc_core_queue_dec(vcpu);
648 else
649 kvmppc_core_dequeue_dec(vcpu);
650
651 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
652 kvmppc_core_queue_watchdog(vcpu);
653 else
654 kvmppc_core_dequeue_watchdog(vcpu);
655 }
656
657 static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
658 {
659 unsigned long *pending = &vcpu->arch.pending_exceptions;
660 unsigned int priority;
661
662 priority = __ffs(*pending);
663 while (priority < BOOKE_IRQPRIO_MAX) {
664 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
665 break;
666
667 priority = find_next_bit(pending,
668 BITS_PER_BYTE * sizeof(*pending),
669 priority + 1);
670 }
671
672 /* Tell the guest about our interrupt status */
673 vcpu->arch.shared->int_pending = !!*pending;
674 }
675
676 /* Check pending exceptions and deliver one, if possible. */
677 int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
678 {
679 int r = 0;
680 WARN_ON_ONCE(!irqs_disabled());
681
682 kvmppc_core_check_exceptions(vcpu);
683
684 if (vcpu->requests) {
685 /* Exception delivery raised request; start over */
686 return 1;
687 }
688
689 if (vcpu->arch.shared->msr & MSR_WE) {
690 local_irq_enable();
691 kvm_vcpu_block(vcpu);
692 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
693 hard_irq_disable();
694
695 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
696 r = 1;
697 };
698
699 return r;
700 }
701
702 int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
703 {
704 int r = 1; /* Indicate we want to get back into the guest */
705
706 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
707 update_timer_ints(vcpu);
708 #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
709 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
710 kvmppc_core_flush_tlb(vcpu);
711 #endif
712
713 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
714 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
715 r = 0;
716 }
717
718 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
719 vcpu->run->epr.epr = 0;
720 vcpu->arch.epr_needed = true;
721 vcpu->run->exit_reason = KVM_EXIT_EPR;
722 r = 0;
723 }
724
725 return r;
726 }
727
728 int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
729 {
730 int ret, s;
731 struct debug_reg debug;
732
733 if (!vcpu->arch.sane) {
734 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
735 return -EINVAL;
736 }
737
738 s = kvmppc_prepare_to_enter(vcpu);
739 if (s <= 0) {
740 ret = s;
741 goto out;
742 }
743 /* interrupts now hard-disabled */
744
745 #ifdef CONFIG_PPC_FPU
746 /* Save userspace FPU state in stack */
747 enable_kernel_fp();
748
749 /*
750 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
751 * as always using the FPU.
752 */
753 kvmppc_load_guest_fp(vcpu);
754 #endif
755
756 #ifdef CONFIG_ALTIVEC
757 /* Save userspace AltiVec state in stack */
758 if (cpu_has_feature(CPU_FTR_ALTIVEC))
759 enable_kernel_altivec();
760 /*
761 * Since we can't trap on MSR_VEC in GS-mode, we consider the guest
762 * as always using the AltiVec.
763 */
764 kvmppc_load_guest_altivec(vcpu);
765 #endif
766
767 /* Switch to guest debug context */
768 debug = vcpu->arch.dbg_reg;
769 switch_booke_debug_regs(&debug);
770 debug = current->thread.debug;
771 current->thread.debug = vcpu->arch.dbg_reg;
772
773 vcpu->arch.pgdir = current->mm->pgd;
774 kvmppc_fix_ee_before_entry();
775
776 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
777
778 /* No need for kvm_guest_exit. It's done in handle_exit.
779 We also get here with interrupts enabled. */
780
781 /* Switch back to user space debug context */
782 switch_booke_debug_regs(&debug);
783 current->thread.debug = debug;
784
785 #ifdef CONFIG_PPC_FPU
786 kvmppc_save_guest_fp(vcpu);
787 #endif
788
789 #ifdef CONFIG_ALTIVEC
790 kvmppc_save_guest_altivec(vcpu);
791 #endif
792
793 out:
794 vcpu->mode = OUTSIDE_GUEST_MODE;
795 return ret;
796 }
797
798 static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
799 {
800 enum emulation_result er;
801
802 er = kvmppc_emulate_instruction(run, vcpu);
803 switch (er) {
804 case EMULATE_DONE:
805 /* don't overwrite subtypes, just account kvm_stats */
806 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
807 /* Future optimization: only reload non-volatiles if
808 * they were actually modified by emulation. */
809 return RESUME_GUEST_NV;
810
811 case EMULATE_AGAIN:
812 return RESUME_GUEST;
813
814 case EMULATE_FAIL:
815 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
816 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
817 /* For debugging, encode the failing instruction and
818 * report it to userspace. */
819 run->hw.hardware_exit_reason = ~0ULL << 32;
820 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
821 kvmppc_core_queue_program(vcpu, ESR_PIL);
822 return RESUME_HOST;
823
824 case EMULATE_EXIT_USER:
825 return RESUME_HOST;
826
827 default:
828 BUG();
829 }
830 }
831
832 static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu)
833 {
834 struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg);
835 u32 dbsr = vcpu->arch.dbsr;
836
837 if (vcpu->guest_debug == 0) {
838 /*
839 * Debug resources belong to Guest.
840 * Imprecise debug event is not injected
841 */
842 if (dbsr & DBSR_IDE) {
843 dbsr &= ~DBSR_IDE;
844 if (!dbsr)
845 return RESUME_GUEST;
846 }
847
848 if (dbsr && (vcpu->arch.shared->msr & MSR_DE) &&
849 (vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM))
850 kvmppc_core_queue_debug(vcpu);
851
852 /* Inject a program interrupt if trap debug is not allowed */
853 if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE))
854 kvmppc_core_queue_program(vcpu, ESR_PTR);
855
856 return RESUME_GUEST;
857 }
858
859 /*
860 * Debug resource owned by userspace.
861 * Clear guest dbsr (vcpu->arch.dbsr)
862 */
863 vcpu->arch.dbsr = 0;
864 run->debug.arch.status = 0;
865 run->debug.arch.address = vcpu->arch.pc;
866
867 if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) {
868 run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT;
869 } else {
870 if (dbsr & (DBSR_DAC1W | DBSR_DAC2W))
871 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE;
872 else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R))
873 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ;
874 if (dbsr & (DBSR_DAC1R | DBSR_DAC1W))
875 run->debug.arch.address = dbg_reg->dac1;
876 else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W))
877 run->debug.arch.address = dbg_reg->dac2;
878 }
879
880 return RESUME_HOST;
881 }
882
883 static void kvmppc_fill_pt_regs(struct pt_regs *regs)
884 {
885 ulong r1, ip, msr, lr;
886
887 asm("mr %0, 1" : "=r"(r1));
888 asm("mflr %0" : "=r"(lr));
889 asm("mfmsr %0" : "=r"(msr));
890 asm("bl 1f; 1: mflr %0" : "=r"(ip));
891
892 memset(regs, 0, sizeof(*regs));
893 regs->gpr[1] = r1;
894 regs->nip = ip;
895 regs->msr = msr;
896 regs->link = lr;
897 }
898
899 /*
900 * For interrupts needed to be handled by host interrupt handlers,
901 * corresponding host handler are called from here in similar way
902 * (but not exact) as they are called from low level handler
903 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
904 */
905 static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
906 unsigned int exit_nr)
907 {
908 struct pt_regs regs;
909
910 switch (exit_nr) {
911 case BOOKE_INTERRUPT_EXTERNAL:
912 kvmppc_fill_pt_regs(&regs);
913 do_IRQ(&regs);
914 break;
915 case BOOKE_INTERRUPT_DECREMENTER:
916 kvmppc_fill_pt_regs(&regs);
917 timer_interrupt(&regs);
918 break;
919 #if defined(CONFIG_PPC_DOORBELL)
920 case BOOKE_INTERRUPT_DOORBELL:
921 kvmppc_fill_pt_regs(&regs);
922 doorbell_exception(&regs);
923 break;
924 #endif
925 case BOOKE_INTERRUPT_MACHINE_CHECK:
926 /* FIXME */
927 break;
928 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
929 kvmppc_fill_pt_regs(&regs);
930 performance_monitor_exception(&regs);
931 break;
932 case BOOKE_INTERRUPT_WATCHDOG:
933 kvmppc_fill_pt_regs(&regs);
934 #ifdef CONFIG_BOOKE_WDT
935 WatchdogException(&regs);
936 #else
937 unknown_exception(&regs);
938 #endif
939 break;
940 case BOOKE_INTERRUPT_CRITICAL:
941 kvmppc_fill_pt_regs(&regs);
942 unknown_exception(&regs);
943 break;
944 case BOOKE_INTERRUPT_DEBUG:
945 /* Save DBSR before preemption is enabled */
946 vcpu->arch.dbsr = mfspr(SPRN_DBSR);
947 kvmppc_clear_dbsr();
948 break;
949 }
950 }
951
952 static int kvmppc_resume_inst_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
953 enum emulation_result emulated, u32 last_inst)
954 {
955 switch (emulated) {
956 case EMULATE_AGAIN:
957 return RESUME_GUEST;
958
959 case EMULATE_FAIL:
960 pr_debug("%s: load instruction from guest address %lx failed\n",
961 __func__, vcpu->arch.pc);
962 /* For debugging, encode the failing instruction and
963 * report it to userspace. */
964 run->hw.hardware_exit_reason = ~0ULL << 32;
965 run->hw.hardware_exit_reason |= last_inst;
966 kvmppc_core_queue_program(vcpu, ESR_PIL);
967 return RESUME_HOST;
968
969 default:
970 BUG();
971 }
972 }
973
974 /**
975 * kvmppc_handle_exit
976 *
977 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
978 */
979 int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
980 unsigned int exit_nr)
981 {
982 int r = RESUME_HOST;
983 int s;
984 int idx;
985 u32 last_inst = KVM_INST_FETCH_FAILED;
986 enum emulation_result emulated = EMULATE_DONE;
987
988 /* update before a new last_exit_type is rewritten */
989 kvmppc_update_timing_stats(vcpu);
990
991 /* restart interrupts if they were meant for the host */
992 kvmppc_restart_interrupt(vcpu, exit_nr);
993
994 /*
995 * get last instruction before being preempted
996 * TODO: for e6500 check also BOOKE_INTERRUPT_LRAT_ERROR & ESR_DATA
997 */
998 switch (exit_nr) {
999 case BOOKE_INTERRUPT_DATA_STORAGE:
1000 case BOOKE_INTERRUPT_DTLB_MISS:
1001 case BOOKE_INTERRUPT_HV_PRIV:
1002 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
1003 break;
1004 case BOOKE_INTERRUPT_PROGRAM:
1005 /* SW breakpoints arrive as illegal instructions on HV */
1006 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1007 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
1008 break;
1009 default:
1010 break;
1011 }
1012
1013 trace_kvm_exit(exit_nr, vcpu);
1014 __kvm_guest_exit();
1015
1016 local_irq_enable();
1017
1018 run->exit_reason = KVM_EXIT_UNKNOWN;
1019 run->ready_for_interrupt_injection = 1;
1020
1021 if (emulated != EMULATE_DONE) {
1022 r = kvmppc_resume_inst_load(run, vcpu, emulated, last_inst);
1023 goto out;
1024 }
1025
1026 switch (exit_nr) {
1027 case BOOKE_INTERRUPT_MACHINE_CHECK:
1028 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
1029 kvmppc_dump_vcpu(vcpu);
1030 /* For debugging, send invalid exit reason to user space */
1031 run->hw.hardware_exit_reason = ~1ULL << 32;
1032 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
1033 r = RESUME_HOST;
1034 break;
1035
1036 case BOOKE_INTERRUPT_EXTERNAL:
1037 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1038 r = RESUME_GUEST;
1039 break;
1040
1041 case BOOKE_INTERRUPT_DECREMENTER:
1042 kvmppc_account_exit(vcpu, DEC_EXITS);
1043 r = RESUME_GUEST;
1044 break;
1045
1046 case BOOKE_INTERRUPT_WATCHDOG:
1047 r = RESUME_GUEST;
1048 break;
1049
1050 case BOOKE_INTERRUPT_DOORBELL:
1051 kvmppc_account_exit(vcpu, DBELL_EXITS);
1052 r = RESUME_GUEST;
1053 break;
1054
1055 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
1056 kvmppc_account_exit(vcpu, GDBELL_EXITS);
1057
1058 /*
1059 * We are here because there is a pending guest interrupt
1060 * which could not be delivered as MSR_CE or MSR_ME was not
1061 * set. Once we break from here we will retry delivery.
1062 */
1063 r = RESUME_GUEST;
1064 break;
1065
1066 case BOOKE_INTERRUPT_GUEST_DBELL:
1067 kvmppc_account_exit(vcpu, GDBELL_EXITS);
1068
1069 /*
1070 * We are here because there is a pending guest interrupt
1071 * which could not be delivered as MSR_EE was not set. Once
1072 * we break from here we will retry delivery.
1073 */
1074 r = RESUME_GUEST;
1075 break;
1076
1077 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
1078 r = RESUME_GUEST;
1079 break;
1080
1081 case BOOKE_INTERRUPT_HV_PRIV:
1082 r = emulation_exit(run, vcpu);
1083 break;
1084
1085 case BOOKE_INTERRUPT_PROGRAM:
1086 if ((vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) &&
1087 (last_inst == KVMPPC_INST_SW_BREAKPOINT)) {
1088 /*
1089 * We are here because of an SW breakpoint instr,
1090 * so lets return to host to handle.
1091 */
1092 r = kvmppc_handle_debug(run, vcpu);
1093 run->exit_reason = KVM_EXIT_DEBUG;
1094 kvmppc_account_exit(vcpu, DEBUG_EXITS);
1095 break;
1096 }
1097
1098 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
1099 /*
1100 * Program traps generated by user-level software must
1101 * be handled by the guest kernel.
1102 *
1103 * In GS mode, hypervisor privileged instructions trap
1104 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
1105 * actual program interrupts, handled by the guest.
1106 */
1107 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
1108 r = RESUME_GUEST;
1109 kvmppc_account_exit(vcpu, USR_PR_INST);
1110 break;
1111 }
1112
1113 r = emulation_exit(run, vcpu);
1114 break;
1115
1116 case BOOKE_INTERRUPT_FP_UNAVAIL:
1117 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
1118 kvmppc_account_exit(vcpu, FP_UNAVAIL);
1119 r = RESUME_GUEST;
1120 break;
1121
1122 #ifdef CONFIG_SPE
1123 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
1124 if (vcpu->arch.shared->msr & MSR_SPE)
1125 kvmppc_vcpu_enable_spe(vcpu);
1126 else
1127 kvmppc_booke_queue_irqprio(vcpu,
1128 BOOKE_IRQPRIO_SPE_UNAVAIL);
1129 r = RESUME_GUEST;
1130 break;
1131 }
1132
1133 case BOOKE_INTERRUPT_SPE_FP_DATA:
1134 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
1135 r = RESUME_GUEST;
1136 break;
1137
1138 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1139 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
1140 r = RESUME_GUEST;
1141 break;
1142 #elif defined(CONFIG_SPE_POSSIBLE)
1143 case BOOKE_INTERRUPT_SPE_UNAVAIL:
1144 /*
1145 * Guest wants SPE, but host kernel doesn't support it. Send
1146 * an "unimplemented operation" program check to the guest.
1147 */
1148 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
1149 r = RESUME_GUEST;
1150 break;
1151
1152 /*
1153 * These really should never happen without CONFIG_SPE,
1154 * as we should never enable the real MSR[SPE] in the guest.
1155 */
1156 case BOOKE_INTERRUPT_SPE_FP_DATA:
1157 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1158 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
1159 __func__, exit_nr, vcpu->arch.pc);
1160 run->hw.hardware_exit_reason = exit_nr;
1161 r = RESUME_HOST;
1162 break;
1163 #endif /* CONFIG_SPE_POSSIBLE */
1164
1165 /*
1166 * On cores with Vector category, KVM is loaded only if CONFIG_ALTIVEC,
1167 * see kvmppc_core_check_processor_compat().
1168 */
1169 #ifdef CONFIG_ALTIVEC
1170 case BOOKE_INTERRUPT_ALTIVEC_UNAVAIL:
1171 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
1172 r = RESUME_GUEST;
1173 break;
1174
1175 case BOOKE_INTERRUPT_ALTIVEC_ASSIST:
1176 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_ASSIST);
1177 r = RESUME_GUEST;
1178 break;
1179 #endif
1180
1181 case BOOKE_INTERRUPT_DATA_STORAGE:
1182 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
1183 vcpu->arch.fault_esr);
1184 kvmppc_account_exit(vcpu, DSI_EXITS);
1185 r = RESUME_GUEST;
1186 break;
1187
1188 case BOOKE_INTERRUPT_INST_STORAGE:
1189 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
1190 kvmppc_account_exit(vcpu, ISI_EXITS);
1191 r = RESUME_GUEST;
1192 break;
1193
1194 case BOOKE_INTERRUPT_ALIGNMENT:
1195 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear,
1196 vcpu->arch.fault_esr);
1197 r = RESUME_GUEST;
1198 break;
1199
1200 #ifdef CONFIG_KVM_BOOKE_HV
1201 case BOOKE_INTERRUPT_HV_SYSCALL:
1202 if (!(vcpu->arch.shared->msr & MSR_PR)) {
1203 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1204 } else {
1205 /*
1206 * hcall from guest userspace -- send privileged
1207 * instruction program check.
1208 */
1209 kvmppc_core_queue_program(vcpu, ESR_PPR);
1210 }
1211
1212 r = RESUME_GUEST;
1213 break;
1214 #else
1215 case BOOKE_INTERRUPT_SYSCALL:
1216 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1217 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
1218 /* KVM PV hypercalls */
1219 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1220 r = RESUME_GUEST;
1221 } else {
1222 /* Guest syscalls */
1223 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
1224 }
1225 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
1226 r = RESUME_GUEST;
1227 break;
1228 #endif
1229
1230 case BOOKE_INTERRUPT_DTLB_MISS: {
1231 unsigned long eaddr = vcpu->arch.fault_dear;
1232 int gtlb_index;
1233 gpa_t gpaddr;
1234 gfn_t gfn;
1235
1236 #ifdef CONFIG_KVM_E500V2
1237 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1238 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1239 kvmppc_map_magic(vcpu);
1240 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1241 r = RESUME_GUEST;
1242
1243 break;
1244 }
1245 #endif
1246
1247 /* Check the guest TLB. */
1248 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
1249 if (gtlb_index < 0) {
1250 /* The guest didn't have a mapping for it. */
1251 kvmppc_core_queue_dtlb_miss(vcpu,
1252 vcpu->arch.fault_dear,
1253 vcpu->arch.fault_esr);
1254 kvmppc_mmu_dtlb_miss(vcpu);
1255 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
1256 r = RESUME_GUEST;
1257 break;
1258 }
1259
1260 idx = srcu_read_lock(&vcpu->kvm->srcu);
1261
1262 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1263 gfn = gpaddr >> PAGE_SHIFT;
1264
1265 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1266 /* The guest TLB had a mapping, but the shadow TLB
1267 * didn't, and it is RAM. This could be because:
1268 * a) the entry is mapping the host kernel, or
1269 * b) the guest used a large mapping which we're faking
1270 * Either way, we need to satisfy the fault without
1271 * invoking the guest. */
1272 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
1273 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1274 r = RESUME_GUEST;
1275 } else {
1276 /* Guest has mapped and accessed a page which is not
1277 * actually RAM. */
1278 vcpu->arch.paddr_accessed = gpaddr;
1279 vcpu->arch.vaddr_accessed = eaddr;
1280 r = kvmppc_emulate_mmio(run, vcpu);
1281 kvmppc_account_exit(vcpu, MMIO_EXITS);
1282 }
1283
1284 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1285 break;
1286 }
1287
1288 case BOOKE_INTERRUPT_ITLB_MISS: {
1289 unsigned long eaddr = vcpu->arch.pc;
1290 gpa_t gpaddr;
1291 gfn_t gfn;
1292 int gtlb_index;
1293
1294 r = RESUME_GUEST;
1295
1296 /* Check the guest TLB. */
1297 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
1298 if (gtlb_index < 0) {
1299 /* The guest didn't have a mapping for it. */
1300 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
1301 kvmppc_mmu_itlb_miss(vcpu);
1302 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
1303 break;
1304 }
1305
1306 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
1307
1308 idx = srcu_read_lock(&vcpu->kvm->srcu);
1309
1310 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1311 gfn = gpaddr >> PAGE_SHIFT;
1312
1313 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1314 /* The guest TLB had a mapping, but the shadow TLB
1315 * didn't. This could be because:
1316 * a) the entry is mapping the host kernel, or
1317 * b) the guest used a large mapping which we're faking
1318 * Either way, we need to satisfy the fault without
1319 * invoking the guest. */
1320 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
1321 } else {
1322 /* Guest mapped and leaped at non-RAM! */
1323 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
1324 }
1325
1326 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1327 break;
1328 }
1329
1330 case BOOKE_INTERRUPT_DEBUG: {
1331 r = kvmppc_handle_debug(run, vcpu);
1332 if (r == RESUME_HOST)
1333 run->exit_reason = KVM_EXIT_DEBUG;
1334 kvmppc_account_exit(vcpu, DEBUG_EXITS);
1335 break;
1336 }
1337
1338 default:
1339 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1340 BUG();
1341 }
1342
1343 out:
1344 /*
1345 * To avoid clobbering exit_reason, only check for signals if we
1346 * aren't already exiting to userspace for some other reason.
1347 */
1348 if (!(r & RESUME_HOST)) {
1349 s = kvmppc_prepare_to_enter(vcpu);
1350 if (s <= 0)
1351 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
1352 else {
1353 /* interrupts now hard-disabled */
1354 kvmppc_fix_ee_before_entry();
1355 kvmppc_load_guest_fp(vcpu);
1356 kvmppc_load_guest_altivec(vcpu);
1357 }
1358 }
1359
1360 return r;
1361 }
1362
1363 static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
1364 {
1365 u32 old_tsr = vcpu->arch.tsr;
1366
1367 vcpu->arch.tsr = new_tsr;
1368
1369 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1370 arm_next_watchdog(vcpu);
1371
1372 update_timer_ints(vcpu);
1373 }
1374
1375 /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1376 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1377 {
1378 int i;
1379 int r;
1380
1381 vcpu->arch.pc = 0;
1382 vcpu->arch.shared->pir = vcpu->vcpu_id;
1383 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
1384 kvmppc_set_msr(vcpu, 0);
1385
1386 #ifndef CONFIG_KVM_BOOKE_HV
1387 vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS;
1388 vcpu->arch.shadow_pid = 1;
1389 vcpu->arch.shared->msr = 0;
1390 #endif
1391
1392 /* Eye-catching numbers so we know if the guest takes an interrupt
1393 * before it's programmed its own IVPR/IVORs. */
1394 vcpu->arch.ivpr = 0x55550000;
1395 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1396 vcpu->arch.ivor[i] = 0x7700 | i * 4;
1397
1398 kvmppc_init_timing_stats(vcpu);
1399
1400 r = kvmppc_core_vcpu_setup(vcpu);
1401 kvmppc_sanity_check(vcpu);
1402 return r;
1403 }
1404
1405 int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1406 {
1407 /* setup watchdog timer once */
1408 spin_lock_init(&vcpu->arch.wdt_lock);
1409 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1410 (unsigned long)vcpu);
1411
1412 /*
1413 * Clear DBSR.MRR to avoid guest debug interrupt as
1414 * this is of host interest
1415 */
1416 mtspr(SPRN_DBSR, DBSR_MRR);
1417 return 0;
1418 }
1419
1420 void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1421 {
1422 del_timer_sync(&vcpu->arch.wdt_timer);
1423 }
1424
1425 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1426 {
1427 int i;
1428
1429 regs->pc = vcpu->arch.pc;
1430 regs->cr = kvmppc_get_cr(vcpu);
1431 regs->ctr = vcpu->arch.ctr;
1432 regs->lr = vcpu->arch.lr;
1433 regs->xer = kvmppc_get_xer(vcpu);
1434 regs->msr = vcpu->arch.shared->msr;
1435 regs->srr0 = kvmppc_get_srr0(vcpu);
1436 regs->srr1 = kvmppc_get_srr1(vcpu);
1437 regs->pid = vcpu->arch.pid;
1438 regs->sprg0 = kvmppc_get_sprg0(vcpu);
1439 regs->sprg1 = kvmppc_get_sprg1(vcpu);
1440 regs->sprg2 = kvmppc_get_sprg2(vcpu);
1441 regs->sprg3 = kvmppc_get_sprg3(vcpu);
1442 regs->sprg4 = kvmppc_get_sprg4(vcpu);
1443 regs->sprg5 = kvmppc_get_sprg5(vcpu);
1444 regs->sprg6 = kvmppc_get_sprg6(vcpu);
1445 regs->sprg7 = kvmppc_get_sprg7(vcpu);
1446
1447 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1448 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
1449
1450 return 0;
1451 }
1452
1453 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1454 {
1455 int i;
1456
1457 vcpu->arch.pc = regs->pc;
1458 kvmppc_set_cr(vcpu, regs->cr);
1459 vcpu->arch.ctr = regs->ctr;
1460 vcpu->arch.lr = regs->lr;
1461 kvmppc_set_xer(vcpu, regs->xer);
1462 kvmppc_set_msr(vcpu, regs->msr);
1463 kvmppc_set_srr0(vcpu, regs->srr0);
1464 kvmppc_set_srr1(vcpu, regs->srr1);
1465 kvmppc_set_pid(vcpu, regs->pid);
1466 kvmppc_set_sprg0(vcpu, regs->sprg0);
1467 kvmppc_set_sprg1(vcpu, regs->sprg1);
1468 kvmppc_set_sprg2(vcpu, regs->sprg2);
1469 kvmppc_set_sprg3(vcpu, regs->sprg3);
1470 kvmppc_set_sprg4(vcpu, regs->sprg4);
1471 kvmppc_set_sprg5(vcpu, regs->sprg5);
1472 kvmppc_set_sprg6(vcpu, regs->sprg6);
1473 kvmppc_set_sprg7(vcpu, regs->sprg7);
1474
1475 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1476 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
1477
1478 return 0;
1479 }
1480
1481 static void get_sregs_base(struct kvm_vcpu *vcpu,
1482 struct kvm_sregs *sregs)
1483 {
1484 u64 tb = get_tb();
1485
1486 sregs->u.e.features |= KVM_SREGS_E_BASE;
1487
1488 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1489 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1490 sregs->u.e.mcsr = vcpu->arch.mcsr;
1491 sregs->u.e.esr = kvmppc_get_esr(vcpu);
1492 sregs->u.e.dear = kvmppc_get_dar(vcpu);
1493 sregs->u.e.tsr = vcpu->arch.tsr;
1494 sregs->u.e.tcr = vcpu->arch.tcr;
1495 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1496 sregs->u.e.tb = tb;
1497 sregs->u.e.vrsave = vcpu->arch.vrsave;
1498 }
1499
1500 static int set_sregs_base(struct kvm_vcpu *vcpu,
1501 struct kvm_sregs *sregs)
1502 {
1503 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1504 return 0;
1505
1506 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1507 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1508 vcpu->arch.mcsr = sregs->u.e.mcsr;
1509 kvmppc_set_esr(vcpu, sregs->u.e.esr);
1510 kvmppc_set_dar(vcpu, sregs->u.e.dear);
1511 vcpu->arch.vrsave = sregs->u.e.vrsave;
1512 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
1513
1514 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
1515 vcpu->arch.dec = sregs->u.e.dec;
1516 kvmppc_emulate_dec(vcpu);
1517 }
1518
1519 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
1520 kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
1521
1522 return 0;
1523 }
1524
1525 static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1526 struct kvm_sregs *sregs)
1527 {
1528 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1529
1530 sregs->u.e.pir = vcpu->vcpu_id;
1531 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1532 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1533 sregs->u.e.decar = vcpu->arch.decar;
1534 sregs->u.e.ivpr = vcpu->arch.ivpr;
1535 }
1536
1537 static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1538 struct kvm_sregs *sregs)
1539 {
1540 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1541 return 0;
1542
1543 if (sregs->u.e.pir != vcpu->vcpu_id)
1544 return -EINVAL;
1545
1546 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1547 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1548 vcpu->arch.decar = sregs->u.e.decar;
1549 vcpu->arch.ivpr = sregs->u.e.ivpr;
1550
1551 return 0;
1552 }
1553
1554 int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1555 {
1556 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1557
1558 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1559 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1560 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1561 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1562 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1563 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1564 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1565 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1566 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1567 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1568 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1569 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1570 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1571 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1572 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1573 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
1574 return 0;
1575 }
1576
1577 int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1578 {
1579 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1580 return 0;
1581
1582 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1583 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1584 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1585 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1586 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1587 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1588 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1589 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1590 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1591 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1592 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1593 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1594 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1595 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1596 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1597 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1598
1599 return 0;
1600 }
1601
1602 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1603 struct kvm_sregs *sregs)
1604 {
1605 sregs->pvr = vcpu->arch.pvr;
1606
1607 get_sregs_base(vcpu, sregs);
1608 get_sregs_arch206(vcpu, sregs);
1609 return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs);
1610 }
1611
1612 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1613 struct kvm_sregs *sregs)
1614 {
1615 int ret;
1616
1617 if (vcpu->arch.pvr != sregs->pvr)
1618 return -EINVAL;
1619
1620 ret = set_sregs_base(vcpu, sregs);
1621 if (ret < 0)
1622 return ret;
1623
1624 ret = set_sregs_arch206(vcpu, sregs);
1625 if (ret < 0)
1626 return ret;
1627
1628 return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs);
1629 }
1630
1631 int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
1632 union kvmppc_one_reg *val)
1633 {
1634 int r = 0;
1635
1636 switch (id) {
1637 case KVM_REG_PPC_IAC1:
1638 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1);
1639 break;
1640 case KVM_REG_PPC_IAC2:
1641 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2);
1642 break;
1643 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1644 case KVM_REG_PPC_IAC3:
1645 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3);
1646 break;
1647 case KVM_REG_PPC_IAC4:
1648 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4);
1649 break;
1650 #endif
1651 case KVM_REG_PPC_DAC1:
1652 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1);
1653 break;
1654 case KVM_REG_PPC_DAC2:
1655 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2);
1656 break;
1657 case KVM_REG_PPC_EPR: {
1658 u32 epr = kvmppc_get_epr(vcpu);
1659 *val = get_reg_val(id, epr);
1660 break;
1661 }
1662 #if defined(CONFIG_64BIT)
1663 case KVM_REG_PPC_EPCR:
1664 *val = get_reg_val(id, vcpu->arch.epcr);
1665 break;
1666 #endif
1667 case KVM_REG_PPC_TCR:
1668 *val = get_reg_val(id, vcpu->arch.tcr);
1669 break;
1670 case KVM_REG_PPC_TSR:
1671 *val = get_reg_val(id, vcpu->arch.tsr);
1672 break;
1673 case KVM_REG_PPC_DEBUG_INST:
1674 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT);
1675 break;
1676 case KVM_REG_PPC_VRSAVE:
1677 *val = get_reg_val(id, vcpu->arch.vrsave);
1678 break;
1679 default:
1680 r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val);
1681 break;
1682 }
1683
1684 return r;
1685 }
1686
1687 int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
1688 union kvmppc_one_reg *val)
1689 {
1690 int r = 0;
1691
1692 switch (id) {
1693 case KVM_REG_PPC_IAC1:
1694 vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val);
1695 break;
1696 case KVM_REG_PPC_IAC2:
1697 vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val);
1698 break;
1699 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1700 case KVM_REG_PPC_IAC3:
1701 vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val);
1702 break;
1703 case KVM_REG_PPC_IAC4:
1704 vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val);
1705 break;
1706 #endif
1707 case KVM_REG_PPC_DAC1:
1708 vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val);
1709 break;
1710 case KVM_REG_PPC_DAC2:
1711 vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val);
1712 break;
1713 case KVM_REG_PPC_EPR: {
1714 u32 new_epr = set_reg_val(id, *val);
1715 kvmppc_set_epr(vcpu, new_epr);
1716 break;
1717 }
1718 #if defined(CONFIG_64BIT)
1719 case KVM_REG_PPC_EPCR: {
1720 u32 new_epcr = set_reg_val(id, *val);
1721 kvmppc_set_epcr(vcpu, new_epcr);
1722 break;
1723 }
1724 #endif
1725 case KVM_REG_PPC_OR_TSR: {
1726 u32 tsr_bits = set_reg_val(id, *val);
1727 kvmppc_set_tsr_bits(vcpu, tsr_bits);
1728 break;
1729 }
1730 case KVM_REG_PPC_CLEAR_TSR: {
1731 u32 tsr_bits = set_reg_val(id, *val);
1732 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
1733 break;
1734 }
1735 case KVM_REG_PPC_TSR: {
1736 u32 tsr = set_reg_val(id, *val);
1737 kvmppc_set_tsr(vcpu, tsr);
1738 break;
1739 }
1740 case KVM_REG_PPC_TCR: {
1741 u32 tcr = set_reg_val(id, *val);
1742 kvmppc_set_tcr(vcpu, tcr);
1743 break;
1744 }
1745 case KVM_REG_PPC_VRSAVE:
1746 vcpu->arch.vrsave = set_reg_val(id, *val);
1747 break;
1748 default:
1749 r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val);
1750 break;
1751 }
1752
1753 return r;
1754 }
1755
1756 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1757 {
1758 return -ENOTSUPP;
1759 }
1760
1761 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1762 {
1763 return -ENOTSUPP;
1764 }
1765
1766 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1767 struct kvm_translation *tr)
1768 {
1769 int r;
1770
1771 r = kvmppc_core_vcpu_translate(vcpu, tr);
1772 return r;
1773 }
1774
1775 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1776 {
1777 return -ENOTSUPP;
1778 }
1779
1780 void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
1781 struct kvm_memory_slot *dont)
1782 {
1783 }
1784
1785 int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
1786 unsigned long npages)
1787 {
1788 return 0;
1789 }
1790
1791 int kvmppc_core_prepare_memory_region(struct kvm *kvm,
1792 struct kvm_memory_slot *memslot,
1793 const struct kvm_userspace_memory_region *mem)
1794 {
1795 return 0;
1796 }
1797
1798 void kvmppc_core_commit_memory_region(struct kvm *kvm,
1799 const struct kvm_userspace_memory_region *mem,
1800 const struct kvm_memory_slot *old,
1801 const struct kvm_memory_slot *new)
1802 {
1803 }
1804
1805 void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
1806 {
1807 }
1808
1809 void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1810 {
1811 #if defined(CONFIG_64BIT)
1812 vcpu->arch.epcr = new_epcr;
1813 #ifdef CONFIG_KVM_BOOKE_HV
1814 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1815 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1816 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1817 #endif
1818 #endif
1819 }
1820
1821 void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1822 {
1823 vcpu->arch.tcr = new_tcr;
1824 arm_next_watchdog(vcpu);
1825 update_timer_ints(vcpu);
1826 }
1827
1828 void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1829 {
1830 set_bits(tsr_bits, &vcpu->arch.tsr);
1831 smp_wmb();
1832 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1833 kvm_vcpu_kick(vcpu);
1834 }
1835
1836 void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1837 {
1838 clear_bits(tsr_bits, &vcpu->arch.tsr);
1839
1840 /*
1841 * We may have stopped the watchdog due to
1842 * being stuck on final expiration.
1843 */
1844 if (tsr_bits & (TSR_ENW | TSR_WIS))
1845 arm_next_watchdog(vcpu);
1846
1847 update_timer_ints(vcpu);
1848 }
1849
1850 void kvmppc_decrementer_func(struct kvm_vcpu *vcpu)
1851 {
1852 if (vcpu->arch.tcr & TCR_ARE) {
1853 vcpu->arch.dec = vcpu->arch.decar;
1854 kvmppc_emulate_dec(vcpu);
1855 }
1856
1857 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1858 }
1859
1860 static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg,
1861 uint64_t addr, int index)
1862 {
1863 switch (index) {
1864 case 0:
1865 dbg_reg->dbcr0 |= DBCR0_IAC1;
1866 dbg_reg->iac1 = addr;
1867 break;
1868 case 1:
1869 dbg_reg->dbcr0 |= DBCR0_IAC2;
1870 dbg_reg->iac2 = addr;
1871 break;
1872 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1873 case 2:
1874 dbg_reg->dbcr0 |= DBCR0_IAC3;
1875 dbg_reg->iac3 = addr;
1876 break;
1877 case 3:
1878 dbg_reg->dbcr0 |= DBCR0_IAC4;
1879 dbg_reg->iac4 = addr;
1880 break;
1881 #endif
1882 default:
1883 return -EINVAL;
1884 }
1885
1886 dbg_reg->dbcr0 |= DBCR0_IDM;
1887 return 0;
1888 }
1889
1890 static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
1891 int type, int index)
1892 {
1893 switch (index) {
1894 case 0:
1895 if (type & KVMPPC_DEBUG_WATCH_READ)
1896 dbg_reg->dbcr0 |= DBCR0_DAC1R;
1897 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1898 dbg_reg->dbcr0 |= DBCR0_DAC1W;
1899 dbg_reg->dac1 = addr;
1900 break;
1901 case 1:
1902 if (type & KVMPPC_DEBUG_WATCH_READ)
1903 dbg_reg->dbcr0 |= DBCR0_DAC2R;
1904 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1905 dbg_reg->dbcr0 |= DBCR0_DAC2W;
1906 dbg_reg->dac2 = addr;
1907 break;
1908 default:
1909 return -EINVAL;
1910 }
1911
1912 dbg_reg->dbcr0 |= DBCR0_IDM;
1913 return 0;
1914 }
1915 void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
1916 {
1917 /* XXX: Add similar MSR protection for BookE-PR */
1918 #ifdef CONFIG_KVM_BOOKE_HV
1919 BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP));
1920 if (set) {
1921 if (prot_bitmap & MSR_UCLE)
1922 vcpu->arch.shadow_msrp |= MSRP_UCLEP;
1923 if (prot_bitmap & MSR_DE)
1924 vcpu->arch.shadow_msrp |= MSRP_DEP;
1925 if (prot_bitmap & MSR_PMM)
1926 vcpu->arch.shadow_msrp |= MSRP_PMMP;
1927 } else {
1928 if (prot_bitmap & MSR_UCLE)
1929 vcpu->arch.shadow_msrp &= ~MSRP_UCLEP;
1930 if (prot_bitmap & MSR_DE)
1931 vcpu->arch.shadow_msrp &= ~MSRP_DEP;
1932 if (prot_bitmap & MSR_PMM)
1933 vcpu->arch.shadow_msrp &= ~MSRP_PMMP;
1934 }
1935 #endif
1936 }
1937
1938 int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid,
1939 enum xlate_readwrite xlrw, struct kvmppc_pte *pte)
1940 {
1941 int gtlb_index;
1942 gpa_t gpaddr;
1943
1944 #ifdef CONFIG_KVM_E500V2
1945 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1946 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1947 pte->eaddr = eaddr;
1948 pte->raddr = (vcpu->arch.magic_page_pa & PAGE_MASK) |
1949 (eaddr & ~PAGE_MASK);
1950 pte->vpage = eaddr >> PAGE_SHIFT;
1951 pte->may_read = true;
1952 pte->may_write = true;
1953 pte->may_execute = true;
1954
1955 return 0;
1956 }
1957 #endif
1958
1959 /* Check the guest TLB. */
1960 switch (xlid) {
1961 case XLATE_INST:
1962 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
1963 break;
1964 case XLATE_DATA:
1965 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
1966 break;
1967 default:
1968 BUG();
1969 }
1970
1971 /* Do we have a TLB entry at all? */
1972 if (gtlb_index < 0)
1973 return -ENOENT;
1974
1975 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1976
1977 pte->eaddr = eaddr;
1978 pte->raddr = (gpaddr & PAGE_MASK) | (eaddr & ~PAGE_MASK);
1979 pte->vpage = eaddr >> PAGE_SHIFT;
1980
1981 /* XXX read permissions from the guest TLB */
1982 pte->may_read = true;
1983 pte->may_write = true;
1984 pte->may_execute = true;
1985
1986 return 0;
1987 }
1988
1989 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
1990 struct kvm_guest_debug *dbg)
1991 {
1992 struct debug_reg *dbg_reg;
1993 int n, b = 0, w = 0;
1994
1995 if (!(dbg->control & KVM_GUESTDBG_ENABLE)) {
1996 vcpu->arch.dbg_reg.dbcr0 = 0;
1997 vcpu->guest_debug = 0;
1998 kvm_guest_protect_msr(vcpu, MSR_DE, false);
1999 return 0;
2000 }
2001
2002 kvm_guest_protect_msr(vcpu, MSR_DE, true);
2003 vcpu->guest_debug = dbg->control;
2004 vcpu->arch.dbg_reg.dbcr0 = 0;
2005
2006 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2007 vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2008
2009 /* Code below handles only HW breakpoints */
2010 dbg_reg = &(vcpu->arch.dbg_reg);
2011
2012 #ifdef CONFIG_KVM_BOOKE_HV
2013 /*
2014 * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1
2015 * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0
2016 */
2017 dbg_reg->dbcr1 = 0;
2018 dbg_reg->dbcr2 = 0;
2019 #else
2020 /*
2021 * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1
2022 * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR
2023 * is set.
2024 */
2025 dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US |
2026 DBCR1_IAC4US;
2027 dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
2028 #endif
2029
2030 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2031 return 0;
2032
2033 for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) {
2034 uint64_t addr = dbg->arch.bp[n].addr;
2035 uint32_t type = dbg->arch.bp[n].type;
2036
2037 if (type == KVMPPC_DEBUG_NONE)
2038 continue;
2039
2040 if (type & !(KVMPPC_DEBUG_WATCH_READ |
2041 KVMPPC_DEBUG_WATCH_WRITE |
2042 KVMPPC_DEBUG_BREAKPOINT))
2043 return -EINVAL;
2044
2045 if (type & KVMPPC_DEBUG_BREAKPOINT) {
2046 /* Setting H/W breakpoint */
2047 if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++))
2048 return -EINVAL;
2049 } else {
2050 /* Setting H/W watchpoint */
2051 if (kvmppc_booke_add_watchpoint(dbg_reg, addr,
2052 type, w++))
2053 return -EINVAL;
2054 }
2055 }
2056
2057 return 0;
2058 }
2059
2060 void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2061 {
2062 vcpu->cpu = smp_processor_id();
2063 current->thread.kvm_vcpu = vcpu;
2064 }
2065
2066 void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
2067 {
2068 current->thread.kvm_vcpu = NULL;
2069 vcpu->cpu = -1;
2070
2071 /* Clear pending debug event in DBSR */
2072 kvmppc_clear_dbsr();
2073 }
2074
2075 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
2076 {
2077 vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu);
2078 }
2079
2080 int kvmppc_core_init_vm(struct kvm *kvm)
2081 {
2082 return kvm->arch.kvm_ops->init_vm(kvm);
2083 }
2084
2085 struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
2086 {
2087 return kvm->arch.kvm_ops->vcpu_create(kvm, id);
2088 }
2089
2090 void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
2091 {
2092 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu);
2093 }
2094
2095 void kvmppc_core_destroy_vm(struct kvm *kvm)
2096 {
2097 kvm->arch.kvm_ops->destroy_vm(kvm);
2098 }
2099
2100 void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2101 {
2102 vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu);
2103 }
2104
2105 void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
2106 {
2107 vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu);
2108 }
2109
2110 int __init kvmppc_booke_init(void)
2111 {
2112 #ifndef CONFIG_KVM_BOOKE_HV
2113 unsigned long ivor[16];
2114 unsigned long *handler = kvmppc_booke_handler_addr;
2115 unsigned long max_ivor = 0;
2116 unsigned long handler_len;
2117 int i;
2118
2119 /* We install our own exception handlers by hijacking IVPR. IVPR must
2120 * be 16-bit aligned, so we need a 64KB allocation. */
2121 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
2122 VCPU_SIZE_ORDER);
2123 if (!kvmppc_booke_handlers)
2124 return -ENOMEM;
2125
2126 /* XXX make sure our handlers are smaller than Linux's */
2127
2128 /* Copy our interrupt handlers to match host IVORs. That way we don't
2129 * have to swap the IVORs on every guest/host transition. */
2130 ivor[0] = mfspr(SPRN_IVOR0);
2131 ivor[1] = mfspr(SPRN_IVOR1);
2132 ivor[2] = mfspr(SPRN_IVOR2);
2133 ivor[3] = mfspr(SPRN_IVOR3);
2134 ivor[4] = mfspr(SPRN_IVOR4);
2135 ivor[5] = mfspr(SPRN_IVOR5);
2136 ivor[6] = mfspr(SPRN_IVOR6);
2137 ivor[7] = mfspr(SPRN_IVOR7);
2138 ivor[8] = mfspr(SPRN_IVOR8);
2139 ivor[9] = mfspr(SPRN_IVOR9);
2140 ivor[10] = mfspr(SPRN_IVOR10);
2141 ivor[11] = mfspr(SPRN_IVOR11);
2142 ivor[12] = mfspr(SPRN_IVOR12);
2143 ivor[13] = mfspr(SPRN_IVOR13);
2144 ivor[14] = mfspr(SPRN_IVOR14);
2145 ivor[15] = mfspr(SPRN_IVOR15);
2146
2147 for (i = 0; i < 16; i++) {
2148 if (ivor[i] > max_ivor)
2149 max_ivor = i;
2150
2151 handler_len = handler[i + 1] - handler[i];
2152 memcpy((void *)kvmppc_booke_handlers + ivor[i],
2153 (void *)handler[i], handler_len);
2154 }
2155
2156 handler_len = handler[max_ivor + 1] - handler[max_ivor];
2157 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
2158 ivor[max_ivor] + handler_len);
2159 #endif /* !BOOKE_HV */
2160 return 0;
2161 }
2162
2163 void __exit kvmppc_booke_exit(void)
2164 {
2165 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
2166 kvm_exit();
2167 }
Linux with added FPC-III support