drivers/memory/tegra/mc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #ifndef MEMORY_TEGRA_MC_H
   7 #define MEMORY_TEGRA_MC_H
   8
   9 #include <linux/bits.h>
  10 #include <linux/io.h>
  11 #include <linux/types.h>
  12
  13 #include <soc/tegra/mc.h>
  14
  15 #define MC_INTSTATUS                                    0x00
  16 #define MC_INTMASK                                      0x04
  17 #define MC_ERR_STATUS                                   0x08
  18 #define MC_ERR_ADR                                      0x0c
  19 #define MC_GART_ERROR_REQ                               0x30
  20 #define MC_EMEM_ADR_CFG                                 0x54
  21 #define MC_DECERR_EMEM_OTHERS_STATUS                    0x58
  22 #define MC_SECURITY_VIOLATION_STATUS                    0x74
  23 #define MC_EMEM_ARB_CFG                                 0x90
  24 #define MC_EMEM_ARB_OUTSTANDING_REQ                     0x94
  25 #define MC_EMEM_ARB_TIMING_RCD                          0x98
  26 #define MC_EMEM_ARB_TIMING_RP                           0x9c
  27 #define MC_EMEM_ARB_TIMING_RC                           0xa0
  28 #define MC_EMEM_ARB_TIMING_RAS                          0xa4
  29 #define MC_EMEM_ARB_TIMING_FAW                          0xa8
  30 #define MC_EMEM_ARB_TIMING_RRD                          0xac
  31 #define MC_EMEM_ARB_TIMING_RAP2PRE                      0xb0
  32 #define MC_EMEM_ARB_TIMING_WAP2PRE                      0xb4
  33 #define MC_EMEM_ARB_TIMING_R2R                          0xb8
  34 #define MC_EMEM_ARB_TIMING_W2W                          0xbc
  35 #define MC_EMEM_ARB_TIMING_R2W                          0xc0
  36 #define MC_EMEM_ARB_TIMING_W2R                          0xc4
  37 #define MC_EMEM_ARB_DA_TURNS                            0xd0
  38 #define MC_EMEM_ARB_DA_COVERS                           0xd4
  39 #define MC_EMEM_ARB_MISC0                               0xd8
  40 #define MC_EMEM_ARB_MISC1                               0xdc
  41 #define MC_EMEM_ARB_RING1_THROTTLE                      0xe0
  42 #define MC_EMEM_ARB_OVERRIDE                            0xe8
  43 #define MC_TIMING_CONTROL_DBG                           0xf8
  44 #define MC_TIMING_CONTROL                               0xfc
  45
  46 #define MC_INT_DECERR_MTS                               BIT(16)
  47 #define MC_INT_SECERR_SEC                               BIT(13)
  48 #define MC_INT_DECERR_VPR                               BIT(12)
  49 #define MC_INT_INVALID_APB_ASID_UPDATE                  BIT(11)
  50 #define MC_INT_INVALID_SMMU_PAGE                        BIT(10)
  51 #define MC_INT_ARBITRATION_EMEM                         BIT(9)
  52 #define MC_INT_SECURITY_VIOLATION                       BIT(8)
  53 #define MC_INT_INVALID_GART_PAGE                        BIT(7)
  54 #define MC_INT_DECERR_EMEM                              BIT(6)
  55
  56 #define MC_ERR_STATUS_TYPE_SHIFT                        28
  57 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE            (0x6 << 28)
  58 #define MC_ERR_STATUS_TYPE_MASK                         (0x7 << 28)
  59 #define MC_ERR_STATUS_READABLE                          BIT(27)
  60 #define MC_ERR_STATUS_WRITABLE                          BIT(26)
  61 #define MC_ERR_STATUS_NONSECURE                         BIT(25)
  62 #define MC_ERR_STATUS_ADR_HI_SHIFT                      20
  63 #define MC_ERR_STATUS_ADR_HI_MASK                       0x3
  64 #define MC_ERR_STATUS_SECURITY                          BIT(17)
  65 #define MC_ERR_STATUS_RW                                BIT(16)
  66
  67 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV                     BIT(0)
  68
  69 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)            ((x) & 0x1ff)
  70 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK          0x1ff
  71
  72 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK            0x1ff
  73 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE    BIT(30)
  74 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE        BIT(31)
  75
  76 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK                  0x3
  77
  78 #define MC_TIMING_UPDATE                                BIT(0)
  79
  80 static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
  81 {
  82         return readl_relaxed(mc->regs + offset);
  83 }
  84
  85 static inline void mc_writel(struct tegra_mc *mc, u32 value,
  86                              unsigned long offset)
  87 {
  88         writel_relaxed(value, mc->regs + offset);
  89 }
  90
  91 extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
  92
  93 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  94 extern const struct tegra_mc_soc tegra20_mc_soc;
  95 #endif
  96
  97 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  98 extern const struct tegra_mc_soc tegra30_mc_soc;
  99 #endif
 100
 101 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 102 extern const struct tegra_mc_soc tegra114_mc_soc;
 103 #endif
 104
 105 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 106 extern const struct tegra_mc_soc tegra124_mc_soc;
 107 #endif
 108
 109 #ifdef CONFIG_ARCH_TEGRA_132_SOC
 110 extern const struct tegra_mc_soc tegra132_mc_soc;
 111 #endif
 112
 113 #ifdef CONFIG_ARCH_TEGRA_210_SOC
 114 extern const struct tegra_mc_soc tegra210_mc_soc;
 115 #endif
 116
 117 #endif /* MEMORY_TEGRA_MC_H */