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Merge tag '5.9-rc-smb3-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6
[linux/fpc-iii.git] / drivers / clk / clk-aspeed.c
blob411ff5fb2c07abc9686012382ec95669a56f7139
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright IBM Corp
3
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
5
6 #include <linux/mfd/syscon.h>
7 #include <linux/of_address.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/slab.h>
12
13 #include <dt-bindings/clock/aspeed-clock.h>
14
15 #include "clk-aspeed.h"
16
17 #define ASPEED_NUM_CLKS 38
18
19 #define ASPEED_RESET2_OFFSET 32
20
21 #define ASPEED_RESET_CTRL 0x04
22 #define ASPEED_CLK_SELECTION 0x08
23 #define ASPEED_CLK_STOP_CTRL 0x0c
24 #define ASPEED_MPLL_PARAM 0x20
25 #define ASPEED_HPLL_PARAM 0x24
26 #define AST2500_HPLL_BYPASS_EN BIT(20)
27 #define AST2400_HPLL_PROGRAMMED BIT(18)
28 #define AST2400_HPLL_BYPASS_EN BIT(17)
29 #define ASPEED_MISC_CTRL 0x2c
30 #define UART_DIV13_EN BIT(12)
31 #define ASPEED_MAC_CLK_DLY 0x48
32 #define ASPEED_STRAP 0x70
33 #define CLKIN_25MHZ_EN BIT(23)
34 #define AST2400_CLK_SOURCE_SEL BIT(18)
35 #define ASPEED_CLK_SELECTION_2 0xd8
36 #define ASPEED_RESET_CTRL2 0xd4
37
38 /* Globally visible clocks */
39 static DEFINE_SPINLOCK(aspeed_clk_lock);
40
41 /* Keeps track of all clocks */
42 static struct clk_hw_onecell_data *aspeed_clk_data;
43
44 static void __iomem *scu_base;
45
46 /* TODO: ask Aspeed about the actual parent data */
47 static const struct aspeed_gate_data aspeed_gates[] = {
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
55 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
56 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
57 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
58 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
59 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
60 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
61 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
62 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
63 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
64 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
65 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
66 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
67 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
68 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
69 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
70 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
72 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
73 };
74
75 static const char * const eclk_parent_names[] = {
76 "mpll",
77 "hpll",
78 "dpll",
79 };
80
81 static const struct clk_div_table ast2500_eclk_div_table[] = {
82 { 0x0, 2 },
83 { 0x1, 2 },
84 { 0x2, 3 },
85 { 0x3, 4 },
86 { 0x4, 5 },
87 { 0x5, 6 },
88 { 0x6, 7 },
89 { 0x7, 8 },
90 { 0 }
91 };
92
93 static const struct clk_div_table ast2500_mac_div_table[] = {
94 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
95 { 0x1, 4 },
96 { 0x2, 6 },
97 { 0x3, 8 },
98 { 0x4, 10 },
99 { 0x5, 12 },
100 { 0x6, 14 },
101 { 0x7, 16 },
102 { 0 }
103 };
104
105 static const struct clk_div_table ast2400_div_table[] = {
106 { 0x0, 2 },
107 { 0x1, 4 },
108 { 0x2, 6 },
109 { 0x3, 8 },
110 { 0x4, 10 },
111 { 0x5, 12 },
112 { 0x6, 14 },
113 { 0x7, 16 },
114 { 0 }
115 };
116
117 static const struct clk_div_table ast2500_div_table[] = {
118 { 0x0, 4 },
119 { 0x1, 8 },
120 { 0x2, 12 },
121 { 0x3, 16 },
122 { 0x4, 20 },
123 { 0x5, 24 },
124 { 0x6, 28 },
125 { 0x7, 32 },
126 { 0 }
127 };
128
129 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
130 {
131 unsigned int mult, div;
132
133 if (val & AST2400_HPLL_BYPASS_EN) {
134 /* Pass through mode */
135 mult = div = 1;
136 } else {
137 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
138 u32 n = (val >> 5) & 0x3f;
139 u32 od = (val >> 4) & 0x1;
140 u32 d = val & 0xf;
141
142 mult = (2 - od) * (n + 2);
143 div = d + 1;
144 }
145 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
146 mult, div);
147 };
148
149 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
150 {
151 unsigned int mult, div;
152
153 if (val & AST2500_HPLL_BYPASS_EN) {
154 /* Pass through mode */
155 mult = div = 1;
156 } else {
157 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */
158 u32 p = (val >> 13) & 0x3f;
159 u32 m = (val >> 5) & 0xff;
160 u32 n = val & 0x1f;
161
162 mult = (m + 1) / (n + 1);
163 div = p + 1;
164 }
165
166 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
167 mult, div);
168 }
169
170 static const struct aspeed_clk_soc_data ast2500_data = {
171 .div_table = ast2500_div_table,
172 .eclk_div_table = ast2500_eclk_div_table,
173 .mac_div_table = ast2500_mac_div_table,
174 .calc_pll = aspeed_ast2500_calc_pll,
175 };
176
177 static const struct aspeed_clk_soc_data ast2400_data = {
178 .div_table = ast2400_div_table,
179 .eclk_div_table = ast2400_div_table,
180 .mac_div_table = ast2400_div_table,
181 .calc_pll = aspeed_ast2400_calc_pll,
182 };
183
184 static int aspeed_clk_is_enabled(struct clk_hw *hw)
185 {
186 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
187 u32 clk = BIT(gate->clock_idx);
188 u32 rst = BIT(gate->reset_idx);
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
190 u32 reg;
191
192 /*
193 * If the IP is in reset, treat the clock as not enabled,
194 * this happens with some clocks such as the USB one when
195 * coming from cold reset. Without this, aspeed_clk_enable()
196 * will fail to lift the reset.
197 */
198 if (gate->reset_idx >= 0) {
199 regmap_read(gate->map, ASPEED_RESET_CTRL, &reg);
200 if (reg & rst)
201 return 0;
202 }
203
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
205
206 return ((reg & clk) == enval) ? 1 : 0;
207 }
208
209 static int aspeed_clk_enable(struct clk_hw *hw)
210 {
211 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
212 unsigned long flags;
213 u32 clk = BIT(gate->clock_idx);
214 u32 rst = BIT(gate->reset_idx);
215 u32 enval;
216
217 spin_lock_irqsave(gate->lock, flags);
218
219 if (aspeed_clk_is_enabled(hw)) {
220 spin_unlock_irqrestore(gate->lock, flags);
221 return 0;
222 }
223
224 if (gate->reset_idx >= 0) {
225 /* Put IP in reset */
226 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
227
228 /* Delay 100us */
229 udelay(100);
230 }
231
232 /* Enable clock */
233 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
234 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
235
236 if (gate->reset_idx >= 0) {
237 /* A delay of 10ms is specified by the ASPEED docs */
238 mdelay(10);
239
240 /* Take IP out of reset */
241 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
242 }
243
244 spin_unlock_irqrestore(gate->lock, flags);
245
246 return 0;
247 }
248
249 static void aspeed_clk_disable(struct clk_hw *hw)
250 {
251 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
252 unsigned long flags;
253 u32 clk = BIT(gate->clock_idx);
254 u32 enval;
255
256 spin_lock_irqsave(gate->lock, flags);
257
258 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
259 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
260
261 spin_unlock_irqrestore(gate->lock, flags);
262 }
263
264 static const struct clk_ops aspeed_clk_gate_ops = {
265 .enable = aspeed_clk_enable,
266 .disable = aspeed_clk_disable,
267 .is_enabled = aspeed_clk_is_enabled,
268 };
269
270 static const u8 aspeed_resets[] = {
271 /* SCU04 resets */
272 [ASPEED_RESET_XDMA] = 25,
273 [ASPEED_RESET_MCTP] = 24,
274 [ASPEED_RESET_ADC] = 23,
275 [ASPEED_RESET_JTAG_MASTER] = 22,
276 [ASPEED_RESET_MIC] = 18,
277 [ASPEED_RESET_PWM] = 9,
278 [ASPEED_RESET_PECI] = 10,
279 [ASPEED_RESET_I2C] = 2,
280 [ASPEED_RESET_AHB] = 1,
281
282 /*
283 * SCUD4 resets start at an offset to separate them from
284 * the SCU04 resets.
285 */
286 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5,
287 };
288
289 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
290 unsigned long id)
291 {
292 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
293 u32 reg = ASPEED_RESET_CTRL;
294 u32 bit = aspeed_resets[id];
295
296 if (bit >= ASPEED_RESET2_OFFSET) {
297 bit -= ASPEED_RESET2_OFFSET;
298 reg = ASPEED_RESET_CTRL2;
299 }
300
301 return regmap_update_bits(ar->map, reg, BIT(bit), 0);
302 }
303
304 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
305 unsigned long id)
306 {
307 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
308 u32 reg = ASPEED_RESET_CTRL;
309 u32 bit = aspeed_resets[id];
310
311 if (bit >= ASPEED_RESET2_OFFSET) {
312 bit -= ASPEED_RESET2_OFFSET;
313 reg = ASPEED_RESET_CTRL2;
314 }
315
316 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
317 }
318
319 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
320 unsigned long id)
321 {
322 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
323 u32 reg = ASPEED_RESET_CTRL;
324 u32 bit = aspeed_resets[id];
325 int ret, val;
326
327 if (bit >= ASPEED_RESET2_OFFSET) {
328 bit -= ASPEED_RESET2_OFFSET;
329 reg = ASPEED_RESET_CTRL2;
330 }
331
332 ret = regmap_read(ar->map, reg, &val);
333 if (ret)
334 return ret;
335
336 return !!(val & BIT(bit));
337 }
338
339 static const struct reset_control_ops aspeed_reset_ops = {
340 .assert = aspeed_reset_assert,
341 .deassert = aspeed_reset_deassert,
342 .status = aspeed_reset_status,
343 };
344
345 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
346 const char *name, const char *parent_name, unsigned long flags,
347 struct regmap *map, u8 clock_idx, u8 reset_idx,
348 u8 clk_gate_flags, spinlock_t *lock)
349 {
350 struct aspeed_clk_gate *gate;
351 struct clk_init_data init;
352 struct clk_hw *hw;
353 int ret;
354
355 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
356 if (!gate)
357 return ERR_PTR(-ENOMEM);
358
359 init.name = name;
360 init.ops = &aspeed_clk_gate_ops;
361 init.flags = flags;
362 init.parent_names = parent_name ? &parent_name : NULL;
363 init.num_parents = parent_name ? 1 : 0;
364
365 gate->map = map;
366 gate->clock_idx = clock_idx;
367 gate->reset_idx = reset_idx;
368 gate->flags = clk_gate_flags;
369 gate->lock = lock;
370 gate->hw.init = &init;
371
372 hw = &gate->hw;
373 ret = clk_hw_register(dev, hw);
374 if (ret) {
375 kfree(gate);
376 hw = ERR_PTR(ret);
377 }
378
379 return hw;
380 }
381
382 static int aspeed_clk_probe(struct platform_device *pdev)
383 {
384 const struct aspeed_clk_soc_data *soc_data;
385 struct device *dev = &pdev->dev;
386 struct aspeed_reset *ar;
387 struct regmap *map;
388 struct clk_hw *hw;
389 u32 val, rate;
390 int i, ret;
391
392 map = syscon_node_to_regmap(dev->of_node);
393 if (IS_ERR(map)) {
394 dev_err(dev, "no syscon regmap\n");
395 return PTR_ERR(map);
396 }
397
398 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
399 if (!ar)
400 return -ENOMEM;
401
402 ar->map = map;
403 ar->rcdev.owner = THIS_MODULE;
404 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
405 ar->rcdev.ops = &aspeed_reset_ops;
406 ar->rcdev.of_node = dev->of_node;
407
408 ret = devm_reset_controller_register(dev, &ar->rcdev);
409 if (ret) {
410 dev_err(dev, "could not register reset controller\n");
411 return ret;
412 }
413
414 /* SoC generations share common layouts but have different divisors */
415 soc_data = of_device_get_match_data(dev);
416 if (!soc_data) {
417 dev_err(dev, "no match data for platform\n");
418 return -EINVAL;
419 }
420
421 /* UART clock div13 setting */
422 regmap_read(map, ASPEED_MISC_CTRL, &val);
423 if (val & UART_DIV13_EN)
424 rate = 24000000 / 13;
425 else
426 rate = 24000000;
427 /* TODO: Find the parent data for the uart clock */
428 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
429 if (IS_ERR(hw))
430 return PTR_ERR(hw);
431 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
432
433 /*
434 * Memory controller (M-PLL) PLL. This clock is configured by the
435 * bootloader, and is exposed to Linux as a read-only clock rate.
436 */
437 regmap_read(map, ASPEED_MPLL_PARAM, &val);
438 hw = soc_data->calc_pll("mpll", val);
439 if (IS_ERR(hw))
440 return PTR_ERR(hw);
441 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
442
443 /* SD/SDIO clock divider and gate */
444 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
445 scu_base + ASPEED_CLK_SELECTION, 15, 0,
446 &aspeed_clk_lock);
447 if (IS_ERR(hw))
448 return PTR_ERR(hw);
449 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
450 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
451 soc_data->div_table,
452 &aspeed_clk_lock);
453 if (IS_ERR(hw))
454 return PTR_ERR(hw);
455 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
456
457 /* MAC AHB bus clock divider */
458 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
459 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
460 soc_data->mac_div_table,
461 &aspeed_clk_lock);
462 if (IS_ERR(hw))
463 return PTR_ERR(hw);
464 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
465
466 if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
467 /* RMII 50MHz RCLK */
468 hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
469 50000000);
470 if (IS_ERR(hw))
471 return PTR_ERR(hw);
472
473 /* RMII1 50MHz (RCLK) output enable */
474 hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
475 scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
476 &aspeed_clk_lock);
477 if (IS_ERR(hw))
478 return PTR_ERR(hw);
479 aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
480
481 /* RMII2 50MHz (RCLK) output enable */
482 hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
483 scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
484 &aspeed_clk_lock);
485 if (IS_ERR(hw))
486 return PTR_ERR(hw);
487 aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
488 }
489
490 /* LPC Host (LHCLK) clock divider */
491 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
492 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
493 soc_data->div_table,
494 &aspeed_clk_lock);
495 if (IS_ERR(hw))
496 return PTR_ERR(hw);
497 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
498
499 /* P-Bus (BCLK) clock divider */
500 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
501 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
502 soc_data->div_table,
503 &aspeed_clk_lock);
504 if (IS_ERR(hw))
505 return PTR_ERR(hw);
506 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
507
508 /* Fixed 24MHz clock */
509 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
510 0, 24000000);
511 if (IS_ERR(hw))
512 return PTR_ERR(hw);
513 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
514
515 hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
516 ARRAY_SIZE(eclk_parent_names), 0,
517 scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
518 &aspeed_clk_lock);
519 if (IS_ERR(hw))
520 return PTR_ERR(hw);
521 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
522
523 hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
524 scu_base + ASPEED_CLK_SELECTION, 28,
525 3, 0, soc_data->eclk_div_table,
526 &aspeed_clk_lock);
527 if (IS_ERR(hw))
528 return PTR_ERR(hw);
529 aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
530
531 /*
532 * TODO: There are a number of clocks that not included in this driver
533 * as more information is required:
534 * D2-PLL
535 * D-PLL
536 * YCLK
537 * RGMII
538 * RMII
539 * UART[1..5] clock source mux
540 */
541
542 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
543 const struct aspeed_gate_data *gd = &aspeed_gates[i];
544 u32 gate_flags;
545
546 /* Special case: the USB port 1 clock (bit 14) is always
547 * working the opposite way from the other ones.
548 */
549 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
550 hw = aspeed_clk_hw_register_gate(dev,
551 gd->name,
552 gd->parent_name,
553 gd->flags,
554 map,
555 gd->clock_idx,
556 gd->reset_idx,
557 gate_flags,
558 &aspeed_clk_lock);
559 if (IS_ERR(hw))
560 return PTR_ERR(hw);
561 aspeed_clk_data->hws[i] = hw;
562 }
563
564 return 0;
565 };
566
567 static const struct of_device_id aspeed_clk_dt_ids[] = {
568 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
569 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
570 { }
571 };
572
573 static struct platform_driver aspeed_clk_driver = {
574 .probe = aspeed_clk_probe,
575 .driver = {
576 .name = "aspeed-clk",
577 .of_match_table = aspeed_clk_dt_ids,
578 .suppress_bind_attrs = true,
579 },
580 };
581 builtin_platform_driver(aspeed_clk_driver);
582
583 static void __init aspeed_ast2400_cc(struct regmap *map)
584 {
585 struct clk_hw *hw;
586 u32 val, div, clkin, hpll;
587 const u16 hpll_rates[][4] = {
588 {384, 360, 336, 408},
589 {400, 375, 350, 425},
590 };
591 int rate;
592
593 /*
594 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
595 * strapping
596 */
597 regmap_read(map, ASPEED_STRAP, &val);
598 rate = (val >> 8) & 3;
599 if (val & CLKIN_25MHZ_EN) {
600 clkin = 25000000;
601 hpll = hpll_rates[1][rate];
602 } else if (val & AST2400_CLK_SOURCE_SEL) {
603 clkin = 48000000;
604 hpll = hpll_rates[0][rate];
605 } else {
606 clkin = 24000000;
607 hpll = hpll_rates[0][rate];
608 }
609 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin);
610 pr_debug("clkin @%u MHz\n", clkin / 1000000);
611
612 /*
613 * High-speed PLL clock derived from the crystal. This the CPU clock,
614 * and we assume that it is enabled. It can be configured through the
615 * HPLL_PARAM register, or set to a specified frequency by strapping.
616 */
617 regmap_read(map, ASPEED_HPLL_PARAM, &val);
618 if (val & AST2400_HPLL_PROGRAMMED)
619 hw = aspeed_ast2400_calc_pll("hpll", val);
620 else
621 hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0,
622 hpll * 1000000);
623
624 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;
625
626 /*
627 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
628 * 00: Select CPU:AHB = 1:1
629 * 01: Select CPU:AHB = 2:1
630 * 10: Select CPU:AHB = 4:1
631 * 11: Select CPU:AHB = 3:1
632 */
633 regmap_read(map, ASPEED_STRAP, &val);
634 val = (val >> 10) & 0x3;
635 div = val + 1;
636 if (div == 3)
637 div = 4;
638 else if (div == 4)
639 div = 3;
640 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
641 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
642
643 /* APB clock clock selection register SCU08 (aka PCLK) */
644 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
645 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
646 ast2400_div_table,
647 &aspeed_clk_lock);
648 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
649 }
650
651 static void __init aspeed_ast2500_cc(struct regmap *map)
652 {
653 struct clk_hw *hw;
654 u32 val, freq, div;
655
656 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
657 regmap_read(map, ASPEED_STRAP, &val);
658 if (val & CLKIN_25MHZ_EN)
659 freq = 25000000;
660 else
661 freq = 24000000;
662 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
663 pr_debug("clkin @%u MHz\n", freq / 1000000);
664
665 /*
666 * High-speed PLL clock derived from the crystal. This the CPU clock,
667 * and we assume that it is enabled
668 */
669 regmap_read(map, ASPEED_HPLL_PARAM, &val);
670 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
671
672 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
673 regmap_read(map, ASPEED_STRAP, &val);
674 val = (val >> 9) & 0x7;
675 WARN(val == 0, "strapping is zero: cannot determine ahb clock");
676 div = 2 * (val + 1);
677 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
678 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
679
680 /* APB clock clock selection register SCU08 (aka PCLK) */
681 regmap_read(map, ASPEED_CLK_SELECTION, &val);
682 val = (val >> 23) & 0x7;
683 div = 4 * (val + 1);
684 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
685 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
686 };
687
688 static void __init aspeed_cc_init(struct device_node *np)
689 {
690 struct regmap *map;
691 u32 val;
692 int ret;
693 int i;
694
695 scu_base = of_iomap(np, 0);
696 if (!scu_base)
697 return;
698
699 aspeed_clk_data = kzalloc(struct_size(aspeed_clk_data, hws,
700 ASPEED_NUM_CLKS),
701 GFP_KERNEL);
702 if (!aspeed_clk_data)
703 return;
704
705 /*
706 * This way all clocks fetched before the platform device probes,
707 * except those we assign here for early use, will be deferred.
708 */
709 for (i = 0; i < ASPEED_NUM_CLKS; i++)
710 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
711
712 map = syscon_node_to_regmap(np);
713 if (IS_ERR(map)) {
714 pr_err("no syscon regmap\n");
715 return;
716 }
717 /*
718 * We check that the regmap works on this very first access,
719 * but as this is an MMIO-backed regmap, subsequent regmap
720 * access is not going to fail and we skip error checks from
721 * this point.
722 */
723 ret = regmap_read(map, ASPEED_STRAP, &val);
724 if (ret) {
725 pr_err("failed to read strapping register\n");
726 return;
727 }
728
729 if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
730 aspeed_ast2400_cc(map);
731 else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
732 aspeed_ast2500_cc(map);
733 else
734 pr_err("unknown platform, failed to add clocks\n");
735
736 aspeed_clk_data->num = ASPEED_NUM_CLKS;
737 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
738 if (ret)
739 pr_err("failed to add DT provider: %d\n", ret);
740 };
741 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
742 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
Linux with added FPC-III support